Integrated circuit with micro-bumps and test bumps

Abstract

Disclosed are integrated circuit structures having small-sized interconnects, also referred to as micro-bumps. As the distance between the micro-bumps becomes smaller, the size of the micro-bumps becomes smaller. This makes it difficult to probe an integrated circuit structure to verify its operation. For probing, a larger pitch of test pads is provided. These test pads are typically formed of metal, which may be protected using solder caps.

Description

Technical Field

[0001] The present disclosure generally relates to novel bump structures for wafer probes with microbumps. Background Art

[0002] As the interconnect pitch decreases, probing (e.g., for testing) becomes challenging at fine pitches. Currently, the pitch of probe cards for bump / solder probing is limited to 80μm. One trend in integrated circuits (ICs) is 3DIC to reduce the area required to manufacture circuits, which also leads to a reduction in the area available for interconnects, while correspondingly reducing the pitch between interconnects. Previously, interconnects were also called bumps. However, as the pitch continues to decrease, the size of the bumps also decreases, so the bumps are called microbumps or μ bumps.

[0003] The manufactured 3DICs are also tested to ensure proper operation. However, the reduction in pitch makes it difficult to accommodate probes used to test the circuits. Accordingly, there is a need for systems, devices, and methods that enable the detection of manufactured circuits when the bump pitch is significantly reduced. Summary of the invention

[0004] A simplified overview of one or more aspects and / or examples associated with each device and method disclosed herein is presented below. As such, the following overview should neither be considered an exhaustive overview of all considered aspects and / or examples, nor should the following overview be considered to identify key or decisive elements associated with all considered aspects and / or examples or to depict the scope associated with any particular aspect and / or example. Accordingly, the sole purpose of the following overview is to present certain concepts related to one or more aspects and / or examples of the device and method disclosed herein in a simplified form before the specific embodiments presented below.

[0005] An exemplary integrated circuit (IC) structure is disclosed. The IC structure may include a wafer including one or more circuits within the wafer. The IC structure may also include a connection layer on the top surface of the wafer. The connection layer may be conductive and configured to couple with the one or more circuits. The connection layer may include a plurality of microbump pads and a plurality of test pads. The IC structure may also include a plurality of test bumps on the plurality of test pads. The plurality of test bumps may be formed by solder and configured to enable a test probe to touch the one or more circuits. The IC structure may also include a plurality of microbumps on the plurality of microbump pads. The plurality of microbumps may be configured to implement signal connections between the one or more circuits and one or more devices outside the IC structure. The microbump spacing may be less than the test bump spacing. The microbump spacing may be the center-to-center distance between adjacent microbumps, and the test bump spacing may be the center-to-center distance between adjacent test bumps.

[0006] An exemplary method for manufacturing an integrated circuit (IC) structure is disclosed. The method may include providing a wafer including one or more circuits within the wafer. The method may also include forming a connection layer on the top surface of the wafer. The connection layer may be conductive and configured to couple with the one or more circuits. The connection layer may include a plurality of microbump pads and a plurality of test pads. The method may also include forming a plurality of test bumps on the plurality of test pads. The plurality of test bumps may be formed of solder and configured to enable a test probe to touch the one or more circuits. The method may also include forming a plurality of microbumps on the plurality of microbump pads. The plurality of microbumps may be configured to enable signal connection between the one or more circuits and one or more devices outside the IC structure. The microbump pitch may be less than the test bump pitch. The microbump pitch may be the center-to-center distance between adjacent microbumps, and the test bump pitch may be the center-to-center distance between adjacent test bumps.

[0007] Another integrated circuit (IC) structure is disclosed. The IC structure may include a wafer including one or more circuits within the wafer. The IC structure may also include a connection layer on the top surface of the wafer. The connection layer may be conductive and configured to couple with the one or more circuits. The connection layer may include a plurality of first microbump pads, a plurality of second microbump pads, and a plurality of test pads. The IC structure may also include a plurality of test metallization layers on the plurality of test pads. The plurality of test metallization layers may be under-bump metallization layers (UBMs), which are configured to enable a test probe to touch the one or more circuits. The IC structure may also include a plurality of first microbumps and a plurality of second microbumps respectively located on the plurality of first microbump pads and the plurality of second microbump pads. The plurality of first microbumps and the plurality of second microbumps may be configured to realize signal connection between the one or more circuits and one or more devices outside the IC structure. The first microbump spacing may be less than the second microbump spacing and less than the test metallization layer spacing. The first microbump pitch may be a center-to-center distance between adjacent first microbumps, the second microbump pitch may be a center-to-center distance between adjacent second microbumps, and the test metallization layer pitch may be a center-to-center distance between adjacent test metallization layers.

[0008] Another method for manufacturing an integrated circuit (IC) structure is disclosed. The method may include providing a wafer, the wafer including one or more circuits within the wafer. The method may also include forming a connection layer on the top surface of the wafer. The connection layer may be conductive and configured to couple with the one or more circuits. The connection layer may include a plurality of first microbump pads, a plurality of second microbump pads, and a plurality of test pads. The method may also include forming a plurality of test metallization layers on the plurality of test pads. The plurality of test metallization layers may be under-bump metallization layers (UBMs), which are configured to enable a test probe to touch the one or more circuits. The method may also include forming a plurality of first microbumps and a plurality of second microbumps on the plurality of first microbump pads and the plurality of second microbump pads, respectively. The plurality of first microbumps and the plurality of second microbumps may be configured to realize signal connection between the one or more circuits and one or more devices outside the IC structure. The first microbump pitch may be less than the second microbump pitch and less than the test metallization pitch. The first microbump pitch may be a center-to-center distance between adjacent first microbumps, the second microbump pitch may be a center-to-center distance between adjacent second microbumps, and the test metallization layer pitch may be a center-to-center distance between adjacent test metallization layers.

[0009] Other features and advantages associated with the various devices and methods disclosed herein will be apparent to those skilled in the art based on the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete appreciation thereof will be readily obtained as various aspects of the present disclosure and many of its attendant advantages become better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented for illustrative purposes only and do not constitute a limitation of the present disclosure in any way.

[0011] Figure 1 An example of a conventional IC structure connected to an external device is illustrated.

[0012] Figure 2A and Figure 2B Another conventional IC structure suitable for enabling probing of the IC structure is illustrated in top view and side view, respectively.

[0013] Figure 3A and Figure 3B A top view and a side view of an IC structure configured to enable probing of the IC structure according to one or more aspects of the present disclosure are illustrated, respectively.

[0014] FIG. 4A to FIG. 4I An example of stages in fabricating an IC structure according to one or more aspects of the present disclosure is illustrated.

[0015] Figure 5 and Figure 6 The differences between conventional IC structures and IC structures fabricated according to one or more aspects of the present disclosure are illustrated.

[0016] 7A to 7H An example of stages in fabricating another IC structure according to one or more aspects of the present disclosure is illustrated.

[0017] Figure 8 and Fig. 9 A flow chart illustrating an example method of fabricating an IC structure according to one or more aspects of the present disclosure is shown.

[0018] Fig.10 and Fig.11 A flow chart illustrating another example method of fabricating an IC structure according to one or more aspects of the present disclosure is shown.

[0019] Fig.12 Various electronic devices are illustrated that may utilize one or more aspects of the present disclosure.

[0020] Based on the drawings and detailed description, other purposes and advantages associated with the various aspects disclosed herein will be apparent to those skilled in the art. According to convention, the features depicted in the drawings may not be drawn to scale. Accordingly, for the sake of clarity, the size of the features depicted may be arbitrarily enlarged or reduced. According to convention, for the sake of clarity, some drawings are simplified. Therefore, the drawings may not depict all components of a particular device or method. In addition, similar reference numerals are used throughout the specification and the drawings to indicate similar features. DETAILED DESCRIPTION

[0021] Various aspects of the present disclosure are illustrated in the following description and related drawings for specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of the present teachings. In addition, well-known elements of the exemplary embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in the present disclosure.

[0022] In some of the described example implementations, the following examples are identified where various component structures and portions of operations may be obtained from known conventional techniques and then arranged according to one or more exemplary embodiments. In such examples, internal details of portions of known conventional component structures and / or operations may be omitted to help avoid potential confusion of the concepts illustrated in the exemplary embodiments disclosed herein.

[0023] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "having", "including", and / or "containing" when used herein indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Traditionally, the interconnects (also known as bumps) of the wafer are tested using signals to verify whether the circuits within the wafer are in normal working order. The detection equipment may be able to detect bumps with a pitch equal to or greater than a certain minimum threshold pitch. If the pitch, which can be measured as the distance between adjacent bumps, is less than the minimum threshold pitch, such bumps may not be detected. Bumps with a pitch equal to or greater than the minimum pitch may also be referred to as "loose pitch" bumps. Currently, loose pitch bumps may have a pitch of about 55μm to 80μm or more.

[0025] However, newer ICs typically have very small bumps with very small pitches to allow for greater integration in a small form factor. Figure 1 A conventional IC structure 100 having small bumps and a small bump pitch is illustrated. The IC structure 100 is illustrated as being connected to an external device 190. The conventional IC structure 100 includes a wafer 110, and a circuit 120 is located within the wafer 110. A conductive connection layer 130 is on the surface of the wafer 110 and is electrically coupled to the circuit 120. An interconnect 140, also referred to as a microbump 140, is coupled to the circuit 120 through the connection layer 130. The microbump 140 implements a signal connection between the circuit 120 and a device external to the IC structure 100 (e.g., an external device 190).

[0026] The interconnects 140 are referred to as microbumps 140 to emphasize that they can be quite small and have a correspondingly small pitch. Table 1 below lists some of the interconnects, pitches, and other parameters.

[0027]

[0028] Table 1

[0029] For example, Table 1 indicates that for interconnect pitches of about ~45 μm to 55 μm, microbumps can be used as interconnects for IC structures. Thus, probing can be skipped entirely (e.g., for bridge die). Note that the number of probes can be relatively small for memory (on the order of hundreds) and relatively large for 3DIC (on the order of thousands to tens of thousands). These can be applicable to high bandwidth memory (HBM), logic 3DIC, interposers, bridge die, etc.

[0030] At very small pitches (eg, ~25 μm or less), probing may be performed on sacrificial pads rather than probing bumps. Figure 2A and Figure 2B A top view and a side view of another conventional IC structure 200 suitable for enabling detection of the IC structure through a sacrificial pad are illustrated respectively. The IC structure 200 includes a wafer 210 having a circuit 220 in the wafer 210. A conductive connection layer 330 is on the surface of the wafer 210 and electrically coupled to the circuit 220. A microbump 240 is coupled to the circuit 220 through a microbump pad 234 of the connection layer 230. The connection layer 230 also has a test pad 232 (sacrificial pad). The microbump 240 realizes a signal connection between the circuit 220 and a device outside the IC structure 200. Each microbump 240 includes a copper (Cu) via 242 on the corresponding microbump pad 234 and a solder bump 244 on the copper via 242.

[0031] Note that the test pads 232 of the connection layer 230 are larger and have a larger pitch than the microbumps 240. It may be assumed that the pitch of the test pads 232 is long enough to allow probing.

[0032] Although the test pad 232 does allow probing of the IC structure 200, there are some disadvantages. The connection layer 230 is typically formed of a metal such as copper or aluminum (Al). Therefore, oxidation may occur at the exposed surface of the connection layer (such as at the test pad 232). In addition, the tip of the probe is pointed, i.e., needle-shaped, to scrape and penetrate the surface oxide so that good electrical contact can be ensured. This probe-pad contact may damage the connection layer 230.

[0033] In order to solve these and other problems associated with conventional transistor IC structures, it is suggested to provide an IC structure that allows probe-solder contact even for IC structures with narrow pitch microbumps. In one or more embodiments, a test pad with sufficient spacing is provided. However, the test pad can be protected, for example, with solder or some other material.

[0034] Figure 3A and Figure 3BA top view and a side view of an IC structure 300 configured to enable probing of the IC structure according to one or more aspects of the present disclosure are illustrated, respectively. As shown, the IC structure 300 may include a wafer 310 having a circuit 320 within the wafer 210. In one aspect, the circuit 320 may be a circuit of a logic die, such as a 3DIC die.

[0035] IC structure 300 may also include a connection layer 330 on the top surface of wafer 310. It should be noted that the terms "top", "bottom", "left", "right", etc. are used only for convenience and are not intended to specify an absolute direction unless otherwise explicitly indicated. Connection layer 330 may be conductive and configured to couple with one or more circuits 320. Connection layer 330 may include a plurality of microbump pads 334 and a plurality of test pads 332. In one aspect, connection layer 330 may be a metal layer formed of a metal including copper, aluminum, or any combination thereof.

[0036] IC structure 300 may further include a plurality of test bumps 350 formed on a plurality of test pads 332 of connection layer 330. Multiple test bumps 350 may be formed of solder. Multiple test bumps 350 may be configured to enable a test probe to reach one or more circuits 320, for example, through connection layer 330.

[0037] IC structure 300 may also include a plurality of microbumps 340 formed on a plurality of microbump pads 334 of connection layer 330. Multiple microbumps 340 may be configured to implement signal connections between one or more circuits 320 and one or more devices outside IC structure 300. Each microbump 340 may include a conductive via 342 on the microbump pad 334 corresponding to the microbump 340. The conductive via 342 may be a metal via formed of a metal such as copper, aluminum, or any combination thereof. Each microbump 340 may also include a solder bump 344 on the conductive via 342.

[0038] IC structure 300 may further include a passivation layer 360 on connection layer 330. Passivation layer 360 may cover the entire top surface of connection layer 330 except for a plurality of microbump pads 334 (which may be covered by a plurality of microbumps 340) and a plurality of test pads 332 (which may be covered by a plurality of test bumps 350). In this way, exposure of connection layer 330 is limited, thereby limiting oxide accumulation.

[0039] In one aspect, the height of microbump 340 may be greater than the height of test bump 350. Alternatively or additionally, the lateral area of ​​test bump 350 may be greater than the lateral area of ​​microbump 340. In another aspect, multiple test bumps 350 may not behave like microbumps. That is, test bump 350 may not be configured to implement a signal connection between one or more circuits 320 and one or more devices external to IC structure 300.

[0040] Note that test bumps 350 may be larger and may have a larger pitch than microbumps 340. For ease of reference, the pitch of test bumps 350 (the center-to-center distance between adjacent test bumps 350) may be referred to as the test bump pitch, and the pitch of microbumps 340 (the center-to-center distance between adjacent microbumps 340) may be referred to as the microbump pitch. It can be said, then, that the microbump pitch is less than the test bump pitch. In one aspect, the test bump pitch may be long enough to allow probing. That is, the test bump pitch may be a "loose pitch". Alternatively or in addition, on the other hand, the microbump pitch may be a "fine pitch", which may describe a pitch that is too small for probing to occur (e.g., less than a minimum probe pitch threshold).

[0041] Note that probing may occur on test bumps 350. Since test bumps 350 are formed of solder, this allows for probe-solder contact. Since solder is ductile, a probe with a flat tip may be used, which reduces damage to test bumps 350. Moreover, any damage to test bumps 350 may be repaired or at least mitigated by solder reflow, which may reshape test bumps 350. Furthermore, since test pads 332 may be protected by test bumps 350, these test pads may not be contaminated.

[0042] FIG. 4A to FIG. 4I An example of stages in manufacturing an IC structure according to one or more aspects of the present disclosure is illustrated. In this example, these stages may be applied to the manufacture of IC structure 300.

[0043] Figure 4A The stage of depositing a connection layer 330 on a wafer 310 is illustrated. The circuit 320 is not illustrated to reduce clutter.

[0044] Figure 4B 4 shows a stage of depositing a first photoresist layer 470 on the connection layer 330. The deposited first photoresist layer 470 may be patterned to form a plurality of test pads 332 ( Figure 4B 4. The test pad opening 472 is not shown in FIG.

[0045] Figure 4CA stage is illustrated at which solder material is deposited in the test pad opening 472. As a result, a plurality of test bumps 350 may be formed. The height of the test bumps 350 may be determined at least in part by the height of the first photoresist layer 470.

[0046] Figure 4D A stage is illustrated at which the first photoresist layer 470 may be removed.

[0047] Figure 4E The stage of depositing the second photoresist layer 480 on the connection layer 330 and the test bump 350 is illustrated. In one aspect, the second photoresist layer 480 may be deposited on the connection layer 330 and the test bump 350. Figure 4B The first photoresist layer 470 deposited in the stage is 470 thick.

[0048] Figure 4F The deposited second photoresist layer 480 is patterned to form a plurality of micro-bump pads 334 ( Figure 4F 4. The stage of micro bump pad opening 484 (not shown) is described below.

[0049] Figure 4G The stage of depositing conductive material in micro bump pad openings 484 to form conductive vias 342 on plurality of micro bump pads 334 is illustrated. Also, solder material may be deposited in micro bump pad openings 484 to form solder bumps 344 on conductive vias 342.

[0050] Figure 4H A stage is illustrated at which the second photoresist layer 480 may be removed. Thereafter, the test bumps 350 may be probed to test the IC structure.

[0051] Fig. 4I illustrates the stages in which solder reflow may be performed. In one aspect, if Figure 4H The tests performed during the phase indicate that the IC structure is functioning properly, then the Fig. 4I stage.

[0052] FIG. 4A to FIG. 4I The illustrated manufacturing stage may be referred to as "two-step plating" because the test bumps 350 and the solder bumps 344 (of the microbumps 340) may be plated in different steps. Although not shown, for example, Figure 4H After the stage or Fig. 4I After the stage of forming a passivation layer 360.

[0053] Recalling the above, unlike conventional IC structures (such as IC structure 200 ), the proposed IC structure (such as IC structure 300 ) protects the test pads from being damaged. Figure 5 The connection layer 230 of the conventional IC structure is illustrated to be susceptible to damage from the probe tip. Figure 6It is illustrated that the connection layer 330 of the proposed IC structure is protected by the test bumps 350 from damage from the probe tip.

[0054] 7A to 7H An example of the stages of manufacturing another IC structure according to one or more aspects of the present disclosure is illustrated. Before describing these stages, the following will first be described. Figure 7G and Figure 7H The fabricated IC structure 700 is illustrated. Figure 7G and Figure 7H A top view and a side view are illustrated, respectively.As will be apparent, the IC structure 700 can allow probing through test pads and also through micro bumps for die attach (eg, to other dies).

[0055] like Figure 7G and Figure 7H As shown, IC structure 700 may include wafer 710 having circuit 720 within wafer 210. In one aspect, circuit 720 may be a circuit of a logic die, such as a 3DIC die.

[0056] The IC structure 700 may also include a connection layer 730 on the top surface of the wafer 710. The connection layer 730 may be conductive and configured to couple with one or more circuits 720. The connection layer 730 may include a plurality of first micro-bump pads 734, a plurality of second micro-bump pads 736, and a plurality of test pads 732. In one aspect, the connection layer 730 may be a metal layer formed of a metal including copper, aluminum, or any combination thereof.

[0057] The IC structure 700 may further include a plurality of test metallization layers 755 on the plurality of test pads 732. The plurality of test metallization layers 755 may be under bump metallization layers (UBM) and may enable a test probe to reach one or more circuits 720, for example, through the connection layer 730. Alternatively or additionally, the test metallization layer 755 may also be formed on the plurality of second micro bump pads 736.

[0058] The IC structure 700 may also include a plurality of first microbumps 740 formed on a plurality of first microbump pads 734 of the connection layer 730. The plurality of first microbumps 740 may be configured to implement signal connections between one or more circuits 720 and one or more devices outside the IC structure 700. Each first microbump 740 may include a first conductive via 742 on the first microbump pad 734 corresponding to the first microbump 740. The first conductive via 742 may be a metal via formed of a metal such as copper, aluminum, or any combination thereof. Each first microbump 740 may also include a first solder bump 744 on the first conductive via 742.

[0059] The IC structure 700 may also include a plurality of second microbumps 745 formed on a plurality of second microbump pads 736 of the connection layer 730. The plurality of second microbumps 745 may be configured to implement signal connections between one or more circuits 720 and one or more devices outside the IC structure 700. Each second microbump 745 may include a second conductive via 747 on the second microbump pad 736 corresponding to the second microbump 745. The second conductive via 747 may be a metal via formed of a metal such as copper, aluminum, or any combination thereof. Each second microbump 745 may also include a second solder bump 749 on the second conductive via 747.

[0060] IC structure 700 may also include a passivation layer 760 on connection layer 730. The passivation layer 760 may cover the entire top surface of connection layer 730 except for a plurality of first microbump pads 734 (which may be covered by a plurality of first microbumps 740), a plurality of second microbump pads 736 (which may be covered by a plurality of second microbumps 745), and a plurality of test pads 732 (which may be covered by a plurality of test metallization layers 755). In this way, exposure of connection 730 is limited, thereby limiting oxide accumulation. Note that in the illustrated top view, the top view of FIG. Figure 7G In FIG. 7 , the passivation layer 760 is not shown so that details of other components such as the connection layer 730 can be shown.

[0061] In one aspect, the height of the first microbump 740 and / or the height of the second microbump 745 may be greater than the height of the test metallization layer 755. Alternatively or additionally, the lateral area of ​​the test metallization layer 755 may be greater than the lateral area of ​​the first microbump 740. Note that the lateral area of ​​the test metallization layer 755 and the lateral area of ​​the second microbump 745 may be substantially equal. In this context, substantially equal is intended to indicate that the areas are within the margin of the equipment used to manufacture the IC structure 700. For example, if it is known that the equipment is ±1% from the indicated setting, the areas should be within 2% of each other to be substantially equal.

[0062] In another aspect, the plurality of test metallization layers 755 may not behave like microbumps. That is, the test metallization layers 755 may not be configured to enable signal connections between the one or more circuits 720 and one or more devices external to the IC structure 700.

[0063] Note that both the test metallization layer 755 and the second microbump 745 can be larger and have a larger spacing than the first microbump 740. For ease of reference, the spacing of the test metallization layer 755 (the center-to-center distance between adjacent test metallization layers 755) can be referred to as the test metallization layer spacing, the spacing of the first microbump 740 (the center-to-center distance between adjacent first microbumps 740) can be referred to as the first microbump spacing, and the spacing of the second microbump 745 (the center-to-center distance between adjacent second microbumps 745) can be referred to as the second microbump spacing. Then, it can be said that the first microbump spacing is less than the test metallization layer spacing and also less than the second microbump spacing. In one aspect, both the test metallization layer spacing and the second microbump spacing can be long enough to allow detection. That is, both the test metallization layer spacing and the second microbump spacing can be loose spacing. In one aspect, the test metallization layer spacing and the second microbump spacing can be substantially equal. Similarly, substantially equal is intended to indicate that the spacing is within the margin of the manufacturing equipment. Alternatively or additionally, in another aspect, the first microbump pitch can be a fine pitch.

[0064] Now, the different stages will be described. Fig. 7A and Figure 7B , respectively, illustrate a top view and a side view, illustrating a stage of forming a connection layer 730 including a plurality of test pads 732, a plurality of first microbump pads 734, and a plurality of second microbump pads 736. Again, for the reasons described above, in the top view, Fig. 7A The passivation layer 760 is not shown in FIG. This is also shown in the top view of other stages. Figure 7C and Fig. 7E are the same.

[0065] Figure 7C and Fig.7D A top view and a side view are shown, respectively, illustrating a stage of forming a test metallization layer 755 on the plurality of test pads 732. Optionally, in one aspect, a test metallization layer 755 (e.g., UBM) may also be formed on the plurality of second micro bump pads 736. Subsequently, a temporary test solder cap 750 may be formed on the test metallization layer 755, and a temporary micro bump solder cap 752 may be formed on the plurality of second micro bump pads 736 (or on the UBM).

[0066] After forming the temporary test solder cap 750 and the temporary microbump solder cap 752, probing can be performed through the temporary test solder cap 750 and / or through the temporary microbump solder cap 752. This is because both have loose spacing. This means that the test pad 732 may be needed only in areas where there are microbumps with fine spacing (such as the first microbump 740). The test pad 732 does not need to be set in areas where there are microbumps with loose spacing (such as the second microbump 745).

[0067] Fig. 7E and Figure 7F A top view and a side view are shown, respectively, illustrating a stage at which the temporary test solder cap 750 and the temporary micro-bump solder cap 752 may be removed.

[0068] at last, Figure 7G and Figure 7H The stage at which a first microbump 740 may be formed on the first microbump pad 734 and a second microbump 745 may be formed on the second microbump pad 736 is illustrated. FIG. 4F to FIG. 4I The illustrated manufacturing stages are to form first microbump 740 and second microbump 745 (eg, see Fig.11 Flowchart of the .

[0069] Figure 8 A flow chart illustrating an example method 800 of fabricating an IC structure (eg, IC structure 300 ) according to one or more aspects of the present disclosure is provided. In block 810 , a wafer 310 including one or more circuits 320 may be provided.

[0070] In block 820, a connection layer 330 may be formed on the top surface of the wafer 310. The connection layer 330 may be conductive. The connection layer 330 may also be configured to couple with one or more circuits 320. The connection layer 330 may include a plurality of micro bump pads 334 and a plurality of test pads 332.

[0071] In block 830, a plurality of test bumps 350 may be formed on the plurality of test pads 332. The plurality of test bumps 350 may be formed of solder and configured to enable a test probe to contact the one or more circuits 320.

[0072] In block 840, a plurality of microbumps 340 may be formed on the plurality of microbump pads 334. The plurality of microbumps 340 may be configured to enable signal connections between the one or more circuits 320 and one or more devices external to the IC structure 300. The microbump pitch may be smaller than the test bump pitch.

[0073] Fig. 9 A flow chart of an example process for implementing blocks 830 and 840 is illustrated. Blocks 910 to 940 may correspond to block 830, and blocks 950 to 990 may correspond to block 840. In block 910, a first photoresist layer 470 may be deposited on the connection layer 330 (see Figure 4B ).

[0074] In block 920, the first photoresist layer 470 may be patterned to form a plurality of test pad openings 472 (see FIG. 1 ) that expose the plurality of test pads 332. Figure 4B ).

[0075] In block 930, solder may be deposited in the plurality of test pad openings 472 to form a plurality of test bumps 350 (see Figure 4C ).

[0076] In block 940, the first photoresist layer 470 may be removed (see Figure 4D ).

[0077] In block 950, a second photoresist layer 480 may be deposited on the connection layer 330. Note that the second photoresist layer 480 may be thicker than the first photoresist layer 470 (see Figure 4E ).

[0078] In block 960, the second photoresist layer 480 may be patterned to form a plurality of micro bump pad openings 484 that expose the plurality of micro bump pads 334 (see FIG. Figure 4F ).

[0079] In block 970, a conductive material may be deposited in the plurality of micro bump pad openings 484 to form a plurality of conductive vias 342 on the plurality of micro bump pads 334 (see Figure 4G ).

[0080] In block 980, solder may be deposited in the plurality of microbump pad openings 484 to form a plurality of solder bumps 344 on the plurality of conductive vias 342 (see Figure 4G ).

[0081] In block 990, the second photoresist layer 480 may be removed (see Figure 4H ). Thereafter, the IC structure 300 may be probed.

[0082] Return to reference Figure 8 In block 850 , a passivation layer 360 may be formed on the connection layer 330 . The passivation layer 360 may cover the entire top surface of the connection layer 330 except for the plurality of micro bump pads 334 and the plurality of test pads 332 .

[0083] Fig.10 A flow chart illustrating an example method 1000 of fabricating an IC structure (eg, IC structure 700 ) according to one or more aspects of the present disclosure is provided. In block 1010 , a wafer 710 including one or more circuits 720 may be provided.

[0084] In block 1020, a connection layer 730 may be formed on the top surface of the wafer 710. The connection layer 730 may be conductive. The connection layer 730 may also be configured to couple with one or more circuits 720. The connection layer 730 may include a plurality of first micro-bump pads 734, a plurality of second micro-bump pads 736, and a plurality of test pads 732.

[0085] In block 1030, a plurality of test metallization layers 755 may be formed on the plurality of test pads 732. The plurality of test metallization layers 755 may be under bump metallization layers (UBM) configured to enable a test probe to access the one or more circuits 720.

[0086] In block 1040, a plurality of first microbumps 740 and a plurality of second microbumps 745 may be formed on the plurality of first microbump pads 734 and the plurality of second microbump pads 736, respectively. The plurality of first microbumps 740 and the plurality of second microbumps 745 may be configured to implement signal connections between the one or more circuits 720 and one or more devices external to the IC structure 700.

[0087] Fig.11 A flow chart for implementing a process of blocks 1030 and 1040 is illustrated. Blocks 1110 to 1140 may correspond to block 1030, and blocks 1150 to 1190 may correspond to block 1040. In block 1110, a plurality of test metallization layers 755 may be deposited on a plurality of test pads 732 (see Figure 7C and Fig.7D ).

[0088] In block 1120, solder may be deposited on the plurality of test metallization layers 755 to form a plurality of temporary test solder caps 750 (see Figure 7C and Fig.7D ).

[0089] In block 1130, solder may be deposited on the plurality of second microbump pads 736 to form a plurality of temporary microbump solder caps 752 (see Figure 7C and Fig.7D Thereafter, the IC structure 700 may be probed by the plurality of temporary test solder caps 750 and / or the plurality of temporary micro-bump solder caps 752 .

[0090] In block 1140, the plurality of temporary test solder caps 750 and the plurality of temporary microbump solder caps 752 (see Figure 7C and Fig.7D ).

[0091] In block 1150, a photoresist layer ( Figure 4E stage of modification).

[0092] In block 1160, the photoresist layer may be patterned to form a plurality of first microbump pad openings exposing the plurality of first microbump pads 734 and a plurality of second microbump pad openings exposing the plurality of second microbump pads 736, respectively. Figure 4F stage of modification).

[0093] In block 1170, a conductive material may be deposited in the plurality of first microbump pad openings and the plurality of second microbump pad openings to form a plurality of first conductive vias 742 on the plurality of first microbump pads 734 and a plurality of second conductive vias 747 on the plurality of second microbump pads 736, respectively. Figure 4G stage of modification).

[0094] In block 1180, solder may be deposited in the plurality of first microbump pad openings and the plurality of second microbump pad openings to form a plurality of first solder bumps 744 on the plurality of first conductive vias 742 and a plurality of second solder bumps 749 on the plurality of second conductive vias 747, respectively. Figure 4G stage of modification).

[0095] In block 1190, the photoresist layer ( Figure 4H stage of modification).

[0096] Return to reference Fig.10 In block 1050 , a passivation layer 760 may be formed on the connection layer 730 . The passivation layer 760 may cover the entire top surface of the connection layer 730 except for the plurality of first micro bump pads 734 , the plurality of second micro bump pads 736 , and the plurality of test pads 732 .

[0097] It will be understood that the aforementioned manufacturing process and related discussions are provided only as general illustrations of some aspects of the present disclosure and are not intended to limit the present disclosure or the appended claims. Further, many details of the manufacturing process known to those skilled in the art may be omitted or combined in each overview process section to facilitate understanding of the various aspects disclosed without presenting each detail and / or all possible process variations in detail. In addition, it will be understood that the illustrated configurations and descriptions are provided only to help illustrate the various aspects disclosed herein. For example, the number and position of inductors, the metallization structure may have more or fewer conductive layers and insulating layers, the orientation of the cavity, the size, whether it is formed by multiple cavities, whether it is closed or disconnected, and other aspects may have variations driven by specific application design features (such as the number of antennas, antenna types, frequency ranges, power, etc.). Accordingly, the aforementioned illustrative examples and associated drawings should not be construed as limiting the various aspects disclosed and claimed herein.

[0098] Fig.12 Various electronic devices 1200 that may be integrated with any of the aforementioned devices according to various aspects of the present disclosure are illustrated. For example, a mobile phone device 1202, a laptop computer device 1204, and a fixed location terminal device 1206 may each be generally considered as a user equipment (UE) and may include one or more IC structures (e.g., 300, 700) as described herein. Fig.12The illustrated devices 1202, 1204, 1206 are merely exemplary. Other electronic devices may also include RF filters, such electronic devices include, but are not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0099] The devices and functionality disclosed above may be designed and configured in computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting products may include semiconductor wafers that are subsequently cut into semiconductor dies and packaged into glass antenna devices. The glass antenna devices may then be used in the devices described herein.

[0100] Specific implementation examples are described in the following numbered clauses:

[0101] Item 1: An integrated circuit (IC) structure, the integrated circuit (IC) structure comprising: a wafer, the wafer including one or more circuits within the wafer; a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of microbump pads and a plurality of test pads; a plurality of test bumps on the plurality of test pads, the plurality of test bumps being formed of solder and configured to enable a test probe to access the one or more circuits; and a plurality of microbumps on the plurality of microbump pads, the plurality of microbumps being configured to enable signal connection between the one or more circuits and one or more devices outside the IC structure, wherein a microbump pitch is less than a test bump pitch, the microbump pitch being the center-to-center distance between adjacent microbumps, and the test bump pitch being the center-to-center distance between adjacent test bumps.

[0102] Item 2: The IC structure of Item 1, wherein a height of at least one micro bump is greater than a height of at least one test bump.

[0103] Clause 3: The IC structure of any of Clauses 1-2, wherein a lateral area of ​​at least one test bump is greater than a lateral area of ​​at least one microbump.

[0104] Clause 4: The IC structure of any one of clauses 1 to 3, wherein the plurality of test bumps are not configured to enable signal connection between the one or more circuits and one or more devices external to the IC structure.

[0105] Clause 5: The IC structure according to any one of clauses 1 to 4, further comprising: a passivation layer on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of micro bump pads and the plurality of test pads.

[0106] Clause 6: The IC structure of clause 5, wherein the connection layer is a metal layer.

[0107] Item 7: The IC structure of Item 6, wherein the connection layer is formed of copper (Cu), aluminum (Al), or both.

[0108] Clause 8: The IC structure of any one of clauses 1 to 7, wherein each microbump comprises: a conductive via on a microbump pad corresponding to the microbump; and a solder bump on the conductive via.

[0109] Clause 9: The IC structure of clause 8, wherein the conductive via is a metal via.

[0110] Clause 10: The IC structure of clause 9, wherein the conductive via is formed of copper (Cu).

[0111] Clause 11: The IC structure of any one of clauses 1 to 10, wherein the one or more circuits within the wafer are circuits of a logic die.

[0112] Clause 12: An IC structure according to any one of clauses 1 to 11, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0113] Item 13: A method for manufacturing an integrated circuit (IC) structure, the method comprising: providing a wafer, the wafer including one or more circuits within the wafer; forming a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of microbump pads and a plurality of test pads; forming a plurality of test bumps on the plurality of test pads, the plurality of test bumps being formed of solder and configured to enable a test probe to access the one or more circuits; forming a plurality of microbumps on the plurality of microbump pads, the plurality of microbumps being configured to enable signal connection between the one or more circuits and one or more devices outside the IC structure, wherein a microbump pitch is less than a test bump pitch, the microbump pitch being the center-to-center distance between adjacent microbumps, and the test bump pitch being the center-to-center distance between adjacent test bumps.

[0114] Clause 14: The method of clause 13, wherein a height of at least one first micro bump is greater than a height of at least one test bump.

[0115] Clause 15: The method of any one of clauses 13 to 14, wherein the lateral area of ​​at least one test bump is greater than the lateral area of ​​at least one micro bump.

[0116] Clause 16: A method according to any one of Clauses 13 to 15, wherein forming the plurality of test bumps comprises: depositing a first photoresist layer on the connection layer; patterning the first photoresist layer to form a plurality of test pad openings exposing the plurality of test pads; depositing solder in the plurality of test pad openings to form the plurality of test bumps; and removing the first photoresist layer.

[0117] Item 17: A method according to Item 16, wherein forming the plurality of microbumps comprises: depositing a second photoresist layer on the connecting layer, the second photoresist layer being thicker than the first photoresist layer; patterning the second photoresist layer to form a plurality of microbump pad openings exposing the plurality of microbump pads; depositing a conductive material in the plurality of microbump pad openings to form a plurality of conductive vias on the plurality of microbump pads; depositing solder in the plurality of microbump pad openings to form a plurality of solder bumps on the plurality of conductive vias; and removing the second photoresist layer.

[0118] Clause 18: The method of Clause 16, wherein the plurality of conductive vias are formed of copper (Cu).

[0119] Clause 19: The method according to any one of Clauses 13 to 18, further comprising: forming a passivation layer on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of micro bump pads and the plurality of test pads.

[0120] Clause 20: The method of any one of clauses 13 to 19, wherein the connection layer is formed of copper (Cu), aluminum (Al), or both.

[0121] Clause 21: The method of any one of clauses 13 to 20, wherein the one or more circuits within the wafer are circuits of a logic die.

[0122] Clause 22: An integrated circuit (IC) structure, the integrated circuit (IC) structure comprising: a wafer, the wafer comprising one or more circuits within the wafer; a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of first micro-bump pads, a plurality of second micro-bump pads, and a plurality of test pads; a plurality of test metallization layers on the plurality of test pads, the plurality of test metallization layers being under-bump metallization layers (UBMs), the under-bump metallization layers (UBMs) being configured to enable a test probe to reach the one or more circuits; and The multiple first microbumps and the multiple second microbumps on the multiple first microbump pads and the multiple second microbumps are configured to realize signal connection between the one or more circuits and one or more devices outside the IC structure, wherein the first microbump spacing is smaller than the second microbump spacing and smaller than the test metallization layer spacing, the first microbump spacing is the center-to-center distance between adjacent first microbumps, the second microbump spacing is the center-to-center distance between adjacent second microbumps, and the test metallization layer spacing is the center-to-center distance between adjacent test metallization layers.

[0123] Item 23: The IC structure of Item 22, wherein the second microbump pitch and the test metallization layer pitch are substantially equal.

[0124] Clause 24: An IC structure according to any one of Clauses 22 to 23, wherein the height of at least one first microbump is greater than the height of at least one test metallization layer, or wherein the height of at least one second microbump is greater than the height of the at least one test metallization layer, or both.

[0125] Clause 25: The IC structure of any one of Clauses 22 to 24, wherein a lateral area of ​​at least one test metallization layer is greater than a lateral area of ​​at least one first microbump.

[0126] Clause 26: The IC structure of any of Clauses 22 to 25, wherein the plurality of test metallization layers are not configured to enable signal connections between the one or more circuits and one or more devices external to the IC structure.

[0127] Clause 27: According to the IC structure described in any one of Clauses 22 to 26, the IC structure further includes: a passivation layer on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the multiple first micro-bump pads, the multiple second micro-bump pads and the multiple test pads.

[0128] Clause 28: The IC structure of any one of Clauses 22 to 27, wherein the connection layer is formed of copper (Cu), aluminum (Al), or both.

[0129] Clause 29: An IC structure according to any one of clauses 22 to 28, wherein each first microbump comprises: a first conductive via on a first microbump pad corresponding to the first microbump; and a first solder bump on the first conductive via, and wherein each second microbump comprises: a second conductive via on a second microbump pad corresponding to the second microbump; and a second solder bump on the second conductive via.

[0130] Clause 30: The IC structure of Clause 29, wherein the first conductive via is formed of copper (Cu), or wherein the second conductive via is formed of Cu, or both.

[0131] Clause 31: The IC structure of any one of clauses 22 to 30, wherein the one or more circuits within the wafer are circuits of a logic die.

[0132] Clause 32: An IC structure according to any one of clauses 22 to 31, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

[0133] Clause 33: A method of manufacturing an integrated circuit (IC) structure, the method comprising: providing a wafer, the wafer including one or more circuits within the wafer; forming a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of first micro-bump pads, a plurality of second micro-bump pads, and a plurality of test pads; forming a plurality of test metallization layers on the plurality of test pads, the plurality of test metallization layers being under-bump metallization layers (UBMs), the under-bump metallization layers (UBMs) being configured to enable a test probe to contact the one or more circuits; and A plurality of first microbumps and a plurality of second microbumps are formed on the plurality of first microbump pads and the plurality of second microbump pads, and the plurality of first microbumps and the plurality of second microbumps are configured to realize signal connection between the one or more circuits and one or more devices outside the IC structure, wherein the first microbump spacing is smaller than the second microbump spacing and smaller than the test metallization layer spacing, the first microbump spacing is the center-to-center distance between adjacent first microbumps, the second microbump spacing is the center-to-center distance between adjacent second microbumps, and the test metallization layer spacing is the center-to-center distance between adjacent test metallization layers.

[0134] Clause 34: The method of clause 33, wherein the second microbump pitch and the test metallization layer pitch are substantially equal.

[0135] Clause 35: A method according to any one of clauses 33 to 34, wherein the height of at least one first microbump is greater than the height of at least one test metallization layer, or wherein the height of at least one second microbump is greater than the height of the at least one test metallization layer, or both.

[0136] Clause 36: The method of any one of Clauses 33 to 35, wherein a lateral area of ​​at least one test metallization layer is greater than a lateral area of ​​at least one first microbump.

[0137] Clause 37: A method according to any one of Clauses 33 to 36, wherein forming the multiple test metallization layers includes: depositing the multiple test metallization layers on the multiple test pads; depositing solder on the multiple test metallization layers to form a multiple temporary test solder caps; depositing solder on the multiple second microbump pads to form a multiple temporary microbump solder caps; and removing the multiple temporary test solder caps and the multiple temporary microbump solder caps.

[0138] Item 38: A method according to Item 37, wherein forming the plurality of first microbumps and the plurality of second microbumps comprises: depositing a photoresist layer on the connecting layer; patterning the photoresist layer to respectively form a plurality of first microbump pad openings exposing the plurality of first microbump pads and a plurality of second microbump pad openings exposing the plurality of second microbump pads; depositing conductive material in the plurality of first microbump pad openings and the plurality of second microbump pad openings to respectively form a plurality of first conductive vias on the plurality of first microbump pads and a plurality of second conductive vias on the plurality of second microbump pads; depositing solder in the plurality of first microbump pad openings and the plurality of second microbump pad openings to respectively form a plurality of first solder bumps on the plurality of first conductive vias and a plurality of second solder bumps on the plurality of second conductive vias; and removing the photoresist layer.

[0139] Clause 39: The method of clause 38, wherein the first conductive via is formed of copper (Cu), or wherein the plurality of second conductive vias are formed of copper (Cu), or both.

[0140] Clause 40: The method according to any one of clauses 33 to 39, further comprising: forming a passivation layer on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of first micro bump pads, the plurality of second micro bump pads and the plurality of test pads.

[0141] Clause 41: The method of any one of clauses 33 to 40, wherein the connection layer is formed of copper (Cu), aluminum (Al), or both.

[0142] Clause 42: The method of any one of clauses 33 to 41, wherein the one or more circuits within the wafer are circuits of a logic die.

[0143] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, onboard devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by an individual and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that is capable of receiving wireless communications and / or navigation signals (such as through a short-range wireless, infrared, wired connection or other connection), regardless of whether satellite signal reception, assistance data reception and / or positioning-related processing occurs at the device or at the other device. In addition, these terms are intended to include all devices, including wireless and wired communication devices, which can communicate with the core network via a radio access network (RAN), and through the core network, the UE can connect to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as through a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.). The UE can be implemented by any of several types of devices, including but not limited to a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet device, a tracking device, an asset tag, etc. The communication link through which the UE can transmit signals to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link through which the RAN can transmit signals to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term "traffic channel (TCH)" may refer to an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0144] Wireless communication between electronic devices may be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), global system for mobile communications (GSM), 3GPP long term evolution (LTE), 5G new radio, Bluetooth (BT), Bluetooth low energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth low energy (also known as Bluetooth LE, BLE and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Technology Alliance that aims to provide significantly reduced power consumption and cost while maintaining a similar communication range. BLE was merged into the main Bluetooth standard in 2010, with the adoption of Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0145] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" is not to be construed as trumping other examples. Likewise, the term "example" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0146] It should be noted that the terms "connected", "coupled" or any variations thereof mean any connection or coupling, direct or indirect, between elements, and may encompass the presence of intermediate elements between two elements via which the two elements are "connected" or "coupled" together, unless the connection is explicitly disclosed as a direct connection.

[0147] Any reference to an element using designations such as "first," "second," etc. herein does not limit the quantity and / or order of those elements. Instead, these designations are used as a convenient method of distinguishing two or more elements and / or element instances. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0148] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0149] Nothing described or illustrated in this application is intended to confer upon the public any component, act, feature, benefit, advantage, or equivalent, regardless of whether such component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0150] In the above specific embodiments, it can be seen that different features are grouped together in each example. This disclosure should not be understood as reflecting the intention that the examples claimed for protection have more features than the features explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of the disclosed examples. Therefore, the attached claims should be considered to be incorporated into this specification, wherein each claim itself may be a separate example. Although each claim itself may be a separate example, it should be noted that although the dependent claims in the claims may be cited in a specific combination with one or more claims, other examples may also cover or include a combination of the subject matter of the dependent claim with any other dependent claim or any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly expressed that a specific combination is not intended to be used. In addition, it is also intended that the features of the claims may be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0151] It should also be noted that the methods, systems and apparatuses disclosed in the description or claims may be implemented by devices including means for performing the corresponding actions and / or functionalities of the disclosed methods.

[0152] In addition, in some examples, a single action can be subdivided into or include one or more sub-actions. Such sub-actions can be included in and can be part of the disclosure of a single action.

[0153] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made therein without departing from the scope of the present disclosure as defined in the appended claims. The functions and / or actions in the method claims of each example of the present disclosure described herein do not necessarily have to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid blurring the relevant details of the various aspects and examples disclosed herein. In addition, although the elements of the present disclosure may be described or claimed in the singular, plural forms may also be considered unless explicitly stated to be limited to the singular.

Claims

1. An integrated circuit (IC) structure, the integrated circuit (IC) structure comprising: a wafer, the wafer including one or more circuits within the wafer; a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of micro-bump pads and a plurality of test pads; a plurality of test bumps on the plurality of test pads, the plurality of test bumps being formed of solder and configured to enable a test probe to access the one or more circuits; and a plurality of microbumps on the plurality of microbump pads, the plurality of microbumps being configured to enable signal connections between the one or more circuits and one or more devices external to the IC structure, The microbump pitch is smaller than the test bump pitch, wherein the microbump pitch is the center-to-center distance between adjacent microbumps, and the test bump pitch is the center-to-center distance between adjacent test bumps. 2 . The IC structure of claim 1 , wherein a height of at least one micro bump is greater than a height of at least one test bump. 3 . The IC structure of claim 1 , wherein a lateral area of ​​at least one test bump is greater than a lateral area of ​​at least one micro bump. 4 . The IC structure of claim 1 , wherein the plurality of test bumps are not configured to enable signal connection between the one or more circuits and one or more devices external to the IC structure.

5. The IC structure according to claim 1, further comprising: A passivation layer is formed on the connection layer, and the passivation layer covers the entire top surface of the connection layer except for the plurality of micro bump pads and the plurality of test pads.

6. The IC structure of claim 5, wherein the connection layer is formed of copper (Cu), aluminum (Al), or both.

7. The IC structure of claim 1 , wherein each microbump comprises: a conductive via on a micro-bump pad corresponding to the micro-bump; and A solder bump is formed on the conductive via.

8. The IC structure of claim 7, wherein the conductive via is formed of copper (Cu).

9. The IC structure of claim 1, wherein the one or more circuits within the wafer are circuits of a logic die.

10. The IC structure of claim 1, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

11. A method of manufacturing an integrated circuit (IC) structure, the method comprising: providing a wafer, the wafer comprising one or more circuits within the wafer; forming a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of micro bump pads and a plurality of test pads; forming a plurality of test bumps on the plurality of test pads, the plurality of test bumps being formed of solder and configured to enable a test probe to contact the one or more circuits; as well as forming a plurality of microbumps on the plurality of microbump pads, the plurality of microbumps being configured to enable signal connection between the one or more circuits and one or more devices external to the IC structure, The microbump pitch is smaller than the test bump pitch, wherein the microbump pitch is the center-to-center distance between adjacent microbumps, and the test bump pitch is the center-to-center distance between adjacent test bumps. 12 . The method of claim 11 , wherein a height of at least one first micro bump is greater than a height of at least one test bump.

13. The method of claim 11, wherein a lateral area of ​​at least one test bump is greater than a lateral area of ​​at least one micro bump.

14. The method according to claim 11, wherein forming the plurality of test bumps comprises: depositing a first photoresist layer on the connecting layer; patterning the first photoresist layer to form a plurality of test pad openings exposing the plurality of test pads; depositing solder in the plurality of test pad openings to form the plurality of test bumps; as well as The first photoresist layer is removed.

15. The method of claim 14, wherein forming the plurality of microbumps comprises: depositing a second photoresist layer on the connecting layer, wherein the second photoresist layer is thicker than the first photoresist layer; patterning the second photoresist layer to form a plurality of micro bump pad openings exposing the plurality of micro bump pads; depositing a conductive material in the plurality of microbump pad openings to form a plurality of conductive vias on the plurality of microbump pads; depositing solder in the plurality of micro bump pad openings to form a plurality of solder bumps on the plurality of conductive vias; as well as The second photoresist layer is removed.

16. The method according to claim 11, further comprising: A passivation layer is formed on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of micro bump pads and the plurality of test pads.

17. The method of claim 11, wherein the one or more circuits within the wafer are circuits of a logic die.

18. An integrated circuit (IC) structure, the integrated circuit (IC) structure comprising: a wafer, the wafer including one or more circuits within the wafer; a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of first micro-bump pads, a plurality of second micro-bump pads, and a plurality of test pads; a plurality of test metallization layers on the plurality of test pads, the plurality of test metallization layers being under bump metallization layers (UBM), the under bump metallization layers (UBM) being configured to enable a test probe to access the one or more circuits; and a plurality of first microbumps and a plurality of second microbumps respectively located on the plurality of first microbump pads and the plurality of second microbump pads, the plurality of first microbumps and the plurality of second microbumps being configured to implement signal connections between the one or more circuits and one or more devices external to the IC structure, Wherein the first microbump pitch is smaller than the second microbump pitch and smaller than the test metallization layer pitch, the first microbump pitch is the center-to-center distance between adjacent first microbumps, the second microbump pitch is the center-to-center distance between adjacent second microbumps, and the test metallization layer pitch is the center-to-center distance between adjacent test metallization layers.

19. The IC structure of claim 18, wherein the second micro-bump pitch and the test metallization layer pitch are substantially equal.

20. The IC structure according to claim 18, wherein the height of at least one first micro-bump is greater than the height of at least one test metallization layer, or wherein the height of at least one second micro-bump is greater than the height of the at least one test metallization layer, or Both situations occur.

21. The IC structure of claim 18, wherein a lateral area of ​​at least one test metallization layer is greater than a lateral area of ​​at least one first microbump.

22. The IC structure of claim 18, further comprising: A passivation layer on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of first micro bump pads, the plurality of second micro bump pads, and the plurality of test pads.

23. The IC structure according to claim 18, Each of the first micro-bumps comprises: a first conductive via on a first microbump pad corresponding to the first microbump; and a first solder bump on the first conductive via, and Each of the second micro-bumps comprises: a second conductive via on a second microbump pad corresponding to the second microbump; and A second solder bump is formed on the second conductive via.

24. The IC structure of claim 18, wherein the one or more circuits within the wafer are circuits of a logic die.

25. The IC structure of claim 18, wherein the IC structure is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in a motor vehicle.

26. A method of manufacturing an integrated circuit (IC) structure, the method comprising: providing a wafer, the wafer comprising one or more circuits within the wafer; forming a connection layer on a top surface of the wafer, the connection layer being conductive and configured to couple with the one or more circuits, the connection layer comprising a plurality of first micro-bump pads, a plurality of second micro-bump pads, and a plurality of test pads; forming a plurality of test metallization layers on the plurality of test pads, the plurality of test metallization layers being under bump metallization layers (UBM), the under bump metallization layers (UBM) being configured to enable a test probe to access the one or more circuits; as well as forming a plurality of first microbumps and a plurality of second microbumps on the plurality of first microbump pads and the plurality of second microbump pads, respectively, the plurality of first microbumps and the plurality of second microbumps being configured to implement signal connections between the one or more circuits and one or more devices outside the IC structure, Wherein the first microbump pitch is smaller than the second microbump pitch and smaller than the test metallization layer pitch, the first microbump pitch is the center-to-center distance between adjacent first microbumps, the second microbump pitch is the center-to-center distance between adjacent second microbumps, and the test metallization layer pitch is the center-to-center distance between adjacent test metallization layers.

27. The method of claim 26, wherein forming the plurality of test metallization layers comprises: depositing the plurality of test metallization layers on the plurality of test pads; depositing solder on the plurality of test metallization layers to form a plurality of temporary test solder caps; depositing solder on the plurality of second micro bump pads to form a plurality of temporary micro bump solder caps; as well as The plurality of temporary test solder caps and the plurality of temporary micro bump solder caps are removed.

28. The method of claim 27, wherein forming the plurality of first microbumps and the plurality of second microbumps comprises: depositing a photoresist layer on the connecting layer; Patterning the photoresist layer to form a plurality of first microbump pad openings exposing the plurality of first microbump pads and a plurality of second microbump pad openings exposing the plurality of second microbump pads, respectively; depositing a conductive material in the plurality of first micro bump pad openings and the plurality of second micro bump pad openings to form a plurality of first conductive vias on the plurality of first micro bump pads and a plurality of second conductive vias on the plurality of second micro bump pads, respectively; depositing solder in the plurality of first microbump pad openings and the plurality of second microbump pad openings to form a plurality of first solder bumps on the plurality of first conductive vias and a plurality of second solder bumps on the plurality of second conductive vias, respectively; as well as The photoresist layer is removed.

29. The method according to claim 26, further comprising: A passivation layer is formed on the connection layer, the passivation layer covering the entire top surface of the connection layer except for the plurality of first micro bump pads, the plurality of second micro bump pads, and the plurality of test pads.

30. The method of claim 26, wherein the one or more circuits within the wafer are circuits of a logic die.

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