Piezoelectric on insulator (POI) substrate and method of producing piezoelectric on insulator (POI) substrate

Abstract

The invention discloses a piezoelectric on insulator (POI) substrate, comprising: a carrier substrate (102), in particular a silicon-based substrate; a piezoelectric layer (108), in particular a lithium tantalate (LTO) layer or a lithium niobate (LNO) layer; a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the substrate (102); and a trapping structure (104) sandwiched between the dielectric layer (106) and the carrier substrate (102). The POI substrate is characterized in that the trapping structure (104) comprises at least two trapping layers (104a, 104c), which are respectively separated by a dielectric intermediate layer (104b). A method for producing a piezoelectric on insulator (POI) substrate is also disclosed.

Description

Technical Field

[0001] The present invention relates to a piezoelectric-on-insulator (POI) substrate, which comprises a supporting substrate, a trapping structure, a dielectric layer and a piezoelectric layer in sequence, and also relates to a method for manufacturing such a POI substrate. Background Art

[0002] Such substrates are known in the prior art. Components such as sensors or filters are produced in and / or on the piezoelectric layer.

[0003] Trapping structures can reduce side-effect losses at the interface between the support substrate and the dielectric layer. This is because the trapping layer, inserted between the support substrate and the dielectric layer, serves to reduce the density of free carriers and prevent variations in the Fermi level. This results in a higher and more constant resistivity of the support substrate, which can reduce side effects such as signal attenuation, harmonic signal generation, or direct coupling.

[0004] However, it has been observed that during the fabrication of the POI substrate or subsequent thermal treatment, metallic elements (e.g., lithium) from the piezoelectric layer may diffuse through the dielectric layer and the trapping structure to the interface with the supporting substrate. The accumulation of these metallic elements degrades the performance quality of the trapping structure, negatively impacting the suppression of side effects.

[0005] It is therefore an object of the present invention to reduce the deleterious effects of diffusion of metallic elements through the POI substrate structure. Summary of the Invention

[0006] The objectives of the present invention are achieved by a piezoelectric-on-insulator (POI) substrate comprising: a support substrate, in particular a silicon-based substrate; a piezoelectric layer, in particular a lithium tantalate (LTO) layer or a lithium niobate (LNO) layer; a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate; and a capture structure sandwiched between the dielectric layer and the support substrate, characterized in that the capture structure comprises at least two capture layers separated from each other by a dielectric intermediate layer. Separating the capture structure into at least two capture layers with a dielectric layer between the two capture layers allows for isolation of a portion of the contamination from metal elements at the interface between the capture layer and the intermediate layer, thereby reducing the accumulation level of metal elements at the interface between the capture structure and the support structure. Thus, side effects can be effectively reduced. The support substrate preferably has a resistivity greater than or equal to 500 Ω.cm.

[0007] According to one embodiment, the trapping layer of the POI substrate may be based on polycrystalline silicon or amorphous silicon or porous silicon or on silicon carbide (SiC).These layers effectively reduce side effects.

[0008] According to one embodiment, the dielectric interlayer of the POI substrate can be a silicon oxide layer, in particular a native silicon oxide layer, or a layer deposited by chemical vapor deposition (CVD) or obtained by thermal oxidation. Silicon oxide is easy to produce, while accumulation of diffused metal elements can be observed at the interface of the interlayer of the trapping structure.

[0009] According to one embodiment, the dielectric intermediate layer of the POI substrate may have a thickness equal to or less than 5 nm, in particular equal to or less than 1 nm. Even layers of such low thickness have shown an effect on reducing side effects.

[0010] According to one embodiment, at least two of the at least two trapping layers may have one or more different physical properties, in particular grain sizes. Thus, the suppression of side effects may be further improved.

[0011] According to one embodiment, each capture layer of the POI substrate may have the same thickness. According to an alternative, at least one capture layer of the POI substrate may have a different thickness than the other capture layers. This makes it possible to optimize the performance of the POI substrate.

[0012] According to one embodiment, the trapping structure of the POI substrate may have a thickness equal to or less than 5 μm, preferably equal to or less than 2 μm. Therefore, even if a thinner trapping structure than in the prior art is used, side effects can be satisfactorily reduced.

[0013] The object of the present invention is also achieved by a method for manufacturing the above-mentioned piezoelectric-on-insulator (POI) substrate, comprising the following stages: providing a support substrate, in particular a silicon-based substrate; providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO); forming a trapping structure above the support substrate; forming a dielectric layer, in particular a silicon oxide layer, above the substrate comprising the piezoelectric layer and / or above the trapping structure; assembling the substrate comprising the piezoelectric layer with the support substrate so that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the stage of forming the trapping structure comprises forming a first trapping layer, forming a dielectric intermediate layer on the first trapping layer, and forming a second trapping layer on the dielectric intermediate layer. By this method, a substrate can be obtained that effectively reduces the negative effects of diffusion of metal elements into the support substrate.

[0014] According to one embodiment, the method for manufacturing a piezoelectric substrate may further include the following steps: forming a weakened region within the piezoelectric layer; and performing a fracture along the weakened region to separate a portion of the piezoelectric layer from the rest of the substrate including the piezoelectric layer after the assembly stage, thereby transferring the portion of the piezoelectric layer to a supporting substrate. This method enables the industrial manufacture of the POI substrate according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention and its advantages will be explained in more detail subsequently with the aid of advantageous embodiments given as examples and with the support of the following drawings, in which the reference characters indicate the characteristics of the invention.

[0016] [ Figure 1 ] schematically shows a piezoelectric-on-insulator (POI) substrate according to a first embodiment of the present invention.

[0017] [ Figure 2 ] schematically shows a piezoelectric-on-insulator (POI) substrate according to a second embodiment of the present invention.

[0018] [ Figure 3 ] schematically shows a piezoelectric-on-insulator (POI) substrate according to a third embodiment of the present invention.

[0019] [ Figure 4 ] schematically shows a method for manufacturing a piezoelectric-on-insulator (POI) substrate according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0020] The described embodiments constitute only possible configurations, and it should be borne in mind that the various features described above may be provided independently of one another, or may be omitted entirely, in the practice of the present invention.

[0021] [ Figure 1 ] schematically shows a piezoelectric-on-insulator (POI) substrate 100 according to a first embodiment of the present invention.

[0022] The piezoelectric-on-insulator substrate 100 comprises a support substrate 102. In this first embodiment, the support substrate 102 is a silicon-based substrate, in particular a single-crystal silicon wafer. The support substrate preferably has a resistivity greater than or equal to 500 Ω·cm.

[0023] A trapping structure 104 is arranged above the support substrate 102. The trapping structure 104 may be in direct contact with the support substrate 102. The trapping structure 104 has a thickness equal to or less than 5 μm, preferably equal to or less than 2 μm.

[0024] According to a first embodiment, the trapping structure 104 includes three layers: a first trapping layer 104a, a dielectric interlayer 104b, and a second trapping layer 104c.

[0025] The trapping layers 104a, 104c are based on polycrystalline silicon or amorphous silicon or porous silicon or on silicon carbide (SiC). Preferably, they are layers deposited by low pressure chemical vapor deposition (LPCVD). In this embodiment, the two trapping layers 104a, 104c have the same thickness.

[0026] The dielectric interlayer 104b may be a silicon oxide layer, preferably a native silicon oxide layer. Alternatively, the dielectric interlayer may be formed by chemical vapor deposition (CVD) or thermal oxidation. The dielectric interlayer 104b preferably has a thickness smaller than that of the capture layers 104a, 104b, specifically equal to or less than 5 nm, and more preferably equal to or less than 1 nm.

[0027] A dielectric layer 106 is disposed above the trapping structure 104, in particular, directly above the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide-based layer. The dielectric layer 106 preferably has a thickness between 100 nm and 1 μm, in particular between 200 nm and 700 nm. The dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.

[0028] The piezoelectric layer 108 is arranged above the dielectric layer 106, in particular directly on the dielectric layer 106. It is preferably a lithium tantalate (LTO) layer or a lithium niobate (LNO) layer. The piezoelectric layer 108 typically has a thickness between 200 nm and 1 μm.

[0029] According to an alternative form, the two trapping layers 104a and 104c may have one or more different physical properties, such as grain size.

[0030] Separating the trapping structure 104 into at least two trapping layers 104a and 104c with a dielectric intermediate layer 104b between the two trapping layers 104a and 104c allows a portion of the contamination of the metal elements to be isolated at the interface between the trapping layers 104a and 104c and the intermediate layer 104b, thereby reducing the concentration of the metal elements at the interface between the trapping structure 104 and the support structure 102. Therefore, the reduction in the suppression of side effects is compensated.

[0031] [ Figure 2 ] schematically shows a piezoelectric-on-insulator (POI) substrate 200 according to a second embodiment of the present invention.

[0032] The piezoelectric-on-insulator substrate 200 includes the support substrate 102, the dielectric layer 106, and the piezoelectric layer 108 of the first embodiment. New descriptions of these layers and their characteristics are omitted, and reference is made to their descriptions related to the first embodiment described above.

[0033] The only difference between the first and second embodiments is that another trapping structure 204 is used.

[0034] In the second embodiment, the trapping structure 204 includes a total of five trapping layers 204a, 204c, 204e, 204g, and 204i, with intervening dielectric layers 204b, 204d, 204f, and 204h interposed between each of the trapping layers.

[0035] The capture layers 204a, 204c, 204e, 204g and 204i are produced in the same manner as the capture layers 104a and 104c of the first embodiment and have the same physical properties as these layers. In particular, they all have the same thickness, in particular a thickness of 0.2 μm or less.

[0036] Likewise, dielectric interlayers 204b, 204d, 204f, and 204h are produced in the same manner as dielectric interlayer 104b of the first embodiment and have the same physical properties as that layer. Specifically, they all have the same thickness, in particular, a thickness of several tens of nanometers (several angstroms), particularly one nanometer or less (10 angstroms or less).

[0037] By increasing the number of interfaces in the trapping structure 204, the concentration of the metal element (particularly lithium) at the interface between the first trapping layer 204a and the supporting substrate 102 can be further reduced because the metal element is trapped at each interface. Therefore, the amount of the metal element reaching the interface with the supporting substrate 102 is lower than that of a structure with fewer interfaces.

[0038] According to alternative forms, more or fewer trapping layers and dielectric interlayers may be provided in the trapping structure, depending on the concentration levels of the metal elements that are acceptable for a given application.

[0039] [ Figure 3 ] schematically shows a piezoelectric-on-insulator (POI) substrate 300 according to a third embodiment of the present invention.

[0040] The piezoelectric substrate on insulator 300 includes the support substrate 102 of the first embodiment, the dielectric layer 106, and the piezoelectric layer 108. These layers and their properties will not be described again, but reference is made to their description in the first embodiment.

[0041] The only difference between the first and third embodiments is the use of another trapping structure 304 .

[0042] In this embodiment, the trapping structure 304 includes several trapping layers 304a, 304c, 304e, 304g, 304i, and 304k, which are separated by dielectric interlayers 304b, 304d, 304f, 304h, and 304j as in the second embodiment.

[0043] The dielectric interlayers 304b, 304d, 304f, 304h and 304j are produced as in the first or second embodiment and have the same thickness, for example, several tens of nanometers (several angstroms), particularly 1 nanometer or less (10 angstroms or less).

[0044] On the other hand, several thin trapping layers 304c, 304e, 304g, 304i and 304k all have the same thickness, eg, 0.1 μm or less, while trapping layer 304a is thicker, specifically 0.5 μm or more.

[0045] By adding an interface to the trapping structure 304, the concentration of the metal element (particularly lithium) at the interface between the first trapping layer 304a and the supporting substrate 102 can be reduced, as in the second embodiment. The layer 304a at the interface with the supporting substrate 102 is thicker, thus retaining its trapping properties.

[0046] According to alternative forms, more or fewer trapping layers and dielectric interlayers may be provided in the trapping structure, depending on the accumulation level of metallic elements that is acceptable for a given application.

[0047] [ Figure 4 ] schematically shows a method for manufacturing a piezoelectric-on-insulator (POI) substrate according to a fourth embodiment of the present invention, to obtain the piezoelectric substrate as described above in conjunction with Figure 1 The POI substrate 100 according to the first embodiment is described. Figure 1 Reference numerals already used in the description of the POI substrate 100 are reused for the description of the method.

[0048] The method for manufacturing a piezoelectric-on-insulator (POI) substrate 100 begins with a stage I) of providing a support substrate 102 , in particular a silicon-based substrate, especially a single-crystal silicon wafer.

[0049] According to this fourth embodiment of the invention, phase II) provides for forming a trapping structure 104 on the free surface 120 of the support substrate 102 .

[0050] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low pressure chemical vapor deposition (LPCVD). According to an alternative form, it can be formed by thermal growth techniques or physical vapor deposition (PVD).

[0051] The capture layer 104a formed on the support substrate 102 is a layer based on polycrystalline silicon, amorphous silicon or porous silicon, or a layer based on silicon carbide. The thickness of the capture layer 104a is equal to or less than 2.5 μm, specifically equal to or less than 1 μm.

[0052] Subsequently, a dielectric interlayer 104b is formed on the first capture layer 104a. The dielectric interlayer 104b may be a silicon oxide layer, preferably a native silicon oxide layer. According to an alternative form, the dielectric interlayer is formed by chemical vapor deposition (CVD) or thermal oxidation. The dielectric interlayer 104b preferably has a thickness smaller than that of the first capture layer 104a, specifically less than 5 nm, and more preferably less than 1 nm.

[0053] To complete the formation of the trapping structure 104 , a second trapping layer 104 c is formed on the dielectric interlayer 104 b in the same manner and, in particular, with the same thickness as the first trapping layer 104 a .

[0054] In an alternative embodiment, the two trapping layers 104a and 104c can be formed to have one or more different physical properties, such as grain size. In another alternative embodiment, the two trapping layers 104a and 104c can be based on different materials from those mentioned above. For example, layer 104a can be made of porous silicon and layer 104b can be made of polycrystalline silicon.

[0055] During phase III), a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104c. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). According to an alternative form, the layer 106a is formed by oxidation of polysilicon.

[0056] The dielectric layer 106 a preferably has a thickness equal to or less than 1 μm, particularly equal to or less than 700 nm.

[0057] A heat treatment may be performed after the dielectric layer 106a is deposited to densify it.

[0058] During phase IV), a substrate 124 is provided, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO), comprising a piezoelectric layer 126. In this embodiment, the piezoelectric layer 124 is arranged above the base substrate 126. In an alternative form, the piezoelectric layer 126 is a bulk layer and integrally forms the substrate 124.

[0059] During phase V), a second dielectric layer 106b, in particular a silicon oxide layer, is formed on the free surface 130 of the piezoelectric layer 126. This layer is formed in the same manner as the dielectric layer 106a formed during phase III). The thickness is selected so that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100 nm and 1 μm, in particular between 200 nm and 700 nm.

[0060] According to an alternative form, the free surface 130 of the substrate 124 including the piezoelectric layer may be subjected to one or more stages of surface treatment before forming the dielectric layer 106b. For example, a surface activation treatment such as a plasma treatment and / or an ozone-based treatment may be performed.

[0061] During phase VI), the substrate 124 obtained after phase V) is assembled with the support substrate 102 obtained in the assembly phase III) to form a support substrate—a substrate comprising the piezoelectric layer assembly 132 .

[0062] The assembly is performed so that the dielectric layers 106a and 106b are in direct contact. The assembly is preferably performed by molecular adhesion.

[0063] Once the two substrates are assembled, a stage VII) of thinning the assembly 132 is performed in order to obtain a POI substrate 100 with a thinner piezoelectric layer 108, such as Figure 1 shown.

[0064] For example, the thinning stage can be performed by milling or by forming a weakened zone in the piezoelectric layer 126 before the assembly stage (VI), thereby defining the piezoelectric layer 108 to be transferred to the support substrate 102 and breaking it. This stage of forming the weakened zone is performed by implanting atomic or ionic entities into the piezoelectric layer 126. The atomic or ion implantation can be performed so that the weakened zone is located inside the piezoelectric layer 126 and defines the piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126. Subsequently, by providing thermal and / or mechanical energy to the weakened zone of the piezoelectric layer 126, a stage of fracturing the assembly 132 is performed to obtain the piezoelectric-on-insulator (POI) substrate 100.

[0065] According to an alternative form, the bonding between the support substrate 102 and the substrate 124 may also be performed between the trapping structure 104 and the dielectric layer 106 b (ie without performing phase III)) or between the dielectric layer 106 a and the piezoelectric layer 126 .

[0066] Before producing the above-mentioned one or more layers, the surface directly below may be subjected to one or more stages of cleaning, scrubbing or polishing in order to remove the presence of particles and dust.

[0067] This method can also be used to obtain Figure 2 and Figure 3 The POI substrates 200 and 300 according to the second and third embodiments of the present invention are described.

Claims

1. A piezoelectric-on-insulator (POI) substrate comprising: - a supporting substrate (102), in particular a silicon-based substrate, a piezoelectric layer (108), in particular a lithium tantalate (LTO) layer or a lithium niobate (LNO) layer, - a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the supporting substrate (102), - a trapping structure (104) sandwiched between a dielectric layer (106) and a supporting substrate (102), It is characterized in that The trapping structure (104) comprises at least two trapping layers (104a, 104c), the trapping layers (104a, 104c) being separated from each other by a dielectric intermediate layer (104b), and at least two of the at least two trapping layers (104a, 104c) having different physical properties, in particular grain sizes.

2. The piezoelectric-on-insulator (POI) substrate according to claim 1, wherein: The trapping layers (104a, 104c) are based on polycrystalline silicon and / or amorphous silicon and / or porous silicon and / or on silicon carbide (SiC).

3. The piezoelectric on insulator (POI) substrate according to claim 1 or 2, wherein: The dielectric intermediate layer (104b) is a silicon oxide layer, in particular a native silicon oxide layer, or a layer deposited by chemical vapor deposition (CVD) or a layer obtained by thermal oxidation.

4. The piezoelectric-on-insulator (POI) substrate according to any one of claims 1 to 3, wherein: The dielectric intermediate layer (104b) has a thickness equal to or less than 5 nm, in particular equal to or less than 1 nm.

5. The piezoelectric-on-insulator (POI) substrate according to any one of claims 1 to 4, wherein: Each trapping layer (104a, 104c) has the same thickness.

6. The piezoelectric-on-insulator (POI) substrate according to any one of claims 1 to 5, wherein: At least one capture layer (304a) has a different thickness from the other capture layers (304c, 304e), and in particular the capture layer (304a) directly disposed on the support substrate is thicker than the other capture layers.

7. The piezoelectric-on-insulator (POI) substrate according to at least one of claims 1 to 6, wherein: The trapping structure (104) has a thickness equal to or less than 5 μm, preferably equal to or less than 2 μm.

8. Method for manufacturing a piezoelectric-on-insulator (POI) substrate according to any one of claims 1 to 7, the method comprising the following stages: - providing a supporting substrate, in particular a silicon-based substrate, - providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), - forming a trapping structure above the supporting substrate, - forming a dielectric layer, in particular a silicon oxide layer, over the substrate comprising the piezoelectric layer and / or over the trapping structure, - assembling the substrate comprising the piezoelectric layer with a support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, It is characterized in that The stages of forming the trapping structure include A first pinning layer is formed, a dielectric interlayer is formed on the first pinning layer, and a second pinning layer is formed on the dielectric interlayer, the two pinning layers having different physical properties, especially grain sizes.

9. The method for manufacturing a piezoelectric substrate according to claim 8, further comprising the following stages: - forming a weakened zone within the piezoelectric layer, and - performing a fracture along the weakened zone in order to separate a portion of the piezoelectric layer from the rest of the substrate comprising the piezoelectric layer after the assembly stage, thereby transferring a portion of the piezoelectric layer to a supporting substrate.

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