Light detection element, timing generator, and AD converter

Abstract

[Problem] To reduce power consumption. [Solution] The light detection element comprises a plurality of pixels, each of the plurality of pixels having a physical signal acquisition unit for acquiring a physical signal, a comparison unit for comparing the physical signal acquired by the physical signal acquisition unit with a reference signal, a signal accumulation floating unit electrically connected to one end of the comparison unit; the signal detection unit is electrically connected with the signal accumulation floating unit and detects the comparison result of the comparison unit, and the signal amplification unit is used for amplifying the detection result of the signal detection unit; the signal storage unit is used for storing time codes; and a signal input / output unit for inputting / outputting a time code, and a signal control unit for performing control so that the storage unit stores the time code output from the signal input / output unit and outputs the time code to the signal input / output unit, the time code when the comparison result is inverted being stored in the signal storage unit, at least two or more pixels operate in parallel.

Description

Technical Field

[0001] Embodiments according to the present disclosure relate to a light detection element, a timing generator, and an AD converter. Background Art

[0002] There is a case where an analog-to-digital converter (ADC) is provided on the signal reading side of the light detection element (see Patent Documents 1 to 3).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: WO 2016 / 136448 A

[0006] Patent Document 2: WO 2018 / 037902 A

[0007] Patent Document 3: WO 2017 / 119220 A Summary of the invention

[0008] Problems to be solved by the present invention

[0009] However, there is a need for power reduction of the ADC.

[0010] Therefore, the present disclosure provides a light detection element, a timing generator, and an AD converter capable of reducing power consumption.

[0011] Solution to the problem

[0012] In order to solve the above problems, according to the present disclosure, a light detection element is provided, comprising:

[0013] A plurality of pixels, wherein

[0014] Each pixel in the plurality of pixels includes:

[0015] A physical signal acquisition unit, which acquires a physical signal;

[0016] A comparing unit, which compares the physical signal acquired by the physical signal acquiring unit with a reference signal;

[0017] A signal accumulation floating unit is electrically connected to one end of the comparison unit;

[0018] A signal detection unit, electrically connected to the signal accumulation floating unit and detecting a comparison result of the comparison unit;

[0019] A signal amplifying unit, amplifying the detection result of the signal detecting unit;

[0020] A signal storage unit for storing a time code;

[0021] a signal input and output unit for inputting and outputting time codes; and

[0022] a signal control unit that performs control to store the time code output by the signal input-output unit in the signal storage unit based on the comparison result, and outputs the time code when the comparison result is inverted to the signal input-output unit, the time code being stored in the signal storage unit, and

[0023] Two or more pixels in a pixel are operated in parallel.

[0024] You can also set:

[0025] at least two pixel groups, each pixel group detecting a physical signal; and

[0026] The storage control unit performs control for each pixel group to store the time code in the signal storage unit, and controls whether to update the time code stored in the signal storage unit.

[0027] The comparison unit may include a transistor including: a gate to which the physical signal acquired by the physical signal acquisition unit is input; a source to which the reference signal is input; and a drain electrically connected to the signal accumulation floating unit;

[0028] The comparison unit may change the voltage of the signal accumulation floating unit based on the gate-source voltage of the transistor and the threshold value of the transistor to enable the signal detection unit to perform detection, and

[0029] The signal detection unit may be arranged in the pixel array unit.

[0030] A capacitor may be further provided, the capacitor being connected between a reference signal generating unit that generates a reference signal and the source of the transistor.

[0031] A connection unit may be further provided, the connection unit being connected between the source of the transistor and the gate of the transistor and electrically connecting the source of the transistor and the gate of the transistor at a predetermined timing.

[0032] A plurality of physical signal acquisition units may share the comparison unit.

[0033] The signal amplifying unit may be a positive feedback circuit.

[0034] The physical signal acquisition unit, the comparison unit, the signal accumulation floating unit, the signal detection unit, the signal amplification unit, the signal control unit, the signal storage unit, and the signal input-output unit may be arranged across at least two semiconductor chips.

[0035] A plurality of physical signal acquisition units may share a signal input and output unit.

[0036] The signal input-output unit may include a trigger.

[0037] The signal input-output unit may include a tri-state inverter.

[0038] At least two signal storage units may be provided.

[0039] At least two signal input and output units may be provided to correspond to one of the at least two signal storage units, respectively.

[0040] A signal processing unit that performs at least one of image processing and subtraction processing between the signals stored in the at least two signal storage units may also be provided.

[0041] According to the present disclosure, a timing generator is provided, comprising:

[0042] A first circuit, a second circuit and an operation circuit, wherein:

[0043] The first circuit outputs a first output signal obtained by delaying the inverse phase timing of the input signal and an activation signal for activating the second circuit based on one input signal,

[0044] The second circuit is activated based on the activation signal and outputs a second output signal, and

[0045] The operation circuit calculates the first output signal and the second output signal to output a third output signal.

[0046] The activation signal may be a first power supply voltage of the second circuit.

[0047] The second circuit may be a second power supply voltage of the first circuit during a period in which the second circuit is not activated.

[0048] The first circuit and the second circuit include a first positive feedback circuit and a second positive feedback circuit connected in series.

[0049] According to the present disclosure, an AD converter is provided, comprising:

[0050] Timing generator;

[0051] a signal storage unit storing a time code; and

[0052] A signal control unit performs control to store the time code in the signal storage unit based on the third output signal.

[0053] The first circuit may output a first output signal which is inverted at a first timing.

[0054] The second circuit may output a second output signal inverted at a second timing after the first timing, and the operation circuit may output a third output signal inverted at the first timing and the second timing, and

[0055] The signal control unit may start storing the time code in the signal storage unit at a first timing, and may stop storing the time code in the signal storage unit at a second timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a diagram showing a schematic configuration of a solid-state imaging device according to the present disclosure.

[0057] Figure 2 is a block diagram showing a detailed configuration example of a pixel.

[0058] Figure 3A This is a conceptual diagram of a solid-state imaging device constructed by stacking two semiconductor substrates.

[0059] Figure 3B is a diagram showing a schematic configuration in the case where a solid-state imaging device is constituted by stacking two semiconductor substrates.

[0060] Figure 4A This is a conceptual diagram of a solid-state imaging device constructed by stacking three semiconductor substrates.

[0061] Figure 4B : is a diagram showing a schematic configuration in the case where the solid-state imaging device is constituted by stacking three semiconductor substrates.

[0062] Figure 5 : is a diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0063] Figure 6 is a circuit diagram showing an example of the configuration of a comparison circuit according to the first embodiment.

[0064] Figure 7 is a circuit diagram showing an example of the configuration of a data storage unit according to the first embodiment.

[0065] Figure 8 : is a timing chart showing an example of the operations of the comparison circuit and the data storage unit according to the first embodiment.

[0066] Fig. 9 is a circuit diagram showing a configuration example of a comparison circuit according to a first modification example of the first embodiment.

[0067] Fig.10 is a circuit diagram showing a configuration example of a comparison circuit according to a second modification example of the first embodiment.

[0068] Fig.11 : is a timing chart showing an example of the operation of the comparison circuit and the data storage unit according to the second modification example of the first embodiment.

[0069] Fig.12is a circuit diagram showing an example of the configuration of a comparison circuit according to a third modification example of the first embodiment.

[0070] Fig.13 is a circuit diagram showing an example of the configuration of a comparison circuit according to a fourth modification example of the first embodiment.

[0071] Fig.14 is a circuit diagram showing an example of the configuration of a comparison circuit according to a fifth modification example of the first embodiment.

[0072] Fig.15A : is a diagram showing an example of a pixel group of a pixel array unit according to a sixth modification example of the first embodiment.

[0073] Fig. 15B It is a graphic Fig.15A A modified diagram of .

[0074] Fig.16 is a block diagram showing an example of the configuration of a timing generator according to the second embodiment.

[0075] Fig.17 is a timing chart showing an example of the operation of the timing generator according to the second embodiment.

[0076] Fig.18 2 is a diagram showing an example of the configuration of a comparison circuit and a data storage unit according to the second embodiment.

[0077] Fig.19 is a circuit diagram showing an example of the configuration of a comparison circuit according to the second embodiment.

[0078] Fig. 20 is a diagram showing an example of the configuration of a data storage unit according to the second embodiment.

[0079] Fig.21 : is a timing chart showing an example of the operations of the comparison circuit and the data storage unit according to the second embodiment.

[0080] Fig. 22 : is a diagram showing an example of a time change of a voltage in a comparison circuit according to the second embodiment.

[0081] Fig.23 : is a circuit diagram showing an example of the configuration of a second circuit according to a first modification example of the second embodiment.

[0082] Fig.24 is a circuit diagram showing an example of the configuration of a second circuit according to a second modification example of the second embodiment.

[0083] Fig.25is a circuit diagram showing an example of the configuration of a second circuit according to a third modification example of the second embodiment.

[0084] Fig.26 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0085] Fig. 27 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging portion. DETAILED DESCRIPTION

[0086] Hereinafter, embodiments of the light detection element, the timing generator, and the AD converter will be described with reference to the accompanying drawings. Next, although the main structures of the light detection element, the timing generator, and the AD converter are mainly described, the light detection element, the timing generator, and the AD converter may also have components and functions that are not shown or described. The following description does not exclude components and functions that are not depicted or described.

[0087] <Schematic Configuration Example of Solid-State Imaging Device>

[0088] Figure 1 A schematic configuration of a solid-state imaging device (light detecting element) according to the present disclosure is shown.

[0089] Figure 1 The solid-state imaging device 1 in the embodiment includes a pixel array unit 22 in which pixels 21 are arranged in a two-dimensional array on a semiconductor substrate 11 by using, for example, silicon (Si) as a semiconductor. A time code transmission unit 23 is also provided in the pixel array unit 22, each of which transfers the time code generated by the time code generation unit 26 to each pixel 21. Then, a pixel driving circuit 24, a D / A converter (DAC) 25, a time code generation unit 26, a vertical driving circuit 27, an output unit 28, and a timing generation circuit 29 are formed around the pixel array unit 22 on the semiconductor substrate 11.

[0090] As will be referenced later Figure 2 As described, each pixel 21 arranged in a two-dimensional array is provided with a pixel circuit 41 and an ADC 42, and the pixel 21 generates a charge signal corresponding to the amount of light received by a light receiving element (e.g., a photodiode) in the pixel, converts the charge signal into an analog pixel signal SIG, and outputs the analog pixel signal SIG.

[0091] The pixel driving circuit 24 drives the pixel circuit 41 in the pixel 21 ( Figure 2). The DAC 25 generates a reference signal (reference voltage signal) REF, and provides the reference signal REF to each pixel 21. The reference signal REF is a ramp signal whose level (voltage) decreases monotonically as time passes. The time code generation unit 26 generates a time code used when each pixel 21 converts the analog pixel signal SIG into a digital signal (AD conversion), and provides the time code to the corresponding time code transmission unit 23. A plurality of time code generation units 26 are provided in the pixel array unit 22, and the same number of time code transmission units 23 as the time code generation units 26 are provided in the pixel array unit 22. That is, the time code generation unit 26 corresponds one-to-one to the time code transmission unit 23 that transmits the generated time code.

[0092] The vertical drive circuit 27 performs control so that the output unit 28 outputs the digital pixel signal SIG generated in the pixel 21 in a predetermined order based on the timing signal supplied from the timing generation circuit 29. The digital pixel signal SIG output from the pixel 21 is output from the output unit 28 to the outside of the solid-state imaging device 1. The output unit 28 performs predetermined digital signal processing such as black level correction processing and correlated double sampling (CDS) processing for correcting the black level as necessary, and then outputs the signal to the outside.

[0093] The timing generation circuit 29 includes a timing generator that generates various timing signals and the like, and supplies the generated various timing signals to the pixel drive circuit 24 , the DAC 25 , the vertical drive circuit 27 , and the like.

[0094] The solid-state imaging device 1 is configured as described above. Note that Figure 1 In the above, it has been described that all the circuits constituting the solid-state imaging device 1 are formed on one semiconductor substrate 11, but as will be described later, by referring to Figure 3A , 3B , 4A and 4B, the circuits constituting the solid-state imaging device 1 can be divided and arranged on a plurality of semiconductor substrates 11.

[0095] <Detailed configuration example of pixels>

[0096] Figure 2 2 is a block diagram showing a detailed configuration example of the pixel 21 .

[0097] The pixel 21 includes a pixel circuit 41 and an AD converter (ADC) 42 .

[0098] The pixel circuit 41 outputs a charge signal corresponding to the amount of received light to the ADC 42 as an analog pixel signal SIG. The ADC 42 converts the analog pixel signal SIG supplied from the pixel circuit 41 into a digital signal.

[0099] The ADC 42 includes a comparison circuit 51 and a data storage unit 52 .

[0100] The comparison circuit 51 compares the reference signal REF supplied from the DAC 25 with the pixel signal SIG and outputs an output signal VCO as a comparison result signal indicating the comparison result. When the reference signal REF and the pixel signal SIG become the same (same voltage), the comparison circuit 51 inverts the output signal VCO.

[0101] The comparison circuit 51 includes a differential input circuit 61 , a voltage conversion circuit 62 , and a positive feedback circuit (PFB) 63 , which will be described in detail later with reference to FIG. 3 .

[0102] In addition to the output signal VCO input from the comparison circuit 51 to the data storage unit 52, a WR signal indicating a pixel signal write operation, an RD signal indicating a pixel signal read operation, and a WORD signal for controlling the read timing of the pixel 21 during the pixel signal read operation are provided from the vertical drive circuit 27. In addition, the time code generated by the time code generation unit 26 is also provided via the time code transmission unit 23.

[0103] The data storage unit 52 includes a latch control circuit 71 that controls a write operation and a read operation of a time code based on a WR signal and an RD signal, and a latch storage unit 72 that stores the time code.

[0104] In the writing operation of the time code, the latch control circuit 71 stores the time code supplied from the time code transmission unit 23 and updated every unit time in the latch storage unit 72 while inputting the Hi (High) output signal VCO from the comparison circuit 51. Then, when the reference signal REF and the pixel signal SIG become the same (voltage) and the output signal VCO supplied from the comparison circuit 51 is inverted to Lo (Low), the writing (updating) of the supplied time code stops, and the time code finally stored in the latch storage unit 72 remains in the latch storage unit 72. The time code stored in the latch storage unit 72 indicates the time when the pixel signal SIG and the reference signal REF become equal to each other, and represents data indicating that the pixel signal SIG has been the reference voltage at that time, that is, the digitized value of the light amount.

[0105] After the scanning of the reference signal REF is completed and the time code is stored in the latch storage unit 72 of all the pixels 21 in the pixel array unit 22, the operation of the pixel 21 is changed from the write operation to the read operation.

[0106] In the time code reading operation, based on the WORD signal that controls the reading timing, the latch control circuit 71 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 72 to the time code transmission unit 23 when the pixel 21 reaches its own reading timing. The time code transmission unit 23 sequentially transmits the supplied time code in the column direction (vertical direction) and supplies the time code to the output unit 28.

[0107] In the following, in order to distinguish from the time code written into the latch storage unit 72 in the time code writing operation, the digitized pixel data is also referred to as AD converted pixel data, which digitized pixel data indicates that the pixel signal SIG is already the reference voltage at that time, and the pixel signal SIG is the inverted time code of the time when the output signal VCO read from the latch storage unit 72 in the time code reading operation is inverted.

[0108] <First Example of Multi-Substrate Configuration>

[0109] Figure 3A This is a conceptual diagram of a solid-state imaging device constructed by stacking two semiconductor substrates. Figure 3B is a diagram showing a schematic configuration in the case where a solid-state imaging device is constituted by stacking two semiconductor substrates.

[0110] Figure 3A A conceptual diagram showing a solid-state imaging device 1 configured by stacking two semiconductor substrates 11 (an upper substrate 11A and a lower substrate 11C) is shown.

[0111] A pixel circuit 41 including at least a photodiode 121 is formed on the upper substrate 11A. At least a data storage unit 52 storing a time code and a time code transmission unit 23 are formed on the lower substrate 11C. The upper substrate 11A and the lower substrate 11C are bonded by metal bonding such as Cu-Cu, for example.

[0112] Figure 3B An example of a circuit configuration formed on each of the upper substrate 11A and the lower substrate 11C is shown.

[0113] The pixel circuit 41 is arranged on the upper substrate 11A. The time code transmission unit 23, the pixel driving circuit 24, the DAC 25, the time code generation unit 26, the vertical driving circuit 27, the output unit 28, the timing generation circuit 29, and the voltage generation unit 30 are formed on the lower substrate 11C.

[0114] The pixel driving signal connection unit 24a arranged on the upper substrate 11A is connected to the pixel driving circuit 24 arranged on the lower substrate 11C. The DAC signal connection unit 25a arranged on the upper substrate 11A is connected to the DAC 25 arranged on the lower substrate 11C. The voltage connection unit 30a arranged on the upper substrate 11A is connected to the voltage generation unit 30 arranged on the lower substrate 11C.

[0115] <Second Example of Multi-Substrate Configuration>

[0116] Figure 4A This is a conceptual diagram of a solid-state imaging device constructed by stacking three semiconductor substrates. Figure 4B : is a diagram showing a schematic configuration in the case where the solid-state imaging device is constituted by stacking three semiconductor substrates.

[0117] Figure 4A A conceptual diagram showing that the solid-state imaging device 1 is constituted by stacking three semiconductor substrates 11 , which are an upper substrate 11A, an intermediate substrate 11B, and a lower substrate 11C.

[0118] On the upper substrate 11A, at least a part of the circuit of the pixel circuit 41 including the photodiode 121 and the comparison circuit 51 is formed. On the lower substrate 11C, at least a part of the data storage unit 52 storing the time code and the time code transmission unit 23 are formed. On the intermediate substrate 11B, the remaining part of the circuit of the comparison circuit 51 not arranged on the upper substrate 11A and the remaining part of the circuit of the data storage unit 52 not arranged on the lower substrate 11C are formed. The upper substrate 11A and the intermediate substrate 11B, and the intermediate substrate 11B and the lower substrate 11C are bonded by metal bonding such as Cu-Cu, for example.

[0119] Figure 4B An example of a circuit configuration formed on each of the upper substrate 11A, the intermediate substrate 11B, and the lower substrate 11C is shown.

[0120] exist Figure 4B In the example of FIG. 1 , the circuits arranged on the upper substrate 11A are Figure 3B The circuits of the upper substrate 11A shown are the same. The DAC 25 is arranged on the middle substrate 11B. The time code transmission unit 23 is provided on the lower substrate 11C.

[0121] The connection unit 28 a arranged on the intermediate substrate 11B is connected to the output unit 28 arranged on the lower substrate 11C.

[0122] <First Embodiment>

[0123] Figure 5is a diagram showing a configuration example of a solid-state imaging device 1 according to a first embodiment. Note that the first embodiment is a configuration example of a solid-state imaging device 1 according to a first embodiment. Figure 4A and 4B The solid-state imaging device is constituted by three semiconductor substrates shown.

[0124] The solid-state imaging device 1 includes a physical signal acquisition unit 31 , a comparison unit 32 , a signal accumulation floating unit 33 , a signal detection unit 34 , a signal amplification unit 35 , a signal control unit 73 , a signal storage unit 74 , and a signal input-output unit 75 .

[0125] The physical signal acquisition unit 31 acquires a physical signal. For example, the physical signal acquisition unit 31 corresponds to the photodiode 121. In this case, the physical signal is a pixel signal.

[0126] The comparison unit 32 compares the physical signal acquired by the physical signal acquisition unit 31 with the reference signal REF. The comparison unit 32 corresponds to the reference signal REF. Figure 6 Transistor 88 is described.

[0127] The signal accumulation floating unit 33 is electrically connected to one end of the comparison unit 32. The signal accumulation floating unit 33 accumulates a signal (charge) in an electrically floating state.

[0128] The signal detection unit 34 detects the physical signal accumulated in the signal accumulation floating unit 33. The signal detection unit 34 corresponds to Figure 6 Transistor 86 of differential input circuit 61 is depicted.

[0129] The signal amplifying unit 35 amplifies the detection result of the signal detecting unit 34. The signal amplifying unit 35 corresponds to Figure 6 The positive feedback circuit 63 is described.

[0130] In the write operation, the signal control unit 73 performs control to store the time code output from the signal input-output unit 75 in the signal storage unit 74 based on the comparison result of the comparison unit 32. In addition, in the read operation, the signal control unit 73 outputs the time code when the comparison result stored in the signal storage unit 74 is inverted to the signal input-output unit 75. The signal control unit 73 corresponds to Figure 2 The latch control circuit 71 is shown.

[0131] The signal storage unit 74 stores the time code. The signal storage unit 74 corresponds to Figure 2 A latch storage unit 72 is shown.

[0132] The signal input / output unit 75 inputs / outputs (transmits) time data. The signal input / output unit 75 corresponds to Figure 2The time code transmission unit 23 is shown.

[0133] Figure 5 A plurality of pixels are shown. At least two or more of the pixels 21 operate in parallel.

[0134] Furthermore, an initialization unit, an individual control unit, a common control unit, and a reference signal generation unit are connected to each pixel 21 .

[0135] Figure 6 : is a circuit diagram showing an example of the configuration of the comparison circuit 51 according to the first embodiment. Figure 6 is a circuit diagram showing the detailed configuration of the differential input circuit 61, the voltage conversion circuit 62, and the positive feedback circuit 63 constituting the comparison circuit 51. Note that Figure 6 A pixel circuit 41 is also shown.

[0136] The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 in the pixel 21 with the reference signal REF output from the DAC 25 , and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

[0137] The differential input circuit 61 includes a transistor 88 constituting the comparison unit 32 , a transistor 89 initializing the signal accumulation floating unit 33 , and a transistor 86 outputting an output signal HVO of the differential input circuit 61 .

[0138] Transistor 88 comprises a negative channel metal oxide semiconductor (NMOS) transistor, and transistors 86 and 89 comprise positive channel metal oxide semiconductor (PMOS) transistors.

[0139] The reference signal REF output from the DAC 25 is input to the source of the transistor 88, and the pixel signal SIG output from the pixel circuit 41 in the pixel 21 is input to the gate of the transistor 88. The drain of the transistor 88 is electrically connected to the signal accumulation floating unit 33. When the gate-source voltage exceeds the threshold voltage, the transistor 88 is turned on, and the charge of the drain of the transistor 88 is extracted to the source of the transistor 88.

[0140] The source of the transistor 89 is connected to the power supply voltage VDD1. The drain of the transistor 88 is connected to the signal accumulation floating unit 33, the drain of the transistor 88, and the gates of the transistor 124 and the transistor 86. The initialization signal xPINI is provided to the gate of the transistor 89.

[0141] When the charge is extracted from the drain of the transistor 88 to the source of the transistor 88, the input voltage to the gate of the transistor 86 decreases, and the transistor 86 is turned on. That is, the signal detection unit 34 operates.

[0142] The voltage conversion circuit 62 includes, for example, an NMOS transistor 91. The drain of the transistor 91 is connected to the drain of the transistor 86 of the differential input circuit 61, the source of the transistor 91 is connected to a predetermined connection point in the positive feedback circuit 63, and the gate of the transistor 91 is connected to the power supply voltage VDD2.

[0143] The transistors 86, 88, and 89 constituting the differential input circuit 61 are circuits that operate at a high voltage up to the power supply voltage VDD1, and the positive feedback circuit 63 is a circuit that operates at a power supply voltage VDD2 lower than the power supply voltage VDD1. The voltage conversion circuit 62 converts the output signal HVO input from the differential input circuit 61 into a low voltage signal (conversion signal) LVI on which the positive feedback circuit 63 can operate, and supplies the signal to the positive feedback circuit 63.

[0144] Based on the conversion signal LVI obtained by converting the output signal HVO from the differential input circuit 61 into a signal corresponding to the power supply voltage VDD2, the positive feedback circuit 63 outputs the comparison result signal which is inverted when the pixel signal SIG is higher than the reference signal REF. In addition, the positive feedback circuit 63 increases the conversion speed of the time when the output signal VCO is outputted as the comparison result signal which is inverted.

[0145] The positive feedback circuit 63 includes three transistors 101 to 103 and a NOR circuit 110. The NOR circuit 110 includes four transistors 106 to 109. Here, the transistors 101, 102, 106, and 107 are formed of PMOS transistors, and the transistors 103, 108, and 109 are formed of NMOS transistors.

[0146] The source of transistor 91, which is the output terminal of voltage conversion circuit 62, is connected to the drain of transistors 102 and 103 and to the gate of transistors 106 and 108. The sources of transistors 101 and 106 are connected to power supply voltage VDD2, the drain of transistor 101 is connected to the source of transistor 102, and the gate of transistor 102 is connected to the drain of transistors 107, 108 and 109, which are also the output terminal of positive feedback circuit 63. The sources of transistors 103, 108 and 109 are connected to a predetermined voltage VSS. Initialization signals INI2 and INI1 are respectively provided to the gates of transistors 101 and 103. FORCE signal is provided to the gates of transistors 107 and 109.

[0147] The transistors 106 to 109 constitute a NOR circuit 110, and a connection point between the drains of the transistors 107 to 109 is an output terminal from which the comparison circuit 51 outputs an output signal VCO.

[0148] Note that Figure 6As shown, a plurality of pixel circuits 41-1 to 41-N are connected to one transistor 88. That is, the transistor 88 is shared by a plurality of photodiodes 121. Similarly, Figure 7 The signal input-output units 75P and 75D shown in FIG. 1 are shared by a plurality of photodiodes 121 .

[0149] <Detailed Configuration Example of Pixel Circuit>

[0150] Reference Figure 6 The detailed configuration of the pixel circuit 41 is described.

[0151] The pixel circuit 41 includes a photodiode (PD) 121 as a photoelectric conversion element, a discharge transistor 122 , a transfer transistor 123 , a reset transistor 124 , a floating diffusion layer (FD) 125 , a gain control transistor 126 , and a capacitor 127 .

[0152] The discharge transistor 122 is used to adjust the exposure process. Specifically, if the discharge transistor 122 is turned on when it is desired to start the exposure period at an optional timing, the charge accumulated in the photodiode 121 is not released until that time point, and therefore, the exposure process starts after the discharge transistor 122 is turned off.

[0153] The transfer transistor 123 transfers the charge generated by the photodiode 121 to the FD 125. The reset transistor 124 and the transistor 127 reset the charge held in the FD 125. The FD 125 is connected to the gate of the transistor 88 of the differential input circuit 61. With this arrangement, the transistor 88 of the differential input circuit 61 also functions as an amplification transistor of the pixel circuit 41.

[0154] The source of the reset transistor 124 is connected to the source of the gain control transistor 126 and the capacitor 127, and the drain of the reset transistor 124 is connected to the drains of the transistors 88 and 89. The reset voltage is set to a reset voltage obtained by setting the gate of the transistor 89 controlled by the initialization signal xPINI to a low voltage to turn on the power supply voltage VDD1.

[0155] A gain control transistor (switching unit) 126 is connected between the transfer transistor 123 and the reset transistor 124. A drive signal FDG is input to the gate of the gain control transistor 126. When the drive signal FDG becomes active, the gain control gate of the gain control transistor 126 becomes conductive, and the FD 125 is electrically connected to the capacitance-adding capacitor (additional capacitance unit) 127. With this arrangement, the sensitivity of signal detection can be controlled.

[0156] Figure 7 is a circuit diagram showing an example of the configuration of the data storage unit 52 according to the first embodiment.

[0157] The data storage unit 52 includes signal control units 73P and 73D, signal storage units 74P and 74D, and signal input and output units 75P and 75D. Figure 7 Also shown are bidirectional buffer circuits 76P, 76D, a signal processing unit 77, and an input-output unit 78.

[0158] The signal control units 73P and 73D correspond to Figure 2 The latch control circuit 71 shown in FIG. The signal storage units 74P and 74D correspond to Figure 2 The latch storage unit 72 shown. The signal input and output units 75P and 75D correspond to Figure 2 The time code transmission unit 23 shown. The signal processing unit 77 and the input and output unit 78 correspond to Figure 4B The output unit 28 shown in FIG.

[0159] Figure 5 The data storage unit 52 shown is composed of a signal control unit 73P, a signal storage unit 74P, and a signal input-output unit 75P for obtaining a reset level during the P phase, and a signal control unit 73D, a signal storage unit 74D, and a signal input-output unit 75D for obtaining a data (pixel signal) level during the D phase (data (pixel signal) acquisition period).

[0160] The signal input-output units 75P and 75D are provided with signals from the corresponding Figure 1 The digital time code of the digital code generating unit 79 of the time code generating unit 26 shown in FIG. 2 is generated, and the signal output from the signal storage units 74P and 74D to the signal input-output units 75P and 75D is output via the signal processing unit 77 and the input-output unit 78.

[0161] The signal input-output units 75P and 75D are, for example, repeaters. In addition, in the signal input-output units 75P and 75D, for example, each of the N shift registers includes a plurality of D flip-flops (DF / F). Note that the signal input-output units 75P and 75D may include tri-state inverters instead of flip-flops.

[0162] Each bidirectional buffer circuit 76P, 76D is connected between the signal storage unit 74P, 74D and the signal input and output unit 75P, 75D. The bidirectional buffer circuits 76P and 76D switch the writing and reading operations of the time code of the signal storage units 74P and 74D based on the writing control signal WR and the reading control signal RD.

[0163] The signal processing unit 77 includes a first signal processing unit 77a and a second signal processing unit 77b.

[0164] The first signal processing unit (CDS unit) 77 a performs a correlated double sampling process of obtaining a difference between a reset level in a P-phase period and a data level in a D-phase period.

[0165] The second signal processing unit (DSP unit) 77b performs digital signal processing on the signal output from the first signal processing unit 77a. The digital signal processing includes, for example, correction of defective pixels having abnormal digital output in addition to image processing such as white balance adjustment of the image, color interpolation (color correction), and compression.

[0166] The input-output unit 78 outputs the signal processed by the second signal processing unit 77 b .

[0167] Notice, Figure 6 and Figure 7 The first embodiment shown shows three semiconductor substrates 11 as Figure 4A and Figure 4B For example, the pixel circuit 41, the reset transistor 124, the FD 125, the gain control transistor 126, the transistor 88, etc. are arranged on the upper substrate 11A. On the intermediate substrate 11B, for example, the transistors 86 and 89 in the differential input circuit 61, the voltage conversion circuit 62, the signal control unit 73P and the signal storage unit 74P in the data storage unit 52, etc. are arranged. On the lower substrate 11C, for example, the signal control unit 73D and the signal storage unit 74D in the data storage unit 52, the signal input and output units 75P and 75D, etc. are arranged.

[0168] <Pixel unit timing diagram>

[0169] Figure 8 1 is a timing chart showing an example of the operations of the comparison circuit 51 and the data storage unit 52 according to the first embodiment.

[0170] Time t1 is the start time of 1V (one vertical scanning period).

[0171] First, at time t2, the reset transistor 124 and the gain control transistor 126 are turned on to reset the charge of the FD 125. Also, at time t2, the initialization signal xPINI supplied to the gate of the transistor 89 is set to Low, and the signal accumulation floating unit 33 is set to an initial state.

[0172] At timing t3, since the initialization signal INI1 supplied to the gate of the transistor 103 is set to Hi, and the initialization signal INI2 is also set to Hi, the positive feedback circuit 63 is set to the initial state. In addition, the FORCE signal input to the gates of the transistors 107 and 109 is set to Low. At this time, since the reference signal REF is greater than the pixel signal SIG, the output signal VCO is Hi. Thereafter, the initialization signals INI1 and INI2 return to Low.

[0173] At time t4, the LATSEL_P signal is set to Hi to enable the signal storage unit 74P. Thereafter, the initialization signal xPINI returns to Hi, the comparison circuit 51 becomes operational, and the comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). As the reference signal REF is scanned, the signal input-output unit 75P transmits the time code. The time code is preferably a Gray code to resist data corruption due to timing offset.

[0174] At time t5, the voltage difference (gate-source voltage) between the voltage of the reference signal REF and the voltage of the pixel signal SIG becomes greater than the threshold voltage of the transistor 88, and the output signal VCO is inverted (switched to Low). As described above, the inversion of the output signal VCO is accelerated by the positive feedback circuit 63. In addition, the signal storage unit 74P of the data storage unit 52 stores the time data (N bits DATA[1] to DATA[N]) at the time point when the output signal VCO is inverted.

[0175] Thereafter, the FORCE signal is set to Hi, the positive feedback circuit 63 of the pixel circuit 41 that is not inverted is forced to be inverted, and a code having a final value is acquired. In addition, the reference signal REF is raised to a predetermined voltage. In addition, by returning the LATSEL_P signal to Low, writing to the signal storage unit 74P is prohibited.

[0176] Subsequently, the circuit is initialized again to obtain the D-phase level (signal level).

[0177] At time t6 , the initialization signal xPINI supplied to the gate of the transistor 89 is set to Low, and the signal accumulation floating unit 33 is set to the initial state.

[0178] At timing t7 , since the initialization signal INI1 is set to Hi and the initialization signal INI2 is also set to Hi, the positive feedback circuit 63 is set to the initial state again.

[0179] At time t8 , the transfer transistor 123 of the pixel circuit 41 is turned on by the transfer signal TX being Hi, and transfers the charge generated by the photodiode 121 to the FD 125 .

[0180] Thereafter, the initialization signals INI1 and INI2 return to Low.

[0181] At time t9, the LATSEL_D signal is set to Hi to enable the signal storage unit 74D. Thereafter, the initialization signal xPINI returns to Hi, the comparison circuit 51 becomes operational, and the comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). As the reference signal REF is scanned, the signal input-output unit 75D transmits the time code. The time code is preferably a Gray code to resist data corruption due to timing offset.

[0182] At time t10, the voltage difference (gate-source voltage) between the voltage of the reference signal REF and the voltage of the pixel signal SIG becomes greater than the threshold voltage of the transistor 88, and the output signal VCO is inverted (switched to Low). The inversion of the output signal VCO is accelerated by the positive feedback circuit 63. In addition, the signal storage unit 74D of the data storage unit 52 stores the time data (N bits DATA[1] to DATA[N]) at the time point when the output signal VCO is inverted.

[0183] Thereafter, the FORCE signal is set to Hi, the positive feedback circuit 63 of the pixel circuit 41 that is not inverted is forced to be inverted, and a code having a final value is acquired. In addition, by returning the LATSEL_D signal to Low, writing to the signal storage unit 74D is prohibited. In addition, the reference signal REF is raised to a predetermined voltage.

[0184] At timings t11, t12, t13, and t14, the WORD_P signal and WARD_D for controlling the read timing become Hi, and an N-bit latch signal Col[n] (n=1 to N) (not shown) is output from the latch control circuit 71 of the data storage unit 52. The data acquired here is the P-phase data of the reset level and the D-phase data of the signal level at the time when the CDS process is performed. Time t15 is the same state as the above-mentioned time t1, and is the next drive of 1V (one vertical scanning cycle).

[0185] According to the driving of the pixel 21 described above, first, the P-phase data (reset level) is acquired, then the D-phase data (signal level) is acquired, and then the P-phase data and the D-phase data are read simultaneously.

[0186] Note that all operations are performed in parallel in the pixel, and when data acquisition (A / D conversion) of each pixel 21 is completed, the data is output to the outside of the pixel array unit 22 through the signal input and output units 75P and 75D. Since the signal input and output units 75P and 75D are provided for each latch group (each P phase and D phase), reading can be performed simultaneously.

[0187] According to the above operation, Figure 6 In the case where N=1 in the pixel 41-N, since one A / D converter is provided for each pixel, each pixel 21 of the pixel array unit 22 of the solid-state imaging device 1 can perform a global shutter operation of resetting all pixels at the same time and exposing all pixels at the same time. Since all pixels can be exposed and read at the same time, it is not necessary to provide a holding unit that is usually provided in a pixel and configured to hold a charge until the charge is read. In addition, in the configuration of the pixel 21, a selection transistor or the like for selecting a pixel that outputs a pixel signal SIG, which is necessary in a column parallel reading type solid-state imaging device, is also unnecessary.

[0188] In reference Figure 8 In the driving of the pixel 21 described above, the discharge transistor 122 is always controlled to be turned off. Figure 8 As indicated by the dotted line in , an optional exposure period can also be set by setting the discharge signal OFG to Hi, temporarily turning on the discharge transistor 122, and then turning off the discharge transistor at a desired time.

[0189] As described above, according to the first embodiment, the transistor 88 as the comparison unit 32 compares the pixel signal SIG as the physical signal input to the gate with the reference signal REF supplied to the source. When the gate-source voltage of the transistor 88 becomes greater than the threshold of the transistor 88, the transistor 88 is turned on, and the charge on the drain side of the transistor 88 is extracted to the source side. As the charge is extracted, the input voltage of the gate of the transistor 86 as the signal detection unit 34 decreases. With this arrangement, the transistor 86 as the signal detection unit 34 is turned on.

[0190] In addition, in the first embodiment, two signal input and output units 75P and 75D are provided. With this arrangement, the reset level during the P phase and the data level during the D phase can be read simultaneously, and the speed can be increased. In addition, the P phase and the D phase can be controlled separately, and the writing and circuit can be simplified.

[0191] Note that, for example, the signal input-output units 75P and 75D may be separately arranged on the intermediate substrate 11B and the lower substrate 11C as different substrates. However, in the case where the signal input-output units 75P and 75D are arranged on the same substrate, efficiency can be improved.

[0192] In addition, in the first embodiment, the signal control unit 73P and the signal storage unit 74P, and the signal control unit 73D and the signal storage unit 74D are arranged on the intermediate substrate 11B and the lower substrate 11C, which are different substrates from each other. However, the signal control unit 73P and the signal storage unit 74P, and the signal control unit 73D and the signal storage unit 74D may be arranged on the same substrate.

[0193] <First Comparative Example>

[0194] As a first comparative example, a case where the differential input circuit 61 includes a differential pair of transistors will be described.

[0195] In the first comparative example, the pixel signal SIG and the reference signal REF are provided to the differential pair transistors (eg, Fig.19 In this case, in order to operate the differential input circuit 61, a current source (for example, Fig.19 Transistor 85 shown in ).

[0196] On the other hand, in the first embodiment, no current source is provided, and it is not necessary to flow a constant current. With this arrangement, power consumption can be reduced.

[0197] <Second Comparative Example>

[0198] As a second comparative example, a case where the ADC 42 is arranged outside the pixel array unit 22 will be described.

[0199] In the second comparative example, AD conversion is performed for each column (pixel column) having a plurality of pixels 21. A vertical signal line connecting a plurality of pixels and a comparison circuit (column processing unit) is provided for each pixel column. As the number of pixels in the pixel array unit 22 increases, the vertical signal line becomes longer. When the charge is extracted from the drain of the transistor 88 to the source, tailing may occur due to the influence of the parasitic capacitance corresponding to the distance of the vertical signal line.

[0200] On the other hand, in the first embodiment, the ADC 42 is arranged in the pixel array unit 22. In this case, since AD ​​conversion is performed for each pixel 21 and the transistor 86 as the signal detection unit 34 is arranged in the pixel array unit 22, wiring through which charge is extracted is arranged in the pixel 21. The distance of the wiring from which charge is extracted is, for example, the distance from the drain of the transistor 88 to the gate of the transistor 86. Therefore, the wiring distance to the signal detection unit 34 can be shortened, and the occurrence of tailing due to parasitic capacitance can be suppressed.

[0201] <First Modification of First Embodiment>

[0202] Fig. 9 1 is a circuit diagram showing an example of the configuration of a comparison circuit 51 according to a first modification of the first embodiment. The first modification of the first embodiment is different from the first embodiment in that a capacitor 90 is provided.

[0203] The solid-state imaging device 1 further includes a capacitor 90. The capacitor 90 is connected between the DAC 25 and the source of the transistor 88. One end of the capacitor 90 is connected to the DAC 25. The other end of the capacitor 90 is connected to the source of the transistor 88.

[0204] Other configurations of the solid-state imaging device 1 in the first modification of the first embodiment may be similar to those of the first embodiment. In addition, the operations of the comparison circuit 51 and the data storage unit 52 according to the first modification of the first embodiment are substantially the same as those of the first modification.

[0205] Assuming that the source capacitance of transistor 88 is Cc and the remaining parasitic capacitance is Cs, the capacitance Ctotal visible from the outside (DAC 25 ) is expressed by Expression 1.

[0206] Ctotal = Cc × Cs / (Cc + Cs) (Expression 1)

[0207] Therefore, the capacitance Ctotal appears smaller from the outside due to the voltage division. With this arrangement, the influence of the reversal of the capacitance variation can be reduced. For example, in the case where there are pixels that have not yet been inverted around the pre-inverted pixels, there is a possibility that the voltage of the reference signal REF is affected by the distortion caused by the fluctuation of the load capacitance, and the AD conversion originally expected cannot be performed correctly, and the input / output characteristics are distorted. This phenomenon is generally referred to as tailing. By providing capacitor 90, tailing can be reduced.

[0208] Furthermore, by providing the capacitor 90 , the charge in the signal accumulation floating unit 33 does not directly flow into the ADC 25 , and the movement of the charge is restricted to achieve low power consumption.

[0209] As in the first modification of the first embodiment, a capacitor 90 may be provided. In this case as well, the same effects as those of the first embodiment can be obtained.

[0210] <Second Modification of First Embodiment>

[0211] Fig.10 2 is a circuit diagram showing an example of the configuration of a comparison circuit 51 according to a second modification of the first embodiment. The second modification of the first embodiment is different from the first modification of the first embodiment in that a transistor 92 as a connection unit is provided.

[0212] In the case where the capacitor 90 remains connected to the source of the transistor 88 as in the first embodiment, for example, there is a possibility that after the transistor 88 is turned on once, the source voltage of the transistor 88 does not immediately return to the initial state due to the capacitor 90. At the time of initialization, the charge at the node is discharged with a resistance of the time constant when the transistor 88 is turned off. Because the transistor 88 is in a high resistance state, the initialization requires a settling time. This is because before the reference signal REF is supplied to the source of the transistor 88 again, it is necessary to wait until the source voltage returns.

[0213] Therefore, the solid-state imaging device 1 further includes a transistor 92 as a connection unit (initialization unit). The transistor 92 is composed of, for example, a PMOS transistor.

[0214] Transistor 92 is connected between the drain of transistor 88 and the source of transistor 88. The drain of transistor 92 is connected to the source of transistor 88 and capacitor 90. The source of the transistor is connected to the drain of transistor 88, the drain of transistor 89 and the gate of transistor 86. The initialization signal xPINI2 is provided to the gate of transistor 92.

[0215] The transistor 92 as a connection unit (initialization unit) is turned on to electrically connect the source of the transistor 88 and the drain of the transistor 88 at a predetermined timing. Note that the predetermined timing is, for example, Fig.11 The timing when the initialization signal xPINI2 shown in becomes Low. That is, the transistor 92 forcibly initializes the source voltage of the transistor 88. With this configuration, the charge moved to the source of the transistor 88 when the transistor 88 is turned on can be forcibly returned to the drain of the transistor 88. Therefore, the initialization settling time can be shortened.

[0216] Furthermore, by performing initialization using the initialization signal xPINI2 before starting the D phase, but by setting the reference signal REF to the same voltage as the voltage at the start of the P phase, the total charge amount of the signal accumulation floating unit 33 and the source of the transistor 88 returns to the initial value and becomes the same. Therefore, it is not necessary to control the initialization signal xPINI again in the D phase period as in the P phase period. Therefore, the influence of the kT / C noise that occurs in the case of controlling the initialization signal xPINI again is reduced. Therefore, the deterioration of the signal quality can be suppressed, that is, the deterioration of the image quality can be suppressed.

[0217] Other configurations of the solid-state imaging device 1 in the first modification example of the first embodiment may be similar to those of the first embodiment.

[0218] Fig.11: is a timing chart showing an example of the operations of the comparison circuit 51 and the data storage unit 52 according to the second modification example of the first embodiment.

[0219] Note that the operations other than the initialization signal xPINI2 supplied to the gate of the transistor 92 and the initialization signal xPINI before the start of the D phase are the same as those described with reference to the first embodiment. Figure 8 The operation is similar to .

[0220] At time t2, the initialization signal xPINI2 supplied to the gate of transistor 92 is set to Low, and the source of transistor 88 is set to the initial state. With this arrangement, the source voltage of transistor 88 is forcibly initialized. After time t4, the initialization signal xPINI2 returns to Hi before scanning of the reference signal REF.

[0221] At time t6, the initialization signal xPINI2 supplied to the gate of transistor 92 is set to Low, and the source of transistor 88 is set to the initial state. With this arrangement, the source voltage of transistor 88 is forcibly initialized. After time t9, the initialization signal xPINI2 returns to Hi before scanning of the reference signal REF.

[0222] As in the second modification of the first embodiment, a transistor 92 may be provided. In this case as well, the same effects as those of the first embodiment can be obtained.

[0223] <Third Modification of First Embodiment>

[0224] Fig.12 1 is a circuit diagram showing an example of the configuration of the comparison circuit 51 according to the third modification of the first embodiment. The third modification of the first embodiment is different from the first embodiment in that the output of the NOR circuit 110 is input to the gate of the transistor 91 of the voltage conversion circuit 62 instead of the power supply voltage VDD2.

[0225] The gate of the transistor 91 is connected to the output terminal of the NOR circuit 110. The output signal VCO which is the output of the NOR circuit 110 is supplied to the gate of the transistor 91. With this arrangement, in the case where the output signal VCO is inverted, the transistor 91 is turned off, and the current from the differential input circuit 61 can be cut off. In addition, in the case where the power supply voltage VDD2 rises earlier than the power supply voltage VDD1 by power-on, the rush current from the power supply voltage VDD2 to the power supply voltage VDD1 can be suppressed.

[0226] As in the third variation of the first embodiment, the connection of the gate of the transistor 91 of the voltage conversion circuit 62 can be changed. In this case, the same effect as the first embodiment can be obtained. In addition, the third variation of the first embodiment can also be combined with the first variation or the second variation of the first embodiment.

[0227] <Fourth Modification of First Embodiment>

[0228] Fig.13 1 is a circuit diagram showing an example of the configuration of a comparison circuit 51 according to a fourth modification of the first embodiment. The fourth modification of the first embodiment is different from the first embodiment in that another power supply voltage is input to the gate of the transistor 91 of the voltage conversion circuit 62.

[0229] The power supply voltage VDD3 (bias voltage VBIAS) is supplied to the gate of the transistor 91. The bias voltage VBIAS may be any voltage as long as the voltage is converted into a voltage that does not damage each transistor of the positive feedback circuit 63 operating at a constant voltage.

[0230] As in the fourth variation of the first embodiment, the connection of the gate of the transistor 91 of the voltage conversion circuit 62 may be changed. In this case, the same effect as the first embodiment can be obtained. In addition, the fourth variation of the first embodiment may be combined with the first variation or the second variation of the first embodiment.

[0231] <Fifth Modification of First Embodiment>

[0232] Fig.14 2 is a circuit diagram showing an example of the configuration of a comparison circuit 51 according to a fifth modification of the first embodiment. The fifth modification of the first embodiment is different from the first embodiment in that the voltage conversion circuit 62 is not provided.

[0233] In the case where the power supply voltage VDD1 and the power supply voltage VDD2 are close to each other, it is possible to omit the voltage conversion circuit 62. With this arrangement, the number of required transistors can be reduced, and the required area can be reduced.

[0234] Note that, in consideration of the influence of noise as a node, it is desirable that the power supply voltage VDD1 and the power supply voltage VDD2 are different voltages. However, the power supply voltage VDD1 and the power supply voltage VDD2 may be the same voltage.

[0235] In addition, Fig.14 In the configuration shown, in order to make the pixel have the same characteristics as when using a high power supply, it is necessary to adjust the operating point, such as setting the substrate potential (Sub potential) on the pixel side to a large negative value.

[0236] As in the fifth variation of the first embodiment, the voltage conversion circuit 62 may not be provided. In this case, the same effect as the first embodiment can be obtained. In addition, the fifth variation of the first embodiment may be combined with the first variation or the second variation of the first embodiment.

[0237] <Sixth Modification of First Embodiment>

[0238] Fig.15A : is a diagram showing an example of a pixel group of the pixel array unit 22 according to the sixth modification of the first embodiment. Fig.15A An example is shown in which a first pixel group PXG1 indicated by a dotted line, a second pixel group PXG2 indicated by a thick line, and a remaining third pixel group PXG3 indicated by a thin line are provided in a pixel array unit 22 having eight pixels in the horizontal direction and six pixels in the vertical direction. The number of pixels in the pixel array unit 22 and the number of pixel groups provided in the pixel array unit 22 are optional.

[0239] The sixth modification of the first embodiment is different from the first embodiment in that a write enable signal is individually provided for each pixel group, and whether to update pixel data in the latch storage unit 72 of each pixel is set for each pixel group.

[0240] Instead of the FORCE signal, connect any one of the multiple enable signals WE1 to WE3 to Figure 6 The gates of the transistors 107 and 109 shown in FIG. 2 are connected to the gates of the transistors 107 and 109 shown in FIG. As will be described later, each pixel in the pixel array unit 22 belongs to any one of a plurality of pixel groups, and each pixel group has a write enable signal, respectively. When the corresponding write enable signal is in an enabled state (e.g., a low level), the positive feedback circuit 63 of each pixel outputs a valid VCO signal. Therefore, in the case where the corresponding write enable signal is not in an enabled state, the valid VCO signal is not output from the positive feedback circuit 63, and therefore, in a subsequent stage, the time code corresponding to the pixel data is not stored in the latch storage unit 72.

[0241] The latch storage unit (storage unit) 72 stores data corresponding to a physical signal (physical quantity) detected by the pixels 21 in each pixel group.

[0242] For example, the storage control unit included in the pixel driving circuit 24 or the vertical driving circuit 27 performs control to store data in the latch storage unit 72 and, at the same time, controls whether to update the data stored in the latch storage unit 72 for each pixel group. The storage control unit provides a write enable signal.

[0243] The first pixel group PXG1 includes a pixel group including three pixels, each pixel group at the left and right ends in the horizontal direction, and the pixel groups are arranged at intervals of two pixels in the vertical direction. The second pixel group PXG2 includes a total of four pixels, and the pixels are arranged at intervals of four pixels in the horizontal direction and at intervals of two pixels in the vertical direction. The third pixel group PXG3 includes pixels in the pixel array unit 22 except the first pixel group PXG1 and the second pixel group PXG2.

[0244] For example, each pixel in the first pixel group PXG1 is a pixel for live view (moving image). Because live view does not require resolution as high as that of still images, the first pixel group PXG1 including partial pixels obtained by thinning out pixels for still images is used.

[0245] Each pixel in the second pixel group PXG2 is a pixel for image plane phase difference detection. Each pixel is divided into two, or half of each pixel is shielded from light, and a phase difference is detected from a light signal captured for each divided area, and is used to perform, for example, focus adjustment.

[0246] For example, each pixel in the third pixel group PXG3 is used to capture a still image. In a still image, the roughness of the image is easily noticed. Therefore, it is desirable that the still image has a larger number of pixels than the first pixel group PXG1 and the second pixel group PXG2.

[0247] In this embodiment, if Fig.15A As shown, a first write enable signal WE1 that allows a pixel signal of each pixel in the first pixel group PXG1 to be stored in the latch storage unit 72, a second write enable signal WE2 that allows a pixel signal of each pixel in the second pixel group PXG2 to be stored in the latch storage unit 72, and a third write enable signal WE3 that allows a pixel signal of each pixel in the third pixel group PXG3 to be stored in the latch storage unit 72 are set. For each pixel, one of the first to third write enable signals WE1 to WE3 is connected to Figure 6 The gates of the transistors 107 and 109 of the positive feedback circuit 63 in FIG. The type of the write enable signal connected to the gates of the transistors 107 and 109 in the pixels belonging to the same pixel group is the same.

[0248] When the first write enable signal WE1 becomes an enable state (e.g., a high level), the pixel data of all pixels in the first pixel group PXG1 (to be exact, according to the time code of the pixel signal) are stored in the corresponding latch storage unit 72. With this arrangement, the pixel data pre-stored in the latch storage unit 72 is updated.

[0249] Similarly, when the second write enable signal WE2 becomes enabled (eg, high level), pixel data of all pixels in the second pixel group PXG2 are stored in the corresponding latch storage units 72. With this arrangement, pixel data previously stored in the latch storage units 72 are updated.

[0250] Similarly, when the third write enable signal WE3 becomes enabled (eg, high level), pixel data of all pixels in the third pixel group PXG3 are stored in the corresponding latch storage units 72. With this arrangement, pixel data pre-stored in the latch storage units 72 are updated.

[0251] If the pixel data stored in the latch storage unit 72 of each pixel in the first pixel group PXG1, the second pixel group PXG2, and the third pixel group PXG3 can be transmitted to the output unit 28 within one frame period, the pixel data in the latch storage unit 72 of each pixel becomes unnecessary in the next frame period, and thus, new pixel data can be stored in the corresponding latch storage unit 72. However, in an area having a large number of pixels like the third pixel group PXG3, there is a possibility that the pixel data of all pixels cannot be transmitted to the output unit 28 within one frame period. Specifically, in a case where the number of pixels in the pixel array unit 22 is large and the number of pixels in the third pixel group PXG3 is also large, there is a possibility that the pixel data is not completely transmitted from the latch storage unit 72 to the output unit 28 of each pixel in the third pixel group PXG3 within one frame period. Alternatively, even in a case where the signal reading time of the pixels in the third pixel group PXG3 is long, there is a possibility that the transmission of all pixel data to the output unit 28 is completed within one frame period.

[0252] Therefore, in the present embodiment, a write enable signal is individually provided for each pixel group, and whether to update the pixel data in the latch storage unit 72 of each pixel can be set for each pixel group.

[0253] exist Fig.15A , the control wiring of the first write enable signal WE1, the control wiring of the second write enable signal WE2, and the control wiring of the third write enable signal WE3 are arranged on the pixels to which write permission is given, and are not arranged on the pixels to which write permission is given as much as possible. Fig.15A A contact indicated by a black circle on each control wiring in indicates a pixel controlled by a corresponding write enable signal. Any one of the first to third write enable signals WE1 to WE3 is connected to each pixel in the pixel array unit 22.

[0254] Through Fig.15AThe arrangement of three control wirings as shown has the advantage that the arrangement area of ​​the control wirings can be reduced and the aperture ratio of each pixel can be improved, but the arrangement density of the control wirings increases or decreases depending on the position in the pixel group, and the wiring density does not become uniform. This may cause changes in pixel characteristics, such as changes in sensitivity.

[0255] Fig. 15B It is shown Fig.15A Schematic diagram of a modified example of . Fig. 15B FIG. 2 shows an example in which three control wirings are arranged on all pixels in the pixel array unit 22. Fig. 15B In the case where three control wirings are arranged in all pixels in the pixel array unit 22, the arrangement density of the control wirings becomes uniform, and the aperture ratio and circuit characteristics of each pixel can be balanced.

[0256] The reading order of pixel data of each pixel in each pixel group in the pixel array unit 22 may be the same, or may be different for each pixel group.

[0257] As in the sixth variation of the first embodiment, a write enable signal may be set separately for each pixel group, and whether to update the pixel data in the latch storage unit 72 of each pixel may be set for each pixel group. In this case, the same effect as that of the first embodiment can be obtained. In addition, the fifth variation of the first embodiment may be combined with the first to fifth variations of the first embodiment.

[0258] <Second Embodiment>

[0259] Fig.16 1 is a block diagram showing an example of the configuration of a timing generator 900 according to the second embodiment. The timing generator is used, for example, in a comparison circuit 51, as will be described later. Fig.18 However, the present invention is not limited to the comparison circuit 51 and can be used for other circuits.

[0260] The timing generator 900 includes a first circuit 910 , a second circuit 920 , and an operation circuit 930 .

[0261] The first circuit 910 receives an input signal. The first circuit 910 generates and outputs a first output signal and an activation signal based on the input signal. The first output signal is delayed from the inverted timing of the input signal. The activation signal is a signal for activating the second circuit 920.

[0262] The second circuit 920 is activated based on the activation signal, and generates and outputs a second output signal.

[0263] The operation circuit 930 generates and outputs a third output signal by calculating the first output signal and the second output signal. The operation circuit performs, for example, a logical operation of the first output signal and the second output signal.

[0264] Fig.17 : is a timing chart showing an example of the operation of the timing generator 900 according to the second embodiment.

[0265] In the initial state, the input signal is in the Hi state.

[0266] First, at time t21, the input signal becomes Lo. With this arrangement, the first circuit 910 receives the input signal and starts generating the activation signal and the first output signal.

[0267] Next, at time t22, the activation signal and the first output signal become Hi. The first circuit 910 outputs the first timing ( Fig.17 At time t22 shown in FIG. 1 , the first output signal and the activation signal are inverted. In addition, the second circuit 920 is activated by the activation signal and starts to generate the second output signal.

[0268] Next, at time t23, the second output signal becomes Hi. The second circuit 920 outputs a second timing signal ( Fig.17 The second output signal is inverted at time t23).

[0269] In addition, the operation circuit 930 performs a logic operation based on the first output signal and the second output signal. At time t22, the first output signal becomes Hi while the second output signal remains in the Low state, and the third output signal becomes Hi. In addition, at time t23, the first output signal remains in the Hi state while the second output signal becomes Hi, and the third output signal becomes Low. That is, the operation circuit 930 outputs the first timing ( Fig.17 The time t22 shown) and the second timing ( Fig.17 The third output signal is inverted at time t23).

[0270] like Fig.17 As shown, a pulse third output signal in the Hi state is generated in the time period from time t22 to time t23. That is, the timing generator 900 generates a third output signal with a short pulse width at a timing delayed according to the inverted timing of the input signal, and the short pulse width rises in the period when the second output signal is delayed from the first output signal.

[0271] Fig.18 2 is a diagram showing an example of the configuration of a comparison circuit 51 and a data storage unit 52 according to the second embodiment.

[0272] The comparison circuit 51 includes a first circuit 910, a second circuit 920, and an operation circuit 930. Fig.18 In the example shown, the pixel circuit 41 and the signal input and output unit 75 are also shown. Fig.18 , the voltage conversion circuit 62 is omitted.

[0273] The pixel circuit 41 includes a photodiode 121 as a photoelectric conversion element. Note that the pixel circuit 41 may be a circuit including a physical quantity detection unit that detects a physical quantity.

[0274] The storage circuit 52 corresponds to Figure 2 The data storage unit 52 in.

[0275] The input signal is the output signal HVO of the differential input circuit 61. Therefore, Fig.17 The inversion timing of the input signal shown is the timing at which the physical signal detected by the physical quantity detection unit and the reference signal REF become substantially the same.

[0276] Fig.19 : is a circuit diagram showing an example of the configuration of the comparison circuit 51 according to the second embodiment.

[0277] The differential input circuit 61 includes transistors 81 and 82 forming a differential pair, transistors 83 and 84 constituting a current mirror, a transistor 85 as a constant current source providing a current IB according to an input bias current Vb, and a transistor 86 outputting an output signal HVO of the differential input circuit 61.

[0278] The transistors 81 , 82 , and 85 are composed of NMOS transistors, and the transistors 83 , 84 , and 86 are composed of PMOS transistors.

[0279] The first circuit 910 is a first positive feedback circuit (PFB). The first circuit 910 includes transistors 911 and 912 and an inverter 913. The transistors 911 and 912 are composed of PMOS transistors.

[0280] The source of the transistor 91, which is the output terminal of the voltage conversion circuit 62, is connected to the drain of the transistor 912 and one end of the inverter 913. The source of the transistor 911 is connected to the power supply voltage node VDD2. The drain of the transistor 911 is connected to the source of the transistor 912. The other end of the inverter 913, which is the output terminal of the first circuit 910, is connected to the gate of the transistor 912 and one input terminal of the operation circuit 930. The initialization signal INI2 is provided to the gate of the transistor 911.

[0281] The second circuit 920 is a second positive feedback circuit (PFB') and is connected in series to the first circuit 910 (first positive feedback circuit). That is, the first circuit 910 and the second circuit 920 include a first positive feedback circuit and a second positive feedback circuit connected in series. The second circuit 920 includes transistors 921, 922, and 923 and an inverter 924. The transistor 923 is composed of a PMOS transistor, and the transistors 921 and 922 are composed of NMOS transistors.

[0282] The source of transistor 91 as the output terminal of voltage conversion circuit 62 is connected to the drain of transistor 921 and the source of transistor 923. The source of transistor 921 as the output terminal of second circuit 920 is connected to the drain of transistor 922, the drain of transistor 923, one end of inverter 924 and the other input terminal of operation circuit 930. The source of transistor 922 is connected to low voltage VSS (e.g., ground). The other end of inverter 924 is connected to the gate of transistor 923. Initialization signal INI3 is provided to the gate of transistor 921. Initialization signal INI is provided to the gate of transistor 922.

[0283] The transistor 921 functions as an activation signal passing unit that passes an activation signal from the first circuit 910 as a leakage current.

[0284] The operation circuit 930 includes a NOR circuit 931 , a NOR circuit 932 , and an inverter 933 .

[0285] One input terminal of the NOR circuit 931 is connected to the output terminal of the first circuit 910. The other input terminal of the NOR circuit 931 is connected to the output terminal of the second circuit 920. The output terminal of the NOR circuit 931 is connected to one input terminal of the NOR circuit 932. The other input terminal of the NOR circuit 932 is provided with a FORCEVCO signal. The output terminal of the NOR circuit 932 is connected to one terminal of the inverter 933. The output signal VCO of the operation circuit 930 is output from the other terminal of the inverter 933.

[0286] Fig.19 The voltage Vpfbl is, for example, the voltage of the wiring at one end of the inverter 913. Fig.19 The voltage Vpfb2 in φpfb2 is, for example, the voltage of the wiring at one end of the inverter 924.

[0287] Fig. 20 : is a diagram showing an example of the configuration of the data storage unit 52 according to the second embodiment.

[0288] The output signal VCO of the operation circuit 930 is connected to one input terminal of each signal control unit 73P and 73D as a multiplexer (MUX). The WORD signal is provided to the other input terminal of each signal control unit 73P and 73D. The outputs of the signal control units 73P and 73D are provided to the signal storage units 74P and 74D, respectively.

[0289] In the write operation, the signal control units 73P and 73D perform control to store the time code output from the signal input-output unit 75 in the signal storage units 74P and 74D based on the output signal VCO (third output signal) of the operation circuit 930. In addition, in the read operation, the signal control units 73P and 73D output the time code of the time inverted (converted to Low) by the output signal VCO (third output signal) of the operation circuit 930 to the signal input-output unit 75, and the time code is stored in the signal storage units 74P and 74D (see Fig. 22 ).

[0290] The signal input-output unit 75 as a repeater performs writing to the signal storage units 74P and 74D via the local bit line (LBL).

[0291] When the switch T (the switch Tp and Td) is closed, writing is performed in the signal storage units 74P and 74D, and when the switch T (the switch Tp and Td) is opened, data in the signal storage units 74P and 74D is determined.

[0292] Fig.21 2 is a timing chart showing an example of the operations of the comparison circuit 51 and the data storage unit 52 according to the second embodiment.

[0293] Time t31 is the start time of 1V (vertical scanning period).

[0294] First, at time t32 , the reset transistor 124 and the gain control transistor 126 are turned on to reset the charge of the FD 125 .

[0295] At timing t33 ​​, the reference signal REF is raised to a predetermined voltage.

[0296] At timing t34, the initialization signals INI, INI2, and INI3 are set to Hi, and the timing generator 900 is set to the initial state. After the initialization signals INI, INI2, and INI3 return to Low, the comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). When the reference signal REF is scanned, the signal input and output unit 75 transmits the time code.

[0297] Note that the voltage Vpfb1 becomes the low voltage VSS, ie, the ground voltage, by the initialization signals INI and INI3. Therefore, in a period in which the second circuit 920 is not activated, the second circuit 920 is the second power supply voltage (low voltage VSS) of the first circuit 910.

[0298] At time t35, when it is determined that the reference signal REF and the pixel signal SIG have become identical, the output signal VCO is inverted (switched to Hi). The signal control unit 73P performs the following operations at the first timing ( Fig.21 The time code is stored in the signal storage unit 74P starting from the time t35 shown.

[0299] At time t36, the output signal VCO is inverted (switched to Low). When the output signal VCO is inverted, the time data (N bits DATA[1] to DATA[N]) when the output signal VCO is inverted is stored in the signal storage unit 74P of the data storage unit 52. The signal control unit 73P stores the signal at the second timing ( Fig.21 The timing t36 shown stops storing the time code into the signal storage unit 74P.

[0300] Reference Fig. 22 A detailed operation in the period from time t35 to time t35 is described.

[0301] Fig. 22 is a diagram showing an example of a time change of a voltage in the comparison circuit 51 according to the second embodiment. Note that, Fig. 22 Too Fig.21 An enlarged view of the vicinity of time t35 and t36 in FIG.

[0302] Fig. 22 The upper part of is a graph showing the time change of the voltage Vpfb1. Fig. 22 The middle part of is a graph showing the temporal change of voltage Vpfb2. Fig. 22 The lower part is a graph showing the temporal variation of the output signal VCO. Fig. 22 The horizontal axis of the graph indicates time. Fig. 22 The vertical axis in the graph represents voltage.

[0303] like Fig. 22 As shown, before time t35, the output signal HVO is inverted (transitioned to Hi), current flows to the first circuit 910, and the voltage Vpfb1 gradually increases. At timing t35, the voltage Vpfb1 exceeds the threshold of the inverter 913. This turns on the transistor 912. As a result, the voltage Vpfb1 rises rapidly due to positive feedback and becomes the voltage VDD2. Since the voltage Vpfb1 is Hi and the voltage Vpfb2 remains Low, the output signal VCO is inverted (transitioned to Hi) at time t35.

[0304] In addition, after time t35, the first circuit 910 is used as a power supply for the second circuit 920. Thereafter, in the off state, the current flowing from the differential input circuit 61 to the first circuit 910 flows to the second circuit 920 via the transistor 921 as a leakage current. This causes charge to accumulate in the second circuit 920, and the voltage Vpfb2 gradually rises. Therefore, the activation signal is the first power supply voltage (voltage VDD2) of the second circuit.

[0305] Note that the current charge from the voltage Vpfv1 to the voltage Vpfb2 is determined by the leakage of the transistor 921. Therefore, the on-voltage is controlled by the Hi voltage of the initialization signal INI3, and the low voltage of the initialization signal xINI3 is controlled to be the off-voltage with adjusted leakage.

[0306] At time t36, the voltage Vpfb2 exceeds the threshold of the inverter 924. This turns on the transistor 923. That is, one end of the inverter 924 is electrically connected to one end of the inverter 913 of the first circuit 910 serving as a power source. Therefore, the voltage Vpfb2 rises rapidly due to positive feedback and becomes the voltage VDD2. Since both the voltages Vpfb1 and Vpfb2 are Hi, the output signal VCO is inverted (converted to Low) at time t36.

[0307] As in Fig.17 In the third output signal shown in Fig. 22 The output signal VCO shown in has a short pulse width in the period from time t35 to time t36.

[0308] Afterwards, if Fig.21 As shown, at time t37, the reference signal REF is raised to a predetermined voltage.

[0309] Subsequently, the circuit is initialized again to obtain the D-phase level (signal level).

[0310] At time t38 , the transfer transistor 123 of the pixel circuit 41 is turned on by the transfer signal TX at Hi, and the charge generated by the photodiode 121 is transferred to the FD 125 .

[0311] At timing t39, the initialization signals INI, INI2, and INI3 are set to Hi, and the timing generator 900 is set to the initial state. Thereafter, after the initialization signals INI, INI2, and INI3 return to Low, the comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). When the reference signal REF is scanned, the signal input and output unit 75 transmits the time code.

[0312] At time t40, when it is determined that the reference signal REF and the pixel signal SIG have become identical, the output signal VCO is inverted (switched to Hi). Note that the operation at time t40 is the same as that at time t41. Fig. 22 The operation at time t35 shown is basically the same. The signal control unit 73D performs the following operations at the first timing ( Fig.21 The time code is stored in the signal storage unit 74D starting from the time t40 shown.

[0313] At time t41, the output signal VCO is inverted (switched to Low). When the output signal VCO is inverted, the time data (N bits DATA[1] to DATA[N]) when the output signal VCO is inverted is stored in the signal storage unit 74D of the data storage unit 52. Note that the operation at time t41 is the same as that at time t41. Fig. 22 The operation at time t36 shown is basically the same. The signal control unit 73D performs the following operations at the second timing ( Fig.21 At time t41 shown, storage of the time code into the signal storage unit 74D is stopped.

[0314] At time t42 and t43, the WORD signal for controlling the read timing becomes Hi, and an N-bit latch signal Col[n] (n=1 to N) (not shown) is output from the latch control circuit 71 of the data storage unit 52. The data acquired here is the P-phase data of the reset level and the D-phase data of the signal level at the time when the CDS process is performed.

[0315] In addition, at each of time t42 and t43, the LATSEL[0] signal becomes Hi, and thereafter, the LATSEL[1] signal becomes Hi. The reset level is acquired by the LATSEL[0] signal, and the signal level is acquired by LATSEL[1]. The reset level and the signal level are alternately output at the read timing.

[0316] Time t44 is the same state as the above-mentioned time t31, and is the next drive of 1V (one vertical scanning period).

[0317] As described above, according to the second embodiment, the first circuit 910 outputs a first output signal obtained by delaying the inverted timing of an input signal based on an input signal and an activation signal for activating the second circuit 920. With this arrangement, the output of the second circuit 920 can be delayed from the output of the first circuit 910. Therefore, a pulse signal can be generated. Power consumption can be suppressed by performing latch control using the generated pulse signal.

[0318] <Third Comparative Example>

[0319] As a third comparative example, a case where a delay signal is not generated will be described.

[0320] In the third comparative example, Fig.21 As shown by the dotted line of the output signal VCO shown in , the output signal VCO is maintained in the Hi state. In this case, when the output signal VCO is Hi, the signal control units 73P and 73D continuously write the signal flowing through the signal input-output unit 75 into the latch. In this case, as the inverters in the signal storage units 74P and 74D continue to operate, power consumption increases.

[0321] On the other hand, in the second embodiment, the signal control units 73P and 73D perform writing to the signal storage units 74P and 74D within a short period of time when the output signal VCO of the operation circuit 930 becomes Hi. That is, in the signal control units 73P and 73D, the switch T (switches Tp and Td) is closed and data is written, and the switch T (switches Tp and Td) is opened and determined. As described above, by closing and opening the switch T in the pulse shape at the time of the inversion of the output signal VCO, unnecessary power consumption in the writing operation of the time code can be reduced. In addition, a circuit with a relatively small area can be used to reduce power.

[0322] <Fourth Comparative Example>

[0323] It is also possible to generate a pulse-shaped output signal VCO by branching an input signal into two paths, setting a delay circuit in one of the paths, and performing a logic operation on the signals of the two branches. However, due to characteristic variations, etc., the delay in the delay circuit is different, and there is a case where the width of the output signal VCO cannot be sufficiently obtained. Therefore, it is necessary to design the circuit carefully, and there is a possibility that the circuit scale becomes large.

[0324] On the other hand, in the second embodiment, the first output signal and the activation signal are generated from one input signal, and no input signal is branched. With this arrangement, the activation of the second circuit 920 is delayed relative to the output of the first circuit 910, and the delayed second output signal can be generated more appropriately without increasing the circuit scale.

[0325] <First Modification of Second Embodiment>

[0326] Fig.23 : is a circuit diagram showing an example of the configuration of the second circuit 920 according to the first modification example of the second embodiment. Fig.23 1 shows the peripheral configuration of the transistor 921. The first modification example of the second embodiment is different from the second embodiment in that a current source 925 is provided.

[0327] The second circuit 920 further includes a current source 925. The current source 925 is connected in parallel with the transistor 921. As the current source 925, a current source 925 in which current leakage is slight is used.

[0328] In the first modification of the second embodiment, the leakage current passes through the current source 925. Compared with the second embodiment in which the off voltage of the transistor 921 is controlled to control the current value, it is not necessary to consider the settling time of the bias line.

[0329] As in the first modification of the second embodiment, a current source 925 may be provided. In this case as well, the same effects as those of the second embodiment can be obtained.

[0330] <Second Modification of Second Embodiment>

[0331] Fig.24 : is a circuit diagram showing an example of the configuration of the second circuit 920 according to the second modification example of the second embodiment. Fig.24 1 shows a peripheral configuration of the transistor 921. The first modification example of the second embodiment is different from the second embodiment in that a transistor 926 is provided.

[0332] The second circuit 920 further includes a transistor 926. The transistor 926 is diode-connected and connected in parallel with the transistor 921. The transistor 926 is constituted by, for example, an NMOS transistor.

[0333] In the second modification of the second example, the leakage current passes through the transistor 926. Compared with the first modification of the second example using the current source 925, a bias line for the current source becomes unnecessary, and the number of wirings can be reduced.

[0334] As in the second modification of the second example, a diode-connected transistor 926 may be provided. In this case as well, the same effects as those of the second embodiment can be obtained.

[0335] Note that a high-resistance dummy resistor may be provided instead of transistor 926 .

[0336] <Third Modification of Second Embodiment>

[0337] Fig.25 : is a circuit diagram showing an example of the configuration of the second circuit 920 according to the third modification example of the second embodiment. Fig.25 1 shows a peripheral configuration of a transistor 921. The third modification example of the second embodiment is different from the second modification example of the second embodiment in that a diode-connected transistor is further provided.

[0338] The second circuit 920 further includes transistors 927 and 928. Each of the transistors 927 and 928 is diode-connected. The transistors 927 and 928 are connected in series and connected in parallel with the transistor 921. The transistor 927 is composed of, for example, a PMOS transistor. The transistor 928 is composed of, for example, an NMOS transistor.

[0339] In the third modification of the second example, the leakage current passes through the transistors 927 and 928 .

[0340] As in the third modification of the second example, diode-connected transistors 927 and 928 may be provided. In this case, the same effects as those of the second modification of the second embodiment can be obtained.

[0341] <Application example of mobile object>

[0342] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile, an airplane, a drone, a ship, or a robot).

[0343] Fig.26 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0344] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0345] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0346] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave or a signal of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0347] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also perform processing for detecting objects such as people, vehicles, obstacles, signs, text on the road surface, etc., or processing for detecting their distances, etc., based on the received image.

[0348] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0349] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0350] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0351] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0352] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0353] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.26 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0354] Fig. 27 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0355] exist Fig. 27 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0356] The imaging units 12101, 12102, 12103, 12104 and 12105 are arranged, for example, at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper part of the windshield inside the vehicle. The imaging unit 12101 arranged at the front nose inside the vehicle and the imaging unit 12105 arranged at the upper part of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0357] Notice, Fig. 27An example of the imaging ranges of the imaging units 12101 to 12104 is shown. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. Imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. Imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging units 12101 to 12104.

[0358] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0359] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object such as the leading vehicle, specifically, the nearest three-dimensional object exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / hour) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to keep in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, it is possible to perform cooperative control aimed at automatic driving, which enables the vehicle to automatically travel without relying on the driver's operation, etc.

[0360] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0361] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaging images of the imaging units 12101 to 12104 as infrared cameras and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0362] Examples of vehicle control systems to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be applied to the imaging units 12031, 12101, 12102, 12103, 12104, 12105, etc. in the above configuration. Specifically, for example, Figure 1 The solid-state imaging device 1 in can be applied to these imaging sections. By applying the technology according to the present disclosure to these imaging sections, a high-definition captured image with little noise can be obtained, and therefore, high-precision control using the captured image can be performed in a mobile body control system.

[0363] It should be noted that the present technology can have the following configurations.

[0364] (1) A light detection element comprising:

[0365] A plurality of pixels, wherein

[0366] Each pixel in the plurality of pixels includes:

[0367] A physical signal acquisition unit, which acquires a physical signal;

[0368] a comparing unit, for comparing the physical signal acquired by the physical signal acquiring unit with a reference signal;

[0369] A signal accumulation floating unit is electrically connected to one end of the comparison unit;

[0370] A signal detection unit, electrically connected to the signal accumulation floating unit and detecting a comparison result of the comparison unit;

[0371] A signal amplifying unit, amplifying the detection result of the signal detecting unit;

[0372] A signal storage unit for storing a time code;

[0373] a signal input and output unit for inputting and outputting time codes; and

[0374] a signal control unit that performs control to store the time code output by the signal input-output unit in the signal storage unit based on the comparison result, and outputs the time code when the comparison result is inverted to the signal input-output unit, the time code being stored in the signal storage unit, and

[0375] Two or more pixels in a pixel are operated in parallel.

[0376] (2) The light detection element according to (1), further comprising:

[0377] at least two pixel groups, each pixel group detecting a physical signal; and

[0378] The storage control unit performs control for each pixel group to store the time code in the signal storage unit, and controls whether to update the time code stored in the signal storage unit.

[0379] (3) The light detection element according to (1) or (2), wherein:

[0380] The comparison unit includes a transistor, and the transistor includes: a gate, a physical signal obtained by the physical signal acquisition unit is input to the gate; a source, a reference signal is input to the source; and a drain, the drain is electrically connected to the signal accumulation floating unit,

[0381] The comparison unit accumulates the voltage of the floating unit based on the gate-source voltage of the transistor and the threshold change of the transistor to enable the signal detection unit to perform detection, and

[0382] The signal detection unit is arranged in the pixel array unit.

[0383] (4) The light detection element according to (3), further including a capacitor connected between a reference signal generation unit that generates a reference signal and a source of the transistor.

[0384] (5) The light detection element according to (4), further including a connection unit that is connected between a source of the transistor and a gate of the transistor and electrically connects the source of the transistor and the gate of the transistor at a predetermined timing.

[0385] (6) The light detection element according to any one of (1) to (5), wherein the plurality of physical signal acquisition units share the comparison unit.

[0386] (7) The light detection element according to any one of (1) to (6), wherein the signal amplification unit includes a positive feedback circuit.

[0387] (8) A light detection element according to any one of (1) to (7), wherein the physical signal acquisition unit, the comparison unit, the signal accumulation floating unit, the signal detection unit, the signal amplification unit, the signal control unit, the signal storage unit and the signal input-output unit are arranged across at least two semiconductor chips.

[0388] (9) The photodetection element according to any one of (1) to (8), wherein the plurality of physical signal acquisition units share a signal input and output unit.

[0389] (10) The light detection element according to any one of (1) to (9), wherein the signal input-output unit includes a trigger.

[0390] (11) The light detection element according to any one of (1) to (9), wherein the signal input-output unit includes a three-state inverter.

[0391] (12) The light detection element according to any one of (1) to (11), wherein at least two signal storage units are provided.

[0392] (13) The light detection element according to (12), wherein at least two signal input and output units are provided to correspond to one of the at least two signal storage units, respectively.

[0393] (14) The light detection element according to (12) or (13), further including a signal processing unit that performs at least one of image processing and subtraction processing between the signals stored in the at least two signal storage units.

[0394] (15) A timing generator comprising:

[0395] A first circuit, a second circuit and an operation circuit, wherein:

[0396] The first circuit outputs a first output signal obtained by delaying the inverse phase timing of the input signal and an activation signal for activating the second circuit based on one input signal,

[0397] The second circuit is activated based on the activation signal and outputs a second output signal, and

[0398] The operation circuit calculates the first output signal and the second output signal to output a third output signal.

[0399] (16) The timing generator according to (15), wherein the activation signal includes a first power supply voltage of the second circuit.

[0400] (17) The timing generator according to (15) or (16), wherein the second circuit includes a second power supply voltage of the first circuit in a period in which the second circuit is not activated.

[0401] (18) The timing generator according to any one of (15) to (17), wherein the first circuit and the second circuit include a first positive feedback circuit and a second positive feedback circuit connected in series.

[0402] (19) An AD converter comprising:

[0403] A timing generator according to any one of (15) to (18);

[0404] a signal storage unit storing a time code; and

[0405] A signal control unit performs control to store the time code in the signal storage unit based on the third output signal.

[0406] (20) The AD converter according to (19), wherein

[0407] The first circuit outputs a first output signal which is inverted at a first timing.

[0408] The second circuit outputs a second output signal inverted at a second timing after the first timing, the operation circuit outputs a third output signal inverted at the first timing and the second timing, and

[0409] The signal control unit starts storing the time code in the signal storage unit at a first timing, and stops storing the time code in the signal storage unit at a second timing.

[0410] The various aspects of the present disclosure are not limited to the above-mentioned embodiments, but include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, modifications, and partial deletions may be made without departing from the concept and spirit of the present disclosure obtained from the contents defined in the claims and their equivalents.

[0411] Reference Symbols List

[0412] 1 Solid-state imaging device

[0413] 11 Semiconductor substrate

[0414] 21 pixels

[0415] 22 pixel array unit

[0416] 23 Time code transmission unit

[0417] 31 Physical signal acquisition unit

[0418] 32 Comparison unit

[0419] 33 signal accumulation floating unit

[0420] 34 Signal detection unit

[0421] 41 Pixel Circuit

[0422] 42ADC

[0423] 51 Comparison Circuit

[0424] 52 Data storage unit

[0425] 35 Signal Amplification Unit

[0426] 71 Latch control circuit

[0427] 72 Latch storage unit

[0428] 73 Signal control unit

[0429] 74 signal storage unit

[0430] 75 Signal input and output unit

[0431] 121 Photodiode

[0432] 900 Timing Generator

[0433] 910 First Circuit

[0434] 920 Second Circuit

[0435] 930 Operational circuits.

Claims

1. A light detection element, comprising: A plurality of pixels, wherein Each pixel of the plurality of pixels comprises: A physical signal acquisition unit, which acquires a physical signal; a comparing unit, configured to compare the physical signal acquired by the physical signal acquiring unit with a reference signal; a signal accumulation floating unit, electrically connected to one end of the comparison unit; a signal detection unit, electrically connected to the signal accumulation floating unit and detecting a comparison result of the comparison unit; a signal amplifying unit, for amplifying the detection result of the signal detecting unit; A signal storage unit for storing time codes; a signal input and output unit for inputting and outputting the time code; and a signal control unit that performs control to store the time code output from the signal input-output unit in the signal storage unit based on the comparison result, and outputs the time code when the comparison result is inverted to the signal input-output unit, the time code being stored in the signal storage unit, and At least two or more of the pixels are operated in parallel.

2. The light detecting element according to claim 1, further comprising: at least two pixel groups, each of the pixel groups detecting a physical signal; as well as A storage control unit controls each of the pixel groups to store the time code in the signal storage unit, and controls whether to update the time code stored in the signal storage unit.

3. The light detecting element according to claim 1, wherein The comparison unit includes a transistor, and the transistor includes: a gate, to which the physical signal acquired by the physical signal acquisition unit is input; a source, to which the reference signal is input; and a drain, which is electrically connected to the signal accumulation floating unit. The comparison unit changes the voltage of the signal accumulation floating unit based on the gate-source voltage of the transistor and the threshold value of the transistor to enable the signal detection unit to perform detection, and The signal detection unit is arranged in the pixel array unit. 4 . The light detection element according to claim 3 , further comprising a capacitor connected between a reference signal generation unit that generates the reference signal and the source of the transistor. 5 . The light detecting element according to claim 4 , further comprising a connection unit that is connected between the source of the transistor and the gate of the transistor and electrically connected to the source of the transistor and the gate of the transistor at a predetermined timing. The light detecting element according to claim 1 , wherein The comparison unit is shared by a plurality of the physical signal acquisition units.

7. The light detecting element according to claim 1, wherein The signal amplifying unit includes a positive feedback circuit.

8. The light detecting element according to claim 1, wherein The physical signal acquisition unit, the comparison unit, the signal accumulation floating unit, the signal detection unit, the signal amplification unit, the signal control unit, the signal storage unit, and the signal input-output unit are arranged across at least two semiconductor chips.

9. The light detecting element according to claim 1, wherein A plurality of the physical signal acquisition units share the signal input and output unit.

10. The light detecting element according to claim 1, wherein The signal input and output unit includes a trigger.

11. The light detecting element according to claim 1, wherein The signal input and output unit includes a tri-state inverter.

12. The light detecting element according to claim 1, wherein At least two signal storage units are provided.

13. The light detecting element according to claim 12, wherein At least two of the signal input and output units are provided to correspond to a corresponding one of the at least two signal storage units. 14 . The light detecting element according to claim 12 , further comprising a signal processing unit that performs at least one of image processing and subtraction processing between the signals stored in at least two of the signal storage units.

15. A timing generator comprising: A first circuit, a second circuit and an operation circuit, wherein: the first circuit outputs a first output signal obtained by delaying the inverted phase timing of one input signal and an activation signal for activating the second circuit based on the input signal, The second circuit is activated based on the activation signal and outputs a second output signal, and The operation circuit calculates the first output signal and the second output signal to output a third output signal.

16. The timing generator according to claim 15, wherein The activation signal includes a first power supply voltage of the second circuit.

17. The timing generator according to claim 15, wherein The second circuit includes a second power supply voltage for the first circuit during a period in which the second circuit is not activated.

18. The timing generator according to claim 15, wherein The first circuit and the second circuit include a first positive feedback circuit and a second positive feedback circuit connected in series.

19. An analog-to-digital (AD) converter comprising: The timing generator according to claim 15; A signal storage unit for storing time codes; as well as A signal control unit performs control to store the time code in the signal storage unit based on a third output signal.

20. The analog-to-digital converter according to claim 19, wherein The first circuit outputs a first output signal which is inverted at a first timing. The second circuit outputs a second output signal inverted at a second timing subsequent to the first timing. The arithmetic circuit outputs the third output signal inverted at the first timing and the second timing, and The signal control unit starts storing the time code in the signal storage unit at the first timing, and stops storing the time code in the signal storage unit at the second timing.

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