Chip support component, atomic deposition device and preparation method of superconducting through silicon via interposer

Abstract

The invention discloses a chip support part, an atomic deposition device and a preparation method of a superconducting through silicon via interposer, the chip support part is used for the atomic deposition device, and the atomic deposition device is used for forming a superconducting layer in a through silicon via of a silicon wafer. The sheet holder component includes a loading structure and a support structure. The loading structure is an annular structural component. The supporting structures are distributed on the lower surface of the loading structure, and an opening is formed between every two adjacent supporting structures. In the superconducting layer growing process, a silicon wafer integrated with a silicon through hole is carried on a loading structure, and a gaseous raw material can reach one end, far away from the loading structure, of the silicon through hole; the gaseous feedstock may also pass through the opening to an end of the loading structure adjacent the support structure. The loading structure is of an annular structure, and the gaseous raw material can further penetrate through the loading structure to reach one end, close to the loading structure, of the silicon through hole. By adopting the sheet support component disclosed by the invention, the gaseous raw material can be deposited on the two sides of the silicon through hole, so that the directionality of the superconducting layer in the growth process is reduced, and the superconducting layer with relatively good thickness consistency is formed in the silicon through hole.

Description

Technical Field

[0001] The present invention relates to the technical field of superconducting quantum integrated circuit processing, and further to a chip support component, an atomic deposition device and a method for preparing a superconducting silicon through-via intermediate layer. Background Art

[0002] The superconducting silicon via interposer can provide short-distance interconnection between bit circuits, realizing 3D integration of bit circuits.

[0003] The superconducting silicon via interposer may include: a wafer and a superconducting silicon via, wherein the superconducting silicon via includes: a through silicon via (TSV) penetrating the upper and lower surfaces of the wafer, and a superconducting layer covering the inner wall of the silicon via.

[0004] In the process of superconducting layer growth, the superconducting layer growing device disclosed in the prior art uses a tray to load a wafer integrated with a through silicon via, and then grows a superconducting layer on the inner wall of the through silicon via. Usually, the thickness consistency of the superconducting layer grown on the inner wall of the through silicon via is poor. Summary of the invention

[0005] The present application discloses a wafer support component, an atomic deposition device and a method for preparing a superconducting silicon via intermediate layer. The wafer support component can be used to simultaneously deposit gaseous raw materials on both sides of the silicon via, and finally form a superconducting layer with good thickness consistency on the inner wall of the silicon via.

[0006] The first aspect of the present application discloses a wafer support component, which is used in an atomic deposition device, and the atomic deposition device is used to form a superconducting layer in a silicon through-hole of a silicon wafer. The wafer support component includes: a loading structure, which is an annular structure component, and the loading structure includes: an annular upper surface and an annular lower surface, an inner wall enclosed between the inner diameters of the upper surface and the lower surface, and an outer wall enclosed between the outer diameters of the upper surface and the lower surface; at least two supporting structures, and the supporting structures are intermittently distributed on the lower surface of the loading structure. There are openings between adjacent supporting structures.

[0007] In the process of growing a superconducting layer using the wafer support component disclosed in the present application: a silicon wafer with integrated through silicon vias is mounted on a loading structure, and a gaseous raw material can reach the end of the through silicon vias away from the loading structure; the gaseous raw material can also pass through the opening to reach the end of the loading structure adjacent to the support structure. Since the loading structure is a ring structure, the gaseous raw material can further pass through the loading structure to reach the end of the through silicon via adjacent to the loading structure.

[0008] It can be seen that during the growth of the superconducting layer using the wafer support component disclosed in the present application, the gaseous raw material can be deposited on both sides of the silicon via, thereby reducing the directionality of the superconducting layer growth process and forming a superconducting layer with good thickness consistency in the silicon via.

[0009] The wafer support component disclosed in the present application can form superconducting layers on both sides of the silicon wafer at the same time, which can reduce the damage to the environmental vacuum caused by multiple growth of superconducting layers; ensure that the gaseous raw materials are in an environment with low vacuum, reduce the oxidation loss of the gaseous raw materials, and improve the utilization rate of the gaseous raw materials.

[0010] The wafer support component disclosed in the present application can deposit a superconducting layer on the upper and lower surfaces of a silicon wafer and the inner wall of a through silicon via at the same time, thereby simplifying the preparation process of the superconducting layer.

[0011] In combination with the first implementation manner of the first aspect, the inner wall includes: at least one annular surface connected in sequence between the upper surface and the lower surface.

[0012] In this implementation, the structure and number of the annular surfaces can be flexibly configured according to needs. If the number of annular surfaces is greater than or equal to 2, the annular surface adjacent to the upper surface can be tilted from top to bottom toward the axial direction of the supporting component to reduce the area of ​​the upper surface, so that the silicon wafer mounted on the upper surface can have a larger effective area for the integration of silicon vias.

[0013] In combination with the second implementation manner of the first aspect, the at least one annular surface includes: a first annular surface, and an angle between the first annular surface and the lower surface is greater than 1 degree.

[0014] In this implementation, if the first annular surface is greater than 1 degree and less than 90 degrees, the first annular surface can be used as a guide surface. During the growth of the superconducting layer, it plays a role in balancing the flow field formed by the gaseous raw material, so that the gaseous raw material can be evenly deposited on the inner wall of the silicon via, and finally a superconducting layer with good thickness consistency is formed on the inner wall of the silicon via.

[0015] In combination with the third implementation of the first aspect, at least one annular surface further includes: a loading surface, which is arranged on a side of the first annular surface close to the lower surface, and an angle between the loading surface and the lower surface is less than or equal to 1 degree.

[0016] In this implementation, the angle between the loading surface and the lower surface is less than 1 degree, which can ensure that the angle between the silicon wafer mounted on the loading surface and the lower surface is small, thereby reducing the directionality during the growth of the superconducting layer and achieving the formation of a superconducting layer with good thickness consistency in the silicon through hole.

[0017] In addition, the loading surface is arranged on the side of the first annular surface away from the upper surface, and the angle between the first annular surface and the lower surface is greater than 1 degree, that is, the first annular surface is inclined, and the side of the first annular surface close to the upper surface is higher than the side of the first annular surface close to the bearing surface. The first annular surface protrudes from the bearing surface. The first annular surface can play a role of limiting the movement of the silicon wafer mounted on the bearing surface, and a superconducting layer with good thickness uniformity can be formed in the silicon through-hole of the silicon wafer.

[0018] In combination with the fourth implementation method of the first aspect, at least one annular surface includes: at least one annular surface connected in sequence between the upper surface and the lower surface: a second annular surface, a loading surface and a third annular surface; the angle between the loading surface and the lower surface is less than or equal to 1 degree; the angle between the second annular surface and the lower surface is greater than 1 degree; the angle between the third annular surface and the lower surface is greater than 1 degree, and the diameter of the end of the second annular surface close to the lower surface is greater than the diameter of the end of the third annular surface away from the lower surface.

[0019] In this implementation, the angle between the loading surface and the lower surface is less than 1 degree, which can ensure that the angle between the silicon wafer mounted on the loading surface and the lower surface is small, thereby reducing the directionality during the growth of the superconducting layer and achieving the formation of a superconducting layer with good thickness consistency in the silicon through hole.

[0020] If the angle between the second annular surface and the lower surface can be greater than 1 degree and less than 90 degrees, the second annular surface can serve as a guide surface, so that the gaseous raw material can be evenly deposited on the inner wall of the silicon through hole, further improving the thickness consistency of the superconducting layer.

[0021] If the angle between the second annular surface and the lower surface can be equal to 90 degrees, the second annular surface can serve as a limiting surface to limit the sliding of the silicon wafer, thereby ensuring that the gaseous raw material can be evenly deposited on the inner wall of the silicon via, further improving the thickness consistency of the superconducting layer.

[0022] In combination with the fifth implementation manner of the first aspect, a distance between an end of the support structure away from the loading structure and the lower surface is greater than or equal to 0.5 mm.

[0023] In this implementation, the height of the support structure is greater than or equal to 0.5 mm. The support structure has a large height, and a large opening can be formed between adjacent support structures, ensuring that more gaseous raw materials can reach the end of the loading structure adjacent to the support structure through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure is small, so that a superconducting layer with good thickness consistency can be formed in the silicon through hole of the silicon wafer mounted on the loading structure.

[0024] In combination with the sixth implementation method of the first aspect, the opening angle is the smallest first angle, the first angle is the angle between the line connecting any two first intersection points and the axis, one of the first intersection points is any point in the plane formed by the intersection of the first plane and a supporting structure, the other first intersection point is any point in the plane formed by the intersection of the first plane and another supporting structure, the first plane is a plane perpendicular to the axis, and the axis is the axis of the supporting structure.

[0025] In this implementation, the opening angle may be greater than or equal to 20 degrees. The size of the opening is relatively large, and during the growth process of the superconducting layer, more gaseous raw materials can reach the end of the loading structure adjacent to the supporting structure through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure is relatively small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure.

[0026] In combination with the seventh implementation method of the first aspect, the support structure angle is less than or equal to 10 degrees, the support structure angle is the largest second angle, the second angle is the angle between the line connecting any two second intersection points and the axis, the second intersection point is any point in the plane formed by the intersection of the first plane and the support structure, the first plane is a plane perpendicular to the axis, and the axis is the axis of the support structure.

[0027] In this implementation, the support structure angle can be less than or equal to 10 degrees. The support structure has a small angle, and adjacent support structures can form a larger opening. During the growth of the superconducting layer, more gaseous raw materials can reach the end of the loading structure adjacent to the support structure through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure is small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure.

[0028] In combination with the eighth implementation method of the first aspect, the area ratio of the first area of ​​the lower surface to the second area of ​​the lower surface is greater than or equal to 2:1, the first area is the exposed area of ​​the lower surface, and the second area is the area of ​​the lower surface where the support structure is arranged.

[0029] In this implementation, the area ratio of the first region to the second region is greater than or equal to 2:1, and the wafer support component may have a relatively large opening. During the growth of the superconducting layer, more gaseous raw materials can reach one end of the loading structure adjacent to the supporting structure through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure is small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure.

[0030] In combination with the ninth implementation manner of the first aspect, at least two support structures are evenly distributed on the lower surface of the loading structure.

[0031] In this implementation, at least two support structures are evenly distributed on the lower surface of the loading structure, ensuring that the opening sizes formed by any two adjacent support structures are consistent or similar, ensuring that the gaseous raw materials can evenly reach the end of the silicon wafer adjacent to the support structure, and realizing the formation of a superconducting layer with good thickness consistency at the end of the silicon wafer adjacent to the support structure. At the same time, it is also possible to achieve good thickness consistency of the superconducting layers of different through silicon vias.

[0032] In combination with the tenth implementation manner of the first aspect, any two support structures have the same height, and the height of the support structure is the distance between an end of the support structure away from the loading structure and the lower surface.

[0033] In this implementation, any two support structures have the same height, ensuring that the opening sizes formed by any two adjacent support structures are consistent or similar, ensuring that the gaseous raw materials can evenly reach the end of the silicon wafer adjacent to the support structure, and realizing the formation of a superconducting layer with good thickness consistency at the end of the silicon wafer adjacent to the support structure. At the same time, it is also possible to achieve good thickness consistency of the superconducting layers in different through-silicon vias.

[0034] The second aspect of the present application discloses an atomic deposition device for forming a superconducting layer in a through silicon via, comprising: a wafer support component and a cavity disclosed in the first aspect, wherein the wafer support component is arranged in the cavity. The wafer support component may include: a loading structure. The loading structure is an annular component. At least two supporting structures are arranged on the lower surface of the loading structure, and the supporting structures are arranged at intervals from each other, and two adjacent supporting structures form an opening.

[0035] In the atomic deposition device disclosed in the present application, the cavity is used to provide a reaction site for growing a superconducting layer in a through silicon via, and the wafer support component is used to load a silicon wafer integrated with the through silicon via.

[0036] During the growth of the superconducting layer: the gaseous raw material can reach the end of the silicon via away from the supporting structure; the gaseous raw material can also pass through the opening to reach the end of the loading structure near the supporting structure. Since the loading structure is a ring structure, the gaseous raw material can further pass through the loading structure to reach the end of the silicon via near the loading structure. It can be seen that by using the atomic deposition device disclosed in the present application, during the growth of the superconducting layer, the gaseous raw material can be deposited on both sides of the silicon via, thereby reducing the directionality of the superconducting layer during the growth process, and realizing the formation of a superconducting layer with good thickness consistency in the silicon via. The superconducting layer has a higher Tc, thereby realizing high-performance superconducting quantum chips and high-performance superconducting quantum computing systems.

[0037] The atomic deposition device disclosed in the present application can deposit a superconducting layer on the upper and lower surfaces of a silicon wafer and the inner wall of a silicon through-hole at the same time. Therefore, there is no need to open the cavity during the growth of the superconducting layer, thereby ensuring a low vacuum degree in the cavity to reduce oxidation losses of gaseous raw materials and improve the utilization rate of gaseous raw materials.

[0038] The atomic deposition device disclosed in the present application can simultaneously deposit a superconducting layer on the upper and lower surfaces of a silicon wafer and the inner wall of a through silicon via, which can simplify the preparation process of the superconducting layer. The atomic deposition device disclosed in the present application can grow a superconducting layer in situ to obtain a superconducting layer with good performance. The atomic deposition device disclosed in the present application can be used to obtain a superconducting layer with a higher Tc.

[0039] In combination with the first implementation of the second aspect, the atomic deposition device further includes: a heating device, which is wrapped around the outer wall of the cavity.

[0040] In this implementation, the heating device is wrapped around the outer wall of the cavity, so that the heating device can provide heat around the cavity, ensuring a lower temperature difference in the cavity.

[0041] The heating device is wound around the outer wall of the cavity, and the heating device can provide an eddy current thermal field for the cavity. The loading structure in the cavity is an annular structure, and the annular loading structure can balance the eddy current thermal field, so that there is a smaller temperature difference in the cavity. The smaller the temperature difference in the cavity, the better the thickness consistency of the obtained superconducting layer. Therefore, the atomic deposition device disclosed in the present implementation method can obtain a superconducting layer with better thickness consistency.

[0042] The third aspect of the present application discloses a method for preparing a superconducting silicon via interposer, comprising: mounting a silicon wafer integrated with the silicon via on the wafer support component disclosed in the first aspect; introducing a gaseous raw material around the wafer support component so that the gaseous raw material forms a superconducting layer on the inner wall of the silicon via.

[0043] The preparation method disclosed in the present application is to mount a silicon wafer with integrated through silicon vias on a wafer support component. The wafer support component may include: a loading structure, which is a ring-shaped component. At least two supporting structures are arranged on the lower surface of the loading structure, and the supporting structures are arranged at intervals from each other, and two adjacent supporting structures form an opening.

[0044] During the growth process of the superconducting layer, the gaseous raw material can reach the end of the silicon via far away from the supporting structure; the gaseous raw material can also pass through the opening to reach the end of the loading structure near the supporting structure. Since the loading structure is a ring structure, the gaseous raw material can further pass through the loading structure to reach the end of the silicon via near the supporting structure.

[0045] It can be seen that by adopting the preparation method disclosed in the present application, during the growth of the superconducting layer, the gaseous raw material can be deposited on both sides of the silicon via, thereby reducing the directionality of the superconducting layer during the growth process, and forming a superconducting layer with good thickness consistency in the silicon via. The superconducting layer has a higher Tc, thereby realizing a high-performance superconducting quantum chip and a high-performance superconducting quantum computing system.

[0046] Similarly, gaseous raw materials can deposit superconducting layers on the upper and lower surfaces of the silicon wafer at the same time. Compared with the method of forming a superconducting silicon via intermediate layer disclosed in the related art, the preparation method disclosed in this implementation simplifies the preparation process to a certain extent and has a higher process yield.

[0047] In combination with the first implementation of the third aspect, the depth of the through silicon via is 200 μm-500 μm.

[0048] In the preparation method disclosed in the present application, the silicon wafer is mounted on a wafer support component, so that a superconducting layer can be deposited on the upper and lower surfaces of the silicon wafer and the inner wall of the silicon through hole at the same time. Therefore, a superconducting layer with good thickness consistency can be formed on the inner wall of the silicon through hole with a depth of 200μm-500μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Schematic diagram of a superconducting quantum computing system;

[0050] Figure 2 This is a schematic diagram of a superconducting quantum chip;

[0051] Figure 3 A process flow chart for preparing a superconducting silicon via interposer;

[0052] Figure 4 A process flow chart for preparing a superconducting silicon via interposer;

[0053] Figure 5 A process flow chart for preparing a superconducting silicon via interposer;

[0054] Figure 6 is a schematic diagram of an atomic deposition apparatus;

[0055] Figure 7 A three-dimensional diagram of a sheet support component disclosed in a feasible embodiment;

[0056] Figure 8 for Figure 7 A front view of the disclosed sheet support component;

[0057] Fig. 9 for Figure 7 A bottom view of the disclosed sheet support component;

[0058] Fig.10 for Figure 7 A cross-sectional view of region B of the disclosed sheet support component on the aa' plane;

[0059] Fig.11 A schematic diagram of an atomic deposition device disclosed in a feasible embodiment;

[0060] Fig.12 An engineering drawing of a cross section of a sheet support component disclosed in a feasible embodiment;

[0061] Fig.13 A flowchart of preparing a superconducting silicon via interposer disclosed in a feasible embodiment;

[0062] Fig.14 for Fig.13 Process flow chart corresponding to the disclosed preparation method. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0064] In the following, the terms "first", "second", etc. are used only for descriptive purposes to distinguish between identical or similar items with substantially identical functions and effects, and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0065] Also, in the description of the present application, unless otherwise specified, “plurality” means two or more than two.

[0066] In addition, in this application, directional terms such as "upper", "lower", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the change of the orientation of the components in the drawings. Unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example: "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0067] Meanwhile, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0068] First, the concepts involved in the embodiments of the present application are introduced:

[0069] Air bridge is a circuit structure that uses a three-dimensional bridge structure to achieve planar circuit bridging. It is suitable for various chips, especially flip-chip chips and superconducting quantum chips.

[0070] Atomic layer deposition (ALD) is a method that can deposit materials layer by layer on the surface of a substrate in the form of a single atomic film. Atomic deposition is similar to ordinary chemical deposition. However, in the atomic deposition process, the chemical reaction of the new atomic film is directly related to the previous layer, so that only one layer of atoms is deposited in each reaction.

[0071] Through silicon via (TSV) technology is a new technical solution for interconnecting stacked chips in three-dimensional integrated circuits.

[0072] The supercritical temperature (Tc) is the temperature at which the superconducting layer changes from a normal state to a superconducting state. The superconducting state can be understood as a state in which the resistance value of the superconducting layer is 0. The supercritical temperature (Tc) is related to the thickness of the superconducting layer.

[0073] Superconductivity refers to the state in which the resistance of a conductor is zero at a certain temperature.

[0074] Thickness consistency can be understood as the difference between the thickness of the superconducting layer attached to one end of the superconducting via and the thickness of the superconducting layer attached to the other end of the superconducting via; the smaller the difference, the better the thickness consistency of the superconducting layer; the larger the difference, the worse the thickness consistency of the superconducting layer.

[0075] Chemical vapor deposition (CVD) is a chemical technology that mainly uses one or more gaseous compounds or single substances containing thin film elements to chemically react on the surface of a substrate to form a thin film.

[0076] Superconducting quantum computing has the advantage of fast operation speed and is widely used. Usually, superconducting quantum computing systems are used to implement superconducting quantum computing.

[0077] The structure of a superconducting quantum computing system is as follows Figure 1 As shown. The superconducting quantum computing system 10 may include: a superconducting quantum chip 101, a control subsystem 102, and a measurement subsystem 103. In some feasible implementations, the control subsystem 102, the superconducting quantum chip 101, and the measurement subsystem 103 may be integrated on one chip. In some feasible implementations, the control subsystem 102, the superconducting quantum chip 101, and the measurement subsystem 103 may be integrated on multiple chips.

[0078] The functions of the control subsystem 102, the superconducting quantum chip 101 and the measurement subsystem 103 are described below respectively:

[0079] The superconducting quantum chip 101 may include: a plurality of quantum bits (Qubits) connected to form a bit circuit. The Qubits carry quantum information. The superconducting quantum chip 101 includes a superconducting layer, and the superconducting quantum chip 101 needs to be placed in a low temperature environment so that the superconducting layer is in a superconducting state.

[0080] The control subsystem 102 is connected to the superconducting quantum chip 101. The control subsystem 102 is used to control the state of the Qubit, thereby realizing quantum computing. Among them, quantum computing may include but is not limited to: single-bit logic gate computing, two-bit logic gate computing, etc. Among them, the single-bit logic gate computing is realized by changing the frequency of the input microwave pulse signal, and the two-bit logic gate computing is realized by adjusting the frequency of the two Qubits so that the two Qubits resonate and interact with each other.

[0081] The measurement subsystem 103 is connected to the superconducting quantum chip 101. The measurement subsystem 103 is used to read the final state of the Qubit and obtain the calculation result of the quantum calculation.

[0082] The working process of the superconducting quantum computing system 10 is generally as follows:

[0083] The superconducting quantum chip 101 is placed in a low-temperature environment, and the control subsystem 102 generates a pulse modulation signal according to the requirements of the quantum computing operation, and inputs a series of microwave pulse sequences into the superconducting quantum chip 101 to operate the quantum state of the Qubit. After all operations are completed, the measurement subsystem 103 outputs a measurement pulse signal to the superconducting quantum chip 101, obtains the state information of the Qubit through the change of the returned signal, and finally obtains the calculation result.

[0084] The superconducting quantum chip 101 is the core part of the superconducting quantum computing system 10 and is a hardware device for performing quantum information storage. Generally, the more quantum bits the superconducting quantum chip 101 integrates, the stronger the parallel acceleration capability of the superconducting quantum chip 101 is, and the faster it can solve the same problem.

[0085] For bit circuits with a small number of quantum bits, the design and processing of bit circuits can be realized on a two-dimensional plane through air bridges. However, as the number of integrated quantum bits further increases to several hundred, it is difficult to design and process bit circuits on a two-dimensional plane through air bridges.

[0086] Therefore, researchers in this field currently use 3D integration to achieve the design and processing of bit circuits, thereby reducing the interconnection density on the quantum bit plane.

[0087] The superconducting silicon via interposer can realize short-distance connection between chips. The superconducting silicon via interposer can realize 3D integration of multi-layer superconducting circuits, providing support for increasing the number of quantum bits in the superconducting quantum chip 101. Specifically, the superconducting silicon via interposer can be used as a connecting component for bit circuits of different layers, realizing 3D integration of superconducting circuits in the superconducting quantum chip 101.

[0088] The structure of the superconducting quantum chip 101 is further described below with reference to the specific drawings:

[0089] See also Figure 2 The superconducting quantum chip 101 may include: a bit circuit 21, a superconducting silicon via interposer 22, and a lead layer 23. The bit circuit 21, the superconducting silicon via interposer 22, and the lead layer 23 are stacked in sequence. For example, the bit circuit 21 may exist in the form of a bit layer (qubit chip).

[0090] The functions of the bit circuit 21, the superconducting silicon via interposer 22 and the lead layer 23 are described below:

[0091] The bit circuit 21 is used for the integration of quantum bits.

[0092] The superconducting silicon via interposer 22 is used for connection between different bit circuits 21 , or for connection between the bit circuit 21 and the lead layer 23 .

[0093] The lead layer (carry chip) 23 is used to connect the bit circuit 21 to the control subsystem 102, so that the pulse modulation signal transmitted by the control subsystem 102 can reach the quantum bit in the bit circuit 21, thereby realizing the operation of the quantum state of the quantum bit.

[0094] The lead layer 23 is also used to connect the bit circuit 21 to the measurement system 103, so that the measurement system 103 can output a measurement pulse signal to the quantum bit through the lead layer 23 and the silicon through-hole 2, obtain the state information of the quantum bit through the return signal change, and finally obtain the calculation result.

[0095] It should be noted that Figure 2 This is merely an exemplary introduction to a possible structure of the superconducting quantum chip 101. The structure of the superconducting quantum chip 101 does not constitute a specific limitation.

[0096] In some feasible implementations, the superconducting quantum chip 101 may include: a multi-layer bit circuit 21 , and different bit circuits 21 may be connected via a superconducting silicon via intermediate layer 22 .

[0097] The superconducting silicon via interposer 22 can provide short-distance interconnection between bit circuits 21 and bit circuits 21, thereby realizing 3D integration of quantum bits.

[0098] Please continue reading Figure 2 It can be seen that the superconducting silicon via interposer 22 may include a wafer 2A and superconducting silicon vias 2B that penetrate the upper and lower surfaces of the wafer 2A. Generally, the material used for the wafer 2A includes silicon (Si), so in the embodiment of the present application, the wafer 2A may also be referred to as a silicon wafer.

[0099] Superconducting silicon via 2B has been widely used in semiconductor integrated devices, whether as a high-performance interconnect for creating 3D circuits or to achieve isolation between components on a designed chip, it has shown irreplaceable superiority. Specifically:

[0100] The bit circuit 21 is connected to the lead layer 23 or the bit circuit 21 of other layers through the superconducting silicon via 2B. Signal transmission needs to pass through the superconducting silicon via 2B. The superconducting silicon via 2B is surrounded by the wafer 2A, which can limit the signal transmission and avoid signal crosstalk between different superconducting silicon vias 2B.

[0101] The superconducting silicon via 2B can ensure that the signal transmission between the bit circuits 21 has better coherence and minimum crosstalk. The superconducting silicon via 2B also provides great possibility for coupling between the bit circuits 21 and the bit circuits 21 .

[0102] Please continue reading Figure 2 It can be seen that the superconducting silicon via 2B may include a through silicon via 221 (TSV) penetrating the upper and lower surfaces of the wafer 2A, and a superconducting layer 222 covering the inner wall of the through silicon via 221 .

[0103] The material used for the superconducting layer 222 is a gaseous material. The gaseous material has the property of zero resistance and repelling magnetic lines of force under certain low temperature conditions.

[0104] The superconducting layer 222 can be used as a carrier for signal transmission to realize the interconnection between different bit circuits 21. The superconducting layer 222 presents a superconducting state under certain low temperature conditions, thus reducing the energy loss generated during the signal transmission process.

[0105] The generation process of the superconducting quantum chip 101 is described below:

[0106] Figure 3 The present invention discloses a process for forming a superconducting silicon via interposer 22 as a related art. Figure 3 The disclosed process of manufacturing the superconducting silicon via interposer 22 is divided into the following six steps:

[0107] Step 1: Etch a 200 μm deep hole on a 500 μm thick silicon wafer 2A. The resulting structure can be found in Figure 3 In (a).

[0108] Step 2: Use ALD technology to grow a 100nm-200nm titanium nitride (TiN) layer 222A. The resulting structure can be found in Figure 3 (ii) in.

[0109] Step 3: Use the handle wafer 31 to bond the front side of the silicon wafer 2A. The resulting structure can be seen in Figure 3 Of (3).

[0110] Step 4: Then, the back side of the silicon wafer 2A is thinned by grinding until the through silicon via 221 can penetrate the upper and lower surfaces of the silicon wafer 2A. The obtained structure can be referred to Figure 3 (IV) in.

[0111] Step 5: Form a 100nm-200nm metal niobium layer 222B on the back of the silicon wafer 2A by evaporation, and pattern the metal niobium layer 222B. Since the through silicon via 221 penetrates the silicon wafer 2A, the TiN layer 222A attached to the inner wall of the through silicon via 221 can communicate with the metal niobium layer 222B covering the back of the silicon wafer 2A. The TiN layer 222A and the metal niobium layer 222B together form a superconducting layer 2B. The obtained structure can be referred to Figure 3 (five) in.

[0112] Step 6: Finally, remove the bonding of the fixing plate 31, and the obtained structure of the superconducting silicon via interposer 22 can be referred to Figure 3 (six) in the figure. The superconducting silicon via interposer 22 may include: a silicon wafer 2A and a superconducting silicon via 2B. The superconducting silicon via 2B may include: a silicon via 221 and a superconducting layer 222. The superconducting layer 222 includes: a TiN layer 222A and a metal niobium layer 222B. Part of the TiN layer 222A covers the inner wall of the silicon via 221, part of the TiN layer 222A covers the front side of the silicon wafer 2A, and the metal niobium layer 222B covers the back side of the silicon wafer 2A. The silicon via 221 runs through the upper and lower surfaces of the silicon wafer 2A.

[0113] Figure 3 The disclosed related technologies have the following problems:

[0114] (1) In step 4, the silicon wafer 2A needs to be thinned. The silicon wafer 2A is usually thinned by grinding. During the grinding process, the surface stress of the silicon wafer 2A will change, resulting in a stress difference between the surface of the silicon wafer 2A and the inside of the silicon wafer 2A. The stress difference may cause the silicon wafer 2A to warp and crack, reducing the yield of the superconducting silicon via interposer 22.

[0115] (2) Figure 3 In the disclosed related technologies, the silicon wafer 2A needs to be thinned, and the preparation process is relatively complicated.

[0116] In order to avoid the thinning process of the silicon wafer 2A, the related art also discloses a process for forming a superconducting silicon via interposer 22. Figure 4 .

[0117] Figure 4In the disclosed related technologies, in order to solve the warping and cracking of the silicon wafer generated during the thinning process, the silicon wafer is directly etched through. The manufacturing process of the superconducting silicon via interposer 22 is divided into the following six steps:

[0118] Step 1: A patterned photoresist (PR) 41 is formed on the front side of a 300 μm thick silicon wafer 2A, and an etching stop layer 42 is formed on the back side of the silicon wafer 2A. The obtained structure can be referred to in Figure 4 In (a).

[0119] Step 2: Forming a through silicon via 221 penetrating the silicon wafer 2A. The obtained structure can be referred to Figure 4 (ii) in.

[0120] Step 3: Use ALD technology to grow a 100nm-200nm titanium nitride (TiN) layer 222A. The resulting structure can be found in Figure 4 of (3).

[0121] Step 4: Grow a 100nm-200nm superconducting metal layer 222B on the TiN layer 222A. The resulting structure can be found in Figure 4 The material of the superconducting metal layer 222B includes at least one of metal aluminum (Al), metal niobium (Nb), and metal tantalum (Ta).

[0122] Step 5: Use ALD technology to grow a 100nm-200nm TiN layer 222C on the back surface. The resulting structure can be found in Figure 4 (five) in.

[0123] Step 6: Patterning the TiN layer 222C. The structure of the obtained superconducting silicon via interposer 22 can be referred to Figure 4 (six) in.

[0124] Figure 4 The disclosed related technologies have the following problems:

[0125] (1) The depth of the silicon through hole 221 is generally between 200 μm and 300 μm. The depth of the silicon through hole 221 is relatively large. The TiN layer 222A formed in step 4 needs to cover the inner wall of the silicon through hole 221 with a depth of 200 μm to 300 μm. In the silicon through hole 221, the thickness of the bottom TiN layer is 50% to 70% less than the thickness of the top TiN layer. This makes the thickness consistency of the TiN layer 222A poor.

[0126] (2) Between step 4 and step 5, the etching stop layer 42 disposed on the back side of the silicon wafer 2A needs to be removed. Removing the etching stop layer 42 will inevitably introduce additional impurities, thereby affecting the yield of the superconducting silicon via interposer 22.

[0127] (3) Steps 1 to 5 need to be performed in a chamber with a low vacuum degree. Between steps 4 and 5, the chamber needs to be opened and the silicon wafer turned over. This process destroys the vacuum degree of the chamber and introduces oxides.

[0128] In order to avoid the thinning process of the silicon wafer 2A, the related art also discloses a process for forming a superconducting silicon via interposer 22. Figure 5 .

[0129] Figure 5 In the disclosed related technologies, in order to solve the warping and cracking of the silicon wafer generated during the thinning process, the silicon wafer is directly etched through. The manufacturing process of the superconducting silicon via interposer 22 is divided into the following six steps:

[0130] Step 1: A patterned photoresist 51 is formed on the front side of a 300 μm thick silicon wafer 2A, and an etching stop layer 52 is formed on the back side of the silicon wafer 2A. The obtained structure can be referred to Figure 5 In (a).

[0131] Step 2: Forming a through silicon via 221 penetrating the silicon wafer 2A. The obtained structure can be referred to Figure 5 (ii) in.

[0132] Step 3: Use CVD technology to grow a 100nm-200nm TiN layer 222A. The resulting structure can be found in Figure 5 Of (3).

[0133] Step 4: Use wet etching to completely etch the etching stop layer 52 on the back of the silicon wafer 2A, and form an etching stop layer 53 on the front of the silicon wafer 2A. The obtained structure can be referred to Figure 5 (IV) in.

[0134] Step 5: Using CVD technology, a 100nm-200nm thick TiN layer 222B is grown on the side of the silicon wafer 2 away from the etching stop layer 53. The obtained structure can be referred to Figure 5 (five) in.

[0135] Step 6: Finally, remove the etching stop layer 53. The structure of the superconducting silicon via interposer 22 can be found in Figure 5 (six) in.

[0136] Figure 5 The disclosed related technologies have the following technical problems:

[0137] (1) Figure 5 The disclosed related technology involves removing the etching stop layer twice, respectively in step 4 and step 6. The process is highly complex, and the subsequent process of removing the etching stop layer will inevitably introduce additional impurities.

[0138] (2) Figure 5 According to the disclosed related technology, the depth of the silicon via is 300 μm, and there is also a problem of poor thickness consistency of the superconducting layer covering the inner wall of the silicon via, and the superconducting layer has a low Tc.

[0139] The superconducting layer 222 is used as a carrier for signal transmission, and the coverage performance and thickness consistency of the superconducting layer 222 are crucial to the properties of the superconducting silicon via interposer 22 .

[0140] In order to obtain a superconducting layer 222 with good coverage performance, the related technology usually adopts atomic layer deposition (ALD) to grow a superconducting layer with good coverage performance.

[0141] ALD is a method that can deposit a substance layer by layer on the surface of a substrate in the form of single atoms. During the atomic deposition process, only one layer of atoms is deposited in each reaction, and the new layer of atoms covers the atoms of the previous layer and physically or chemically combines with the atoms of the previous layer to obtain a superconducting layer 222 in the form of a compound. During the deposition of the superconducting layer 222, a new layer of atoms covers the atoms of the previous layer, so the obtained superconducting layer 222 has better coverage performance.

[0142] ALD is usually formed by using an atomic deposition device. The atomic deposition device disclosed in the related art is described below with reference to specific drawings:

[0143] See also Figure 6 , Figure 6 The schematic diagram of the atomic deposition device disclosed in the related art is as follows. The atomic deposition device may include: a first chamber 61, a second chamber 62, a gas separator 63, a tray 64 and a heating device (not shown in the figure).

[0144] The first cavity 61 is communicated with the second cavity 62 .

[0145] The gas inlet of the gas separator 63 is communicated with the first cavity 61 , and the gas outlet of the gas separator 63 is communicated with the second cavity 62 .

[0146] The tray 64 is disposed in the first cavity 61, and is used to load silicon wafers integrated with through silicon vias. The second cavity 62 provides a reaction place for the generation of superconducting layers.

[0147] The heating device 65 is disposed at the bottom of the tray 64 and is used to heat the silicon wafers mounted on the tray 64 .

[0148] The working process of the above-mentioned preparation device is generally as follows:

[0149] The gaseous raw material can enter the first cavity 61 through the gas inlet 611 that penetrates the first cavity 61. The gaseous raw material in the first cavity 61 flows uniformly to the second cavity 62 through the gas separator 63, and deposits on the surface of the silicon wafer and the inner wall of the silicon through-hole to form a superconducting layer.

[0150] Figure 6 In the disclosed preparation of the superconducting layer, a silicon wafer integrated with through silicon vias is mounted on a tray. During the deposition of the superconducting layer, the gaseous raw material can only diffuse through the through silicon via from the side away from the tray to the side adjacent to the tray, which will cause inconsistent concentrations of the gaseous raw material at both ends of the through silicon via, resulting in poor thickness consistency of the finally formed superconducting layer.

[0151] The superconducting layer of the superconducting quantum chip 101 is formed by using an atomic deposition device disclosed in the related art. The thickness consistency of the superconducting layer is poor, so that the silicon through hole has a lower superconducting critical temperature, resulting in the superconducting quantum computing system 10 having a larger system fault tolerance.

[0152] In order to solve the problems existing in the related art, the present application provides a wafer support component. The wafer support component 100 is used to form a superconducting layer in a silicon through-silicon via of a silicon wafer. Figure 7-10 It can be seen that the wafer support component 100 may include a loading structure 1 for loading a silicon wafer (the silicon wafer is integrated with through silicon vias) and at least two supporting structures 2 .

[0153] The loading structure 1 is an annular structural component, and the loading structure includes: an annular upper surface 11 and an annular lower surface 12, an inner wall 13 arranged between the inner diameters of the upper surface 11 and the lower surface 12, and an outer wall 14 arranged between the outer diameters of the upper surface 11 and the lower surface 12. At least two supporting structures 2 are arranged on the lower surface 11 at intervals, and there is an opening A between adjacent supporting structures 2.

[0154] In the process of growing the superconducting layer using the wafer support component disclosed in the embodiment of the present application: the silicon wafer with integrated through silicon vias is mounted on the loading structure 1, and the gaseous raw material can reach the end of the through silicon vias away from the loading structure 1; the gaseous raw material can also pass through the opening A to reach the end of the loading structure 1 near the support structure 2. Since the loading structure 1 is a ring structure, the gaseous raw material can further pass through the loading structure 1 and reach the end of the through silicon vias near the loading structure 1.

[0155] It can be seen that during the growth of the superconducting layer using the wafer support component 100 disclosed in the embodiment of the present application, the gaseous raw material can be deposited on both sides of the silicon via, thereby reducing the directionality of the superconducting layer growth process and forming a superconducting layer with good thickness consistency in the silicon via.

[0156] Furthermore, the wafer support component 100 disclosed in the embodiment of the present application can form a superconducting layer on both sides of the silicon wafer at the same time, which can reduce the damage to the environmental vacuum caused by multiple growth of superconducting layers; ensure that the gaseous raw material is in an environment with a low vacuum degree, reduce the oxidation loss of the gaseous raw material, and improve the utilization rate of the gaseous raw material.

[0157] The wafer support component 100 disclosed in the embodiment of the present application can deposit a superconducting layer on the upper and lower surfaces of the silicon wafer and the inner wall of the through silicon via at the same time, which can simplify the preparation process of the superconducting layer.

[0158] The following is a further description of the various components of the sheet support component 100 disclosed in the embodiment of the present application:

[0159] The sheet support component 100 disclosed in the embodiment of the present application may include: a loading structure 1 .

[0160] Please continue reading Figure 7-10 It can be seen that the loading structure 1 is an annular component, comprising an annular upper surface 11 and an annular lower surface 12 , an inner wall 13 disposed between the inner diameters of the upper surface 11 and the lower surface 11 , and an outer wall 14 disposed between the outer diameters of the upper surface 11 and the lower surface 12 .

[0161] During the growth of the superconducting layer, if the medium frequency coil is used to heat the sheet support component 100, the annular loading structure can generate eddy currents to regulate and stabilize the temperature field, thereby further improving the thickness consistency of the superconducting layer.

[0162] In the embodiment of the present application, the loading structure 1 is used to load a silicon wafer with integrated through silicon vias. For the convenience of description, the end of the silicon wafer adjacent to the loading structure 1 is called the first end of the silicon wafer, and the end of the silicon wafer away from the loading structure 1 is called the second end of the silicon wafer.

[0163] In some feasible implementations, the silicon wafer can be placed on the upper surface 11 of the loading structure. Since the upper surface 11 is a ring-shaped structure, a part of the second end of the silicon wafer can be suspended in the air.

[0164] In practical applications, TSVs are usually integrated in the suspended area of ​​the silicon wafer. The gaseous raw materials can reach the first end and the second end of the TSV, so that the gaseous raw materials can be deposited from both sides of the TSV, and finally form a superconducting layer with good consistency in the TSV.

[0165] The embodiment of the present application does not specifically limit the structure of the inner wall 13, and the structure of the inner wall 13 can be set according to requirements.

[0166] As a feasible implementation, the inner wall 13 may include: an annular surface.

[0167] For example, see Fig.10As can be seen from (a) in the figure, the inner wall 13 may include: a vertically arranged limiting surface 1A. Fig.10 In the wafer support component 100 disclosed in (a), during the superconducting layer growth process, the silicon wafer is mounted on the upper surface 11 of the loading structure 1. Fig.10 The limiting surface 1A in (I) may also be referred to as a first annular surface in the embodiment of the present application.

[0168] In the embodiment of the present application, the limiting surface can be understood as an annular surface with an angle greater than 1 degree and less than 90 degrees with the lower surface 12. During the growth of the superconducting layer, the lower surface is usually arranged parallel to the horizontal plane, so the lower surface can also be approximately understood as a horizontal plane.

[0169] For example, see Fig.10 As can be seen from (ii), the inner wall 13 may include: an inclined guide surface 1B, Fig.10 The guide surface 1B in (ii) in the embodiment of the present application may also be referred to as a first annular surface.

[0170] In the embodiment of the present application, the guide surface can be understood as an annular surface with an angle greater than 1 degree and less than 90 degrees with the lower surface 12. The guide surface 1B can play a role in regulating and stabilizing the flow field, thereby allowing the gaseous raw material to be uniformly deposited on the inner wall of the silicon via.

[0171] Fig.10 In the wafer support component 100 disclosed in (ii), if the size of the silicon wafer is larger than the inner diameter of the upper surface 11, the silicon wafer can be mounted on the upper surface 11 of the loading structure.

[0172] If the size of the silicon wafer is smaller than the inner diameter of the upper surface 11, the silicon wafer can be mounted on the guide surface 1B. Since the guide surface 1B is inclined, the contact area between the silicon wafer and the guide surface 1B is smaller, and the silicon wafer can have more suspended areas for integrating silicon through vias.

[0173] As a feasible implementation manner, the inner wall 13 may also include: a plurality of annular surfaces sequentially connected between the upper surface 11 and the lower surface 12 .

[0174] The embodiment of the present application does not specifically limit the number of annular surfaces included in the inner wall 13. For example, the number of annular surfaces may be 2, 3, 4, etc.

[0175] It is considered that the larger the angle between the silicon wafer and the lower surface 12 is, the worse the thickness consistency of the superconducting layer deposited on the inner wall of the through silicon via will be.

[0176] In order to ensure that the superconducting layer has better thickness consistency, the inner wall 13 may also include: in an implementation mode of multiple annular surfaces, the multiple annular surfaces may include: a loading surface.

[0177] In the embodiment of the present application, the loading surface can be understood as an annular surface with an angle less than 1 degree with the lower surface 12, and the loading surface is used to load silicon wafers.

[0178] In this implementation, the angle between the loading surface and the lower surface is less than 1 degree, which can ensure that the angle between the silicon wafer mounted on the loading surface and the lower surface 12 is small, thereby reducing the directionality during the growth of the superconducting layer and forming a superconducting layer with good thickness consistency in the silicon through hole.

[0179] The loading surface is arranged on the side of the first annular surface away from the upper surface 11, and the loading surface is arranged on the side of the first annular surface away from the upper surface 11. The angle between the first annular surface and the lower surface 12 is greater than 1 degree, that is, the first annular surface is inclined, and the first annular surface protrudes from the bearing surface. The first annular surface can play a limiting role, limiting the movement of the silicon wafer mounted on the bearing surface, so as to form a superconducting layer with good thickness consistency in the silicon through hole.

[0180] For example, see Fig.10 (three) and Fig.10 (iv) in the above. In some feasible implementations, at least one annular surface may include: a second annular surface 1C, a loading surface 1D, and a third annular surface 1E connected in sequence between the upper surface 11 and the lower surface 12. The diameter of the end of the second annular surface 1C adjacent to the lower surface 12 is greater than the diameter of the end of the third annular surface 1E away from the lower surface 12. One end of the loading surface 1D is connected to the end of the second annular surface 1C adjacent to the lower surface 12, and the other end of the loading surface 1D is connected to the end of the third annular surface 1E away from the lower surface 12.

[0181] The embodiment of the present application does not specifically limit the angle between the second annular surface 1C and the lower surface 12 .

[0182] For example, please refer to Fig.10 As can be seen from (iii) in the figure: the angle between the second annular surface 1C and the lower surface 12 can be greater than 1 degree and less than 90 degrees, so that the second annular surface 1C can be used as a guide surface, so that the gaseous raw material can be evenly deposited on the inner wall of the silicon via, and finally a superconducting layer with good thickness consistency is formed on the inner wall of the silicon via.

[0183] For example, please refer to Fig.10 It can be seen from (iv) that the angle between the second annular surface 1C and the lower surface can be equal to 90 degrees, so that the second annular surface 1C can be used as a limiting surface to limit the sliding of the silicon wafer, thereby ensuring that the gaseous raw material can be evenly deposited on the inner wall of the silicon via, and finally forming a superconducting layer with good thickness consistency on the inner wall of the silicon via.

[0184] It is worth noting that Fig.10The above-mentioned structures are merely examples of possible structures of the inner wall of the loading structure, and do not constitute specific limitations.

[0185] In actual application, the structure of the inner wall 13 can be adjusted according to requirements. For example, the number of annular surfaces included in the inner wall, the angle between the annular surface and the lower surface, the size of the inner diameter of the annular surface, and the size of the outer diameter of the annular surface can be set according to requirements.

[0186] The embodiment of the present application does not specifically limit the structures of the upper surface 11 , the lower surface 12 , and the outer wall 14 .

[0187] The embodiment of the present application does not specifically limit the size of the loading structure 1 .

[0188] As a feasible implementation method, the inner diameter of the loading structure 1 can be designed according to the size of the silicon wafer. The silicon wafer can be loaded on the inner wall 13 or loaded on the upper surface 11.

[0189] As a feasible implementation method, the outer diameter of the loading structure can be designed according to the size of the superconducting layer cavity so that the loading structure can be mounted in the superconducting layer cavity. The superconducting layer cavity is used to provide a reaction place for growing the superconducting layer. In the embodiment of the present application, the superconducting layer cavity can also be referred to as the first cavity.

[0190] In the embodiment of the present application, the sheet support component 100 further includes: at least two support structures 2. The at least two support structures 2 are intermittently distributed on the lower surface 12 of the loading structure 1. The support structure 2 is used to support the loading structure 1.

[0191] In order to realize a wafer support component 100 with better structural stability, as a feasible implementation method, at least two support structures 2 can be evenly distributed on the lower surface 12 of the loading structure 1 to ensure the structural stability of the wafer support component 100.

[0192] As a feasible implementation method, the support structure 2 and the loading structure 1 can be formed in one piece.

[0193] The present application embodiment does not specifically limit the structure of the support structure 2, and any structure with supporting performance can be used as the structure of the support structure 2 and applied to the present application embodiment. For example, the support structure 2 can include but is not limited to: a pyramid structure, a prism structure, a cone structure, a cylindrical structure, etc.

[0194] Please continue reading Figure 8 , considering that the larger the height H of the support structure 2 is, the larger the size of the opening A formed by two adjacent support structures 2 is. The more gaseous raw materials reach the bottom of the loading structure 1 through the opening A, the lower the concentration difference of the gaseous raw materials at the top and the bottom of the loading structure 1 is, and the better the thickness consistency of the superconducting layer finally formed on the inner wall of the through silicon via is.

[0195] In order to form a superconducting layer with good thickness consistency in the through silicon via, as a feasible implementation method, the height H of the support structure 2 can be greater than or equal to 0.5 mm. Exemplarily, the height H of the support structure 2 can be: 0.6 mm, 0.7 mm, 0.8 mm, etc.

[0196] In this implementation, the height H of the support structure 2 is greater than or equal to 0.5 mm. The support structure 2 has a greater height, and a larger opening can be formed between adjacent support structures 2, so that more gaseous raw materials can reach the end of the loading structure 1 adjacent to the support structure 2 through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure 1 is lower, and the thickness consistency of the superconducting layer finally formed on the inner wall of the silicon through hole is better.

[0197] Considering that the smaller the opening angle is, the larger the size of the opening A formed by two adjacent support structures 2 is, the better the thickness consistency of the superconducting layer finally formed in the through silicon via is.

[0198] In order to further improve the thickness consistency of the superconducting layer on the inner wall of the through silicon via, as a feasible implementation, the opening angle may be greater than or equal to 20 degrees, and for example, the opening angle may be, but is not limited to, 21 degrees, 22 degrees, 23 degrees, etc.

[0199] Please continue reading Fig. 9 In the embodiment of the present application, the opening angle can be understood as the first angle θ at which the opening angle is the smallest, and the first angle is the angle between the line connecting any two first intersection points and the axis (OO'), wherein one first intersection point is any point in the plane formed by the intersection of the first plane and a supporting structure 21, and the other first intersection point is any point in the plane formed by the intersection of the first plane and another supporting structure 22, the first plane is a plane perpendicular to the axis, and the axis is the axis of the supporting structure.

[0200] In this implementation, the opening angle can be greater than or equal to 20 degrees, and the size of the opening is relatively large. During the growth process of the superconducting layer, more gaseous raw materials can reach the end of the loading structure 1 adjacent to the supporting structure 2 through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure 1 is relatively small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure 1.

[0201] Considering that the smaller the angle of the support structure 2 is, the larger the size of the opening A formed by two adjacent support structures 2 is, the better the thickness consistency of the superconducting layer finally formed in the through-silicon via is.

[0202] In order to further improve the thickness consistency of the superconducting layer on the inner wall of the through silicon via, as a feasible implementation, the angle of the support structure 2 can be less than or equal to 10 degrees, and illustratively, the angle of the support structure 2 can be, but not limited to, 9 degrees, 8 degrees, 7 degrees, etc.

[0203] Please continue reading Fig. 9 , the supporting structure angle α is the largest second angle, the second angle is the angle between the line connecting any two second intersection points and the axis, the second intersection point is any point in the plane formed by the intersection of the first plane and the supporting structure, the first plane is a plane perpendicular to the axis, and the axis is the axis of the supporting structure.

[0204] In this implementation, the support structure angle can be less than or equal to 10 degrees, the support structure 2 has a small angle, and adjacent support structures 2 can form a larger opening. During the growth of the superconducting layer, more gaseous raw materials can reach the end of the loading structure 1 adjacent to the support structure 2 through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure 1 is small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure 1.

[0205] In the embodiment of the present application, the sheet support component 100 includes at least two support structures 2, so that the support structure 2 can support the loading structure 1.

[0206] The embodiment of the present application does not specifically limit the number of supporting structures 2. By way of example, the number of supporting structures 2 may include: 2, 3, 3, 4, and the like.

[0207] This completes the description of the support structure 2.

[0208] In the embodiment of the present application, the area of ​​the lower surface 12 of the loading structure not covered by the supporting structure can be called the first area, or the exposed area of ​​the lower surface can be called the first area; the area of ​​the lower surface 12 of the loading structure covered by the supporting structure 2 is called the second area.

[0209] Considering that the larger the area ratio of the first region to the second region is, the larger the opening size of the wafer support component 100 is, the better the thickness consistency of the superconducting layer formed in the through silicon via using the wafer support component 100 is.

[0210] In order to further improve the thickness consistency of the superconducting layer on the inner wall of the through silicon via, as a feasible implementation method, the area ratio of the first area to the second area of ​​the lower surface 12 is greater than or equal to 2:1. Exemplarily, the area ratio of the first area to the second area can be, but is not limited to, 3:1, 4:1, 5:1, etc.

[0211] In this implementation, the area ratio of the first region to the second region is greater than or equal to 2:1, and the wafer support component 100 may have a relatively large opening. During the growth of the superconducting layer, more gaseous raw materials can reach the end of the loading structure 1 adjacent to the supporting structure 2 through the opening, and the concentration difference of the gaseous raw materials at both ends of the loading structure 1 is relatively small, so that a superconducting layer with good thickness consistency can be formed in the silicon through-hole of the silicon wafer mounted on the loading structure 1.

[0212] This completes the description of the sheet support member 100.

[0213] The present application also discloses an atomic deposition device, which is used to form a superconducting layer in a through silicon via. Fig.11 It can be seen that the atomic deposition device may include: the wafer support component 100 and the cavity 200 disclosed in the embodiment of the present application. The wafer support component 100 is disposed in the cavity 200 .

[0214] In the atomic deposition device disclosed in the embodiment of the present application, the cavity 200 is used to provide a reaction site for growing a superconducting layer in a through silicon via. The wafer support component 100 is used to load a silicon wafer integrated with a through silicon via. The wafer support component 100 may include: a loading structure 1, which is a ring-shaped component. At least two supporting structures 2 are arranged on the lower surface of the loading structure 1, and the supporting structures 2 are arranged at intervals from each other, and two adjacent supporting structures 2 form an opening A.

[0215] During the growth of the superconducting layer: the gaseous raw material can reach the end of the silicon through hole away from the support structure 2; the gaseous raw material can also pass through the opening A to reach the end of the loading structure 1 near the support structure 2. Since the loading structure 1 is a ring structure, the gaseous raw material can further pass through the loading structure 1 and reach the end of the silicon through hole near the loading structure 1. It can be seen that by using the atomic deposition device disclosed in the embodiment of the present application, during the growth of the superconducting layer, the gaseous raw material can be deposited on both sides of the silicon through hole, thereby reducing the directionality of the superconducting layer during the growth process, and realizing the formation of a superconducting layer with good thickness consistency in the silicon through hole. The superconducting layer has a higher Tc, thereby realizing a high-performance superconducting quantum chip and a high-performance superconducting quantum computing system.

[0216] The atomic deposition device disclosed in the embodiment of the present application can deposit a superconducting layer on the upper and lower surfaces of a silicon wafer and the inner wall of a silicon through-hole at the same time. Therefore, during the growth of the superconducting layer, there is no need to open the cavity 200, thereby ensuring that the vacuum degree of the cavity 200 is low, reducing the oxidation loss of the gaseous raw materials and improving the utilization rate of the gaseous raw materials.

[0217] The atomic deposition device disclosed in the embodiment of the present application can simultaneously deposit a superconducting layer on the upper and lower surfaces of a silicon wafer and the inner wall of a through silicon via, which can simplify the preparation process of the superconducting layer. The atomic deposition device disclosed in the embodiment of the present application can grow a superconducting layer in situ to obtain a superconducting layer with good performance. The atomic deposition device disclosed in the embodiment of the present application can be used to obtain a superconducting layer with a higher Tc.

[0218] For the sake of distinction, the embodiment of the present application refers to the cavity for accommodating the wafer support component 100 as the first cavity 200 .

[0219] In some feasible implementations, the atomic deposition apparatus may further include: a second chamber 300 and a gas separator 400 , wherein a gas inlet 401 of the gas separator 400 is connected to the second chamber 300 , and a gas outlet 402 of the gas separator 400 is connected to the first chamber 200 .

[0220] The second chamber 300 can be used as a plasma power source to dissociate the raw materials in the compound state into atomic gaseous raw materials. The gaseous raw materials involved in the embodiments of the present application refer to atomic gaseous raw materials unless otherwise specified. For example, the atomic gaseous raw materials may include: gaseous nitrogen (N), gaseous chlorine (Cl), etc.

[0221] The gas separator 400 serves to release the gaseous raw material uniformly into the first chamber.

[0222] The gaseous raw material can enter the first cavity 200 through the gas inlet 301 that penetrates the second cavity 300. The gaseous raw material in the first cavity 200 flows uniformly to the first cavity 200 through the gas separator 400, and the gaseous raw material is uniformly distributed in the first cavity 200, thereby further improving the thickness consistency of the superconducting layer deposited on the inner wall of the through silicon via.

[0223] As a feasible implementation, the gas outlet of the gas separator 400 faces the upper surface of the loading structure, so that the gas released by the gas separator 400 can fall evenly around the wafer support component 100 .

[0224] The embodiment of the present application does not specifically limit the distance between the gas separator 400 and the upper surface 11 of the loading structure.

[0225] In order to make the gas released by the gas separator 400 fall evenly around the sheet support component 100, as a feasible implementation method, the distance between the gas separator 400 and the upper surface 11 of the loading structure is greater than or equal to the use distance of the gas separator 400. The use distance of the gas separator 400 can be understood as the required distance that the gas separator 400 can evenly disperse the gas into the environment. Exemplarily, the use distance of the gas separator 400 can be: 10mm.

[0226] The growth process of the superconducting layer needs to be carried out in a high temperature environment. Accordingly, the atomic deposition device needs to have a heating device 500, which is used to provide heat in the first cavity to provide a high temperature environment for the generation of the superconducting layer. The heating device 500 may include but is not limited to: a heating wire, and the heating wire may be an illustrative resistance wire, etc.

[0227] The embodiment of the present application does not specifically limit the position of the heating device. For example, the heating device 500 can be disposed at the bottom of the sheet support component 100.

[0228] Considering that the thickness of the superconducting layer is related to the temperature difference in the first cavity 200, the greater the temperature difference in the first cavity 200, the worse the thickness consistency of the superconducting layer; the smaller the temperature difference of each part in the first cavity 200, the better the thickness consistency of the superconducting layer.

[0229] The temperature difference in the first cavity 200 can be understood as the temperature difference between different areas in the first cavity 200. Exemplarily, the temperature difference in the first cavity 200 can include the temperature difference between the periphery of the first cavity 200 and the axis of the first cavity 200; the temperature difference between the top of the first cavity 200 and the bottom of the first cavity 200, etc.

[0230] In order to further improve the thickness consistency of the superconducting layer, as a feasible implementation method, the heating device 500 can be wrapped around the outer wall of the first cavity 200 so that the heating device 500 can provide heat around the first cavity 200 to ensure a lower temperature difference in the first cavity 200.

[0231] The heating device 500 is wound around the outer wall of the first cavity 200, and the heating device 500 can provide an eddy current thermal field for the first cavity 200. The loading structure 1 in the first cavity 200 is an annular structure, and the annular loading structure 1 can balance the eddy current thermal field, so that there is a small temperature difference in the first cavity 200. The atomic deposition device disclosed in this implementation can obtain a superconducting layer with good thickness consistency.

[0232] As a feasible implementation, the atomic deposition device may further include a tray 600. The tray is disposed at the bottom of the wafer support component 100 and is used to receive the dropped objects generated during the process of growing the superconducting layer.

[0233] The embodiment of the present application does not specifically limit the sizes of the wafer support component 100, the first cavity 200, the second cavity 300, and the gas separator 400, and the sizes of the wafer support component 100, the first cavity 200, the second cavity 300, and the gas separator 400 can be set according to requirements.

[0234] The dimensions of the wafer support component 100, the first cavity 200, the second cavity 300, and the gas separator 400 are introduced below in conjunction with specific examples:

[0235] Embodiment 1:

[0236] The atomic deposition apparatus disclosed in the first embodiment is suitable for growing a superconducting layer in a through silicon via of a 2-inch silicon wafer.

[0237] The dimensions of the components of the atomic deposition apparatus are as follows:

[0238] The first cavity 200 is a cylindrical structure with a diameter of 300 mm and a height of 1000 mm.

[0239] The second cavity 300 has a diameter of 150 mm and a height of 500 mm; the diameter of the air inlets on both sides of the second cavity 300 is 8 mm.

[0240] The diameter of the gas beam splitter 400 is 150 mm.

[0241] The heating device 500 is a heating wire that uniformly surrounds the first cavity 200 .

[0242] Embodiment 1 provides an engineering drawing of a wafer support component 100 used in an atomic deposition device. Fig.12 , the dimensions of the sheet support component 100 are as follows:

[0243] The inner diameter A1 of the loading surface 1D is 46 mm.

[0244] The outer diameter A2 of the loading surface 1D is 51.5 mm.

[0245] The angle between the loading surface and the lower surface 12 of the pallet / loading structure is 0 degrees.

[0246] The outermost diameter A3 of the mounting structure 1 (outer diameter of the upper surface / lower surface) is 55 mm.

[0247] The distance between the upper surface 11 of the loading structure 1 and the gas beam splitter 400 is 10 mm. The area ratio of the first area to the second area of ​​the lower surface of the loading structure 1 is 2:1.

[0248] The support structure angle is 10 degrees and the support structure height H is 5m.

[0249] The opening angle of the wafer support member 100 is 20 degrees.

[0250] Embodiment 2:

[0251] The atomic deposition apparatus disclosed in the second embodiment is suitable for growing a superconducting layer in a through silicon via of a 4-inch silicon wafer.

[0252] The atomic deposition device disclosed in the second embodiment may include: a wafer support component 100, a first cavity 200, a second cavity 300, and a gas beam splitter 400. In the atomic deposition device disclosed in the second embodiment, the first cavity 200, the second cavity 300, and the gas beam splitter 400 have the same size as the first cavity 200, the second cavity 300, and the gas beam splitter 400 disclosed in the first embodiment. The difference is that the wafer support component 100 used in the second embodiment is different from the wafer support component 100 used in the first embodiment.

[0253] The engineering drawing of the wafer support component 100 used in the atomic deposition device provided in the second embodiment can be referred to in Fig.12 , the dimensions of the sheet support component 100 are as follows:

[0254] The inner diameter A1 of the loading surface 1D is 96 mm.

[0255] The outer diameter A2 of the loading surface 1D is 101.5 mm.

[0256] The angle between the loading surface and the lower surface 12 of the pallet / loading structure is 0 degrees.

[0257] The outermost diameter A3 of the loading structure 1 is 105 mm.

[0258] The distance between the upper surface 11 of the loading structure 1 and the gas beam splitter 400 is 10 mm.

[0259] The area ratio of the first area to the second area on the lower surface of the loading structure 1 is 11:4.

[0260] The support structure angle is 8 degrees and the support structure height H is 5m.

[0261] The opening angle of the wafer support member 100 is 22 degrees.

[0262] It can be seen from the first and second embodiments that the atomic deposition device disclosed in the embodiments of the present application can form a superconducting layer in the through silicon vias of silicon wafers of different sizes by replacing the wafer support component 100.

[0263] In addition, the first and second embodiments are merely exemplary introductions of the dimensions of the components in the two atomic deposition devices, and the above dimensions do not constitute specific limitations.

[0264] The working process of the atomic deposition device disclosed in the embodiment of the present application is described below by taking the superconducting layer including the TiN layer as an example:

[0265] (1) The first cavity 200 is evacuated to a high vacuum and the heating wire 500 is turned on. The heating is maintained for 1 hour to ensure that the entire first cavity 200 reaches thermal equilibrium.

[0266] (2) TiCl4 gas is introduced into the first chamber 200 and a plasma power supply is turned on at the same time. The plasma power supply is used to ionize the TiCl4 gas into plasma (Ti atoms and Cl atoms). The Ti atoms and Cl atoms are deposited on the upper and lower surfaces of the silicon wafer and the inner wall of the silicon through hole. After the pulse ends, the plasma power supply is turned off and the TiCl4 gas is used for purging.

[0267] (3) NH3 gas is introduced into the first chamber 200, and the plasma power supply is turned on at the same time. The plasma power supply is used to ionize the NH3 gas into plasma (N atoms and H atoms). After the pulse ends, the plasma power supply is turned off. The NH3 gas is used for purging for a period of time.

[0268] In step (3), N atoms replace Cl atoms on the upper and lower surfaces of the silicon wafer and the inner wall of the silicon through hole, and finally a TiN layer is obtained on the upper and lower surfaces of the silicon wafer and the inner wall of the silicon through hole. After the pulse ends, the plasma power is turned off and NH3 gas is used for a period of time.

[0269] The above steps (2) and (3) are repeated until a TiN layer of appropriate thickness is achieved.

[0270] This completes the description of the atomic deposition apparatus.

[0271] The present application also discloses a method for preparing a superconducting silicon via interposer. Fig.13 , the preparation method may include:

[0272] S1: forming a through silicon via that penetrates the silicon wafer to obtain a silicon wafer with integrated through silicon via.

[0273] The present application does not specifically limit the implementation method of forming the through silicon via, and the through silicon via can be formed by an etching process, wherein the etching process may include dry etching, wet etching, etc.

[0274] The etching gas used in the dry etching process may include: oxygen (O2), fluorine-containing gas, chlorine-containing gas, bromine-containing gas, iodine-containing gas, etc. The wet etching process may include the etchant used, including but not limited to: hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, nitric acid (HNO3), acetic acid (CH3COOH) solution, etc.

[0275] As a feasible implementation method, after step S1, the preparation method can also use BOE cleaning agent to remove excess oxides. The BOE cleaning agent may include: hydrofluoric acid, nitric acid, etc.

[0276] In the implementation of forming the through silicon via by etching process, the preparation method further includes before step S1: SA forms a patterned sacrificial layer on one surface of the silicon wafer and forms an etching stop layer on the other surface of the silicon wafer. The sacrificial layer may be but is not limited to photoresist.

[0277] The sacrificial layer and the etching stop layer may be formed by using conventional techniques in the art, and the applicant does not make any further limitations here.

[0278] S2: A gaseous raw material is passed around the silicon wafer with integrated through silicon via to form a superconducting layer on the inner wall of the through silicon via. The silicon wafer with integrated through silicon via is mounted on the wafer support component disclosed in the embodiment of the present application.

[0279] The superconducting layer can be formed by using the atomic deposition device disclosed in the embodiment of the present application, specifically:

[0280] The silicon wafer with integrated through silicon via is placed on the wafer support component 100 disclosed in the embodiment of the present application. The wafer support component 100 is located in the first cavity 200. A gaseous raw material is introduced into the first cavity 200. The gas reacts on the surface of the silicon wafer and the inner wall of the through silicon via by applying pulses and purging time to obtain a superconducting layer.

[0281] The gaseous raw material is a material for forming a superconducting layer, and may include but is not limited to titanium tetrachloride (TiCl4), ammonia (NH3), and the like.

[0282] The following is an explanation of the formation process of the superconducting silicon via interposer with reference to a specific example:

[0283] Embodiment three.

[0284] SA: First, a 500nm silicon oxide is grown on a 300mm silicon wafer 131 as an etching barrier layer 132, and then a photoresist is uniformly coated on the front of the silicon wafer 131 to form a pattern to obtain a patterned photoresist 133. The obtained structure can be referred to Fig.14 The structure in (A).

[0285] S1: Then use deep silicon etching to etch holes in the silicon wafer 131 to obtain silicon through-holes 134. Use BOE to clean the silicon oxide. The obtained structure can be referred to Fig.14 The structure in (1).

[0286] S2: forming a superconducting layer on the inner wall of the through silicon via 134 and the surface of the silicon wafer 131. In the third embodiment, the superconducting layer is formed by using the atomic deposition device disclosed in the embodiment of the present application.

[0287] The growth process of the superconducting layer can be:

[0288] (a) The first cavity 200 is evacuated to a pressure below 5×10-5Pa, and the heating wire 500 is turned on to heat the first cavity 200 to 400°C-450°C for 1 hour to ensure that the entire first cavity 200 reaches thermal equilibrium.

[0289] (b) TiCl4 gas is introduced at a flow rate of 100 sccm-200 sccm, and the power of the plasma power supply is set at 150w-300w, with a pulse duration of 0.1s-0.2s. The plasma power supply is used to ionize the TiCl4 gas into plasma (Ti atoms and Cl atoms).

[0290] Ti atoms and Cl atoms are deposited on the upper surface of the silicon wafer 131 and the inner surface of the silicon through hole 134. After the pulse ends, the plasma power is turned off and TiCl4 gas is used to purge for 3s-5s. The obtained structure can be referred to Fig.14 The structure in (A).

[0291] (c) NH3 gas is introduced at a gas flow rate of 50sccm-150sccm, and the power of the plasma power supply is set at 150w-300w. The plasma power supply is used to ionize the NH3 gas into plasma (N atoms and H atoms). The pulse is 0.2s-0.4s. The obtained structure can be referred to Fig.14 The structure in (b).

[0292] The Cl atoms are replaced by N atoms to generate TiN which is attached to the upper and lower surfaces and the inner wall of the substrate. After the pulse ends, the plasma power is turned off and NH3 gas is used to purge for 4s-6s.

[0293] The superconducting silicon via interposer structure obtained by cycling (b) and (c) can be found in Fig.14 The structure in (3).

[0294] The preparation method disclosed in the embodiment of the present application mounts a silicon wafer with integrated through silicon vias on a wafer support component 100. The wafer support component 100 may include: a loading structure 1, which is a ring-shaped component. At least two supporting structures 2 are arranged on the lower surface of the loading structure 1, and the supporting structures 2 are arranged at intervals from each other, and two adjacent supporting structures 2 form an opening A.

[0295] During the growth process of the superconducting layer, the gaseous raw material can also reach the end of the silicon through via far away from the support structure 2; the gaseous raw material can also pass through the opening A to reach the end of the loading structure 1 near the support structure 2. Since the loading structure 1 is a ring structure, the gaseous raw material can further pass through the loading structure and reach the end of the silicon through via near the support structure 2.

[0296] It can be seen that by adopting the preparation method disclosed in the embodiment of the present application, during the growth of the superconducting layer, the gaseous raw material can be deposited on both sides of the silicon via, thereby reducing the directionality of the superconducting layer during the growth process, and forming a superconducting layer with good thickness consistency in the silicon via. The superconducting layer has a higher Tc, thereby realizing a high-performance superconducting quantum chip and a high-performance superconducting quantum computing system.

[0297] Similarly, gaseous raw materials can deposit superconducting layers on the upper and lower surfaces of the silicon wafer at the same time. Compared with the method of forming a superconducting silicon via intermediate layer disclosed in the related art, the preparation method disclosed in this implementation simplifies the preparation process to a certain extent and has a higher process yield.

[0298] In the preparation method disclosed in the embodiment of the present application, the silicon wafer is mounted on a wafer support component, so that a superconducting layer can be deposited on the upper and lower surfaces of the silicon wafer and the inner wall of the silicon via at the same time. Therefore, a superconducting layer with good thickness consistency can be formed on the inner wall of the silicon via with a depth of 200μm-500μm.

[0299] This is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wafer support component, the wafer support component is used in an atomic deposition device, the atomic deposition device is used to form a superconducting layer in a through silicon via of a silicon wafer, characterized in that: The wafer support component carries the silicon wafer, and the wafer support component includes: A loading structure, the loading structure is an annular structure, the loading structure comprising: an annular upper surface and an annular lower surface, an inner wall arranged between the inner diameters of the upper surface and the lower surface, and an outer wall arranged between the outer diameters of the upper surface and the lower surface; At least two supporting structures are intermittently distributed on the lower surface of the loading structure, and an opening is formed between two adjacent supporting structures.

2. The sheet support component according to claim 1, characterized in that: The inner wall includes: at least one annular surface sequentially connected between the upper surface and the lower surface.

3. The sheet support component according to claim 2, characterized in that: The at least one annular surface includes: a first annular surface, and an angle between the first annular surface and the lower surface is greater than 1 degree.

4. The sheet support component according to claim 3, characterized in that: The at least one annular surface further includes: a loading surface, which is arranged on a side of the first annular surface close to the lower surface, and an angle between the loading surface and the lower surface is less than or equal to 1 degree.

5. The sheet support component according to claim 2, characterized in that: The at least one annular surface includes: a second annular surface, a loading surface, and a third annular surface; The angle between the loading surface and the lower surface is less than or equal to 1 degree; The angle between the second annular surface and the lower surface is greater than 1 degree; The included angle between the third annular surface and the lower surface is greater than 1 degree, and the diameter of the end of the second annular surface close to the lower surface is greater than the diameter of the end of the third annular surface away from the lower surface.

6. The sheet support component according to any one of claims 1 to 5, characterized in that: The height of the support structure is greater than or equal to 0.5 mm; The height of the supporting structure is the distance between an end of the supporting structure away from the loading structure and the lower surface.

7. The sheet support component according to any one of claims 1 to 6, characterized in that: Any two of the support structures have the same height, and the height of the support structure is the distance between one end of the support structure away from the loading structure and the lower surface.

8. The sheet support component according to any one of claims 1 to 7, characterized in that: The opening angle is greater than or equal to 20 degrees; The opening angle is the smallest first angle, the first angle is the angle between the line connecting any two first intersection points and the axis, one of the first intersection points is any point in the plane formed by the intersection of the first plane and one of the supporting structures, the other first intersection point is any point in the plane formed by the intersection of the first plane and another of the supporting structures, the first plane is a plane perpendicular to the axis, and the axis is the axis of the supporting structure.

9. The sheet support component according to any one of claims 1 to 8, characterized in that: The support structure angle is less than or equal to 10 degrees; The supporting structure angle is the largest second angle, the second angle is the angle between the line connecting any two second intersection points and the axis, the second intersection point is any point in the plane formed by the intersection of the first plane and the supporting structure, the first plane is a plane perpendicular to the axis, and the axis is the axis of the supporting structure.

10. The sheet support component according to any one of claims 1 to 9, characterized in that: The area ratio of the first area of ​​the lower surface to the second area of ​​the lower surface is greater than or equal to 2:1, the first area is an exposed area of ​​the lower surface, and the second area is an area of ​​the lower surface where the support structure is arranged.

11. The sheet support component according to any one of claims 1 to 10, characterized in that: The at least two supporting structures are evenly distributed on the lower surface of the loading structure.

12. An atomic deposition apparatus for forming a superconducting layer in a through silicon via, characterized in that: include: The sheet support component according to any one of claims 1 to 11; A cavity, wherein the sheet support component is arranged in the cavity.

13. The atomic deposition device according to claim 12, characterized in that: Also includes: A heating device is arranged on the outer wall of the cavity.

14. A method for preparing a superconducting silicon via interposer, characterized in that: include: Mounting a silicon wafer with integrated through silicon vias on a wafer support component according to any one of claims 1 to 11; A gaseous raw material is introduced around the wafer support component so that the gaseous raw material forms a superconducting layer on the inner wall of the through silicon via.

15. The preparation method according to claim 14, characterized in that: The through silicon via has a depth of 200 μm-500 μm.

Images