Band-gap reference source circuit, all-gallium nitride band-gap reference circuit and preparation method of all-gallium nitride band-gap reference circuit

Abstract

The invention discloses a band-gap reference source circuit, an all-gallium nitride band-gap reference circuit and a preparation method of the all-gallium nitride band-gap reference circuit. According to the invention, high-precision reference voltage can be provided for a GaN-based circuit, and the working stability of the circuit is improved; all components of the all-gallium nitride band-gap reference circuit can be manufactured on a GaN-based platform, so that the all-gallium nitride band-gap reference circuit is highly compatible with the process of a GaN power device, the structure is simpler, and the advantages of GaN in the aspect of transverse integration can be brought into full play. The all-GaN band-gap reference circuit provided by the invention is a monolithic integrated GaN-based band-gap reference source circuit, so that the signal transmission distance and various parasitic effects caused by interconnection of external circuits can be reduced, and the high-frequency performance of GaN in power electronic application can be fully exerted.

Description

Technical Field

[0001] The present invention belongs to the technical field of gallium nitride power electronics, and in particular relates to a bandgap reference source circuit, a full gallium nitride bandgap reference circuit and a preparation method thereof. Background Art

[0002] GaN materials are widely used in high-power and high-frequency electronics due to their large bandgap, high breakdown electric field, high electron mobility, radiation resistance and high temperature resistance. HEMT (High electron mobility transistor) devices made of GaN materials have gradually become the first choice in high-frequency and high-power applications due to their excellent high-frequency characteristics and high-voltage resistance.

[0003] At present, in GaN monolithic integrated circuits, the reference voltage can be generated by resistor voltage division, which has the disadvantages of low precision and susceptibility to temperature interference, often resulting in the circuit being unable to be turned on and off in time, which will reduce the circuit's operating efficiency and damage the device. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a bandgap reference source circuit, a full gallium nitride bandgap reference circuit and a preparation method thereof.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a bandgap reference source circuit, comprising: a current mirror circuit, a two-stage operational amplifier circuit and a reference voltage output circuit; the current mirror circuit, the two-stage operational amplifier circuit and the reference voltage output circuit are electrically connected;

[0007] The current mirror circuit includes a lateral temperature sensor, a resistor and an enhancement mode transistor, and is used to generate a PTAT current with a positive temperature coefficient;

[0008] The secondary operational amplifier circuit includes an enhancement transistor, a depletion transistor and a resistor, and is used to clamp the drain voltage of the transistors on both sides of the current mirror in the current mirror circuit so that the voltages at the two points remain equal;

[0009] The reference voltage output circuit includes a lateral temperature sensor, a resistor and an enhancement transistor, and is used to output a reference voltage;

[0010] The voltage of the lateral temperature sensor in the current mirror circuit and the reference voltage output circuit has a negative temperature coefficient.

[0011] The present invention also provides a full gallium nitride bandgap reference circuit, comprising: a wafer and connecting wires, on which all lateral temperature sensors, all resistors, all enhancement-mode transistors and all depletion-mode transistors in the above-mentioned bandgap reference source circuit are integrated; the connecting wires are used to connect the lateral temperature sensors, the resistors, the enhancement-mode transistors and the depletion-mode transistors according to the connection method in the above-mentioned bandgap reference source circuit.

[0012] The present invention also provides a method for preparing a full-gallium nitride bandgap reference circuit, which is used to prepare the above-mentioned full-gallium nitride bandgap reference circuit, and the method comprises:

[0013] S1. Prepare an epitaxial wafer, wherein the epitaxial wafer comprises, from bottom to top, a Si substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a P-GaN layer;

[0014] S2, defining a gate P-GaN region of the enhancement mode HEMT and a P-GaN region of the lateral temperature sensor on the surface of the P-GaN layer, and etching downwards the P-GaN region except the gate P-GaN region of the enhancement mode HEMT and the P-GaN region of the lateral temperature sensor, and the etching depth extends to the AlGaN barrier layer;

[0015] S3, defining a mesa region on the surface of the AlGaN barrier layer, and etching downwards the region outside the mesa region, with the etching depth extending to the GaN channel layer, to obtain a current sample;

[0016] S4, depositing a first SiO2 passivation layer on the surface of the current sample;

[0017] S5, defining the source and drain groove regions of the enhancement-mode HEMT, the source and drain groove regions of the depletion-mode HEMT, the cathode groove region of the lateral temperature sensor, and the electrode groove region of the 2DEG resistor on the surface of the first SiO2 passivation layer, and etching the defined groove regions downwards, with the etching depth extending to the lower surface of the AlN insertion layer, to form the source and drain grooves of the enhancement-mode HEMT, the source and drain grooves of the depletion-mode HEMT, the cathode groove of the lateral temperature sensor, and the ohmic electrode groove of the 2DEG resistor;

[0018] S6, depositing an ohmic contact metal in the ohmic electrode groove;

[0019] S7, performing a rapid thermal annealing process on the ohmic contact metal to form an ohmic contact electrode;

[0020] S8, depositing a second SiO2 passivation layer on the surface of the current sample obtained after S7;

[0021] S9, defining a gate region of the enhancement-mode HEMT in the gate P-GaN region of the enhancement-mode HEMT, and etching downward to the upper surface of the P-GaN layer to form a gate groove of the enhancement-mode HEMT, and defining a gate groove region of the depletion-mode HEMT on the surface of the second SiO2 passivation layer, and etching downward to the upper surface of the AlGaN barrier layer to form a gate groove of the depletion-mode HEMT; defining an anode region of the lateral temperature sensor around the P-GaN region of the lateral temperature sensor, and etching downward to the upper surface of the AlGaN barrier layer to form an anode groove of the lateral temperature sensor;

[0022] S10, depositing Schottky metal in the gate groove of the enhancement-mode HEMT, the gate groove of the depletion-mode HEMT and the anode groove of the lateral temperature sensor to form the gate of the enhancement-mode HEMT, the gate of the depletion-mode HEMT and the anode of the lateral temperature sensor;

[0023] S11, metallization interconnection of various components is performed by depositing metal to complete the preparation of the full gallium nitride bandgap reference circuit.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The current mirror circuit in the bandgap reference source circuit provided by the present invention adopts a two-stage operational amplifier to clamp the drain voltage of the transistors on both sides of the current mirror, so that the voltages at the two points can be kept equal. The high gain characteristic of the two-stage operational amplifier is utilized to improve the stability and accuracy of the clamping point voltage, thereby making the PTAT current generated by the current mirror circuit more accurate and reliable.

[0026] 2. The reference source circuit provided by the present invention can generate a reference voltage that is independent of temperature. The current generated by the current mirror circuit has a positive temperature coefficient, and the voltage of the lateral temperature sensor has a negative temperature coefficient. Considering the influence of the device manufacturing process error, the ratio of the first resistor R1 and the second resistor R2 can be adjusted to finally output a reference voltage that is independent of temperature, providing a high-precision reference voltage for the GaN-based circuit and improving the working stability of the circuit.

[0027] 3. The existing scheme of generating a reference voltage through a silicon-based bandgap reference source circuit and then making the silicon-based circuit and the GaN-based circuit on a PCB board has the disadvantages of low integration, high design and production costs, large board-level circuit volume, not conforming to the design trend of miniaturization and high power density of power chips, and generating a series of parasitic crosstalk, which is not conducive to the efficient operation and energy conservation of power modules. However, all circuit elements in the full gallium nitride bandgap reference circuit of the present invention all use GaN devices, and are all prepared on the same wafer, which improves the power density and integration of the circuit, reduces the cost, fully utilizes the advantages of GaN lateral integration, reduces the parasitic crosstalk effect of the circuit, and the manufacturing process of all circuit elements in the full gallium nitride bandgap reference circuit of the present invention is highly compatible with GaN power devices, and can be made on the same wafer with GaN power devices to further improve the power density and integration of the circuit and give full play to the high frequency and high power density characteristics of GaN materials.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a circuit structure schematic diagram of a bandgap reference source circuit provided by an embodiment of the present invention;

[0030] Figure 2 is a circuit connection diagram of a two-stage operational amplifier circuit provided by an embodiment of the present invention;

[0031] Figure 3 It is a schematic diagram of the structure of a fully GaN integrated bandgap reference source circuit wafer provided by an embodiment of the present invention;

[0032] Figure 4 It is a flowchart of the steps of a method for preparing a full gallium nitride bandgap reference circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] The embodiment of the present invention provides a bandgap reference source circuit, comprising: a current mirror circuit, a two-stage operational amplifier circuit and a reference voltage output circuit; the current mirror circuit, the two-stage operational amplifier circuit and the reference voltage output circuit are electrically connected.

[0035] The current mirror circuit includes a lateral temperature sensor, a resistor and an enhancement transistor, and the current mirror circuit is used to generate a PTAT current with a positive temperature coefficient; the two-stage operational amplifier circuit includes an enhancement transistor, a depletion transistor and a resistor, and the two-stage operational amplifier circuit is used to clamp the drain voltage of the transistors on both sides of the current mirror in the current mirror circuit to keep the voltages at the two points equal; the reference voltage output circuit includes a lateral temperature sensor, a resistor and an enhancement transistor, and the reference voltage output circuit is used to output a reference voltage; wherein the voltage of the lateral temperature sensor in the current mirror circuit and the reference voltage output circuit has a negative temperature coefficient.

[0036] In some embodiments, Figure 1 A schematic diagram of a circuit structure of a bandgap reference source circuit provided by the present invention. Figure 1 As shown, the current mirror circuit includes: a first lateral temperature sensor D1, a second lateral temperature sensor D2, a first resistor R1, a first enhancement transistor M1, and a second enhancement transistor M2. Specifically, the anode of the first lateral temperature sensor D1, the anode of the second lateral temperature sensor D2, and the anode of the lateral temperature sensor in the reference voltage output circuit are all used to access the working voltage VDD; the cathode of the first lateral temperature sensor D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is simultaneously connected to the drain of the first enhancement transistor M1 and the positive input terminal Vin+ of the secondary operational amplifier circuit; the source of the first enhancement transistor M1 is grounded, and the gate of the first enhancement transistor M1 is simultaneously connected to the output terminal V OUT , the gate of the second enhancement transistor M2 is connected to the gate of the enhancement transistor M3 in the reference voltage output circuit; the source of the second enhancement transistor M2 and the source of the enhancement transistor M3 in the reference voltage output circuit are both grounded; the cathode of the second lateral temperature sensor D2 is simultaneously connected to the drain of the second enhancement transistor M2 and the reverse input terminal Vin- of the secondary operational amplifier circuit.

[0037] Here, the working principle of the current mirror circuit is: the same current can be generated in the two branches of the current mirror composed of M1 and M2. Since the current density flowing through D1 and D2 is inversely proportional to the area of ​​the diode, a voltage difference is generated across D1 and D2. Figure 1 The input terminal V X and V Y ) are the same, so the voltage difference between D1 and D2 is the voltage drop of R1, which ultimately determines the current of the current mirror.

[0038] In the present invention, the current source of the secondary operational amplifier circuit is generated by short-circuiting the gate and source of the depletion-type transistor. Exemplarily, Figure 2 A circuit connection diagram of a two-stage operational amplifier circuit provided by the present invention. Figure 2As shown, the secondary operational amplifier circuit includes: a fourth enhancement transistor M4, a fifth enhancement transistor M5, a sixth enhancement transistor M6, a seventh enhancement transistor M7, a first depletion transistor M8, a second depletion transistor M9, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6. Specifically, the gate of the fourth enhancement transistor M4 serves as the positive input terminal Vin+ of the two-stage operational amplifier circuit, wherein the positive input terminal Vin+ is the positive input terminal of the first-stage operational amplifier in the two-stage operational amplifier circuit, the drain of the fourth enhancement transistor M4 is simultaneously connected to one end of the third resistor R3 and the gate of the sixth enhancement transistor M6, wherein the gate of the sixth enhancement transistor M6 is the positive input terminal of the second-stage operational amplifier in the two-stage operational amplifier circuit, the other end of the third resistor R3 is used to access the working voltage VDD, the source of the fourth enhancement transistor M4 is connected to the drain of the first depletion-mode transistor M8; the gate of the fifth enhancement transistor M5 serves as the reverse input terminal Vin- of the two-stage operational amplifier circuit, wherein the reverse input terminal Vin- is the reverse input terminal of the first-stage operational amplifier, the drain of the fifth enhancement transistor M5 is simultaneously connected to one end of the fourth resistor R4 and the gate of the seventh enhancement transistor M7, wherein , the gate of the seventh enhancement transistor M7 is the inverting input terminal of the second stage operational amplifier, the other end of the fourth resistor R4 is connected to the operating voltage VDD, the source of the fifth enhancement transistor M5 is connected to the drain of the first depletion transistor M8, and the source and gate of the first depletion transistor M8 are connected to the ground; the drain of the sixth enhancement transistor M6 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is used to access the operating voltage VDD, the source of the sixth enhancement transistor M6 is connected to the drain of the second depletion transistor M9, the drain of the seventh enhancement transistor M7 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is used to access the operating voltage VDD, the source of the seventh enhancement transistor M7 is connected to the drain of the second depletion transistor M9, and the gate and source of the second depletion transistor M9 are grounded, and the drain of the sixth enhancement transistor M6 is connected to the output terminal V OUT connected.

[0039] Here, the working principle of the secondary op amp circuit is: when V X >V Y When the current mirror current is less than the set value, the input voltage difference of the secondary operational amplifier circuit is positive, the output voltage of the secondary operational amplifier circuit becomes larger, and the gate-source voltage of the current mirror increases, thereby increasing the current mirror current; conversely, when V X <V Y When the current mirror current is greater than the set value, the input voltage difference of the secondary op amp circuit is negative, the output voltage of the secondary op amp circuit becomes smaller, and the gate-source voltage of the current mirror decreases, thereby reducing the current mirror current. The secondary op amp circuit and the current mirror composed of M1 and M2 form a negative feedback network to keep V X 、VY The voltages at the two ports remain equal, so that the currents in the two branches of the current mirror are stably maintained at the set values.

[0040] In some embodiments, continue to refer to the above Figure 1 The reference voltage output circuit includes: a third lateral temperature sensor D3, a second resistor R2 and a third enhancement transistor M3. Specifically, the anode of the third lateral temperature sensor D3 is used to access the working voltage VDD, the cathode of the third lateral temperature sensor D3 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the third enhancement transistor M3, and the gate of the third enhancement transistor M3 is simultaneously connected to the gate of the enhancement transistor in the current mirror circuit and the output terminal V OUT The source of the third enhancement mode transistor M3 is connected to the ground, and the drain of the third enhancement mode transistor M3 is connected to the output terminal V REF connected.

[0041] Here, the working principle of the reference voltage output circuit is: the current of M1 and M2 in the D3 replica current mirror circuit has a positive temperature coefficient, the current passing through D3 increases with the increase of temperature, and the voltage of D3 has a negative temperature coefficient. By adjusting the ratio of R1 and R2, a reference voltage that does not change with temperature can be finally obtained.

[0042] Specifically, the above D1, D2 and D3 are all Schottky barrier field effect rectifiers.

[0043] An embodiment of the present invention further provides a full gallium nitride bandgap reference circuit, comprising: a wafer and connecting wires, on which all lateral temperature sensors, all resistors, all enhancement-mode transistors and all depletion-mode transistors in the bandgap reference source circuit proposed in the present invention are integrated; the connecting wires are used to connect the lateral temperature sensors, resistors, enhancement-mode transistors and depletion-mode transistors according to the connection method in the bandgap reference source circuit proposed in the present invention.

[0044] For example, Figure 3 The schematic diagram of the structure of the fully GaN integrated bandgap reference source circuit wafer provided by the present invention is as follows: Figure 3 As shown, the wafer includes, from bottom to top: a Si substrate, an AlN nucleation layer located on the upper surface of the Si substrate, an AlGaN buffer layer located on the upper surface of the AlN nucleation layer, a GaN channel layer located on the upper surface of the AlGaN buffer layer, an AlN insertion layer located on the upper surface of the GaN channel layer, an AlGaN barrier layer located on the upper surface of the AlN insertion layer, a P-GaN cap layer (i.e., a P-type GaN cap layer) located on the upper surface of the AlGaN barrier layer, and a passivation layer located on the upper surface of the P-GaN cap layer; wherein the GaN channel layer and the AlGaN barrier layer form a 2DEG near the AlN insertion layer.

[0045] Continue to refer Figure 3 The gate of each enhancement mode transistor is located in the first groove, the source is located in the second groove, and the drain is located in the third groove. The etching depth of the first groove extends downward from the upper surface of the passivation layer to the upper surface of the P-GaN cap layer, and the etching depths of the second groove and the third groove both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer.

[0046] Here, the realization principle of each enhancement-mode HEMT is: the built-in voltage generated in the P-GaN / AlGaN / GaN layer is greater than the polarization electric field generated by the piezoelectric effect of the AlGaN / GaN heterojunction, thereby raising the potential energy at the 2DEG channel to above the Fermi level, depleting the 2DEG and realizing an enhancement-mode HEMT.

[0047] Continue to refer Figure 3 The gate of each depletion-mode transistor is located in the fourth groove, the source is located in the fifth groove, and the drain is located in the sixth groove. The etching depth of the fourth groove extends downward from the upper surface of the passivation layer to the upper surface of the AlGaN barrier layer; the etching depths of the fifth and sixth grooves both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer.

[0048] Here, the realization principle of each depletion-mode HEMT is as follows: when no gate voltage is applied, 2DEG is generated near the AlGaN / GaN heterojunction due to piezoelectric polarization and spontaneous polarization, and the transistor remains normally on, realizing a depletion-mode HEMT.

[0049] Continue to refer Figure 3 The two ohmic electrodes of each resistor are respectively located in the seventh groove and the eighth groove, and the etching depths of the seventh groove and the eighth groove both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer.

[0050] Here, the realization principle of each 2DEG resistor (i.e., each resistor) is that 2DEG is generated near the AlGaN / GaN heterojunction due to piezoelectric polarization and spontaneous polarization to form a conductive channel. The resistance value of the resistor is adjusted by designing the distance of the ohmic electrodes and / or the channel width to realize the 2DEG resistor.

[0051] Continue to refer Figure 3 The cathode of each lateral temperature sensor is located in the ninth groove, a part of the anode is located in the tenth groove, another part of the anode covers a portion of the surface of the passivation layer, and a P-GaN cap layer is provided under the portion of the passivation layer covered by the anode. The etching depth of the ninth groove extends downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer, and the etching depth of the tenth groove extends downward from the upper surface of the passivation layer to the upper surface of the AlGaN barrier layer.

[0052] Here, the gate of each depletion-mode transistor, the gate of each enhancement-mode transistor, and the anode of each lateral temperature sensor are all Schottky metals.

[0053] Here, the implementation principle of each lateral temperature sensor is: the junction voltage of the Schottky diode formed by the Schottky anode and the AlGaN barrier layer has a negative temperature coefficient, and the conductive path formed by the Schottky anode and the P-GaN can increase the temperature sensitivity of the sensor.

[0054] The present invention also provides a method for preparing a full-gallium nitride bandgap reference circuit, which is used to prepare the full-gallium nitride bandgap reference circuit provided by the present invention, such as Figure 4 As shown, the method includes:

[0055] S1. Prepare an epitaxial wafer, which includes a Si substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a P-GaN layer from bottom to top;

[0056] S2, defining a gate P-GaN region of the enhancement mode HEMT and a P-GaN region of the lateral temperature sensor on the surface of the P-GaN layer, and etching downwards the P-GaN region except the gate P-GaN region of the enhancement mode HEMT and the P-GaN region of the lateral temperature sensor, and the etching depth extends to the AlGaN barrier layer;

[0057] S3, defining a mesa region on the surface of the AlGaN barrier layer, and etching downwards the region outside the mesa region, with the etching depth extending to the GaN channel layer, to obtain the current sample;

[0058] S4, depositing a first SiO2 passivation layer on the surface of the current sample;

[0059] S5, defining source and drain groove regions of the enhancement-mode HEMT, source and drain groove regions of the depletion-mode HEMT, a cathode groove region of the lateral temperature sensor, and an electrode groove region of the 2DEG resistor on the surface of the first SiO2 passivation layer, and etching the defined groove regions downwards, with the etching depth extending to the lower surface of the AlN insertion layer, to form source and drain grooves of the enhancement-mode HEMT, source and drain grooves of the depletion-mode HEMT, a cathode groove of the lateral temperature sensor, and an ohmic electrode groove of the 2DEG resistor;

[0060] S6, depositing an ohmic contact metal in the ohmic electrode groove;

[0061] S7, performing a rapid thermal annealing process on the ohmic contact metal to form an ohmic contact electrode;

[0062] S8, depositing a second SiO2 passivation layer on the surface of the current sample obtained after S7;

[0063] S9, defining a gate region of the enhancement-mode HEMT in the gate P-GaN region of the enhancement-mode HEMT, and etching downward to the upper surface of the P-GaN layer to form a gate groove of the enhancement-mode HEMT, and defining a gate groove region of the depletion-mode HEMT on the surface of the second SiO2 passivation layer, and etching downward to the upper surface of the AlGaN barrier layer to form a gate groove of the depletion-mode HEMT; defining an anode region of the lateral temperature sensor around the P-GaN region of the lateral temperature sensor, and etching downward to the upper surface of the AlGaN barrier layer to form an anode groove of the lateral temperature sensor;

[0064] S10, depositing Schottky metal in the gate groove of the enhancement-mode HEMT, the gate groove of the depletion-mode HEMT and the anode groove of the lateral temperature sensor to form the gate of the enhancement-mode HEMT, the gate of the depletion-mode HEMT and the anode of the lateral temperature sensor;

[0065] S11. Metallization is performed to interconnect the components by depositing metal to complete the preparation of the full gallium nitride bandgap reference circuit.

[0066] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0067] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0068] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0069] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A bandgap reference source circuit, characterized in that: include: Current mirror circuit, secondary operational amplifier circuit and reference voltage output circuit; The current mirror circuit, the secondary operational amplifier circuit and the reference voltage output circuit are electrically connected; The current mirror circuit includes a lateral temperature sensor, a resistor and an enhancement mode transistor, and is used to generate a PTAT current with a positive temperature coefficient; The secondary operational amplifier circuit includes an enhancement transistor, a depletion transistor and a resistor, and is used to clamp the drain voltage of the transistors on both sides of the current mirror in the current mirror circuit so that the voltages at the two points remain equal; The reference voltage output circuit includes a lateral temperature sensor, a resistor and an enhancement transistor, and is used to output a reference voltage; The voltage of the lateral temperature sensor in the current mirror circuit and the reference voltage output circuit has a negative temperature coefficient.

2. The bandgap reference source circuit according to claim 1, characterized in that: The current source of the secondary operational amplifier circuit is generated by short-circuiting the gate and source of the depletion-type transistor.

3. The bandgap reference source circuit according to claim 1, characterized in that: The current mirror circuit includes: a first lateral temperature sensor D1, a second lateral temperature sensor D2, a first resistor R1, a first enhancement transistor M1 and a second enhancement transistor M2; The anode of the first lateral temperature sensor D1, the anode of the second lateral temperature sensor D2 and the anode of the lateral temperature sensor in the reference voltage output circuit are all used to access the working voltage VDD; the cathode of the first lateral temperature sensor D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is simultaneously connected to the drain of the first enhancement transistor M1 and the positive input terminal Vin+ of the secondary operational amplifier circuit; the source of the first enhancement transistor M1 is grounded, and the gate of the first enhancement transistor M1 is simultaneously connected to the output terminal V OUT , the gate of the second enhancement transistor M2 is connected to the gate of the enhancement transistor in the reference voltage output circuit; the source of the second enhancement transistor M2 and the source of the enhancement transistor in the reference voltage output circuit are both grounded; the cathode of the second lateral temperature sensor D2 is simultaneously connected to the drain of the second enhancement transistor M2 and the reverse input terminal Vin- of the secondary operational amplifier circuit.

4. The bandgap reference source circuit according to claim 2, characterized in that: The secondary operational amplifier circuit includes: a fourth enhancement transistor M4, a fifth enhancement transistor M5, a sixth enhancement transistor M6, a seventh enhancement transistor M7, a first depletion transistor M8, a second depletion transistor M9, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; The gate of the fourth enhancement mode transistor M4 serves as the positive input terminal Vin+ of the two-stage operational amplifier circuit, wherein the positive input terminal Vin+ is the positive input terminal of the first stage operational amplifier in the two-stage operational amplifier circuit, the drain of the fourth enhancement mode transistor M4 is simultaneously connected to one end of the third resistor R3 and the gate of the sixth enhancement mode transistor M6, wherein the gate of the sixth enhancement mode transistor M6 is the positive input terminal of the second stage operational amplifier in the two-stage operational amplifier circuit, the other end of the third resistor R3 is used to access the working voltage VDD, the source of the fourth enhancement mode transistor M4 is connected to the drain of the first depletion mode transistor M8; The gate of the enhancement transistor M5 serves as the reverse input terminal Vin- of the secondary operational amplifier circuit, wherein the reverse input terminal Vin- is the reverse input terminal of the first-stage operational amplifier, the drain of the fifth enhancement transistor M5 is simultaneously connected to one end of the fourth resistor R4 and the gate of the seventh enhancement transistor M7, wherein the gate of the seventh enhancement transistor M7 is the reverse input terminal of the second-stage operational amplifier, the other end of the fourth resistor R4 is connected to the operating voltage VDD, the source of the fifth enhancement transistor M5 is connected to the drain of the first depletion transistor M8, and the source and gate of the first depletion transistor M8 are connected to the ground; The drain of the sixth enhancement-mode transistor M6 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is used to access the working voltage VDD. The source of the sixth enhancement-mode transistor M6 is connected to the drain of the second depletion-mode transistor M9. The drain of the seventh enhancement-mode transistor M7 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is used to access the working voltage VDD. The source of the seventh enhancement-mode transistor M7 is connected to the drain of the second depletion-mode transistor M9. The gate and source of the second depletion-mode transistor M9 are grounded. The drain of the sixth enhancement-mode transistor M6 is connected to the output terminal V OUT connected.

5. The bandgap reference source circuit according to claim 1, characterized in that: The reference voltage output circuit includes: a third lateral temperature sensor D3, a second resistor R2 and a third enhancement transistor M3; The anode of the third lateral temperature sensor D3 is used to access the working voltage VDD, the cathode of the third lateral temperature sensor D3 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the drain of the third enhancement transistor M3, and the gate of the third enhancement transistor M3 is connected to the gate of the enhancement transistor in the current mirror circuit and the output terminal VDD of the secondary operational amplifier circuit. OUT The source of the third enhancement mode transistor M3 is connected to the ground, and the drain of the third enhancement mode transistor M3 is connected to the output terminal V REF connected.

6. A full gallium nitride bandgap reference circuit, characterized in that: include: A wafer and connecting wires, wherein all lateral temperature sensors, all resistors, all enhancement-mode transistors and all depletion-mode transistors in the bandgap reference source circuit described in any one of claims 1 to 5 are integrated on the wafer; the connecting wires are used to connect the lateral temperature sensors, the resistors, the enhancement-mode transistors and the depletion-mode transistors according to the connection method in the bandgap reference source circuit described in any one of claims 1 to 5.

7. The all-gallium nitride bandgap reference circuit according to claim 6, characterized in that: The wafer comprises, from bottom to top, a Si substrate, an AlN nucleation layer located on the upper surface of the Si substrate, an AlGaN buffer layer located on the upper surface of the AlN nucleation layer, a GaN channel layer located on the upper surface of the AlGaN buffer layer, an AlN insertion layer located on the upper surface of the GaN channel layer, an AlGaN barrier layer located on the upper surface of the AlN insertion layer, a P-GaN cap layer located on the upper surface of the AlGaN barrier layer, and a passivation layer located on the upper surface of the P-GaN cap layer; wherein the GaN channel layer and the AlGaN barrier layer form a 2DEG near the AlN insertion layer; The gate of each enhancement mode transistor is located in the first groove, the source is located in the second groove, and the drain is located in the third groove, the etching depth of the first groove extends downward from the upper surface of the passivation layer to the upper surface of the P-GaN cap layer, and the etching depths of the second groove and the third groove both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer; The gate of each depletion-mode transistor is located in the fourth groove, the source is located in the fifth groove, and the drain is located in the sixth groove. The etching depth of the fourth groove extends downward from the upper surface of the passivation layer to the upper surface of the AlGaN barrier layer; the etching depths of the fifth groove and the sixth groove both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer; The two ohmic electrodes of each resistor are respectively located in the seventh groove and the eighth groove, and the etching depths of the seventh groove and the eighth groove both extend downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer; The cathode of each of the lateral temperature sensors is located in the ninth groove, a portion of the anode is located in the tenth groove, another portion of the anode covers a portion of the surface of the passivation layer, and the P-GaN cap layer is provided below the portion of the passivation layer covered by the anode, the etching depth of the ninth groove extends downward from the upper surface of the passivation layer to the lower surface of the AlN insertion layer, and the etching depth of the tenth groove extends downward from the upper surface of the passivation layer to the upper surface of the AlGaN barrier layer.

8. The all-gallium nitride bandgap reference circuit according to claim 7, characterized in that: The gate of each of the depletion-mode transistors, the gate of each of the enhancement-mode transistors, and the anode of each of the lateral temperature sensors are Schottky metals.

9. The all-gallium nitride bandgap reference circuit according to claim 7, characterized in that: The resistance value of each resistor is changed by changing the distance between the two ohmic electrodes of the resistor and / or the channel width.

10. A method for preparing a full gallium nitride bandgap reference circuit, characterized in that: For preparing the full gallium nitride bandgap reference circuit according to any one of claims 6 to 9, the method comprises: S1. Prepare an epitaxial wafer, wherein the epitaxial wafer comprises, from bottom to top, a Si substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a P-GaN layer; S2, defining a gate P-GaN region of the enhancement mode HEMT and a P-GaN region of the lateral temperature sensor on the surface of the P-GaN layer, and etching downwards the P-GaN region except the gate P-GaN region of the enhancement mode HEMT and the P-GaN region of the lateral temperature sensor, and the etching depth extends to the AlGaN barrier layer; S3, defining a mesa region on the surface of the AlGaN barrier layer, and etching downwards the region outside the mesa region, with the etching depth extending to the GaN channel layer, to obtain a current sample; S4, depositing a first SiO2 passivation layer on the surface of the current sample; S5, defining the source and drain groove regions of the enhancement-mode HEMT, the source and drain groove regions of the depletion-mode HEMT, the cathode groove region of the lateral temperature sensor, and the electrode groove region of the 2DEG resistor on the surface of the first SiO2 passivation layer, and etching the defined groove regions downwards, with the etching depth extending to the lower surface of the AlN insertion layer, to form the source and drain grooves of the enhancement-mode HEMT, the source and drain grooves of the depletion-mode HEMT, the cathode groove of the lateral temperature sensor, and the ohmic electrode groove of the 2DEG resistor; S6, depositing an ohmic contact metal in the ohmic electrode groove; S7, performing a rapid thermal annealing process on the ohmic contact metal to form an ohmic contact electrode; S8, depositing a second SiO2 passivation layer on the surface of the current sample obtained after S7; S9, defining a gate region of the enhancement-mode HEMT in the gate P-GaN region of the enhancement-mode HEMT, and etching downward to the upper surface of the P-GaN layer to form a gate groove of the enhancement-mode HEMT, and defining a gate groove region of the depletion-mode HEMT on the surface of the second SiO2 passivation layer, and etching downward to the upper surface of the AlGaN barrier layer to form a gate groove of the depletion-mode HEMT; defining an anode region of the lateral temperature sensor around the P-GaN region of the lateral temperature sensor, and etching downward to the upper surface of the AlGaN barrier layer to form an anode groove of the lateral temperature sensor; S10, depositing Schottky metal in the gate groove of the enhancement-mode HEMT, the gate groove of the depletion-mode HEMT and the anode groove of the lateral temperature sensor to form the gate of the enhancement-mode HEMT, the gate of the depletion-mode HEMT and the anode of the lateral temperature sensor; S11, metallization interconnection of various components is performed by depositing metal to complete the preparation of the full gallium nitride bandgap reference circuit.

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