Apparatus and method for aggressor queue based mitigation thresholds

Abstract

An apparatus and method for an aggressor queue based mitigation threshold. A memory device detects an aggressor row by changing a count value associated with the row when accessing the row and comparing the count value to a mitigation threshold. The identified aggressor rows are stored in an aggressor queue. The value of the mitigation threshold is set based on a number of addresses stored in the aggressor queue. For example, the threshold may increase as the number of addresses in the queue increases.

Description

Technical Field

[0001] The present disclosure relates to apparatus and methods for aggressor cohort-based mitigation thresholds. Background Art

[0002] Information can be stored in memory cells of a memory device. Memory cells can be organized at the intersection of word lines (rows) and bit lines (columns). The information in a memory cell can decay over time. For example, information can be stored as charge on a capacitor, which can decay over time. A memory device can perform a refresh operation to restore information and prevent information loss.

[0003] Certain access patterns can cause an increased rate of information decay in nearby memory cells (e.g., memory cells along nearby word lines). Memory devices can use various schemes to identify these access patterns so that additional targeted refresh operations can be performed. Some access patterns can overwhelm the memory's ability to perform targeted refresh operations, and it can request additional time from the controller for the targeted refresh operation. It may be desirable to reduce the instances in which the memory needs to request this additional time. Summary of the Invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: an aggressor queue circuit configured to store identified aggressor addresses; a counter circuit configured to receive a row address and change a count value associated with the row address; a threshold comparator circuit configured to compare the changed count value with a mitigation threshold and store the row address as an identified aggressor address in the aggressor queue; and a mitigation threshold circuit configured to set a value of the mitigation threshold based on the number of the identified aggressor addresses stored in the aggressor queue.

[0005] In another aspect, the present disclosure provides an apparatus comprising: a memory array comprising a plurality of word lines, each word line being associated with a row address and a count value; an aggressor queue comprising a plurality of slots, wherein the aggressor queue is configured to provide a used slot signal indicating a number of the plurality of slots storing addresses; an aggressor detection circuit configured to set a value of a mitigation threshold based on the used slot signal, and configured to determine whether a row address is an aggressor address based on a comparison of the count value with the mitigation threshold when a row address is accessed, and configured to store the aggressor row address in one of the plurality of slots.

[0006] In another aspect, the present disclosure provides a method comprising: receiving an address, changing a count value associated with the address and comparing the count value to a threshold; identifying the address as an aggressor address based on the comparison; adding the aggressor address to an aggressor queue; and changing a value of the threshold based on the number of aggressor addresses in the queue. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0009] Figure 3 is a block diagram of a layout of a portion of a column of memory devices according to some embodiments of the present disclosure.

[0010] Figure 4 is a timing diagram of access operations with adjustable mitigation thresholds according to some embodiments of the present disclosure.

[0011] Figure 5 is a flowchart of a method of setting a mitigation threshold according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its applications or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are presented in a manner that illustrates specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, when certain features are obvious to those skilled in the art, the detailed description of the features will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined solely by the appended claims.

[0013] Information in a memory array can be accessed through one or more access operations, such as read or write operations. During an example access operation, a word line can be activated based on a row address, and information from selected memory cells along the active word line can then be read or written based on which bit lines are accessed, which can be based on a column address. The memory array can be refreshed row by row (e.g., as part of an auto-refresh and / or self-refresh mode), where the memory cells along each row are periodically refreshed. The speed at which rows are refreshed (e.g., the maximum time any given row will go between refreshes) can be determined based on the expected rate of information decay.

[0014] Various access patterns to a row (aggressor row) can result in an increased rate of information decay in nearby memory cells (e.g., along the victim row). For example, 'row hammering' can involve repeated accesses to an aggressor row, which can increase the decay rate in adjacent rows (and / or rows further away). Therefore, it can be important to track the number of accesses to each row to determine whether it is an aggressor so that the victim row can be identified and refreshed as part of a targeted refresh operation. For example, each word line can have an associated count value that is used to determine how many times the word line has been accessed.

[0015] As the row is accessed, a count may be changed (e.g., incremented) and compared to a mitigation threshold. If the count exceeds the mitigation threshold, an address may be added to an aggressor queue. As a targeted refresh operation is performed, addresses are removed from the queue. If addresses are added faster than they are removed, the queue may become full. Because subsequent aggressor addresses may be lost (which can compromise data integrity), the memory may send an alarm signal to the controller when the aggressor queue becomes full. The controller may take one or more actions to allow more targeted refresh operations to occur (e.g., by pausing access operations, sending refresh management commands, or a combination thereof). However, this may reduce the availability of the memory, which is undesirable. The mitigation threshold may be set at a level based on a 'worst-case' scenario, which may make it easier to add addresses to the queue, leading to a situation where the queue fills up too quickly. Therefore, better aggressor queue management is needed.

[0016] The present disclosure relates to devices, systems, and methods for managing mitigation thresholds based on an aggressor queue. A mitigation threshold can be set based on the number of slots in the aggressor queue that are filled with aggressor addresses. In an example embodiment, when the aggressor queue is empty (no slots are filled), the mitigation threshold can be set to a minimum value. As the queue fills (as more slots are filled), the mitigation threshold increases until it reaches a maximum value (in some embodiments, the mitigation threshold may reach the maximum value when the queue is full, or in some embodiments, the mitigation threshold may reach the maximum value before the queue is full). The maximum mitigation threshold can still be below the risk level of damage expected to occur before performing a targeted refresh. By increasing the threshold based on the number of filled slots, adding a row requires fewer accesses when the queue is empty, and more accesses when the queue is full. This allows for more relaxed criteria for identifying aggressors when there is sufficient storage space for aggressors, but stricter criteria when space in the queue becomes more scarce. Therefore, when targeted refreshes occur rapidly compared to the rate at which aggressors are identified, rows with relatively low counts can be refreshed, but when many aggressors have been identified quickly, only the more dangerous rows are refreshed. This can help reduce instances where the queue becomes full and requires controller intervention, thereby helping to increase the uptime of the memory device.

[0017] Figure 1 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0018] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of FIG. 1 , the memory array 118 is shown as including eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0019] The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1In the embodiment of the present invention, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL are coupled to corresponding sense amplifiers (SAMPs). Data read from bit lines BL are amplified by sense amplifiers SAMPs and transmitted to read / write amplifiers 120 via complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B). Conversely, write data output from read / write amplifiers 120 is transmitted to sense amplifiers SAMPs via complementary main data lines MIOT / B, transfer gates TG, and complementary local data lines LIOT / B, and written into memory cells MC coupled to bit lines BL.

[0020] Some memory cells may be set aside as counter memory cells 126. The counter memory cells may store count values ​​XCount, each count value XCount being associated with one of the word lines. Each count value XCount may be stored in a counter memory cell 126 along the word line associated with the count value. The count value XCount may be stored as a binary number, with each bit stored in a memory cell along the word line. For clarity, Figure 1 A single bit line of counter memory cells 126 is shown. The number of counter memory cells along each word line can be based on the number of bits of the count value XCount. In some embodiments, additional counter memory cells (e.g., greater than the length of the number XCount) can be used, for example, to store error correction information for the count value XCount.

[0021] The counter memory cells 126 may be so called due to their purpose (storing count values) and, in some embodiments, may be structurally similar or identical to other memory cells of the array. In some embodiments, the counter memory cells 126 may be grouped together (e.g., at the ends of a word line). In other example embodiments, other distributions of the counter memory cells 126 along the word line may be used. In some embodiments, the counter memory cells 126 may not be directly accessible to an external device such as a controller (e.g., to prevent the count value from being overwritten). In other words, the bit lines associated with the counter memory cells 126 may not be accessed by normal column addresses.

[0022] The semiconductor device 100 may employ a plurality of external terminals, including a command and address terminal coupled to a command and address (C / A) bus for receiving commands and addresses and a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0023] The clock terminal is supplied with external clocks CK and / CK, which are provided to input circuit 112. The external clocks may be complementary. Input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to command decoder 110 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits included in input / output circuit 122. For example, it is provided to a data receiver to time the receipt of write data.

[0024] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell(s) to be accessed.

[0025] The command may be provided as an internal command signal via command / address input circuit 102 to command decoder 106. Command decoder 106 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing an operation. For example, command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0026] The device 100 may receive an access command as a row active command ACT. When the row active command ACT is received, the bank address BADD and the row address XADD are supplied in time with the row active command ACT.

[0027] The device 100 can receive an access command as a read command. When the read command is received and the bank address BADD and column address YADD are supplied in time with the read command, read data is read from the memory cell in the memory array 118 corresponding to the row address XADD and column address YADD. The read command is received by the command decoder 106, which provides an internal command so that the data read from the memory array 118 is provided to the read / write amplifier 120. The read data is output to the outside from the data terminal DQ via the input / output circuit 122. The access count XCount stored in the counter memory cell 126 of the row associated with the row address XADD is read to the refresh address control circuit 116, and the updated value of the access count XCount' is written back to the counter memory cell 126 of the row XADD.

[0028] Device 100 can receive an access command as a write command. When the write command is received and the bank address BADD and column address YADD are supplied in time with the write command, write data supplied to data terminal DQ is written to the memory cell in memory array 118 corresponding to the row and column addresses. The write command is received by command decoder 106, which provides an internal command so that the write data is received by the data receiver in input / output circuit 122. A write clock may also be provided to an external clock terminal to time the receipt of the write data by the data receiver in input / output circuit 122. The write data is supplied to read / write amplifier 120 via input / output circuit 122 and supplied by read / write amplifier 120 to memory array 118 for writing into memory cell MC. Similar to the read operation described above, the access count Xcount stored in counter memory cell 126 of the row associated with row address XADD is read to refresh address control circuit 116, and the updated value of access count Xcount′ is written back to counter memory cell 126 of row XADD.

[0029] Device 100 may also receive a command causing it to perform a refresh operation. For example, a memory controller may place device 100 in an auto-refresh mode and provide an auto-refresh signal, AREF. Device 100 may also enter a self-refresh mode in which the refresh signal is internally generated. Because the two operations may be substantially similar except for the source of the refresh signal, this disclosure will generally describe the auto-refresh operation (e.g., the refresh signal may be referred to as an 'auto-refresh signal'). However, it should be understood that this disclosure is also applicable to self-refresh (or other refresh modes).

[0030] Refresh signal AREF may be a pulse signal that is activated when command decoder 106 receives a signal indicating an auto-refresh command. In some embodiments, the auto-refresh command may be externally issued to memory device 100. In some embodiments, the auto-refresh command may be periodically generated by a component of the device (e.g., as part of a self-refresh mode). In some embodiments, refresh signal AREF may also be activated when an external signal indicates a self-refresh enter command. Refresh signal AREF may be activated once immediately after the command is input and may thereafter be cyclically activated at desired internal timings. Thus, the refresh operation may continue automatically. A self-refresh exit command may stop the automatic activation of refresh signal AREF and return it to an idle state.

[0031] The refresh signal AREF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which then refreshes the word line WL identified by the refresh row address RXADD. The refresh address control circuit 116 controls a certain type of refresh operation with timing based on the refresh signal AREF and generates and provides the refresh address RXADD. The refresh address control circuit 116 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or can operate based on internal logic.

[0032] The refresh address control circuit 116 can selectively output a target refresh address (e.g., a victim address) or a sequential refresh address (e.g., an auto-refresh address) as the refresh address RXADD. The sequential refresh address can be a sequence of addresses provided based on the activation of the auto-refresh refresh signal AREF. The refresh address control circuit 116 can cycle through the sequential address sequence at a rate determined by AREF. In some embodiments, the sequential address sequence can include all addresses in the memory bank 118. In some embodiments, the auto-refresh signal AREF can be issued at a frequency such that most or all addresses in the memory bank 118 are refreshed within a specific cycle (e.g., such that a maximum specified time exists between two consecutive sequential refreshes of a given word line). The frequency can be based on the expected rate at which information in the memory cells MC decays.

[0033] The refresh address control circuit 116 may also determine a target refresh address as an address that needs to be refreshed (e.g., a victim address corresponding to a victim row) based on the access pattern of nearby addresses in the memory array 118 (e.g., an aggressor address associated with an aggressor row). The refresh address control circuit 116 may monitor accesses to different word lines WL of the memory bank. When the row decoder 108 sends an access command to a particular row, the counter memory cells 126 along that row may have their information read as an access count Xcount (and any redundant information for error correction) to the refresh address control circuit 116. The refresh address control circuit 116 may determine the access count for the row based on the values ​​of the bits of the access count XCount.

[0034] The refresh address control circuit 116 may update the count value and determine whether the accessed row is an aggressor row based on the updated count value XCount'. For example, the updated count value XCount' may be compared with a mitigation threshold MT (or threshold value). If the updated count value XCount' exceeds the threshold (or meets / exceeds MT), the current row address may be determined to be an aggressor. If the current row is not an aggressor row, the updated count value XCount' may be written back to the counter memory unit 126 of the accessed word line. In some embodiments, the refresh address control circuit 116 may update the count value by decreasing the count value XCount. For example, the value of XCount may be decremented for each access.

[0035] If the refresh address control circuit 116 determines that the accessed row is an aggressor, the refresh address control circuit 116 may identify the row address XADD of the current word line as the aggressor address. The identified aggressor address is added to the aggressor address queue (or aggressor queue) for future target refresh operations. During the target refresh operation, the aggressor address in the queue can be used to determine one or more victim row addresses and provide them as refresh addresses RXADD. When the accessed row is determined to be an aggressor, the access count XCount associated with the row may be changed. For example, the access count may be reset (e.g., reset to an initial value) or decreased (e.g., decreased by an amount based on a mitigation threshold). In some embodiments, the threshold may be a maximum value of the count XCount, and when the count increases to exceed the threshold, the count may roll back to the initial value.

[0036] The refresh control circuit 116 sets the value of the mitigation threshold based on how full the aggressor queue is. The mitigation threshold may start at an initial value close to the initial state of the counter when the queue is empty and move further away from the initial state of the counter as the queue fills up. For example, if the counter value starts out with an initial value of 0 (or close to 0) and increases with each access, the mitigation threshold may start at a minimum value and then increase as the queue becomes fuller. For example, each time an aggressor address is added to the queue, the mitigation threshold rises, and each time an aggressor address is removed from the queue (e.g., due to a target refresh operation), the mitigation threshold falls.

[0037] The refresh address RXADD may be provided at a timing based on the timing of the refresh signal AREF. The refresh address control circuit 116 may have time slots corresponding to the timing of AREF and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be issued in a time slot (e.g., "stealing" the time slot) that would otherwise be allocated for the auto-refresh address. In some embodiments, certain time slots may be reserved for the target refresh address, and the refresh address control circuit 116 may determine whether to provide the target refresh address, not provide an address during the time slot, or instead provide the auto-refresh address during the time slot.

[0038] The refresh address control circuit 116 can use different methods to calculate the target refresh address based on the row address XADD that is identified as the aggressor address based on the access count. For example, the refresh address control circuit 116 can determine whether a given row is an aggressor address and then calculate and provide an address corresponding to the victim address of the aggressor address as the target refresh address. For example, the victim address may include word lines adjacent to the aggressor word line (e.g., XADD+1 and XADD-1) and / or may include word lines farther away (e.g., XADD+ / -2, XADD+ / -3, etc.). In some embodiments, more than one victim address may correspond to a given aggressor address. In this case, the refresh address control circuit 116 may queue up multiple target refresh addresses and provide the target refresh addresses sequentially when it determines that a target refresh address should be provided. The refresh address control circuit 116 may provide the target refresh address immediately, or may queue up the target refresh address to be provided at a later time (e.g., in the next time slot available for target refresh).

[0039] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is primarily used in the row decoder 108, the internal potential VARY is primarily used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many other peripheral circuit blocks.

[0040] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In one embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0041] Figure 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. Figure 2 It can be shown that a memory device (such as Figure 1 For example, the memory array 218 may implement Figure 1 The memory array 118, the row decoder 208 may implement Figure 1 The row decoder 108, the refresh control circuit 216 may implement Figure 1 The refresh control circuit 116, and so on.

[0042] Specific internal components and signals of refresh address control circuit 216 are shown to illustrate the operation of refresh address control circuit 216. For example, refresh control circuit 216 may include: RHR state control circuit 242, which determines whether to perform a sequential refresh or a targeted refresh; an aggressor address register or aggressor address queue 244, which stores identified aggressor addresses; and refresh address generator 250, which generates refresh address RXADD. Also shown are counter circuit 248, which adjusts the count values ​​XCount stored in counter storage cells 226 of array 218; threshold comparator circuit 246, which determines whether those counts are above a mitigation threshold MT; and mitigation threshold calculator circuit 252, which sets the MT level based on the state of aggressor queue 244. Counter circuit 248, threshold comparator circuit 246, and MT calculator circuit 252 may operate together as aggressor detector circuit 217.

[0043] The dashed lines around the refresh address control circuit 216, row decoder 208, and memory array 218 are shown to indicate that, in certain embodiments, each component within the dashed lines may correspond to a specific memory bank, and these components may be repeated for each of the memory banks. In some embodiments, the components shown within the dashed lines may be associated with each of the memory banks. Thus, there may be multiple refresh address control circuits 216 and row decoders 208. For the sake of brevity, only the components of a single memory bank will be described.

[0044] Figure 2 Components grouped together as part of the refresh control circuit 216 are shown, such as the counter 248, the mitigation threshold calculator circuit 252, and the threshold comparator 246. However, one or more of these components may be spatially distributed throughout the memory. For example, the aggressor detector circuit 217, which includes the counter circuit 248, the mitigation threshold calculator circuit 252, and the threshold comparator 246, may be spatially located in a logic region closer to each word line, while other components of the refresh control circuit may be located in a memory bank logic region. To illustrate the spatial distribution, two separate boxes are shown for the refresh control circuit 216, with the lower box representing the components of the aggressor detector circuit 217. Other distributions may be used in other example embodiments.

[0045] DRAM interface 240 can provide one or more signals to address refresh control circuitry 216 and row decoder 208, which in turn (along with a column decoder (not shown)) can perform access operations on memory array 218. When a row of memory array 218 is accessed, the values ​​of counter memory cells 226 along that row are read to counter circuitry 248. For example, counter memory cells 226 can store bits of a binary number representing a count value. For example, if the number is a 16-bit number, 16 or more counter memory cells can store the bits of the number. In some embodiments, counter memory cells 226 can provide additional information that can be used for count error correction.

[0046] The counter 248 may determine the value of the access count for the row based on the value read from the counter memory unit 226. The counter 248 may be a count control circuit that manages the value of the count stored in the counter memory unit 226 (e.g., by reading the original data in the counter memory unit 226 as a value, writing a new value to the counter memory unit 226, etc.). The counter circuit 248 may change the count value (e.g., by incrementing the count value) and provide the changed count value to the threshold comparator 246. The threshold comparator 246 may determine whether the changed count value exceeds the threshold MT (e.g., whether the value is greater than the threshold or greater than or equal to the threshold). If the value does not exceed the threshold (e.g., if the value is less than the threshold or less than or equal to the threshold), the counter circuit 248 may write the changed count back to the counter memory unit 226. If the value does exceed the threshold, the current address XADD may be determined to be the aggressor address HitXADD, and the threshold comparator circuit 246 may provide the aggressor detected signal Agg to the aggressor queue 244. In response to signal Agg, aggressor address register 244 stores row address XADD. Also in response to signal Agg, counter circuit 248 may change count value XCount. In some embodiments, the count value may be reset (e.g., to an initial value) or change in a direction opposite to the direction in which it changes in response to an access (e.g., if the count is incremented in response to an access, it may be decremented in response to signal Agg). In some embodiments, the change in count value may be inherent. For example, mitigation threshold MT may be set to the maximum value of count value XCount, and when XCount reaches the threshold and increments again, the count may roll back to the initial value (e.g., 0).

[0047] Aggressor address register 244 includes several 'slots,' each capable of storing a row address identified as an aggressor, HitXADD. For example, a slot may represent a number of latches capable of storing bits of a row address. The aggressor queue may have a slot count (or depth) that indicates how many aggressor addresses can be stored at a time. Aggressor address register 244 provides a signal, UsedSlot, indicating how many slots are currently full. When all slots contain addresses, aggressor queue 244 also provides a signal, Full. In response to the Full signal, DRAM interface 240 may provide an alert signal to the memory controller.

[0048] The mitigation threshold calculation circuit 252 sets the value of the mitigation threshold MT based on the state of the aggressor address register 244. The mitigation threshold calculation circuit 252 calculates the value of the mitigation threshold MT based on the signal UsedSlot from the aggressor address register 244. The mitigation threshold calculation circuit 252 can use any method to generate the mitigation threshold based on UsedSlot. For example, a linear function, a nonlinear function, or a step function can be used.

[0049] In an example embodiment in which the counter circuit 248 increments the value of XCount in response to an access, the mitigation threshold calculation circuit 252 may set MT to a minimum value when the signal UsedSlot indicates that the aggressor queue 244 is empty (e.g., does not store any aggressor addresses), and increase the value of MT when the signal UsedSlot indicates that more slots have been used. In some embodiments, MT may reach a maximum value before the aggressor queue 244 is full and then remain at the maximum value. In some embodiments, because the signal UsedSlots indicates that more slots have been used, MT may continue to increase until the maximum value of UsedSlots is reached (e.g., all slots are full).

[0050] In some embodiments, the maximum value of the mitigation threshold may be represented by the following equation 1:

[0051] MT MAX ≤ DHL – GAP – MD MAX Equation 1

[0052] Where DHL represents the process limit of the device, GAP represents the buffer, and MD MAX Indicates the mitigation delay when the queue is full. The process limit DHL is a device-specific value that represents the number of accesses at which information loss is expected based on the device layout / architecture, etc. The buffer GAP is a value that can be used to add buffering to help ensure that the mitigation threshold is always below DHL. Maximum Mitigation Delay MD MAX Indicates the maximum expected time required to flush victims of a certain address from the queue when the queue is full.

[0053] The RHR state controller 242 may provide a signal RHR to indicate that a target refresh operation, such as a row hammer refresh (e.g., a refresh of a victim row corresponding to an identified aggressor row), should occur. The RHR state controller 242 may also provide an internal refresh signal IREF to indicate that an auto-refresh operation should occur. In response to activation of RHR, the aggressor address register 244 may provide an aggressor address HitXADD, and the refresh address generator 250 may provide a refresh address RXADD, which may be one or more victim addresses associated with HitXADD. In response to IREF, the refresh address generator 250 may provide an auto-refresh address as the refresh address RXADD. The row decoder 208 may perform a refresh operation in response to the refresh address RXADD and the row hammer refresh signal RHR. The row decoder 208 may perform a sequential refresh operation based on the refresh address RXADD and the internal refresh signal IREF.

[0054] DRAM interface 240 may represent one or more components that provide signals to a memory bank. In some embodiments, DRAM interface 240 may represent a component coupled to a semiconductor memory device (e.g., Figure 1 In some embodiments, DRAM interface 240 may represent a component such as Figure 1 The command address input circuit 102, the address decoder 104, and / or the command decoder 106 of the memory array 218 may be configured to receive a row address XADD, an auto-refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF may be a periodic signal that indicates when an auto-refresh operation will occur. The activation signal ACT may be provided to activate a given bank of memory. The precharge signal Pre may be provided to precharge a given bank of memory. The row address XADD may be a signal that specifies one or more specific word lines of the memory array 218 and may be a signal comprising multiple bits that may be transmitted serially or in parallel.

[0055] In some embodiments, the counter 248 and the threshold comparator 246 may be physically close to the memory array 218, making the counter bus XCount relatively short compared to other buses in and out of the memory array 218. When the comparator 246 or the counter 248 determines that the value of XCount exceeds the threshold, a signal Agg may be sent to the aggressor address register 244 (and / or other components of the address refresh control circuitry 216). In some embodiments, the counter 248 and the comparator 246 may be closer to the memory array 218 than other components of the refresh address control circuitry 216 (e.g., the RHR state controller 242, the aggressor address register 244, and / or the refresh address generator 250). In some embodiments, the counter 248 and the threshold comparator 246 may be circuitry local to the memory array 218, while the other components of the refresh address control circuitry 216 may be bank-level circuitry. In some embodiments, only the signal Agg needs to reach the bank-level circuitry, which can reduce the area and power required for the XCount bus.

[0056] The RHR state controller 242 can receive an auto-refresh address AREF and provide a row hammer refresh signal RHR. The auto-refresh signal AREF can be generated periodically and can be used to control the timing of refresh operations. The memory device can perform a series of auto-refresh operations to periodically refresh the rows of the memory device. The RHR signal can be generated to indicate that the device should refresh a specific target row (e.g., a victim row) rather than an address from the auto-refresh address sequence. The RHR state controller 242 can use internal logic to provide the RHR signal. In some embodiments, the RHR state controller 242 can provide the RHR signal based on a specific number of activations of AREF (e.g., every 4 AREF activations). The RHR state controller 242 can also provide an internal refresh signal IREF, which can indicate that an auto-refresh operation should occur. In some embodiments, the RHR and IREF signals can be generated so that they are not simultaneously active (e.g., both are not at a high logic level at the same time).

[0057] The refresh address generator 250 may receive a row hammer refresh signal RHR and a matching address HitXADD. The matching address HitXADD may represent an aggressor row. The refresh address generator 250 may determine the location of one or more victim rows based on the matching address HitXADD and provide the locations as the refresh address RXADD. In some embodiments, the victim rows may include rows physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD-1). In some embodiments, the victim rows may also include rows physically adjacent to the aggressor row (e.g., HitXADD+2 and HitXADD-2). The relationship between the victim rows and the identified aggressor rows may be used in other examples.

[0058] The refresh address generator 250 may determine the value of the refresh address RXADD based on the row hammer refresh signal RHR and the internal auto-refresh signal IREF. In some embodiments, when the signal IREF is inactive, the refresh address generator 250 may provide one of a series of auto-refresh addresses. When the signal RHR is active, the refresh address generator 250 may provide a target refresh address (e.g., a victim address) as the refresh address RXADD.

[0059] The row decoder 208 may perform one or more operations on the memory array 218 based on the received signals and addresses. For example, in response to the activation signal ACT and the row address XADD (and IREF and RHR at low logic levels), the row decoder 208 may direct one or more access operations (e.g., read operations) to the designated row address XADD. In response to the RHR signal being active, the row decoder 208 may refresh the refresh address RXADD.

[0060] Figure 3 is a block diagram of a layout of a portion of a memory device column according to some embodiments of the present disclosure. Memory device 300 may represent the layout of a portion of a memory device, such as Figure 1 118. The memory device 300 shows an inset of a target refresh circuit 340 showing details of a portion of a refresh control circuit that may implement, for example, Figure 1 116 and / or Figure 2 The refresh control circuit portion 216 is a circuit diagram of a refresh control circuit. Figure 3 The diagram of FIG. 1 shows an example layout and implementation, which represents where certain circuits related to a targeted refresh operation may be located within a memory device.

[0061] Memory device 300 shows a bank 310 including a memory array 312 with bit lines (shown as vertical lines) coupled to GIO lines through LIO lines and from the GIO lines to a bank logical region 320 and a central region 330 associated with the bank. Figure 3 Only a single bank is discussed, but the memory device 300 may include multiple banks, such as 310, each of which may include a similar layout and bank logic area 320. The central area 330 may be coupled to the multiple banks and may include circuits commonly used by the multiple banks. The bank logic area 320 includes a target refresh circuit 340 that can be used to perform a target refresh operation on the bank 310, while the central area includes other refresh circuits 338. The target refresh circuit includes an aggressor detector circuit 350 (e.g., Figure 2 217), which is used to detect invaders based on the count value and the mitigation threshold MT.

[0062] The central logic region 330 may be positioned in the central region of a chip housing the memory device 300. The central logic region 330 may be elongated in a first direction (in Figure 3 310 can be arranged in two rows of side-by-side memory banks, with each memory bank arranged along either side of the central logic region 330. Each memory bank can be positioned in a second direction from the elongated axis of the central logic region 330, wherein the second direction is perpendicular to the first direction.

[0063] Memory bank 310 includes a row decoder 314 (e.g., Figure 1 108 and / or Figure 2 208 ), which activates a word line (shown here as horizontal or elongated in a first direction). Example word lines are shown, along with several example bit lines in section 312 of memory bank 310. The bit lines are coupled to GIOs via LIOs, which are coupled to data terminals 332 in central region 330 via memory bank logic region 320. Memory bank logic region 320 can be positioned between central logic region 330 and memory bank 310.

[0064] The memory bank logic section 320 includes a command logic circuit 324, a target refresh circuit 340, and a counter circuit 322 (eg, Figure 2 248). The central area 330 includes data or DQ terminals 332, which send data to the controller or receive data from the controller. The central area 330 also includes a command decoder 336 (e.g., Figure 1 110), refresh control circuit 338 and mode register 334 that stores the memory settings. The central area 330 also includes alarm logic 339, which can be used to send an alarm signal to the controller.

[0065] The refresh control circuit 338 and the target refresh circuit 340 may be implemented together, for example Figure 1 116 and / or Figure 2 As described in more detail herein, the target refresh circuit 340 may include, for example, a threshold calculation circuit 352 (e.g., Figure 2 252), aggressor register and control circuit 354 (e.g., Figure 2 244 and 246) and components of victim computation circuitry 342 (e.g., which may implement part of refresh address generator 250) and mitigation circuitry 344. Mitigation computation circuitry 352, aggressor queue 354, and counter 322 may be part of aggressor detector circuitry 350. Figure 2 In an embodiment, some components are shared between the sequential refresh operation and the target refresh operation, such as the refresh address generator circuit. Figure 3In the embodiment, these functions are separated, where the targeted refresh circuit 340 implements the targeted refresh operation, while the refresh control circuit 338 implements the sequential refresh operation and the timing and type of the refresh operation.

[0066] During an access operation, command decoder 336 receives an access command (e.g., a read or write command). Based on the received row and column addresses, row decoder 314 activates the word line, and column decoder (not shown) couples the selected bit line to the GIO. Counter memory cells along the word line are read out along their corresponding GIO lines to counter circuit 322, which updates the count and provides it to target refresh circuit 340.

[0067] The target refresh circuit 340 includes an aggressor queue circuit 350, which includes a threshold calculation circuit 352 and an aggressor queue 354 (which also includes associated control circuitry). Figure 3 In an embodiment, the aggressor queue 354 may be a FIFO register. The threshold calculation circuit 352 sets the mitigation threshold value. When an address XADD is detected as an aggressor HitXADD based on its count exceeding MT, it is added to the queue 354, and the queue 354 updates the signal UsedSlot. The MT calculation circuit 352 updates the value of MT based on the value of UsedSlot. When a target refresh operation is required, the queue 354 provides the stored aggressor HitXADD to the victim calculation circuit 342 (and updates the value of UsedSlot), which generates the refresh address RXADD. The mitigation circuit 344 includes various timing and command circuits that instruct the row decoder 314 to refresh the word line associated with RXADD.

[0068] exist Figure 3 In the embodiment of the present invention, the mitigation threshold calculation circuit 352 uses the settings stored in the mode register 334 to determine the current value of the mitigation threshold. The mode register 334 stores the settings of the base MT and the MT step size. The base MT setting sets the minimum value of the MT. The MT step size sets the step size, and for each increment of the UsedSlot, the MT is set by the following equation 2:

[0069] MT = Basic MT + MT Step Size * UsedSlot Equation 2

[0070] The values ​​of the MT step size and the base MT may be settings that can be adjusted by a client or other user of the memory to control the behavior of the MT calculation circuit 352. In some embodiments, MT calculation may be disabled, for example, by setting the base MT to a desired value and the MT step size to 0. Other methods of determining MT may be used in other example embodiments.

[0071] If the aggressor queue 354 becomes full, it provides a full signal or full flag to the alarm logic 339 in the central block 330. In response to the full signal, the alarm logic provides an alarm signal to the controller. For example, by providing an alarm signal at an active level along an alarm pin / alarm bus. In response to the alarm signal, the controller may provide a refresh management command that causes the target refresh operation to be performed.

[0072] Figure 4 is a timing diagram of access operations with adjustable mitigation thresholds according to some embodiments of the present disclosure. Figure 4 A timing diagram 400 is shown. In some embodiments, the timing diagram 400 may represent operations in a memory, such as Figure 1 100, Figure 2 200 and / or Figure 3 of 300.

[0073] Timing diagram 400 shows a set of tables 410-460, each of which represents an aggressor queue or aggressor register (e.g., Figure 2 244 and / or Figure 3 The timing diagram shows a set of row accesses along the command / address bus, showing access commands for different row addresses (labeled herein as i, j, m, l, and n), and the status of the row counter or PRHT counter XCount associated with the row address. Commands are also received along the command / address bus. An alarm signal / alarm bus is also shown.

[0074] Timing diagram 400 shows a scenario set up to illustrate how the mitigation threshold MT varies. In this illustrative example, each row is repeatedly accessed until the mitigation threshold is exceeded and the row address is added to the queue. Command mitigation shows when a target refresh operation is performed.

[0075] Example aggressor queues 410-460 include several slots (each shown as a row in the table), each of which stores an identified aggressor address, two aggressor flags, and input and output pointers InP and OutP. When an address is first added to the queue, its address is added to the queue and the first aggressor flag, RHR1, is set. If the same address is identified again, the second aggressor flag, RHR2, may be set. Addresses with both aggressor flags set can be refreshed only if one aggressor flag is set. Once a targeted refresh operation (or mitigation) is performed on the victim storing the address, both of its flags are reset to an unset state. This clears the row count (but the address cannot be removed until it is overwritten with a new address).

[0076] Table 410 shows the aggressor queue in its first state, where row address j has just been identified as an aggressor. Prior to the state shown in Table 410, row address i was accessed 700 times, which is the base MT in this example. Address i was added to the empty queue and its slot flag, RHR1, was set. Table 410 shows the state after row j has been accessed 750 times. Because the queue contains one address, the threshold is increased to 750. Therefore, after 750 accesses, address j is also added to the queue and its RHR1 flag is set.

[0077] Table 420 shows the state of the queue after mitigation is performed (e.g., due to an RFM command or internal logic during an auto- or self-refresh operation). Because address i was added first, its victim row is refreshed and flag RHR1 is unset. Because there is now only one address in the queue, MT returns a value of 750. By the time of Table 430, the queue contains three addresses, one of which (row m) has both flags set.

[0078] Jumping forward in time, at the time represented by table 440, all but one row in the queue are full. The mitigation threshold has risen to a value of 1000. When row n is accessed 1000 times, an address is added to the queue, as represented by table 450, however, at this point the queue is full. In response to this, the alarm signal is activated. In this embodiment, the alarm signal may be active low, so its logic state may change from logic high to logic low. The controller may issue a mode register read MRR operation in response to the alarm signal becoming active to determine which problem caused the alarm signal to be active. In response to performing the mitigation, in this case in response to a refresh management command from the controller. As shown in table 460, this results in the three rows of victims being refreshed, which in turn means that the queue is no longer empty. The alarm signal returns to an inactive level.

[0079] Figure 5 is a flow chart of a method for setting a mitigation threshold according to some embodiments of the present disclosure. In some embodiments, the method 500 may be implemented by one or more of the systems or devices described herein. For example, the method may be implemented by Figures 1 to 3 Executed by the memory devices (or portions thereof) 100, 200 and / or 300.

[0080] Method 500 begins at block 510, which depicts receiving an address, changing a count value associated with the address, and comparing the count value to a threshold. The address may be received as part of an access operation to a memory cell along a word line associated with the address. For example, method 500 may include receiving an address from a controller along a CA bus. Method 500 may include accessing a counter memory cell (e.g., a memory cell) along a word line associated with the address. Figure 1 126 and / or Figure 2226) reads the count value, and uses a counter circuit (for example, Figure 2 248 and / or Figure 3 322) modifies the count value and writes the modified count value back to the counter memory unit. In some embodiments, the change may include changing the count value in a first direction, such as by incrementing the count value.

[0081] Block 510 may be followed by block 520, which describes identifying the address as an aggressor address based on the comparison. For example, method 500 may include identifying the address as an aggressor if the count value exceeds a threshold. Method 500 may include changing the count value in a second direction opposite to the first direction in response to determining that the address is an aggressor address. For example, if the first direction increases the count value (e.g., by incrementing it for each access), the second direction may include decreasing the count value (e.g., by subtracting a value, such as a threshold, or resetting the count value to an initial value in response to determining that the address is an aggressor).

[0082] Block 520 may be followed by block 530, which depicts adding the aggressor address to an aggressor queue (e.g., Figure 2 244 and / or Figure 3 354). Method 500 may include determining whether there is an open slot in the aggressor queue and storing the aggressor address identified in block 520 in the open slot.

[0083] Block 530 may be followed by block 540, which describes changing the value of the threshold based on the number of aggressor addresses in the queue. For example, method 500 may include changing the threshold in a first direction (e.g., increasing) in response to adding an address to the queue, and changing the threshold in a second direction (e.g., decreasing) in response to removing an address from the queue. In some embodiments, method 500 may include setting the value of the threshold based on a base threshold (e.g., base MT) plus the product of the number of addresses in the queue and the threshold step size (e.g., MT step size * UsedSlot). The base threshold and the threshold step size may be settings of a mode register.

[0084] The method 500 may include performing a targeted refresh operation on one or more addresses based on a selected aggressor address in the aggressor queue and removing the selected aggressor address from the aggressor queue. In some embodiments, the method 500 may include providing a queue full signal when the aggressor queue becomes full (e.g., when the last slot is filled), and activating an alarm signal in response to the queue full signal.

[0085] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in a separate device or device portion according to the present systems, devices, and methods.

[0086] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the present system has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present system as subsequently set forth in the appended claims. Accordingly, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: an aggressor queue circuit configured to store identified aggressor addresses; a counter circuit configured to receive a row address and to change a count value associated with the row address; a threshold comparator circuit configured to compare the changed count value to a mitigation threshold and store the row address as an identified aggressor address in the aggressor queue; and A mitigation threshold circuit is configured to set a value of the mitigation threshold based on a number of the identified aggressor addresses stored in the aggressor queue.

2. The apparatus of claim 1, further comprising a memory array comprising word lines associated with row addresses, wherein the count values ​​are stored in memory cells along the word lines.

3. The apparatus of claim 1, wherein the mitigation threshold circuit is configured to increase the mitigation threshold as the number of addresses in the aggressor queue increases.

4. The apparatus of claim 1, wherein the counter circuit is configured to increment the count value when the row address is received as part of an access operation.

5. The apparatus of claim 1 , further comprising a refresh address generator configured to generate at least one refresh address based on a selected one of the identified aggressor addresses in the aggressor queue circuit as part of a targeted refresh operation, wherein the selected one of the identified aggressor addresses is removed from the aggressor queue circuit in response to the targeted refresh operation.

6. The apparatus of claim 1, further comprising an alarm logic circuit configured to issue an alarm signal along an alarm bus when the aggressor queue circuit is full.

7. The apparatus of claim 1 , further comprising a mode register configured to store a base threshold and a threshold step value, wherein the mitigation threshold circuit is configured to set the value of the mitigation threshold based on the base threshold plus a product of the threshold step value and a number of the identified aggressor addresses stored in the aggressor queue circuit.

8. A device comprising: a memory array including a plurality of word lines, each word line being associated with a row address and a count value; an aggressor queue comprising a plurality of slots, wherein the aggressor queue is configured to provide a used slot signal indicating a number of the plurality of slots storing addresses; an aggressor detection circuit configured to set a value of a mitigation threshold based on the used slots signal, and configured to determine whether a row address is an aggressor address based on a comparison of the count value with the mitigation threshold when accessing a row address, and configured to store the aggressor row address in one of the plurality of slots.

9. The apparatus of claim 8, wherein the memory array comprises a plurality of counter memory cells along each of the plurality of word lines, wherein the plurality of counter memory cells are configured to store the count values ​​associated with the word lines.

10. The apparatus of claim 8, further comprising a refresh address generator configured to generate a refresh address based on a selected one of the memory addresses in the aggressor queue as part of a targeted refresh operation, wherein the selected one of the memory addresses is removed from the aggressor queue in response to the targeted refresh operation.

11. The apparatus of claim 8, further comprising an aggressor detection circuit configured to change the count value in a first direction when the row is accessed and configured to reset the count value when the address is added to the queue.

12. The apparatus of claim 8, wherein the aggressor queue is configured to issue a queue full signal in response to all of the plurality of slots being filled, The apparatus further includes an alarm logic circuit configured to issue an alarm signal in response to the queue full signal.

13. The apparatus of claim 8, wherein the aggressor detection circuit is configured to increase the mitigation threshold when the used slots signal indicates a higher number of the plurality of slots are filled, and is configured to decrease the mitigation threshold when the used slots signal indicates a lower number of the plurality of slots are filled.

14. A method comprising: receiving an address, changing a count value associated with the address and comparing the count value to a threshold; identifying the address as an aggressor address based on the comparing; adding the aggressor address to an aggressor queue; as well as The value of the threshold is varied based on the number of aggressor addresses in the queue.

15. The method according to claim 14, further comprising: changing the value of the threshold in a first direction in response to increasing the number of aggressor addresses in the queue; and In response to decreasing the number of aggressor addresses in the queue, changing the value of the threshold in a second direction opposite to the first direction.

16. The method of claim 14, further comprising changing the value of the threshold by adding a base threshold size to a threshold step size multiplied by the number of the aggressor addresses in the queue.

17. The method of claim 14, further comprising performing a targeted refresh operation on the aggressor address and removing the aggressor address from the aggressor queue in response to the targeted refresh operation.

18. The method of claim 14, further comprising receiving the address as part of performing an access operation on a word line associated with the address.

19. The method of claim 18, wherein changing the count value comprises reading the count value from a memory cell along the word line, changing the count value, and writing the changed count value back to the memory cell.

20. The method of claim 14, further comprising activating an alarm signal when the aggressor queue becomes full.

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