Multi-conditional branch instructions for conditional branch operations

Abstract

The invention discloses a multi-conditional branch instruction for conditional branch operations, and various embodiments of the present disclosure relate to conditional execution of program code. In an example embodiment, a system is provided that includes instruction fetch circuitry, decoder circuitry, and multi-conditional branch circuitry. The instruction fetch circuitry is configured to fetch a multi-conditional branch instruction (MCBI) from the memory. The MCBI identifies a plurality of state registers and a plurality of branch destinations. A plurality of state registers of the MCBI represent registers that hold results of the plurality of conditional evaluations such that each state register corresponds to a different conditional evaluation of the plurality of conditional evaluations. Similarly, multiple branch destinations of the MCBI also correspond to different ones of the multiple condition evaluations. The instruction fetch circuitry provides the MCBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the multi-conditional branch circuitry to execute the multi-conditional branch instruction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to and claims the benefit of priority of Indian Provisional Patent Application No. 202341042580, filed on June 23, 2023, and entitled “A technique for optimizing decision tree and switch statement execution in a CPU”, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to computing hardware and software, and particularly to multiple conditional branch instructions. Background Art

[0004] Conditional execution describes a method of executing program code in a non-sequential manner. Conditional branch statements represent a type of program statement that supports conditional execution of a program. For example, a conditional branch statement, when compiled into assembly code, may cause (one or more) program instructions to branch to another part of the program when a specified condition is true.

[0005] A switch statement represents a type of multi-conditional branching statement. Generally speaking, a switch statement identifies multiple execution cases and corresponding condition evaluations for each of the multiple execution cases. An execution case represents a program function that is executed when the corresponding condition evaluation is true. For example, a switch statement may identify two execution cases, such that the program branches to a first execution case when a first condition evaluation is true, or the program branches to a second execution case when a second condition evaluation is true.

[0006] Current methods for executing switch statements include a series of comparison and branch instructions. For example, in the switch statement above, current technology can utilize a first comparison instruction to perform a first conditional evaluation, and then utilize a first branch instruction to determine where to branch to in the program code. If the first conditional evaluation is true, the program branches to the first execution case, otherwise the program sequentially continues to the second comparison instruction. If the program continues to the second comparison instruction, the second comparison instruction is followed by a second branch instruction, which determines where to proceed next in the program.

[0007] Problematically, many current methods for executing switch statements (and other multi-conditional branch statements) are limited to checking one condition at a time. Therefore, devices that implement conditional branching techniques can be expensive in execution cycles. Summary of the invention

[0008] Improvements to the compilation and execution of conditional branch statements are disclosed herein. In various example embodiments, a multiple conditional branch instruction (MCBI) is introduced that directs a processing system or a component thereof to perform a conditional branch operation based on the results of multiple condition evaluations.

[0009] In one example embodiment, a system includes an instruction fetch circuit system, a decoder circuit system coupled to the instruction fetch circuit system, and a multi-conditional branch circuit system coupled to the decoder circuit system. The instruction fetch circuit system fetches a multi-conditional branch instruction (MCBI) from a memory. The MCBI identifies multiple state registers and multiple branch destinations. The multiple state registers of the MCBI represent registers that store the results of multiple conditional evaluations, so that each state register corresponds to a different conditional evaluation in the multiple conditional evaluations. Similarly, the multiple branch destinations of the MCBI also correspond to different conditional evaluations in the multiple conditional evaluations. The instruction fetch circuit system provides the MCBI to the decoder circuit system. In response, the decoder circuit system causes the multi-conditional branch circuit system to execute the MCBI.

[0010] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. It should be understood that this summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Many aspects of the present disclosure may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, but rather emphasize the clear illustration of the principles of the present disclosure. In addition, in the drawings, similar reference numerals represent corresponding parts throughout several views. Although several embodiments are described in conjunction with these drawings, the present disclosure is not limited to the embodiments disclosed herein. On the contrary, it is intended to cover all alternatives, modifications, and equivalents.

[0012] Figure 1 An operating environment in an embodiment is shown.

[0013] Figure 2 The multi-conditional branching process in an embodiment is shown.

[0014] Figure 3 Another multi-conditional branching process in an embodiment is shown.

[0015] Figure 4A and Figure 4B An operation sequence in an embodiment is shown.

[0016] FIG. 5A to FIG. 5C A multi-conditional branch circuit and related operation scenarios in an embodiment are shown.

[0017] Figure 6 An operating environment in an embodiment is shown.

[0018] FIG. 7A to FIG. 7C An operation scenario in an embodiment is shown.

[0019] Figure 8 A computing system suitable for implementing the various operating environments, architectures, processes, scenarios, and sequences discussed below with respect to other figures is shown. DETAILED DESCRIPTION

[0020] This article discloses techniques for improving the execution of conditional branch statements. Conditional branch statements describe a type of program statement that allows conditional execution of program code. Conditional execution describes a decision-making technique within an instruction set architecture (ISA) for determining a path through code.

[0021] In general, a conditional branch statement identifies one or more conditions to be evaluated and one or more branch destinations to be selected based on these conditions. For example, a switch statement represents a type of multi-conditional branch statement that identifies multiple conditional evaluations and a set of corresponding branch destinations. The conditional evaluation of a switch statement represents a comparison operation performed between two values. For example, a conditional evaluation can determine whether a value stored in a first register is equal to a value stored in a second register. If equal, the conditional evaluation is true, otherwise the conditional evaluation is false. The branch destination of a switch statement represents a memory location where program functions are stored. When executed, the switch statement causes an execution device (e.g., a central processing unit (CPU)) to perform multiple conditional evaluations and determine the appropriate branch destination to branch to based on the results of the multiple conditional evaluations.

[0022] Existing techniques for executing multi-conditional branch statements may require multiple execution cycles to complete. For example, a switch statement that recognizes two conditional evaluations and two branch destinations may require multiple execution cycles to complete: 1) one or more execution cycles for performing the first conditional evaluation and the first branch operation; and 2) one or more execution cycles for performing the second conditional evaluation and the second branch operation (for when the result of the first conditional evaluation is false). In contrast, a new multi-conditional branch instruction (MCBI) is disclosed herein that executes multi-conditional branch statements, such as switch statements, within the same cycle overhead required to execute a single conditional branch instruction (CBI). This means that the new MCBI that recognizes multiple conditions can be executed in the same number of cycles as a CBI that only recognizes a single condition.

[0023] Initially, when expressed in assembly code, the conditional evaluation of the same switch statement is compiled into two comparison instructions, whose results are stored in two registers. The checking of those results is done by the new MCBI in a single execution cycle, rather than two execution cycles. The new MCBI takes as input the results of the two conditional evaluations and checks their results to determine the appropriate destination to branch to. Advantageously, the new MCBI allows the same multiple conditional branch statements to be executed in the same amount of cycles required to execute the CBI.

[0024] In an example embodiment, a system is provided that includes an instruction fetch circuit system, a decoder circuit system coupled to the instruction fetch circuit system, and a multi-conditional branch circuit system coupled to the decoder circuit system. The instruction fetch circuit system is configured to fetch a multi-conditional branch instruction (MCBI) from a memory and provide the MCBI to the decoder circuit system. In response, the decoder circuit system causes the multi-conditional branch circuit system to execute the MCBI.

[0025] MCBI represents a program instruction that identifies multiple status registers and multiple branch destinations. The multiple status registers of the MCBI represent registers that store the results of multiple conditional evaluations, so that each status register stores the results of different conditional evaluations. In an embodiment, the results of the conditional evaluations indicate whether the comparison operation is true or false. Thus, the multiple status registers store indications of whether the first set of comparison operations is true or false. The multiple branch destinations of the MCBI represent memory locations that store program functions corresponding to the results of the multiple conditional evaluations.

[0026] In an embodiment, the plurality of status registers include a first status register storing a first condition evaluation result and a second status register storing a second condition evaluation result. The first condition evaluation result represents an indicator of whether a first comparison operation between a first variable and a second variable is true or false. The second condition evaluation result represents an indicator of whether a second comparison operation between a first variable and a third variable is true or false. Thus, the plurality of branch destinations include a first branch destination corresponding to the first condition evaluation result and a second branch destination corresponding to the second condition evaluation result.

[0027] When executed, the MCBI causes the multi-conditional branch circuit system to determine an appropriate branch destination to provide to the instruction fetch circuit system. If the first conditional evaluation result indicates that the first comparison operation is true, the multi-conditional branch circuit system provides the first branch destination to the instruction fetch circuit system. Alternatively, if the first conditional evaluation result indicates that the first comparison operation is false, and the second conditional evaluation result indicates that the second comparison operation is true, the multi-conditional branch circuit system provides the second branch destination to the instruction fetch circuit system. In an embodiment, if the first conditional evaluation result and the second conditional evaluation result indicate that the first comparison operation and the second comparison operation are false, the multi-conditional branch circuit system indicates that branching is not required and instruction execution can continue with the next instruction.

[0028] Advantageously, the disclosed technology improves the efficiency of systems utilizing conditional branching techniques. Existing solutions for executing multiple conditional branch statements are limited to checking one condition at a time. Therefore, existing solutions require a large number of execution cycles to execute conditional branch operations. In contrast, this paper describes a system and method for executing multiple conditional branch statements with the same cycle penalty as a single conditional branch statement, thereby reducing the time and code size required to execute multiple conditional branch statements.

[0029] Now turning to the attached figure, Figure 1 An operating environment 100 in an embodiment is shown. Operating environment 100 represents an example operating environment that can be configured to execute program code, such as a multi-conditional branch instruction (MCBI). Operating environment 100 includes instruction acquisition circuit system 101, decoder circuit system 103, processing circuit system 105, and memory 121. In some embodiments, the elements shown in operating environment 100 can be included inside a processing system, such as a microcontroller unit (MCU) or a central processing unit (CPU). In some embodiments, some of the elements shown in operating environment 100 can be included outside the processing system.

[0030] Instruction fetch circuitry 101 represents circuitry configured to fetch instructions from memory and provide instructions to decoders. For example, instruction fetch circuitry 101 may fetch instructions from memory 121 and provide instructions to decoder circuitry 103. In an embodiment, instruction fetch circuitry 101 is configured to fetch instruction packets from memory 121. For example, instruction fetch circuitry 101 may first fetch instruction packet 123 in a first clock cycle and fetch instruction packet 126 in a subsequent clock cycle.

[0031] Decoder circuitry 103 represents circuitry configured to decode instructions fetched from memory. For example, instruction fetch circuitry 101 may fetch instruction packets from memory 121 and provide the fetched instructions to decoder circuitry 103. In response, decoder circuitry 103 decodes the fetched instructions of the instruction packets and routes the decoded instructions to appropriate circuitry of processing circuitry 105. It should be noted that although Figure 1 Only one decoder (ie, decoder circuitry 103) is shown, but several decoders or decoder circuits may be included in operating environment 100. For example, each circuit of processing circuitry 105 may include a separate decoder circuitry.

[0032] Processing circuit system 105 represents one or more circuits capable of executing program instructions. Processing circuit system 105 may be coupled to instruction fetch circuit system 101, decoder circuit system 103, and memory 121. Processing circuit system 105 includes, but is not limited to, arithmetic logic unit (ALU) 107, program control unit (PCU) 111, register 115, and register 116.

[0033] ALU 107 represents circuitry configured to perform arithmetic logic operations. For example, ALU 107 may perform various comparison operations, such as determining whether a value stored in a first register is less than, greater than, and / or equal to a value stored in a second register. The output of ALU 107 may be stored by memory 121 or analyzed by corresponding circuitry. For example, PCU 111 may analyze the output of ALU 107 to determine which instruction should be executed next. It should be noted that although Figure 1 Only one arithmetic logic unit (ie, ALU 107) is shown, but operating environment 100 may include several arithmetic logic units.

[0034] PCU 111 represents a circuit system configured to manage the execution of program code. In various examples, as other circuit systems (such as ALU 107) execute instructions during runtime operation, PCU 111 directs instruction acquisition circuit system 101 to acquire certain instructions in a specific order. PCU 111 further represents a circuit system configured to perform conditional evaluation. Conditional evaluation represents an analysis performed on the result of a comparison operation. For example, ALU 107 can perform a comparison operation, and PCU 111 can evaluate the output of ALU 107 to determine whether the comparison operation meets a specific condition. The condition of the conditional evaluation represents the expected output for the comparison operation. For example, the condition may expect that a variable stored by a first register is equal to a variable stored by a second register. If the condition is met, PCU 111 outputs a true indication (e.g., 1), otherwise PCU 111 outputs a false indication (e.g., 0). The output of PCU 111 is stored by a register of processing circuit system 105. For example, if the PCU 111 determines that the first condition is satisfied, the PCU 111 may store 1 in the register 115, otherwise the PCU 111 may store 0 in the register 115. In an embodiment, the PCU 111 includes, but is not limited to, a multi-conditional branch circuit system (MCBC) 113.

[0035] MCBC 113 represents a circuit system configured to execute a multiple conditional branch instruction (MCBI) in a single execution cycle or cycle used for a single conditional branch. In this context, a single execution cycle includes both a condition where the processing circuit system 105 can proceed from receiving an instruction to a result in a single clock cycle, and a pipeline architecture where the processing circuit system 105 takes several clock cycles from receiving an instruction to a result, but the instruction only occupies a single slot in the pipeline. In this latter case, a first instruction may allow a second instruction to complete in a clock cycle immediately before the first instruction is completed, and may allow a third instruction to complete in a clock cycle immediately after the first instruction is completed. Therefore, in practice, the first instruction only delays the subsequent third instruction by one clock cycle.

[0036] MCBI represents an instruction that identifies multiple status registers and multiple branch destinations. Multiple status registers represent registers that store conditional evaluation results, such as registers of processing circuit system 105. Multiple branch destinations represent locations in memory 121 where various program functions are stored. When MCBI is executed, MCBC 113 analyzes the conditional evaluation results stored by the status registers (i.e., register 115 and register 116) to determine appropriate branch destinations. In an embodiment, MCBC 113 outputs the appropriate branch destination to instruction acquisition circuit system 101. In response, instruction acquisition circuit system 101 obtains instructions corresponding to the appropriate branch destination from memory 121. It should be noted that although shown within PCU 111, MCBC 113 can reside outside PCU 111.

[0037] Registers 115 and 116 represent locations where data and / or instructions are stored for use during execution of program code. Registers 115 and 116 may be architecturally distinct and / or portions (e.g., different bits) of a single larger register. In an embodiment, registers 115 and 116 represent status registers that store conditional evaluation results. For example, PCU 111 may output conditional evaluation results to registers 115 and 116, and MCBC 113 analyzes the data stored in registers 115 and 116 to form a determination. It should be noted that while only two registers are shown, processing circuitry 105 may include more than two registers.

[0038] Memory 121 represents one or more volatile or non-volatile computer-readable storage media (e.g., random access memory, flash memory) including instructions, data, etc. For example, memory 121 stores instruction packets 123 and 126 and includes memory locations 143, 144, 145, 146, 149, 153, 154, 155, 156, and 159. The instruction packets of memory 121 represent packets of one or more instructions that direct the processing units of processing circuit system 105 to perform various operations within a single execution cycle or a cycle used for a single conditional branch. The memory locations of memory 121 represent locations in the memory where data is stored. For example, the data at the memory locations may include values, program functions, or data, etc.

[0039] Instruction packet 123 represents the first packet of instructions that can be executed in a single execution cycle. Instruction packet 123 includes instruction 124 and instruction 125. Instructions 124 and 125 represent conditional evaluations, each of which identifies a comparison operation to be performed (e.g., greater than, less than, equal to, etc.), a memory location to store data for performing the comparison operation, and a condition for the result of the comparison operation. When executed, instruction packet 123 causes ALU 107 to perform the comparison operation identified by instructions 124 and 125 and output the result of the comparison operation to PCU 111. PCU 111 then evaluates the output of ALU 107 to determine whether the condition of the instruction is satisfied.

[0040] For example, instruction 124 causes ALU 107 to compare the data stored in memory locations 143 and 144 and output the result to PCU 111. PCU 111 evaluates the output of ALU 107 and stores an indication in register 115 of whether the condition of instruction 124 is satisfied. For example, if the condition of instruction 124 is satisfied, PCU stores a true indication (e.g., 1) in register 115, otherwise PCU 111 stores a false indication (e.g., 0). Additionally or alternatively, ALU 107 may write directly to register 115. Similarly, instruction 125 causes ALU 107 to compare the data stored in memory locations 143 and 145 and output the result to PCU 111. PCU 111 evaluates the output of ALU 107 and stores an indication in register 116 of whether the condition of instruction 125 is satisfied. In some examples, ALU 107 includes multiple sets of execution circuitry configured to execute instruction 124 and instruction 125 in parallel, and PCU 111 and / or ALU 107 are configured to write the results of the comparison to register 115 and register 116 in parallel.

[0041] Instruction packet 126 represents a second packet of instructions that can be executed in the same number of cycles used by a single conditional branch instruction. In an embodiment, instruction packet 126 is executed after the execution of instruction packet 123. Instruction packet 126 includes, but is not limited to, instruction 127. Instruction packet 126 may further include other instructions, such as conditional evaluation, but for purposes of explanation, instruction packet 126 depicts instruction 127.

[0042] Instruction 127 represents a MCBI that identifies a plurality of status registers and a plurality of branch destinations. When executed, instruction packet 126 causes MCBC 113 to determine an appropriate branch destination to provide to instruction fetch circuitry 101 based on the results of instructions 124 and 125. For example, if the condition of instruction 124 is satisfied as indicated by register 115, MCBC 113 provides memory location 153 to instruction fetch circuitry 101. Alternatively, if the condition of instruction 124 is not satisfied, but the condition of instruction 125 is satisfied as indicated by register 116, MCBC 113 provides memory location 154 to instruction fetch circuitry 101. In an embodiment, if the condition of either instruction is not satisfied, MCBC 113 may provide memory location 159 to instruction fetch circuitry 101.

[0043] Memory locations 143, 144, 145, 146, and 149 represent memory locations where values ​​are stored. Such values ​​may include fixed point numbers, floating point numbers, or other values, etc. Alternatively, memory locations 153, 154, 155, 156, and 159 represent branch destinations for stored program functions, referred to herein as execution conditions. The execution conditions of memory locations 153, 154, 155, 156, and 159 represent program instructions to which PCU 111 may branch.

[0044] Figure 2 The multiple conditional branch (MCB) process 200 in an embodiment is shown. The MCB process 200 may be implemented in the context of program instructions that, when executed by a suitable computing system, may be referred to as Figure 2 The steps in the MCB process 200 instruct the processing circuit system of the computing system to operate as follows. For the purpose of explanation, the MCB process 200 will be used as Figure 1 This is not meant to limit the application of the MCB process 200 but rather to provide an example.

[0045] Initially, PCU 111 performs a first set of conditional evaluations (step 201). For example, PCU 111 may execute instruction packet 123. Instruction packet 123 represents a packet of instructions including instructions 124 and 125. Instructions 124 and 125 represent conditional evaluations that direct ALU 107 and PCU 111 to determine whether data stored in identified memory locations satisfy the conditions of the instructions. For example, instruction 124 directs ALU 107 and PCU 111 to determine whether data stored in memory locations 143 and 144 satisfy the conditions of instruction 124. Similarly, instruction 125 directs ALU 107 and PCU 111 to determine whether data stored in memory locations 143 and 145 satisfy the conditions of instruction 125. In an embodiment, the conditions of instructions 124 and 125 determine whether a value stored in a first memory location (i.e., memory location 143) is equal to a value stored in a second memory location (i.e., memory location 144 or memory location 145).

[0046] Next, PCU 111 stores the results of the conditional evaluation in a plurality of status registers (step 203). In an embodiment, PCU 111 stores the results of the conditional evaluation in registers of processing circuit system 105. For example, PCU 111 may store the result of instruction 124 in register 115 and the result of instruction 125 in register 116. If the condition is met, PCU 111 stores 1, otherwise PCU 111 stores 0.

[0047] After evaluating the conditions of instructions 124 and 125, PCU 111 directs instruction fetch circuitry 101 to fetch MCBI from memory 121 (step 205). For example, PCU 111 may direct instruction fetch circuitry 101 to fetch instruction packet 126 from memory 121. Once fetched, instruction fetch circuitry 101 provides instruction packet 126 to decoder circuitry 103. In response, decoder circuitry 103 decodes instruction packet 126 and causes MCBC 113 to execute instruction 127 with respect to the results stored in registers 115 and 116 (step 207). In particular, this may enable MCBC 113 to determine which instruction should be executed next.

[0048] Figure 3 Process 300 in an embodiment is shown. Process 300 represents a process for performing MCBI. In an embodiment, process 300 represents a sub-process for performing step 207 of MCB process 200. Process 300 can be implemented in the context of program instructions that, when executed by a suitable computing system, incidentally refer to Figure 3 The steps in instruct the processing circuit system of the computing system to operate as follows.

[0049] Initially, MCBC 113 receives a decoded representation of instruction 127 from decoder circuitry 103, and in response, determines whether a first state register is set (step 301). For example, MCBC 113 may determine whether register 115 stores a 1 or a 0. If register 115 stores a 1, MCBC 113 determines that the first state register is set, and in response provides a first branch destination to instruction fetch circuitry 101 (step 302). For example, MCBC 113 may provide memory location 153 to instruction fetch circuitry 101. In response, instruction fetch circuitry 101 fetches the instruction corresponding to memory location 153. For some MCBI instructions, such as instruction 127, when the first state register is set, MCBC 113 does not need to evaluate the second state register (i.e., register 116).

[0050] Alternatively, if register 115 stores a 0, MCBC 113 determines that the first state register is not set, and in response, determines whether the second state register is set (step 303). For example, MCBC 113 may determine whether register 116 stores a 1 or a 0. If register 116 stores a 1, MCBC 113 determines that the second state register is set, and provides the second branch destination to instruction fetch circuitry 101 (step 304). For example, MCBC 113 may provide memory location 154 to instruction fetch circuitry 101, and in response, instruction fetch circuitry 101 fetches the instruction corresponding to memory location 154.

[0051] When MCBC 113 determines that the first status register and the second status register are not set, MCBC 113 provides a default branch destination to instruction fetch circuitry 101 (step 305). For example, MCBC 113 may provide memory location 159 to instruction fetch circuitry 101. The default branch destination represents a location in memory that stores default program instructions when the conditions of instructions 124 and 124 are not satisfied. In an embodiment, when both status registers are not set, MCBC 113 notifies PCU 111, and in response, PCU 111 directs instruction fetch circuitry 101 to fetch the next instruction packet from memory 121. In other words, PCU 111 directs instruction fetch circuitry 101 not to branch in the program code, but to continue fetching code linearly.

[0052] Figure 4A 400 is an operational sequence of an embodiment. The operational sequence 400 shows the MCB process 200 and the process 300 with respect to Figure 1Thus, operation sequence 400 includes register 115, register 116, memory 121, instruction fetch circuitry 101, decoder circuitry 103, ALU 107, PCU 111, and MCBC 113.

[0053] Initially, instruction fetch circuitry 101 fetches an instruction packet from memory 121. For example, instruction fetch circuitry 101 may fetch instruction packet 123 from memory 121. Instruction packet 123 represents a packet of instructions including instruction 124 and instruction 125. Instruction 124 represents a conditional evaluation (i.e., OP1) that identifies a first comparison operation, a memory location for performing the first comparison operation, and a condition for the result of the first comparison operation. Instruction 125 represents another conditional evaluation (i.e., OP2) that identifies a second comparison operation, a memory location for performing the second comparison operation, and a condition for the result of the second comparison operation.

[0054] Instruction fetch circuitry 101 provides instructions 124 and 125 to decoder circuitry 103. Decoder circuitry 103 decodes instructions 124 and 125 and provides associated memory locations (i.e., memory locations L1, L2, and L3) for performing the first and second comparison operations to ALU 107. ALU 107 receives the associated memory locations and, in response, reads the values ​​stored by memory locations 143, 144, and 145 (i.e., V1, V2, V3).

[0055] Next, ALU 107 performs a first comparison operation and a second comparison operation. For example, ALU 107 may determine whether V1 is equal to V2 or equal to V3. Once determined, ALU 107 outputs the results of the comparison operation (i.e., OP1 output and OP2 output) to PCU 111. PCU 111 analyzes the output of ALU 107 to determine whether the result of the comparison operation meets the condition of instruction 124 or the condition of instruction 125. If the condition is met, PCU 111 stores a true indication (e.g., 1) in the corresponding status register, otherwise PCU 111 stores a false indication (e.g., 0). For the purpose of explanation, PCU 111 determines that the result of the first comparison operation meets the condition of instruction 124, and therefore stores a true indication in register 115. In addition, PCU 111 determines that the result of the second comparison operation does not meet the condition of instruction 125, and stores a false indication in register 116.

[0056] Instruction fetch circuitry 101 also fetches the next instruction packet from memory 121. For example, instruction fetch circuitry 101 may fetch instruction packet 126 from memory 121. Instruction packet 126 represents a packet of instructions including, but not limited to, instruction 127. Instruction 127 represents an MCBI (i.e., OP3) that identifies a plurality of status registers and a set of corresponding branch destinations. Instruction fetch circuitry 101 provides instruction packet 126 to decoder circuitry 103. In response, decoder circuitry 103 decodes instruction packet 126 and provides MCBC 113 with the relevant registers (i.e., R1 and R2) and branch destinations (i.e., L21 and L22) for executing instruction 127.

[0057] MCBC 113 receives the associated registers and the branch destination and, in response, reads the value stored by the first state register (i.e., register 115). MCBC 113 evaluates the data of register 115 to determine whether the first state register has been set. Since register 115 stores a true output (i.e., register 115 is set), MCBC 113 does not need to evaluate the data of register 116 and provides memory location 153 (i.e., L21) to instruction fetch circuitry 101.

[0058] Figure 4B An operation sequence 410 in an embodiment is shown. Operation sequence 410 represents a variation of operation sequence 400. As such, operation sequence 410 includes registers 115, registers 116, memory 121, instruction fetch circuitry 101, decoder circuitry 103, ALU 107, PCU 111, and MCBC 113.

[0059] Initially, instruction fetch circuitry 101 fetches instruction packet 123 from memory 121. Instruction fetch circuitry 101 provides instruction packet 123 to decoder circuitry 103. Decoder circuitry 103 decodes instruction packet 123 and provides the relevant memory locations (i.e., L1, L2, and L3) to ALU 107 for performing comparison operations of instructions 124 and 125.

[0060] ALU 107 receives the associated memory locations and in response reads the values ​​(i.e., V1, V2, and V3) stored by memory locations 143, 144, and 145. Next, ALU 107 performs the comparison operations of instructions 124 and 125 and outputs the results (i.e., OP1 output and OP2 output) to PCU 111. PCU 111 analyzes the output of ALU 107 and determines that the result of the first comparison operation does not satisfy the condition of instruction 124 and therefore stores a false indication in register 115. In addition, PCU 111 determines that the result of the second comparison operation satisfies the condition of instruction 125 and stores a true indication in register 116.

[0061] Instruction fetch circuitry 101 fetches instruction packet 126 from memory 121. Instruction fetch circuitry 101 provides instruction packet 126 to decoder circuitry 103. In response, decoder circuitry 103 decodes instruction packet 126 and provides relevant registers (i.e., R1 and R2) and branch destinations (i.e., L21 and L22) for executing instruction 127 to MCBC 113.

[0062] MCBC 113 receives the relevant registers and the branch destination, and in response, reads the value stored by the first status register (i.e., register 115) to determine whether the first status register has been set. Since register 115 stores a false output (i.e., register 115 is not set), MCBC 113 then reads the value stored by the second status register (i.e., register 116) to determine whether the second status register has been set. Since register 116 stores a true output (i.e., register 116 is set), MCBC 113 provides memory location 154 (i.e., L22) to instruction fetch circuitry 101.

[0063] In an embodiment, if neither of the status registers (i.e., registers 115 and 116) are set, MCBC 113 determines the next instruction to execute based on the branch destination. This may include MCBC 113 providing a default branch destination to instruction fetch circuitry 101 to determine whether to fetch the next instruction from memory 121. For example, MCBC 113 may provide memory location 159 to instruction fetch circuitry 101. Alternatively, MCBC 113 may provide its output to PCU 111 to enable PCU 111 to determine the next instruction that should be fetched.

[0064] Now, moving on to the next figure, Figure 5AA multi-conditional branch (MCB) circuit 500 in an embodiment is shown. The MCB circuit 500 represents a circuit system (e.g., MCBC 113) configured to execute an MCBI. The MCBI represents a program instruction that identifies multiple state registers and multiple branch destinations. The multiple state registers of the MCBI represent registers (e.g., registers 115 and 116) that store conditional evaluation results. The conditional evaluation result represents an indication of whether the comparison operation is true or false. For example, the state register can store 1 to indicate a true output and store 0 to indicate a false output. Multiple branch destinations represent addresses in a memory that store various execution conditions (e.g., memory locations 153 and 154). In an embodiment, the MCBI identifies a first state register, a second state register, a first branch destination (which corresponds to the first state register), and a second branch destination (which corresponds to the second state register). The MCB circuit 500 includes, but is not limited to, a multiplexer (MUX) circuit 501 and a MUX circuit 503.

[0065] MUX circuit 501 represents a circuit including two input channels (i.e., CH 0 and CH 1 ) of a 2-to-1 multiplexer. The first input channel (i.e., CH 0 ) represents routing a null value (ie, NULL) to the first input channel (ie, CH 0 ) channel. It should be noted that the null value is an exemplary value and can represent any type of data (e.g., a value, an address, etc.). The second input channel (i.e., CH 1 ) represents routing the address of the second branch destination (ie, ADD2) to the first input channel (ie, CH) of the MUX circuit 503. 0 ) channel.

[0066] The input to the MUX circuit 501 includes a select input signal. The select input signal indicates which input channel (i.e., CH) the MUX circuit 501 selects. 0 or CH 1 ) should be used as a signal of the output channel. In an embodiment, the select input signal of the MUX circuit 501 is based on the condition evaluation result stored by the second state register. For example, if the second state register stores 0, the select input signal is low, and the MUX circuit 501 routes the data of the first input channel (i.e., NULL) to the first input channel (i.e., CH ) of the MUX circuit 503. 0 Alternatively, if the second state register stores 1, the select input signal is high, and the MUX circuit 501 routes the data of the second input channel (ie, ADD2) to the first input channel (ie, CH) of the MUX circuit 503. 0 ).

[0067] MUX circuit 503 represents another 2-to-1 multiplexer, which also includes two input channels (i.e., CH 0 and CH 1 The first input channel (i.e., CH 0 ) represents a channel for routing the output of MUX circuit 501 (i.e., NULL or ADD2) to an appropriate circuit system. For example, the appropriate circuit system may represent an instruction fetch circuit system (e.g., instruction fetch circuit system 101) configured to fetch instructions from a memory. The second input channel of MUX circuit 503 (i.e., CH 1 ) represents a path that routes the address of the first branch destination (ie, ADD1) to the appropriate circuit system.

[0068] The input to the MUX circuit 503 includes a select input signal. The select input signal indicates which input channel (i.e., CH) the MUX circuit 503 selects. 0 or CH 1 ) should be used as a signal of the output channel. In an embodiment, the selection input signal of the MUX circuit 503 is based on the condition evaluation result stored by the first state register. For example, if the first state register stores 0, the selection input signal is low, and the MUX circuit 503 routes the data of the first input channel (i.e., NULL or ADD2) to the appropriate circuit system. Alternatively, if the first state register stores 1, the selection input signal is high, and the MUX circuit 503 routes the data of the second input channel (i.e., ADD1) to the appropriate circuit system.

[0069] Figure 5B An operation scenario 510 in an embodiment is shown. Figure 5A The operation scenario 510 represents an example scenario for performing MCBI. The operation scenario 510 includes a MUX circuit 501 and a MUX circuit 503.

[0070] Initially, MUX circuit 501 receives a select input signal based on the value stored by the second status register. Since the conditional evaluation result is equal to zero, the select input signal is low, and MUX circuit 501 routes the data of the first input channel (i.e., NULL) to the first input channel (i.e., CH 1 ) of MUX circuit 503. 0 ). Next, the MUX circuit 503 receives a select input signal based on the value stored by the first state register. Since the conditional evaluation result is equal to 1, the select input signal is high and the MUX circuit 503 routes the data of the second input channel (ie, ADD1) to the appropriate circuit system.

[0071] Figure 5C An operation scenario 520 in an embodiment is shown. Figure 5AThe operation scenario 520 represents another example scenario for performing MCBI. The operation scenario 520 includes a MUX circuit 501 and a MUX circuit 503.

[0072] Initially, MUX circuit 501 receives a select input signal based on the value stored by the second status register. Since the conditional evaluation result is equal to 1, the select input signal is high, and MUX circuit 501 routes the data of the second input channel (i.e., ADD2) to the first input channel (i.e., CH1) of MUX circuit 503. 0 ). Next, MUX circuit 503 receives a select input signal based on the value stored by the first state register. Since the conditional evaluation result is equal to zero, the select input signal is low, and MUX circuit 503 routes the data of the first input channel (i.e., ADD2) to the appropriate circuit system. In an embodiment, if both conditional evaluation results are equal to zero, both select input signals will be low, and MUX circuit 501 will route the data of its first input channel (i.e., NULL) to the first input channel of MUX circuit 503, and MUX circuit 503 will route the data of its first input channel (i.e., NULL) to the appropriate circuit system.

[0073] Figure 6 1 shows an operating environment 600 in an embodiment. Operating environment 600 represents another example operating environment that can be configured to execute program instructions. For example, operating environment 600 can represent Figure 1 The operating environment 100 of FIG. 600 includes, but is not limited to, a memory 601, a program control unit (PCU) 615, a data register 621, and a status register 623. In some embodiments, the elements shown in the operating environment 600 may be included inside a processing system (such as an MCU or a CPU). In some embodiments, some of the elements shown in the operating environment 600 may be included outside the processing system.

[0074] Memory 601 represents one or more volatile or non-volatile computer-readable storage media (e.g., random access memory, flash memory) on which instructions, data, etc. are included. For example, memory 601 includes instruction packets 602, 605, and 609. An instruction packet represents a packet of one or more instructions that can be executed in a single execution cycle, or in the same number of cycles used to execute a single conditional branch instruction (as opposed to a multi-conditional branch instruction). Memory 601 can be coupled to a circuit system (e.g., instruction fetch circuit system 101) that is configured to fetch instruction packets from memory 601 and provide the instructions (of the instruction packet) to the appropriate circuit system. In an embodiment, memory 601 represents Figure 1 The memory 121 in.

[0075] Instruction packet 602 represents the first packet of instructions that can be executed in a single execution cycle. Instruction packet 602 includes instruction 603 and instruction 604. Instructions 603 and 604 represent conditional evaluations that command PCU 615 to determine whether the output of a comparison operation generates a desired result. In an embodiment, instructions 603 and 604 each identify a comparison operation to be performed, an input memory / register location, a condition for the result of the comparison operation, and an output memory / register location. When executed, instructions 603 and 604 command PCU 615 to determine whether the data stored by the registers of data registers 621 is equal to a specified value, and output the result of its determination to the registers of status registers 623.

[0076] In an embodiment, the specified value of the conditional evaluation represents an identifier of the execution situation. For example, the specified value of instruction 603 is equal to the number 1 (i.e., #CASE1), while the specified value of instruction 604 is equal to the number 2 (i.e., #CASE2). When executed, instructions 603 and 604 instruct PCU 615 to determine whether the data stored by the register of data register 621 is equal to the number 1 or the number 2. Instructions 603 and 604 further instruct PCU 615 to output an indicator (e.g., 1 or 0) indicating whether the comparison operation of each instruction is true or false to the corresponding register of status register 623.

[0077] Instruction packet 605 represents a second packet of instructions that can be executed in a single execution cycle or in the same number of cycles used to execute a single conditional branch instruction. In other words, instruction packet 605 can be executed in one execution cycle, or if necessary, can be executed in the same number of execution cycles used to execute a single conditional branch operation. In an embodiment, instruction packet 605 is executed after the execution of instruction packet 602. Instruction packet 605 includes instruction 606, instruction 607 and instruction 608.

[0078] Instruction 606 represents a multiple conditional branch instruction (MCBI) that identifies multiple state registers and multiple branch destinations. The multiple state registers of instruction 606 represent registers that store the results of conditional evaluations, such as state register 623. The multiple branch destinations represent locations in memory that store execution conditions to which PCU 615 can branch. When executed, instruction 606 causes MCBC 619 to determine appropriate branch destinations to output based on the results of instructions 603 and 604. In an embodiment, MCBC 619 outputs the appropriate branch destinations to PCU 615. In response, PCU 615 branches to the specified destination in memory.

[0079] Alternatively, instructions 607 and 608 represent conditional evaluations that command PCU 615 to determine whether the output of a comparison operation generates an expected result. Instructions 607 and 608 each identify a comparison operation to be performed, an input memory / register location, a condition for the result of the comparison operation, and an output memory / register location. When executed, instructions 607 and 608 command PCU 615 to determine whether the data stored by the register of data register 621 is equal to a specified value (i.e., the number 3 or the number 4), and output the result of its determination to the register of status register 623.

[0080] Instruction packet 609 represents a third packet of instructions that can also be executed in a single execution cycle, or in the same number of cycles used to execute a single conditional branch instruction. In other words, instruction packet 609 can be executed in one execution cycle, or if necessary, can be executed in the same number of execution cycles used to execute a single conditional branch operation. In an embodiment, instruction packet 609 is executed after the execution of instruction packet 605. Instruction packet 609 includes, but is not limited to, instruction 610.

[0081] Instruction 610 represents another MCBI that identifies multiple status registers and multiple branch destinations. When executed, instruction 610 causes MCBC 619 to determine the appropriate branch destination to output based on the results of instructions 607 and 608. In an embodiment, MCBC 619 outputs the appropriate branch destination to PCU 615. In response, PCU 615 branches to the specified destination in memory.

[0082] PCU 615 represents one or more circuits (e.g., PCU 111) configured to manage the execution of program code. PCU 615 further represents a circuit system configured to perform conditional evaluations and store the results of the conditional evaluations in status register 623. For example, PCU 615 can execute instructions 603, 604, 607, and 608. In an embodiment, PCU 615 is coupled to an arithmetic logic unit (e.g., ALU 107) configured to perform arithmetic logic operations. For example, the arithmetic logic unit can perform a comparison operation identified by instructions 603, 604, 607, and 608. PCU 615 can then evaluate the output of the arithmetic logic unit to determine whether the comparison operation satisfies the condition of the corresponding instruction. PCU 615 includes a program counter 617 and an MCBC 619.

[0083] Program counter 617 represents a register that stores the memory location for the instruction currently being executed. For example, if PCU 615 is currently executing instruction 603, program counter 617 stores an address corresponding to the location in memory 601 storing instruction 603. In an embodiment, program counter 617 may represent multiple registers that store memory locations for instructions currently being executed in parallel.

[0084] MCBC 619 represents one or more circuits configured to execute MCBI in a single execution cycle or cycle used for a single conditional branch. For example, MCBC 619 can execute instructions 606 and 610. In an embodiment, MCBC 619 represents Figure 1 MCBC 113 or Figure 5A MCB circuit 500.

[0085] Data register 621 represents a memory location for storing data and / or instructions used during the execution of the program code. Data register 621 can represent an addressing register, a fixed-point register, a floating-point register, or a combination thereof. In this way, data register 621 can store addressing data, fixed-point data, floating-point data, or a combination of data types. In an embodiment, PCU 615 performs conditional evaluation on the data stored by data register 621.

[0086] The status register 623 also represents a memory location that stores data and / or instructions for use during the execution of program code. The status register 623 may represent an interrupt status register, a decode phase status register, an execution phase status register, or a combination thereof. In an embodiment, the status register 623 represents a register that stores the results of conditional evaluations, such as Figure 1 The PCU 615 may output the condition evaluation result to the status register 623, and the MCBC 619 may analyze the data of the status register 623 to form a determination. In an embodiment, the status register 623 includes four separate registers for storing the results of the condition evaluation.

[0087] Fig. 7A , Figure 7B and Figure 7C The operation scenario for executing program code in the implementation is shown. More specifically, FIG. 7A to FIG. 7C Shown is the Figure 6 The elements perform a series of stages of MCBI. In an embodiment, Fig. 7A The first stage of operation is depicted, Figure 7B depicts the second stage of operation, and Figure 7C The third operational phase is depicted.

[0088] Now go to Fig. 7A , stage 710 represents the first stage of operation. In an embodiment, stage 710 depicts the operations occurring during the first execution cycle. Stage 710 includes instruction packet 602, PCU 615, data register 621, and status register 623.

[0089] Initially, PCU 615 receives instructions 603 and 604. In response, PCU 615 identifies the register within data register 621 for executing instructions 603 and 604. Once identified, PCU 615 determines whether the data stored in register A0 is equal to 1 or 2. In an embodiment, an arithmetic logic unit (not shown) determines whether the data stored in register A0 is equal to 1 or 2, and outputs the result to PCU 615. If the arithmetic logic unit determines that the data in register A0 is equal to 1, PCU 615 stores a true indication (i.e., 1) in the status register identified by instruction 603, and stores a false indication (i.e., 0) in the status register identified by instruction 604. Alternatively, if the arithmetic logic unit determines that the data in register A0 is equal to 2, PCU 615 stores a false indication in the status register identified by instruction 603, and stores a true indication in the status register identified by instruction 604. Since the data in register A0 is equal to 1, PCU 615 stores 1 in register TA0 and stores 0 in register TA1.

[0090] Figure 7B Stage 720 is shown representing the second stage of operation. In an embodiment, stage 720 depicts operations occurring during a second execution cycle. Stage 720 includes instruction packet 605, PCU 615, data register 621, and status register 623.

[0091] Initially, MCBC 619 receives instruction 607 while PCU 615 receives instructions 608 and 609. In response, MCBC 619 and PCU 615 identify the relevant registers for executing the respective instructions. Instruction 607 represents an MCBI, which commands MCBC 619 to evaluate the data of registers TA0 and TA1 and determine which register is set (if any). MCBC 619 first evaluates the data of register TA0, and if it is set, MCBC 614 outputs the branch destination corresponding to the set register TA0. Alternatively, if TA0 is not set, MCBC 619 evaluates the data of register TA1. If register TA1 is set, MCBC 619 outputs the branch destination corresponding to the set register TA1. Since register TA0 is set, MCBC 619 does not evaluate the data of register TA1, but outputs the branch destination corresponding to the set register TA0.

[0092] Instructions 608 and 609 represent conditional evaluations that instruct PCU 615 to determine whether the data stored in register A0 is equal to 3 or 4. Since the data in register A0 is equal to 4, PCU 615 stores 0 in register TA2 and 1 in register TA3. It should be noted that when MCBC 619 executes instruction 606, PCU 615 may execute instructions 607 and 608 simultaneously.

[0093] Figure 7C Stage 730 is shown representing the third stage of operation. In an embodiment, stage 730 depicts operations occurring during the third execution cycle. Stage 730 includes instruction packet 609, PCU 615, data register 621, and status register 623.

[0094] Initially, MCBC 619 receives instruction 610 and, in response, identifies the relevant registers for executing instruction 610. Instruction 610 represents an MCBI that instructs MCBC 619 to evaluate the data of registers TA2 and TA3 and determine which register is set (if any). MCBC 619 first evaluates the data of register TA2 and determines that register TA2 has not been set. MCBC 619 then evaluates the data of register TA3 and determines that register TA3 has been set. Thus, MCBC 619 outputs the branch destination corresponding to the set register TA3 to PCU 615.

[0095] Figure 8 An example computer system that can be used for various embodiments is shown. For example, computing system 801 represents a computing device that can execute software composed of program instructions with multiple conditional branch instructions as described herein. Computing system 801 represents any system or system set that can be adopted together with various operating architectures, processes, scenarios and sequences for conditional branches disclosed herein. Computing system 801 can be implemented as a single device, system or device, or can be implemented as multiple devices, systems or devices in a distributed manner. Computing system 801 includes, but is not limited to, processing system 802, storage system 803, software 805, communication interface system 807 and user interface system 809 (optional). Processing system 802 is operably coupled to storage system 803, communication interface system 807 and user interface system 809. Computing system 801 can represent cloud computing equipment, distributed computing equipment, etc.

[0096] Processing system 802 loads and executes software 805 from storage system 803, or alternatively, runs software 805 directly from storage system 805. Software 805 includes and implements multiple conditional branch instructions (MCBI) 806, which represent any of the multiple conditional branch instructions discussed with respect to the previous figures (e.g., instruction 127, instruction 606, and instruction 610). When executed by processing system 802, software 805 (including instruction 127, instruction 606, and instruction 610) directs processing system 802 to operate as described herein at least for the various processes, operating scenarios, and sequences discussed in the foregoing embodiments. Computing system 801 may optionally include additional devices, features, or functions that are not discussed for the purpose of brevity.

[0097] Still reference Figure 8 , processing system 802 may include a microprocessor and other circuitry that retrieves and executes software 805 from a storage system 803. Processing system 802 may be implemented within a single processing device, but may also be distributed across multiple processing devices or subsystems that collaborate to execute program instructions. Examples of processing system 802 include general-purpose central processing units, graphics processing units, digital signal processing units, data processing units, special-purpose processors and logic devices, and any other type of processing device, combination, or variation thereof. Processing system 802 includes special-purpose circuitry capable of executing MCBI, examples of which include MCBC113, MCB circuit 500, and MCBC 619.

[0098] The storage system 803 may include any computer-readable storage medium that can be read and written by the processing system 802 and that can store the software 805. The storage system 803 may include volatile and nonvolatile, removable and non-removable, mutable and non-mutable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, optical media, flash memory, virtual and non-virtual memory, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices, or any other suitable storage medium. In any case, a computer-readable storage medium is not a propagated signal.

[0099] In addition to computer-readable storage media, in some embodiments, storage system 803 may also include computer-readable communication media through which at least some of software 805 can communicate internally or externally. Storage system 803 can be implemented as a single storage device, but can also be implemented across multiple storage devices or subsystems that are co-located or distributed relative to each other. Storage system 803 may include additional elements, such as a controller, that can communicate with processing system 802 or possibly other systems.

[0100] The software 805 (including the MCBI 806) may be implemented in program instructions and, among other functions, when executed by the processing system 802, may direct the processing system 802 to operate as described with respect to the various operational scenarios, sequences, and processes illustrated herein. For example, the software 805 includes an MCBI for implementing multiple conditional branch operations as described herein.

[0101] In particular, program instructions can include various components or modules that collaborate or otherwise interact to perform various processes and operation scenarios described herein. Various components or modules can be embodied in compiled or interpreted instructions, or embodied in some other variants or combinations of instructions. Various components or modules can be executed in a synchronous or asynchronous manner, serially or in parallel, in a single-threaded environment or a multi-threaded environment, in a single processor or a multi-processor environment, in a single host or a multi-host environment, or according to any other suitable execution paradigm, variant or combination thereof. Software 805 can include additional processes, programs or components, such as operating system software, virtualization software or other application software. Software 805 can also include firmware or some other form of machine-readable processing instructions that can be executed by processing system 802.

[0102] Typically, when loaded into processing system 802 and executed, software 805 can transform an appropriate device, system, or apparatus (of which computing system 801 is representative) from a general-purpose computing system as a whole to a special-purpose computing system that is customized to provide memory access as described herein. In practice, the encoded software 805 on storage system 803 can transform the physical structure of storage system 803. The specific transformation of the physical structure can depend on various factors in different embodiments of the present description. Examples of such factors can include, but are not limited to, the technology of the storage medium used to implement storage system 803 and whether the computer storage medium is characterized as primary storage or secondary storage, as well as other factors.

[0103] For example, if the computer-readable storage medium is implemented as a semiconductor-based memory, then when program instructions are encoded therein, the software 805 can transform the physical state of the semiconductor memory, such as by transforming the state of transistors, capacitors, or other discrete circuit elements that make up the semiconductor memory. Similar transformations can occur with respect to magnetic or optical media. Other transformations of the physical media are possible without departing from the scope of this description, and the above examples are provided only to facilitate this discussion.

[0104] The communication interface system 807 may include communication connections and devices that allow communication with other computing systems (not shown) through a communication network (not shown). Examples of connections and devices that together allow inter-system communication may include network interface cards, antennas, power amplifiers, radio frequency circuitry, transceivers, and other communication circuitry. The connections and devices may communicate through a communication medium to exchange communications with other computing systems or systems networks (such as metal, glass, air, or any other suitable communication medium). The above-mentioned media, connections, and devices are well known and need not be discussed in detail here.

[0105] Communications between computing system 801 and other computing systems (not shown) may be performed over one or more communications networks and according to various communications protocols, combinations of protocols, or variations thereof. Examples include intranets, the Internet, local area networks, wide area networks, wireless networks, wired networks, virtual networks, software-defined networks, data center buses and backplanes, or any other type of network, combination of networks, or variations thereof. The above-mentioned communications networks and protocols are well known and need not be discussed in detail here.

[0106] As will be appreciated by those skilled in the art, aspects of the present invention may be embodied as systems, methods, or computer program products. Thus, aspects of the present invention may take the form of a complete hardware implementation, a complete software implementation (including firmware, resident software, microcode, etc.), or a combination of software and hardware aspects, all of which are generally referred to herein as "circuits," "modules," or "systems." Additionally, aspects of the present invention may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0107] In fact, the included description and drawings depict specific embodiments to teach those skilled in the art how to make and use the best mode. In order to teach the principles of the invention, some conventional aspects have been simplified or omitted. Those skilled in the art will understand variations from these embodiments that fall within the scope of the present disclosure. Those skilled in the art will also understand that the above features can be combined in various ways to form multiple embodiments. Therefore, the present invention is not limited to the above specific embodiments, but only by the claims and their equivalents.

[0108] The above description and the associated drawings teach the best mode of the present invention. The appended claims specify the scope of the present invention. Note that some aspects of the best mode may not fall within the scope of the present invention specified by the claims. Those skilled in the art will appreciate that the above features may be combined in various ways to form multiple variations of the present invention. Therefore, the present invention is not limited to the above specific embodiments, but is only limited by the appended claims and their equivalents.

Claims

1. A system comprising: instruction fetch circuit system; decoder circuitry coupled to the instruction fetch circuitry; as well as multiple conditional branching circuitry coupled to the decoder circuitry; The instruction fetch circuit system is configured to: fetching a multiple conditional branch instruction from a memory, wherein the multiple conditional branch instruction identifies a plurality of registers and a plurality of branch destinations, wherein each of the plurality of branch destinations corresponds to a respective register of the plurality of registers; as well as providing the multiple conditional branch instructions to the decoder circuitry; Wherein the decoder circuitry is configured to cause the multi-conditional branch circuitry to execute the multi-conditional branch instruction.

2. The system of claim 1 , wherein the plurality of registers include a first register storing a first condition evaluation result and a second register storing a second condition evaluation result, and wherein the plurality of branch destinations include a first branch destination corresponding to the first condition evaluation result and a second branch destination corresponding to the second condition evaluation result.

3. The system of claim 2, wherein the first condition evaluation result indicates whether a first comparison operation between a first variable and a second variable is true or false, and wherein the second condition evaluation result indicates whether a second comparison operation between the first variable and a third variable is true or false.

4. The system of claim 3, wherein the multi-conditional branch circuit system is configured to: providing the first branch destination to the instruction fetch circuitry when the first conditional evaluation result indicates that the first comparison operation is true; providing the second branch destination to the instruction fetch circuitry when the second conditional evaluation result indicates that the second comparison operation is true; and A default branch destination is provided to the instruction fetch circuitry when the first conditional evaluation indicates that the first comparison operation is false and the second conditional evaluation indicates that the second comparison operation is false. 5 . The system of claim 4 , further comprising a PCU, wherein the PCU includes the multi-conditional branch circuit system.

6. The system of claim 4, wherein the multi-conditional branch circuit system comprises a first multiplexer (a first MUX) and a second MUX, the first MUX comprising two input channels and the second MUX comprising another two input channels.

7. The system of claim 6, wherein the multi-conditional branch circuit system is further configured to: When the output of the second MUX includes the address of the first branch destination, providing the first branch destination; and When the output of the second MUX includes the address of the second branch destination, the second branch destination is provided.

8. The system of claim 2 , wherein the plurality of registers further include a third register storing a third condition evaluation result and a fourth register storing a fourth condition evaluation result, and wherein the plurality of branch destinations further include a third branch destination corresponding to the third condition evaluation result and a fourth branch destination corresponding to the fourth condition evaluation result.

9. A computing device comprising: Memory devices; as well as one or more processors operably coupled to the memory device; wherein the one or more processors are configured to at least: fetching a multiple conditional branch instruction from a memory, wherein the multiple conditional branch instruction identifies a plurality of registers and a plurality of branch destinations, wherein each of the plurality of branch destinations corresponds to a respective register of the plurality of registers; as well as The multiple conditional branch instructions are executed.

10. The computing device of claim 9, wherein the plurality of registers include a first register storing a first condition evaluation result and a second register storing a second condition evaluation result, and wherein the plurality of branch destinations include a first branch destination corresponding to the first condition evaluation result and a second branch destination corresponding to the second condition evaluation result.

11. The computing device of claim 10, wherein the first condition evaluation result indicates whether a first comparison operation between a first variable and a second variable is true or false, and wherein the second condition evaluation result indicates whether a second comparison operation between the first variable and a third variable is true or false.

12. The computing device of claim 11, wherein the one or more processors are further configured to: providing the first branch destination to the instruction fetch circuitry when the first conditional evaluation result indicates that the first comparison operation is true; providing the second branch destination to the instruction fetch circuitry when the second conditional evaluation result indicates that the second comparison operation is true; and A default branch destination is provided to the instruction fetch circuitry when the first conditional evaluation indicates that the first comparison operation is false and the second conditional evaluation indicates that the second comparison operation is false.

13. The computing device of claim 10, wherein the one or more processors include a first multiplexer circuit, namely a first MUX circuit, and a second MUX circuit, wherein the first MUX circuit includes two input channels and the second MUX circuit includes another two input channels.

14. The computing device of claim 13, wherein the one or more processors are further configured to: providing the first branch destination when the output of the second MUX circuit includes the address of the first branch destination; and When the output of the second MUX circuit includes the address of the second branch destination, the second branch destination is provided.

15. One or more computer-readable storage media comprising: program instructions stored thereon, the program instructions comprising a multiple conditional branch instruction that identifies a plurality of registers and a plurality of branch destinations, wherein each of the plurality of branch destinations corresponds to a respective register of the plurality of registers, and wherein the program instructions, when read and executed by processing circuitry, direct the processing circuitry to: The multiple conditional branch instructions are executed.

16. One or more computer-readable storage media according to claim 15, wherein the plurality of registers includes a first register storing a first conditional evaluation result and a second register storing a second conditional evaluation result, and wherein the plurality of branch destinations includes a first branch destination corresponding to the first conditional evaluation result and a second branch destination corresponding to the second conditional evaluation result.

17. One or more computer-readable storage media according to claim 16, wherein the first condition evaluation result indicates whether a first comparison operation between a first variable and a second variable is true or false, and wherein the second condition evaluation result indicates whether a second comparison operation between the first variable and a third variable is true or false.

18. The one or more computer-readable storage media of claim 17, wherein the program instructions further direct the processing circuitry to: providing the first branch destination to the instruction fetch circuitry when the first conditional evaluation result indicates that the first comparison operation is true; providing the second branch destination to the instruction fetch circuitry when the second conditional evaluation result indicates that the second comparison operation is true; and A default branch destination is provided to the instruction fetch circuitry when the first conditional evaluation indicates that the first comparison operation is false and the second conditional evaluation indicates that the second comparison operation is false.

19. The one or more computer-readable storage media of claim 16, wherein the processing circuit system includes a first multiplexer circuit (i.e., a first MUX circuit) and a second MUX circuit, wherein the first MUX circuit includes two input channels and the second MUX circuit includes another two input channels.

20. The one or more computer-readable storage media of claim 19, wherein the program instructions further direct the processing circuitry to: providing the first branch destination when the output of the second MUX circuit includes the address of the first branch destination; and When the output of the second MUX circuit includes the address of the second branch destination, the second branch destination is provided.

Images