Interrupt verification method, system, device and equipment of controller and storage medium

Abstract

The embodiment of the invention provides an interrupt verification method, system, device and equipment for a controller and a storage medium. The method comprises the steps that an interrupt test case of a to-be-verified controller is generated through a sequence generator; executing the interrupt behavior test case through an interrupt reference module to obtain an expected test result of the interrupt behavior test case; executing the interrupt behavior test case through the to-be-verified controller to obtain an actual test result of the interrupt behavior test case; under the condition that the scoreboard receives the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case, whether the controller to be verified meets the design requirement of the interrupt behavior or not is determined according to the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case. According to the method and the device, the complex interrupt logic, namely the interrupt behavior, of the controller to be verified is verified through the independent interrupt reference module, so that the sufficiency and the interrupt verification accuracy of the controller are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of function verification, and in particular to a controller interrupt verification method, system, device, equipment and storage medium. Background Art

[0002] As an important part of the SGPIO (Serial General Purpose Input / Output) controller, interrupts are responsible for triggering responses under specific conditions to achieve real-time monitoring and exception handling of devices. Therefore, thoroughly verifying the interrupts of the SGPIO controller to ensure that it can respond accurately in various complex scenarios is a necessary condition to ensure system stability and data security.

[0003] The existing interrupt verification method of the SGPIO controller usually integrates the verification of the interrupt into a comprehensive reference module, and verifies the interrupt of the SGPIO controller through the comprehensive reference module. However, interrupts often involve multi-level interactions between hardware and software, and it is necessary to consider all possible interrupt trigger conditions, priorities, and complex logic such as nested interrupts, which not only increases the difficulty of building a verification environment, but also makes the verification process extremely cumbersome. It is extremely difficult to ensure that the verification covers all possible interrupt scenarios and their boundary conditions, which greatly reduces the adequacy of interrupt verification. In addition, interrupt verification needs to handle multiple concurrent events while ensuring the real-time response, which is often difficult to take into account in existing methods, especially when the interrupt enable, shielding and response logic are complex, it is easy to have problems with low verification accuracy and incomplete verification. Therefore, the existing interrupt verification method of the SGPIO controller has the problems of insufficient verification and low verification accuracy. Summary of the invention

[0004] In view of this, the present application aims to propose a controller interrupt verification method, system, device, equipment and storage medium to solve the problems of insufficient verification and low verification accuracy caused by the difficulty in ensuring that verification covers all possible interrupt scenarios and their boundary conditions, and the difficulty in simultaneously taking into account the real-time processing of multiple concurrent events and responses when processing complex interrupt logic.

[0005] According to a first aspect of the present application, a controller interrupt verification method is provided, characterized in that it is applied to an interrupt verification architecture, the interrupt verification architecture includes a sequencer, a reference module, a controller to be verified, and a scoreboard, wherein the reference module includes an interrupt reference module and a function reference module, the sequencer establishes communication connections with the reference module and the controller to be verified respectively, and the scoreboard establishes communication connections with the reference module and the controller to be verified respectively, and the method includes:

[0006] Generate an interrupt test case of the controller to be verified by the sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified;

[0007] Executing the interrupt behavior test case through the interrupt reference module to obtain an expected test result of the interrupt behavior test case, and sending the expected test result of the interrupt behavior test case to the scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified;

[0008] Execute the interruption behavior test case through the controller to be verified to obtain an actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard;

[0009] When the scoreboard receives the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case, the interruption behavior of the controller to be verified is verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

[0010] Optionally, generating an interrupt test case of the controller to be verified by the sequence generator includes:

[0011] Acquiring functional characteristic data of the controller to be verified through the sequence generator;

[0012] When the sequence generator obtains the functional characteristic data of the controller to be verified, the interrupt of the controller to be verified is decomposed into test function points according to the functional characteristic data of the controller to be verified to obtain test function points;

[0013] When the sequence generator obtains the test function point, an interruption test case of the controller to be verified is designed according to the test function point.

[0014] Optionally, before the step of generating an interruption test case of the controller to be verified by the sequence generator, the method includes:

[0015] Set up the verification environment in advance;

[0016] When the verification environment is built, the interrupt registers of the reference module and the controller to be verified are configured by the sequence generator;

[0017] When the interrupt register configuration is completed, the timing of the controller to be verified and the reference module are aligned according to the signal timing relationship of the controller to be verified.

[0018] Optionally, the interrupt verification architecture includes an interrupt register configuration component, the interrupt register configuration component establishes communication connections with the sequencer and the controller to be verified respectively, and the interrupt register configuration of the reference module and the controller to be verified through the sequencer includes:

[0019] Sending interrupt register configuration data to the interrupt register configuration component and the reference module respectively through the sequence generator;

[0020] When the interrupt register configuration component receives the interrupt register configuration data, the interrupt register configuration data is sent to the controller to be verified;

[0021] When the controller to be verified receives the interrupt register configuration data, configuring the interrupt register of the controller to be verified according to the interrupt register configuration data;

[0022] When the reference module receives the interrupt register configuration data, the reference module performs interrupt register configuration according to the interrupt register configuration data.

[0023] Optionally, the interruption test case includes a random interruption function test case and a directional interruption function test case. Before the step of executing the interruption behavior test case through the interruption reference module to obtain an expected test result of the interruption behavior test case, the method includes:

[0024] Sending the random interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator, wherein the interrupt function of the function reference module is the same as that of the controller to be verified;

[0025] When the function reference module receives the random interruption function test case, the function reference module executes the random interruption function test case to obtain an expected test result of the random interruption function test case, and sends the expected test result of the random interruption function test case to the scoreboard;

[0026] When the controller to be verified receives the random interrupt function test case, the controller executes the random interrupt function test case to obtain an actual test result of the random interrupt function test case, and sends the actual test result of the random interrupt function test case to the scoreboard;

[0027] In a case where the scoreboard receives the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case, determining whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case;

[0028] After determining whether the controller to be verified meets the design requirements of the random interrupt function, sending the directional interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator;

[0029] In the case where the function reference module receives the directional interrupt function test case, executing the directional interrupt function test case, obtaining an expected test result of the directional interrupt function test case, and sending the expected test result of the directional interrupt function test case to the scoreboard;

[0030] When the controller to be verified receives the directional interrupt function test case, the directional interrupt function test case is executed to obtain an actual test result of the directional interrupt function test case, and the actual test result of the directional interrupt function test case is sent to the scoreboard;

[0031] In a case where the scoreboard receives the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case, determining whether the controller to be verified meets the design requirements of the directional interrupt function according to the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case;

[0032] After determining whether the controller to be verified meets the design requirements of the directional interrupt function, the interrupt behavior test case is executed through the interrupt reference module to obtain an expected test result of the interrupt behavior test case.

[0033] Optionally, the verifying the interruption behavior of the controller to be verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case includes:

[0034] If the expected test result of the interruption behavior test case is consistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified passes the interruption behavior verification;

[0035] If the expected test result of the interruption behavior test case is inconsistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified has failed the interruption behavior verification.

[0036] According to a second aspect of the present application, there is provided a controller interrupt verification system, the controller interrupt verification system comprising a sequence generator, a reference module, a controller to be verified and a scoreboard, wherein the reference module comprises an interrupt reference module and a function reference module;

[0037] The sequence generator is used to generate interrupt test cases of the controller to be verified, wherein the interrupt test cases include interrupt behavior test cases, wherein the interrupt behavior test cases are used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified;

[0038] The interruption reference module is used to execute the interruption behavior test case, obtain the expected test result of the interruption behavior test case, and send the expected test result of the interruption behavior test case to the scoreboard, wherein the interruption reference module has the same interruption function as the controller to be verified;

[0039] The controller to be verified is used to execute the interruption behavior test case, obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard;

[0040] The scoreboard is used to verify the interruption behavior of the controller to be verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case when receiving the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

[0041] According to a third aspect of the present application, there is provided an interrupt verification device for a controller, the device comprising:

[0042] An interrupt test case generation module, used for generating an interrupt test case of the controller to be verified through the sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used for testing the interrupt enable, interrupt mask and interrupt priority of the controller to be verified;

[0043] An interrupt reference module processing module, used for executing the interrupt behavior test case through the interrupt reference module, obtaining the expected test result of the interrupt behavior test case, and sending the expected test result of the interrupt behavior test case to the scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified;

[0044] A controller processing module to be verified, used for executing the interruption behavior test case through the controller to be verified, obtaining an actual test result of the interruption behavior test case, and sending the actual test result of the interruption behavior test case to the scoreboard;

[0045] An interrupt verification module is used to verify the interrupt behavior of the controller to be verified according to the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case when the scoreboard receives the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case.

[0046] Optionally, the interruption test case generation module includes:

[0047] A design data acquisition submodule, used for acquiring the design data and functional characteristic data of the controller to be verified through the sequence generator;

[0048] A functional test point decomposition module, used for, when the sequencer obtains the functional characteristic data of the controller to be verified, performing test function point decomposition on the interrupt of the controller to be verified according to the functional characteristic data of the controller to be verified to obtain the test function points;

[0049] The test case design submodule is used to design an interrupt test case of the controller to be verified according to the test function point when the sequence generator obtains the test function point.

[0050] Optionally, the device further comprises:

[0051] Verification environment building module, used to build the verification environment in advance;

[0052] An interrupt register configuration module, used to configure interrupt registers of the reference module and the controller to be verified through the sequence generator when the verification environment is built;

[0053] The signal timing alignment module is used to align the timing of the controller to be verified and the reference module according to the signal timing relationship of the controller to be verified when the interrupt register configuration is completed.

[0054] Optionally, the interrupt verification architecture includes an interrupt register configuration component, the interrupt register configuration component establishes communication connections with the sequence generator and the controller to be verified respectively, and the interrupt register configuration module includes:

[0055] An interrupt register configuration data sending submodule, used for sending interrupt register configuration data to the interrupt register configuration component and the reference module respectively through the sequence generator;

[0056] An interrupt register configuration component receiving submodule, configured to send the interrupt register configuration data to the controller to be verified when the interrupt register configuration component receives the interrupt register configuration data;

[0057] a configuration submodule of the controller to be verified, configured to configure the interrupt register of the controller to be verified according to the interrupt register configuration data when the controller to be verified receives the interrupt register configuration data;

[0058] The reference module configuration submodule is used to configure the interrupt register of the reference module according to the interrupt register configuration data when the reference module receives the interrupt register configuration data.

[0059] Optionally, the interruption test case includes a random interruption function test case and a directional interruption function test case, and the device further includes:

[0060] A random interrupt function test case sending module, used for sending the random interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator, wherein the interrupt function of the function reference module is the same as that of the controller to be verified;

[0061] A random expected test result determination module, used for executing the random interruption function test case when the function reference module receives the random interruption function test case, obtaining the expected test result of the random interruption function test case, and sending the expected test result of the random interruption function test case to the scoreboard;

[0062] A random actual test result determination module, configured to execute the random interruption function test case, obtain the actual test result of the random interruption function test case, and send the actual test result of the random interruption function test case to the scoreboard when the controller to be verified receives the random interruption function test case;

[0063] A random interrupt function verification module, used for determining whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case when the scoreboard receives the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case;

[0064] a directional interrupt function test case sending module, configured to send the directional interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator when determining whether the controller to be verified meets the design requirements of the random interrupt function;

[0065] a directional expected test result determination module, configured to execute the directional interruption function test case when the function reference module receives the directional interruption function test case, obtain the expected test result of the directional interruption function test case, and send the expected test result of the directional interruption function test case to the scoreboard;

[0066] a directional actual test result determination module, configured to execute the directional interrupt function test case, obtain the actual test result of the directional interrupt function test case, and send the actual test result of the directional interrupt function test case to the scoreboard when the controller to be verified receives the directional interrupt function test case;

[0067] a directional interrupt function verification module, configured to determine whether the controller to be verified meets the design requirements of the directional interrupt function according to the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case when the scoreboard receives the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case;

[0068] The interrupt behavior test case execution module is used to execute the interrupt behavior test case through the interrupt reference module after determining whether the controller to be verified meets the design requirements of the directional interrupt function, so as to obtain the expected test result of the interrupt behavior test case.

[0069] Optionally, the interrupt verification module includes:

[0070] A first interrupt behavior verification submodule, configured to determine that the controller to be verified passes the interrupt behavior verification if the expected test result of the interrupt behavior test case is consistent with the actual test result of the interrupt behavior test case;

[0071] The second interrupt behavior verification submodule is used to determine that the controller to be verified fails the interrupt behavior verification if the expected test result of the interrupt behavior test case is inconsistent with the actual test result of the interrupt behavior test case.

[0072] According to another aspect of the present application, there is also provided an electronic device, including:

[0073] processor;

[0074] a memory for storing instructions executable by the processor;

[0075] The processor is configured to execute the instructions to implement the interrupt verification method of the controller as described above.

[0076] According to another aspect of the present application, a readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the interrupt verification method of the controller as described above are implemented.

[0077] The interrupt verification method of the controller provided in the embodiment of the present application is applied to the interrupt verification architecture, and generates interrupt test cases of the controller to be verified through a sequence generator, wherein the interrupt test cases include interrupt behavior test cases, wherein the interrupt behavior test cases are used to test the interrupt enable, interrupt masking and interrupt priority of the controller to be verified; the interrupt behavior test cases are executed through an interrupt reference module to obtain expected test results of the interrupt behavior test cases, and the expected test results of the interrupt behavior test cases are sent to a scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified; the interrupt behavior test cases are executed through the controller to be verified to obtain actual test results of the interrupt behavior test cases, and the actual test results of the interrupt behavior test cases are sent to the scoreboard; when the scoreboard receives the expected test results of the interrupt behavior test cases and the actual test results of the interrupt behavior test cases, it is determined whether the controller to be verified meets the design requirements of the interrupt behavior according to the expected test results of the interrupt behavior test cases and the actual test results of the interrupt behavior test cases. The present application tests complex interrupt logic, interrupt enable, interrupt masking and interrupt priority through a separate interrupt reference module, which not only ensures that interrupt verification covers all possible interrupt scenarios and their boundary conditions, but also ensures the real-time processing of multiple concurrent events and responses when verifying the complex interrupt logic, thereby improving the adequacy of interrupt verification and the accuracy of interrupt verification. Furthermore, it solves the problems of insufficient verification and low verification accuracy in the prior art due to the difficulty in ensuring that verification covers all possible interrupt scenarios and their boundary conditions and the difficulty in taking into account the real-time processing of multiple concurrent events and responses when processing complex interrupt logic.

[0078] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0080] Figure 1 One of the step flow charts of a controller interrupt verification method provided in an embodiment of the present application;

[0081] Figure 2 is a schematic diagram of an interrupt verification architecture provided by an embodiment of the present application;

[0082] Figure 3 This is the second step flow chart of a controller interrupt verification method provided by an embodiment of the present application;

[0083] Figure 4 This is a flowchart of the third step of a controller interrupt verification method provided by an embodiment of the present application;

[0084] Figure 5 This is a fourth step flow chart of a controller interrupt verification method provided by an embodiment of the present application;

[0085] Figure 6 It is a schematic diagram of a signal timing relationship of an SGPIO controller to be verified provided in an embodiment of the present application;

[0086] Figure 7 It is a device block diagram of an interrupt verification device of a controller provided in an embodiment of the present application;

[0087] Figure 8 It is a schematic diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0088] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

[0089] Reference Figure 1 , shows one of the flow charts of the interrupt verification method of the controller provided in an embodiment of the present application, which is applied to the interrupt verification architecture, such as Figure 2 As shown, the interrupt verification architecture includes a sequencer, a reference module, a controller to be verified, and a scoreboard, wherein the reference module includes an interrupt reference module and a function reference module, the sequencer establishes communication connections with the reference module and the controller to be verified respectively, and the scoreboard establishes communication connections with the reference module and the controller to be verified respectively. The method may include:

[0090] Step 101 , generating interrupt test cases of the controller to be verified by a sequence generator, wherein the interrupt test cases include interrupt behavior test cases, wherein the interrupt behavior test cases are used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified.

[0091] It should be noted that in the embodiment of the present application, the controller to be verified is an SGPIO controller. In order to verify whether the interrupt enable, interrupt mask and interrupt priority of the SGPIO controller to be verified meet the design requirements, it is necessary to generate interrupt test cases of the SGPIO controller to be verified by a sequence generator in advance, and the interrupt test cases include interrupt behavior test cases. The interrupt enable, interrupt mask and interrupt priority of the SGPIO controller to be verified are verified based on the interrupt behavior test cases.

[0092] Step 102, executing the interrupt behavior test case through the interrupt reference module, obtaining the expected test result of the interrupt behavior test case, and sending the expected test result of the interrupt behavior test case to the scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified.

[0093] It should be noted that in the embodiment of the present application, the interrupt reference module has the same function as the SGPIO controller to be verified. When the sequencer generates an interrupt behavior test case of the SGPIO controller to be verified, the sequencer sends the interrupt behavior test case to the interrupt reference module and the SGPIO controller to be verified respectively.

[0094] When the interruption reference module receives the interruption behavior test case sent by the sequence generator, the interruption behavior test case is executed to obtain the expected test result of the interruption behavior test case, and the expected test result of the interruption behavior test case is sent to the scoreboard.

[0095] Step 103: Execute the interruption behavior test case through the controller to be verified to obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard.

[0096] It should be noted that in an embodiment of the present application, when the SGPIO controller to be verified receives an interrupt behavior test case sent by the sequence generator, the interrupt behavior test case is executed to obtain the actual test result of the interrupt behavior test case, and the actual test result of the interrupt behavior test case is sent to the scoreboard.

[0097] Step 104 , when the scoreboard receives the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case, the interruption behavior of the controller to be verified is verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

[0098] It should be noted that in an embodiment of the present application, when the scoreboard receives the expected test results of the interrupt behavior test case sent by the interrupt reference module and the actual test results of the interrupt behavior test case sent by the SGPIO controller to be verified, the scoreboard verifies the interrupt behavior of the controller to be verified based on the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case, that is, determines whether the SGPIO controller to be verified meets the design requirements of the interrupt behavior.

[0099] The present application tests complex interrupt logic, interrupt enable, interrupt masking and interrupt priority through a separate interrupt reference module, which not only ensures that interrupt verification covers all possible interrupt scenarios and their boundary conditions, but also ensures the real-time processing of multiple concurrent events and responses when verifying the complex interrupt logic, thereby improving the adequacy of interrupt verification and the accuracy of interrupt verification. Furthermore, it solves the problems of insufficient verification and low verification accuracy in the prior art due to the difficulty in ensuring that verification covers all possible interrupt scenarios and their boundary conditions and the difficulty in taking into account the real-time processing of multiple concurrent events and responses when processing complex interrupt logic.

[0100] Furthermore, if Figure 3 FIG. 2 shows a second flow chart of the interrupt verification method of the controller provided in an embodiment of the present invention. In the embodiment of the present application, step 101 may further include the following steps:

[0101] Step 301: Acquire functional characteristic data of the controller to be verified through a sequence generator.

[0102] Step 302: When the sequencer obtains functional characteristic data of the controller to be verified, the interrupt of the controller to be verified is decomposed into test function points according to the functional characteristic data of the controller to be verified to obtain test function points.

[0103] Step 303: When the sequence generator obtains the test function point, an interrupt test case of the controller to be verified is designed according to the test function point.

[0104] It should be noted that, in the embodiment of the present application, the design document of the SGPIO controller to be verified is obtained through a sequencer, and the functional characteristic data of the SGPIO controller to be verified is obtained from the design document of the SGPIO controller to be verified. When the sequencer obtains the functional characteristic data of the SGPIO controller to be verified, the interrupt of the SGPIO controller to be verified is decomposed into test function points according to the functional characteristic data of the SGPIO controller to be verified to obtain the test function points. When the sequencer obtains the test function points, the interrupt test case of the SGPIO controller to be verified is designed according to the test function points.

[0105] The present application decomposes the test function points according to the functional characteristic data of the controller to be verified to obtain the test function points, and then designs the interrupt test cases of the controller to be verified according to the test function points. This can not only ensure that the interrupt test cases are consistent with the actual design specifications of the SGPIO controller to be verified, thereby reducing test omissions or errors caused by misunderstanding, but also take the details of each interrupt into consideration, thereby designing more comprehensive interrupt test cases and ensuring that all possible interrupt scenarios are tested.

[0106] Furthermore, if Figure 4 As shown, a flowchart of the third step of the interrupt verification method of the controller provided in the embodiment of the present application is shown. In the embodiment of the present application, the following steps may be included before step 201:

[0107] Step 401, pre-build a verification environment.

[0108] Step 402: When the verification environment is set up, interrupt registers of the reference module and the controller to be verified are configured through a sequencer.

[0109] Step 403 , when the interrupt register configuration is completed, align the timing of the controller to be verified and the reference module according to the signal timing relationship of the controller to be verified.

[0110] It should be noted that in the embodiment of the present application, the verification environment is set up in advance according to the test function points. When the verification environment is set up, in order to ensure that the reference module and the SGPIO controller to be verified can execute the test cases and output results normally, it is necessary to configure the interrupt registers of the reference module and the SGPIO controller to be verified respectively through the sequence generator. When the interrupt register configuration of the reference module and the SGPIO controller to be verified is completed, in order to ensure that the SGPIO controller to be verified and the reference module can receive data normally, it is necessary to align the timing of the SGPIO controller to be verified and the reference module according to the signal timing relationship of the SGPIO controller to be verified.

[0111] This application can ensure that the test cases are executed in a consistent and reliable verification environment by setting up a verification environment and configuring interrupt registers for the reference module and the controller to be verified, thereby reducing the impact of external factors on the test results. In addition, this application can not only ensure that the SGPIO controller to be verified and the reference module can receive data normally, but also ensure that the controller to be verified and the reference module have consistent timing when processing data, thereby improving the reliability of the test results and reducing test errors caused by inconsistent timing.

[0112] Furthermore, if Figure 5 As shown, a fourth step flow chart of the interrupt verification method of the controller provided in the embodiment of the present application is shown. In the embodiment of the present application, step 402 may also include the following steps:

[0113] Step 501: Send interrupt register configuration data to the interrupt register configuration component and the reference module respectively through a sequence generator.

[0114] Step 502: When the interrupt register configuration component receives the interrupt register configuration data, the interrupt register configuration data is sent to the controller to be verified.

[0115] Step 503 : When the controller to be verified receives the interrupt register configuration data, the interrupt register of the controller to be verified is configured according to the interrupt register configuration data.

[0116] Step 504: When the reference module receives the interrupt register configuration data, configure the interrupt register of the reference module according to the interrupt register configuration data.

[0117] It should be noted that, in the embodiment of the present application, the interrupt verification architecture further includes an interrupt register configuration component, and the interrupt register configuration component establishes communication connections with the sequence generator and the SGPIO controller to be verified respectively.

[0118] The interrupt register configuration data is sent to the interrupt register configuration component and the reference module respectively through the sequence generator. When the interrupt register configuration component receives the interrupt register configuration data, the interrupt register configuration data is sent to the SGPIO controller to be verified. When the SGPIO controller to be verified receives the interrupt register configuration data, the interrupt register of the SGPIO controller to be verified is configured according to the interrupt register configuration data, including configuring the interrupt enable register, configuring the interrupt mask register, and configuring the interrupt priority register.

[0119] When the reference module receives the interrupt register configuration data, the reference module configures the interrupt register of the reference module according to the interrupt register configuration data, thereby ensuring that the reference module and the SGPIO controller to be verified have the same interrupt register configuration.

[0120] The present application uses a sequence generator to uniformly send interrupt register configuration data to the interrupt register configuration component and the reference module, so that the controller to be verified and the reference module receive consistent interrupt register configuration data, which can ensure that the controller to be verified and the reference module have the same interrupt register configuration, thereby ensuring the reliability and comparability of the test results and reducing test errors caused by differences in interrupt register configurations.

[0121] Furthermore, in the embodiment of the present application, the following steps may be included before step 102:

[0122] A random interrupt function test case is sent to the function reference module and the controller to be verified respectively through a sequence generator, wherein the interrupt function of the function reference module is the same as that of the controller to be verified.

[0123] When the function reference module receives the random interruption function test case, the random interruption function test case is executed to obtain the expected test result of the random interruption function test case, and the expected test result of the random interruption function test case is sent to the scoreboard.

[0124] When the controller to be verified receives the random interrupt function test case, the random interrupt function test case is executed to obtain an actual test result of the random interrupt function test case, and the actual test result of the random interrupt function test case is sent to the scoreboard.

[0125] When the scoreboard receives the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case, it determines whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case.

[0126] After determining whether the controller to be verified meets the design requirements of the random interrupt function, a directional interrupt function test case is sent to the functional reference module and the controller to be verified respectively through a sequence generator.

[0127] When the function reference module receives the directional interrupt function test case, the directional interrupt function test case is executed to obtain the expected test result of the directional interrupt function test case, and the expected test result of the directional interrupt function test case is sent to the scoreboard.

[0128] When the controller to be verified receives a directional interrupt function test case, the directional interrupt function test case is executed to obtain an actual test result of the directional interrupt function test case, and the actual test result of the directional interrupt function test case is sent to the scoreboard.

[0129] When the scoreboard receives the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case, it determines whether the controller to be verified meets the design requirements of the directional interrupt function based on the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case.

[0130] After determining whether the controller to be verified meets the design requirements of the directional interrupt function, the interrupt behavior test case is executed through the interrupt reference module to obtain the expected test result of the interrupt behavior test case.

[0131] It should be noted that in the embodiment of the present application, the functional reference module has the same function as the SGPIO controller to be verified. The interrupt verification architecture also includes a detector, which establishes communication connections with the scoreboard and the SGPIO controller to be verified respectively.

[0132] In the process of interrupt function testing of the SGPIO controller to be verified, a random interrupt function test is first performed to cover most of the test function points, and then a targeted interrupt function test is performed on the boundary conditions of the verification or more complex verification situations.

[0133] The specific implementation process of the random interrupt function test is as follows: a random interrupt function test case is sent to the function reference module and the SGPIO controller to be verified respectively through a sequence generator. When the function reference module receives the random interrupt function test case, the random interrupt function test case is executed to obtain the expected test result of the random interrupt function test case, and the expected test result of the random interrupt function test case is sent to the scoreboard.

[0134] When the controller to be verified receives a random interruption function test case, the random interruption function test case is executed to obtain an actual test result of the random interruption function test case, and the actual test result of the random interruption function test case is sent to the detector. When the detector receives an actual test result of the random interruption function test case, the actual test result of the random interruption function test case is sampled, and the actual test result of the random interruption function test case obtained by sampling is sent to the scoreboard.

[0135] When the scoreboard receives the expected test results of the random interrupt function test case sent by the function reference module and the actual test results of the random interrupt function test case sent by the SGPIO controller to be verified, it is determined whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case. Specifically, the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case are compared. If the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case are consistent, it is determined that the SGPIO controller to be verified meets the design requirements of the random interrupt function. If the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case are inconsistent, it is determined that the SGPIO controller to be verified does not meet the design requirements of the random interrupt function.

[0136] After completing the random interrupt function test, the SGPIO controller to be verified is subjected to a directional interrupt function test. The specific implementation process of the directional interrupt function test is as follows: a directional interrupt function test case is sent to the functional reference module and the controller to be verified respectively through a sequence generator. When the functional reference module receives the directional interrupt function test case, the directional interrupt function test case is executed to obtain the expected test result of the directional interrupt function test case, and the expected test result of the directional interrupt function test case is sent to the scoreboard.

[0137] In the case where the SGPIO controller to be verified receives a directional interrupt function test case, the directional interrupt function test case is executed to obtain an actual test result of the directional interrupt function test case, and the actual test result of the directional interrupt function test case is sent to the detector. In the case where the detector receives an actual test result of the directional interrupt function test case sent by the SGPIO controller to be verified, the actual test result of the directional interrupt function test case is sampled, and the actual test result of the directional interrupt function test case obtained by the sampling is sent to the scoreboard.

[0138] When the scoreboard receives the expected test results of the directional interrupt function test case sent by the functional reference module and the actual test results of the directional interrupt function test case sent by the SGPIO controller to be verified, it is determined whether the SGPIO controller to be verified meets the design requirements of the directional interrupt function according to the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case. Specifically, the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case are compared. If the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case are consistent, it is determined that the SGPIO controller to be verified meets the design requirements of the directional interrupt function. If the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case are inconsistent, it is determined that the SGPIO controller to be verified does not meet the design requirements of the directional interrupt function.

[0139] After completing the directed interrupt function test of the SGPIO controller to be verified, the interrupt enable, interrupt mask and interrupt priority tests are performed on the SGPIO controller to be verified, that is, the interrupt behavior test case is executed through the interrupt reference module to obtain the expected test result of the interrupt behavior test case.

[0140] The present application first performs a random interrupt function test on the controller to be verified, and then performs a directed interrupt function test. The combination of random interrupt function test and directed interrupt function test can enable the interrupt function test of the controller to be verified to cover most test function points and verification boundary conditions or more complex verification situations, thereby improving the coverage and reliability of interrupt verification of the controller to be verified.

[0141] Further, in an embodiment of the present application, step 104 may also include the following steps: if the expected test result of the interruption behavior test case is consistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified has passed the interruption behavior verification; if the expected test result of the interruption behavior test case is inconsistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified has not passed the interruption behavior verification.

[0142] It should be noted that, in the embodiment of the present application, the specific implementation process of determining whether the controller to be verified meets the design requirements of the interrupt behavior based on the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case is: comparing the expected test results of the interrupt behavior test case with the actual test results of the interrupt behavior test case; if the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case are consistent, then it is determined that the controller to be verified meets the design requirements of the interrupt behavior; if the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case are inconsistent, then it is determined that the controller to be verified does not meet the design requirements of the interrupt behavior.

[0143] This application determines whether the controller to be verified meets the design requirements of interrupt behavior based on the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case, thereby ensuring the reliability and comparability of the test results and reducing test errors caused by functional differences.

[0144] Further, in an embodiment of the present application, step 403 may also include the following steps: when the sequence generator sends test cases to the reference module and the controller to be verified respectively, the test cases are sent to the reference module and the controller to be verified respectively according to the signal timing relationship of the controller to be verified, wherein the signal timing relationship of the controller to be verified includes the timing relationship of the clock signal, the data output signal, the data input signal and the loading signal.

[0145] It should be noted that, in the embodiment of the present application, the specific implementation process of aligning the timing of the controller to be verified and the reference module according to the signal timing relationship of the controller to be verified is as follows: when the sequence generator sends test cases to the reference module and the SGPIO controller to be verified respectively, the sequence generator sends test cases to the reference module and the SGPIO controller to be verified respectively according to the signal timing relationship of the SGPIO controller to be verified, so that the timing of the SGPIO controller to be verified and the reference module can be aligned, and the SGPIO controller to be verified and the reference module can receive data normally, wherein, Figure 6 As shown, the signal timing relationship of the SGPIO controller to be verified includes the timing relationship of the clock (SClock) signal, the data output (SDataOut) signal, the data input (SDataIn) signal and the load (SLoad) signal.

[0146] The present application ensures that the timing of the controller to be verified and the reference module are aligned by sending test cases to the reference module and the controller to be verified respectively according to the signal timing relationship of the controller to be verified when the sequence generator sends test cases to the reference module and the controller to be verified respectively, thereby enabling the controller to be verified and the reference module to receive data normally, thereby providing a good foundation for the subsequent interrupt verification process of the controller to be verified.

[0147] According to an embodiment of the present application, a controller interrupt verification system is also provided. The controller interrupt verification system includes a sequence generator, a reference module, a controller to be verified, and a scoreboard, wherein the reference module includes an interrupt reference module and a function reference module.

[0148] The sequence generator is used to generate interrupt test cases of the controller to be verified, and the interrupt test cases include interrupt behavior test cases, wherein the interrupt behavior test cases are used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified.

[0149] The interruption reference module is used to execute the interruption behavior test case, obtain the expected test result of the interruption behavior test case, and send the expected test result of the interruption behavior test case to the scoreboard, wherein the interruption reference module has the same function as the controller to be verified.

[0150] The controller to be verified is used to execute the interruption behavior test case, obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard.

[0151] The scoreboard is used to verify the interruption behavior of the controller to be verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case when receiving the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

[0152] It should be noted that in the embodiment of the present application, the controller to be verified is an SGPIO controller. In order to verify whether the interrupt enable, interrupt mask and interrupt priority of the SGPIO controller meet the design requirements, it is necessary to generate interrupt test cases of the SGPIO controller to be verified in advance through a sequence generator, and the interrupt test cases include interrupt behavior test cases. The interrupt enable, interrupt mask and interrupt priority of the SGPIO controller to be verified are verified based on the interrupt behavior test cases.

[0153] The interrupt reference module has the same function as the SGPIO controller to be verified. When the sequencer generates an interrupt behavior test case of the SGPIO controller to be verified, the sequencer sends the interrupt behavior test case to the interrupt reference module and the SGPIO controller to be verified respectively.

[0154] When the interruption reference module receives the interruption behavior test case sent by the sequence generator, the interruption behavior test case is executed to obtain the expected test result of the interruption behavior test case, and the expected test result of the interruption behavior test case is sent to the scoreboard.

[0155] When the SGPIO controller to be verified receives the interrupt behavior test case sent by the sequencer, the interrupt behavior test case is executed to obtain an actual test result of the interrupt behavior test case, and the actual test result of the interrupt behavior test case is sent to the scoreboard.

[0156] When the scoreboard receives the expected test results of the interrupt behavior test case sent by the interrupt reference module and the actual test results of the interrupt behavior test case sent by the SGPIO controller to be verified, the scoreboard verifies the interrupt behavior of the SGPIO controller to be verified based on the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case, that is, determines whether the SGPIO controller to be verified meets the design requirements of the interrupt behavior.

[0157] The present application tests complex interrupt logic, interrupt enable, interrupt masking and interrupt priority through a separate interrupt reference module, which not only ensures that interrupt verification covers all possible interrupt scenarios and their boundary conditions, but also ensures the real-time processing of multiple concurrent events and responses when verifying the complex interrupt logic, thereby improving the adequacy of interrupt verification and the accuracy of interrupt verification. Furthermore, it solves the problems of insufficient verification and low verification accuracy in the prior art due to the difficulty in ensuring that verification covers all possible interrupt scenarios and their boundary conditions and the difficulty in taking into account the real-time processing of multiple concurrent events and responses when processing complex interrupt logic.

[0158] According to an embodiment of the present application, a controller interrupt verification device is also provided, referring to Figure 7 , Figure 7 : is a device block diagram of an interrupt verification device of a controller provided in an embodiment of the present application, and the interrupt verification device of the controller includes:

[0159] An interrupt test case generation module 701 is used to generate an interrupt test case of the controller to be verified through a sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified;

[0160] An interrupt reference module processing module 702 is used to execute an interrupt behavior test case through an interrupt reference module, obtain an expected test result of the interrupt behavior test case, and send the expected test result of the interrupt behavior test case to a scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified;

[0161] The controller processing module 703 to be verified is used to execute the interruption behavior test case through the controller to be verified, obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard;

[0162] The interrupt verification module 704 is used to verify the interrupt behavior of the controller to be verified according to the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case when the scoreboard receives the expected test results of the interrupt behavior test case and the actual test results of the interrupt behavior test case.

[0163] Optionally, the interruption test case generation module includes:

[0164] A design data acquisition submodule is used to acquire functional characteristic data of the controller to be verified through a sequence generator;

[0165] The functional test point decomposition module is used to decompose the interrupt of the controller to be verified according to the functional characteristic data of the controller to be verified to obtain the test function points when the sequence generator obtains the functional characteristic data of the controller to be verified;

[0166] The test case design submodule is used to design interrupt test cases of the controller to be verified according to the test function points when the sequence generator obtains the test function points.

[0167] Optionally, the device further comprises:

[0168] Verification environment building module, used to build the verification environment in advance;

[0169] An interrupt register configuration module is used to configure the interrupt registers of the reference module and the controller to be verified through a sequence generator when the verification environment is set up;

[0170] The signal timing alignment module is used to align the timing of the controller to be verified and the reference module according to the signal timing relationship of the controller to be verified when the interrupt register configuration is completed.

[0171] Optionally, the interrupt verification architecture includes an interrupt register configuration component, the interrupt register configuration component establishes communication connections with the sequence generator and the controller to be verified respectively, and the interrupt register configuration module includes:

[0172] An interrupt register configuration data sending submodule, used for sending interrupt register configuration data to the interrupt register configuration component and the reference module respectively through a sequence generator;

[0173] The interrupt register configuration component receiving submodule is used to send the interrupt register configuration data to the controller to be verified when the interrupt register configuration component receives the interrupt register configuration data;

[0174] The controller configuration submodule to be verified is used to configure the interrupt register of the controller to be verified according to the interrupt register configuration data when the controller to be verified receives the interrupt register configuration data;

[0175] The reference module configuration submodule is used to configure the interrupt register of the reference module according to the interrupt register configuration data when the reference module receives the interrupt register configuration data.

[0176] Optionally, the interruption test case includes a random interruption function test case and a directional interruption function test case, and the device further includes:

[0177] A random interrupt function test case sending module is used to send random interrupt function test cases to the function reference module and the controller to be verified respectively through a sequence generator, wherein the interrupt function of the function reference module is the same as that of the controller to be verified;

[0178] A random expected test result determination module is used to execute the random interruption function test case when the function reference module receives the random interruption function test case, obtain the expected test result of the random interruption function test case, and send the expected test result of the random interruption function test case to the scoreboard;

[0179] A random actual test result determination module is used to execute the random interruption function test case when the controller to be verified receives the random interruption function test case, obtain the actual test result of the random interruption function test case, and send the actual test result of the random interruption function test case to the scoreboard;

[0180] A random interrupt function verification module, used to determine whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case when the scoreboard receives the expected test results of the random interrupt function test case and the actual test results of the random interrupt function test case;

[0181] A directional interrupt function test case sending module is used to send directional interrupt function test cases to the function reference module and the controller to be verified through a sequence generator respectively after determining whether the controller to be verified meets the design requirements of the random interrupt function;

[0182] A directional expected test result determination module is used to execute the directional interruption function test case when the function reference module receives the directional interruption function test case, obtain the expected test result of the directional interruption function test case, and send the expected test result of the directional interruption function test case to the scoreboard;

[0183] A directional actual test result determination module is used to execute the directional interrupt function test case when the controller to be verified receives the directional interrupt function test case, obtain the actual test result of the directional interrupt function test case, and send the actual test result of the directional interrupt function test case to the scoreboard;

[0184] A directional interrupt function verification module, used to determine whether the controller to be verified meets the design requirements of the directional interrupt function according to the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case when the scoreboard receives the expected test results of the directional interrupt function test case and the actual test results of the directional interrupt function test case;

[0185] The interrupt behavior test case execution module is used to execute the interrupt behavior test case through the interrupt reference module after determining whether the controller to be verified meets the design requirements of the directional interrupt function, so as to obtain the expected test result of the interrupt behavior test case.

[0186] Optionally, the interrupt verification module includes:

[0187] A first interrupt behavior verification submodule, configured to determine that the controller to be verified passes the interrupt behavior verification if the expected test result of the interrupt behavior test case is consistent with the actual test result of the interrupt behavior test case;

[0188] The second interrupt behavior verification submodule is used to determine that the controller to be verified fails the interrupt behavior verification if the expected test result of the interrupt behavior test case is inconsistent with the actual test result of the interrupt behavior test case.

[0189] The present application also provides an electronic device, such as Figure 8 As shown, it includes a processor 801, a communication interface 802, a memory 803 and a communication bus 804, wherein the processor 801, the communication interface 802, and the memory 803 communicate with each other through the communication bus 804.

[0190] Memory 803, used for storing computer programs;

[0191] The processor 801 is used to execute the program stored in the memory 803, and implements the following steps:

[0192] Generate an interrupt test case of the controller to be verified by a sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified;

[0193] Execute the interrupt behavior test case through the interrupt reference module to obtain the expected test result of the interrupt behavior test case, and send the expected test result of the interrupt behavior test case to the scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified;

[0194] Execute the interruption behavior test case through the controller to be verified, obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard;

[0195] When the scoreboard receives the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case, the interruption behavior of the controller to be verified is verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

[0196] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0197] The communication interface is used for communication between the above terminal and other devices.

[0198] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0199] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0200] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is executed on a computer, the computer executes the interrupt verification method of the controller described in any of the above embodiments.

[0201] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Sol logo State Disk (SSD)), etc.

[0202] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0203] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0204] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A controller interrupt verification method, characterized in that: Applied to an interrupt verification architecture, the interrupt verification architecture includes a sequencer, a reference module, a controller to be verified, and a scoreboard, wherein the reference module includes an interrupt reference module and a function reference module, the sequencer establishes communication connections with the reference module and the controller to be verified respectively, the scoreboard establishes communication connections with the reference module and the controller to be verified respectively, and the method includes: Generate an interrupt test case of the controller to be verified by the sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified; Executing the interrupt behavior test case through the interrupt reference module to obtain an expected test result of the interrupt behavior test case, and sending the expected test result of the interrupt behavior test case to the scoreboard, wherein the interrupt reference module has the same interrupt function as the controller to be verified; Execute the interruption behavior test case through the controller to be verified to obtain an actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard; When the scoreboard receives the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case, the interruption behavior of the controller to be verified is verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

2. The method according to claim 1, characterized in that The generating of the interrupt test case of the controller to be verified by the sequence generator comprises: Acquiring functional characteristic data of the controller to be verified through the sequence generator; When the sequence generator obtains the functional characteristic data of the controller to be verified, the interrupt of the controller to be verified is decomposed into test function points according to the functional characteristic data of the controller to be verified to obtain test function points; When the sequence generator obtains the test function point, an interruption test case of the controller to be verified is designed according to the test function point.

3. The method according to claim 1, characterized in that Before the step of generating an interrupt test case of the controller to be verified by the sequence generator, the method includes: Set up the verification environment in advance; When the verification environment is built, the interrupt registers of the reference module and the controller to be verified are configured by the sequence generator; When the interrupt register configuration is completed, the timing of the controller to be verified and the reference module are aligned according to the signal timing relationship of the controller to be verified.

4. The method according to claim 1, characterized in that: The interrupt verification architecture includes an interrupt register configuration component, and the interrupt register configuration component establishes communication connections with the sequence generator and the controller to be verified respectively. The interrupt register configuration of the reference module and the controller to be verified through the sequence generator includes: Sending interrupt register configuration data to the interrupt register configuration component and the reference module respectively through the sequence generator; When the interrupt register configuration component receives the interrupt register configuration data, the interrupt register configuration data is sent to the controller to be verified; When the controller to be verified receives the interrupt register configuration data, configuring the interrupt register of the controller to be verified according to the interrupt register configuration data; When the reference module receives the interrupt register configuration data, the interrupt register of the reference module is configured according to the interrupt register configuration data.

5. The method according to claim 1, characterized in that The interruption test case includes a random interruption function test case and a directional interruption function test case. Before the step of executing the interruption behavior test case through the interruption reference module to obtain an expected test result of the interruption behavior test case, the method includes: Sending the random interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator, wherein the interrupt function of the function reference module is the same as that of the controller to be verified; When the function reference module receives the random interruption function test case, the function reference module executes the random interruption function test case to obtain an expected test result of the random interruption function test case, and sends the expected test result of the random interruption function test case to the scoreboard; When the controller to be verified receives the random interrupt function test case, the controller executes the random interrupt function test case to obtain an actual test result of the random interrupt function test case, and sends the actual test result of the random interrupt function test case to the scoreboard; In a case where the scoreboard receives the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case, determining whether the controller to be verified meets the design requirements of the random interrupt function according to the expected test result of the random interrupt function test case and the actual test result of the random interrupt function test case; After determining whether the controller to be verified meets the design requirements of the random interrupt function, sending the directional interrupt function test case to the function reference module and the controller to be verified respectively through the sequence generator; In the case where the function reference module receives the directional interrupt function test case, executing the directional interrupt function test case, obtaining an expected test result of the directional interrupt function test case, and sending the expected test result of the directional interrupt function test case to the scoreboard; When the controller to be verified receives the directional interrupt function test case, the directional interrupt function test case is executed to obtain an actual test result of the directional interrupt function test case, and the actual test result of the directional interrupt function test case is sent to the scoreboard; In a case where the scoreboard receives the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case, determining whether the controller to be verified meets the design requirements of the directional interrupt function according to the expected test result of the directional interrupt function test case and the actual test result of the directional interrupt function test case; After determining whether the controller to be verified meets the design requirements of the directional interrupt function, the interrupt behavior test case is executed through the interrupt reference module to obtain an expected test result of the interrupt behavior test case.

6. The method according to claim 1, characterized in that The verifying the interruption behavior of the controller to be verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case includes: If the expected test result of the interruption behavior test case is consistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified passes the interruption behavior verification; If the expected test result of the interruption behavior test case is inconsistent with the actual test result of the interruption behavior test case, it is determined that the controller to be verified has failed the interruption behavior verification.

7. A controller interrupt verification system, characterized in that: The interrupt verification system of the controller includes a sequence generator, a reference module, a controller to be verified and a scoreboard, wherein the reference module includes an interrupt reference module and a function reference module; The sequence generator is used to generate interrupt test cases of the controller to be verified, wherein the interrupt test cases include interrupt behavior test cases, wherein the interrupt behavior test cases are used to test the interrupt enable, interrupt mask and interrupt priority of the controller to be verified; The interruption reference module is used to execute the interruption behavior test case, obtain the expected test result of the interruption behavior test case, and send the expected test result of the interruption behavior test case to the scoreboard, wherein the interruption reference module has the same interruption function as the controller to be verified; The controller to be verified is used to execute the interruption behavior test case, obtain the actual test result of the interruption behavior test case, and send the actual test result of the interruption behavior test case to the scoreboard; The scoreboard is used to verify the interruption behavior of the controller to be verified according to the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case when receiving the expected test result of the interruption behavior test case and the actual test result of the interruption behavior test case.

8. An interrupt verification device for a controller, characterized in that: The interrupt verification device of the controller comprises: An interrupt test case generation module, used for generating an interrupt test case of the controller to be verified through the sequence generator, wherein the interrupt test case includes an interrupt behavior test case, wherein the interrupt behavior test case is used for testing the interrupt enable, interrupt mask and interrupt priority of the controller to be verified; An interruption reference module processing module, used for executing the interruption behavior test case through the interruption reference module, obtaining the expected test result of the interruption behavior test case, and sending the expected test result of the interruption behavior test case to the scoreboard, wherein the interruption reference module has the same function as the controller to be verified; A controller processing module to be verified, used for executing the interruption behavior test case through the controller to be verified, obtaining an actual test result of the interruption behavior test case, and sending the actual test result of the interruption behavior test case to the scoreboard; An interrupt verification module is used to verify the interrupt behavior of the controller to be verified according to the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case when the scoreboard receives the expected test result of the interrupt behavior test case and the actual test result of the interrupt behavior test case.

9. An electronic device, characterized in that: include: a memory for storing processor-executable instructions; The processor is configured to execute the instructions to implement the interrupt verification method of the controller according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the interrupt verification method of the controller according to any one of claims 1 to 6 is implemented.

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