Bus access control system and method based on bypass configuration

Abstract

The invention belongs to the field of system bus design, and discloses a bus access control system and method based on bypass configuration, the bus access control system comprises a routing unit, N bypass components and a scoreboard unit, a CPU realizes access to N peripherals through the routing unit and the N bypass components; the bypass assembly comprises a locking unit, an isolation unit, a recording unit and an arbitration unit; according to the system and the method disclosed by the invention, the routing unit and the bypass component are utilized to construct the system bus capable of configuring the bypass, and the host and the peripheral are interconnected through the bus interface. The operation way of the prior art is reserved, and a certain access request (read access or write access) of the host can be filtered through configuration, so that the access efficiency is improved, and the power consumption is reduced. And meanwhile, the universality of the peripheral can be improved, and the received request does not need to be judged by additional logic.

Description

Technical Field

[0001] The invention belongs to the field of system bus design, and in particular relates to a bus access control system and method based on bypass configuration. Background Art

[0002] The processor contains a variety of peripherals to meet the processor's needs for different data sources. All peripherals need to be connected to the system bus, and the CPU and other hosts access each peripheral through the system bus. In order to ensure the efficiency of system operation, invalid access requests need to be filtered.

[0003] The existing system bus has a simple structure, mainly including a routing unit and an arbitration unit. Once the host initiates an access request, the request will reach the peripheral through the routing unit and arbitration unit of the system bus. However, in some scenarios, some peripherals under the system bus need to ignore a certain access request (read access or write access) from the host. Since the existing bus does not filter the access request passing through the routing unit, it cannot meet this scenario. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a bus access control system and method based on bypass configuration, so as to filter invalid access requests, improve access efficiency and reduce power consumption.

[0005] To achieve the above object, the technical solution of the present invention is as follows: A bus access control system based on bypass configuration includes a routing unit, N bypass components and a scoreboard unit, wherein a CPU accesses N peripherals through the routing unit and the N bypass components; The routing unit: completes the sending and receiving of bus requests from the CPU to the bypass component according to the bus request type and address information sent by the CPU; The bypass component includes a locking unit, an isolation unit, a recording unit and an arbitration unit; The locking unit is used to lock and unlock the isolation unit to prevent misoperation; The isolation unit: determines the peripheral access request issued by the routing unit according to the unlocking signal output by the locking unit and the isolation unit configuration request issued by the routing unit. Once the access type matches, the isolation unit will not issue the peripheral access request to the arbitration unit, and at the same time, generates filtering request information; The recording unit: saves the filtering request information sent by the isolation unit, and sends the available depth information to the scoreboard unit; The arbitration unit: arbitrates the requests passing through the isolation unit and the unfinished requests. If there is an unfinished request in the arbitration unit, the current request enters the cache of the arbitration unit and the unfinished request is preferentially sent to the corresponding peripheral device; otherwise, the current request is directly sent to the corresponding peripheral device; The scoreboard unit generates a record full interrupt flag according to the available depth information sent by the recording unit in each bypass component, and sends it to the interrupt controller; the interrupt controller generates a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing.

[0006] In the above scheme, the bus request of the CPU includes an access request to each peripheral device, a configuration request to the locking unit and the isolation unit in each bypass component, and an access request to the recording unit in the bypass component.

[0007] In the above scheme, the locking unit needs to be configured before configuring the isolation unit, outputting a valid unlocking signal to complete unlocking of the isolation unit, and the isolation unit can be configured after unlocking; after completing the expected operation, the locking unit can be configured again, outputting an invalid unlocking signal to complete locking of the isolation unit, and the isolation unit cannot be configured at this time.

[0008] In the above scheme, the depth of the recording unit is set to 128. Every time a group of filtered bus requests is received, the available depth of the recording unit is reduced by 1. When the available depth of the recording unit is 0, a record full interrupt flag is generated to the interrupt controller.

[0009] A bus access control method based on bypass configuration, using the above-mentioned bus access control system based on bypass configuration, comprises the following steps: (1) The CPU configures the locking unit in a bypass component through the bus interface, thereby generating an unlocking signal that is effective for the isolation unit in the bypass component; the isolation unit is configured to specify the access requests that need to be filtered out; the locking unit is then configured to make the unlocking signal invalid, and the isolation unit cannot be configured any more at this time; the effect after the configuration is completed is that the isolation unit in the bypass component is configured to filter read requests; (2) The CPU issues a read request to the peripheral corresponding to the bypass component through the bus interface; (3) The read request passes through the routing unit and reaches the isolation unit in the bypass component; (4) The isolation unit starts working, and the CPU's read request to the peripheral is filtered. At the same time, the recording unit in the bypass component records the filtered read request information and sends the available depth information to the scoreboard unit; (5) The arbitration unit in the bypass component will not receive any access request and will not work; (6) The peripheral corresponding to the bypass component will not receive access requests and will not work.

[0010] In a further technical solution, when the available depth of a certain recording unit is 0, the scoreboard unit will generate a record full interrupt flag and send it to the interrupt controller. The interrupt controller will generate a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing.

[0011] In a further technical solution, when there is no request that needs to be filtered in the system, the CPU does not configure the locking unit and the isolation unit, and the bypass component does not filter the access request, and all requests can reach the peripheral device.

[0012] Through the above technical solution, a bus access control system and method based on bypass configuration provided by the present invention has the following beneficial effects: The present invention uses routing units and bypass components to construct a system bus with configurable bypass (isolation unit, locking unit, recording unit, arbitration unit as a whole are referred to as bypassable components), and the host and peripherals are interconnected through a bus interface. It not only retains the operation path of the prior art, but also can filter out certain access requests (read access or write access) of the host through configuration, improve access efficiency, and reduce power consumption. At the same time, it can improve the versatility of peripherals, and no additional logic is required to distinguish the received requests. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0014] Figure 1 A schematic diagram of a bus access control system based on bypass configuration disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0016] The present invention provides a bus access control system based on bypass configuration, such as Figure 1 As shown, it includes a routing unit, N bypass components and a scoreboard unit. The CPU accesses N peripherals through the routing unit and the N bypass components.

[0017] Routing unit: completes the sending and receiving of bus requests from the CPU to the bypass component according to the bus request type and address information sent by the CPU; the CPU's bus requests include access requests to various peripherals, configuration requests for the locking unit and isolation unit in each bypass component, and access requests to the recording unit in the bypass component.

[0018] Each bypass component includes a locking unit, an isolation unit, a recording unit and an arbitration unit.

[0019] Locking unit: locks and unlocks the isolation unit to prevent misoperation. Before configuring the isolation unit, the locking unit needs to be configured to output a valid unlocking signal to unlock the isolation unit. After unlocking, the isolation unit can be configured. After completing the expected operation, the locking unit can be configured again to output an invalid unlocking signal to lock the isolation unit. At this time, the isolation unit cannot be configured.

[0020] Isolation unit: Based on the unlocking signal output by the locking unit and the isolation unit configuration request issued by the routing unit, the isolation unit determines the peripheral access request issued by the routing unit. Once the access type matches, the isolation unit will not issue the peripheral access request to the arbitration unit, and at the same time, generates filtering request information.

[0021] Recording unit: saves the filtering request information sent by the isolation unit, and sends the available depth information to the scoreboard unit; the CPU can obtain the request filtering information and the empty and full information of the recording unit saved in the recording unit through the bus interface.

[0022] Arbitration unit: arbitrates requests that pass through the isolation unit and unfinished requests. If there are unfinished requests in the arbitration unit, the current request enters the cache of the arbitration unit and gives priority to sending the unfinished request to the corresponding peripheral; otherwise, the current request is directly sent to the corresponding peripheral.

[0023] Scoreboard unit: generates a record full interrupt flag based on the available depth information sent by the recording unit in each bypass component, and sends it to the interrupt controller; the interrupt controller generates a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing.

[0024] The depth of the recording unit is set to 128 according to actual conditions. Every time a group of filtered bus requests is received, the available depth of the recording unit is reduced by 1. When the available depth of the recording unit is 0, a record full interrupt flag is generated to the interrupt controller.

[0025] Therefore, the system bus structure of the present invention can filter access requests in a targeted manner to improve access efficiency.

[0026] Set the application scenario: the CPU continuously sends read requests to peripheral 1; peripheral 1 does not respond to the CPU's read request.

[0027] The processing steps of the prior art are as follows: (1) The CPU sends a read request to peripheral 1 through the bus interface; (2) The read request passes through the routing unit and reaches the arbitration unit; (3) The arbitration unit arbitrates the CPU's read request and sends the CPU's read request to peripheral 1; (4) Peripheral 1 identifies the received request and does not respond if it is a read request initiated by the CPU.

[0028] Since the bus does not have a filtering function, all requests need to be arbitrated, which increases the workload of the arbitration unit and reduces access efficiency. At the same time, the peripherals need to add additional logic to identify the received requests, which reduces the versatility of the peripherals.

[0029] In view of the above scenario, a bus access control method based on bypass configuration of the present invention adopts the above bus access control system based on bypass configuration, comprising the following steps: (1) The CPU configures the locking unit in the bypass component 1 through the bus interface, thereby generating an effective unlocking signal for the isolation unit in the bypass component 1; the isolation unit is configured to specify the access requests that need to be filtered out; the locking unit is then configured to make the unlocking signal invalid, and the isolation unit cannot be configured again at this time; the effect after the configuration is completed is: the isolation unit in the bypass component 1 is configured to filter read requests; (2) The CPU sends a read request to peripheral 1 through the bus interface; (3) The read request passes through the routing unit and reaches the isolation unit in bypass component 1; (4) The isolation unit starts working, the CPU's read request to the peripheral device 1 is filtered, and at the same time, the recording unit in the bypass component 1 records the filtered read request information and sends the available depth information to the scoreboard unit; (5) The arbitration unit in bypass component 1 will not receive any access request and will not work; (6) The peripheral device corresponding to the bypass component will not receive the access request and will not work.

[0030] When there are no requests that need to be filtered in the system, the CPU does not configure the locking unit and the isolation unit, and the bypass component does not filter the access requests, and all requests can reach the peripherals.

[0031] When the available depth of a certain recording unit is 0, the scoreboard unit will generate a record full interrupt flag and send it to the interrupt controller. The interrupt controller generates a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing. In general, if accurate real-time information is required, the user can first read the relevant information of the recording unit in the interrupt service program, then clear the above-mentioned related information that has been read, and clear the counter at the same time to ensure that the recording unit can re-record the filtered information. If you do not pay attention to the relevant information, for example, the user does not care about the filtered request information. The interrupt service program can do nothing. In this case, the bus continues to filter requests according to the configuration and sends and receives normally. However, the recording unit will overwrite the previous recorded information, making the recorded information confusing and unable to reflect the filtered requests in real time.

[0032] In summary, the system bus structure of the present invention can filter invalid access requests, improve access efficiency, and reduce power consumption. At the same time, it can improve the versatility of peripherals and does not require additional logic to identify received requests.

[0033] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bus access control system based on bypass configuration, characterized in that: It includes a routing unit, N bypass components and a scoreboard unit, and the CPU accesses N peripherals through the routing unit and the N bypass components; The routing unit: completes the sending and receiving of bus requests from the CPU to the bypass component according to the bus request type and address information sent by the CPU; The bypass component includes a locking unit, an isolation unit, a recording unit and an arbitration unit; The locking unit is used to lock and unlock the isolation unit to prevent misoperation; The isolation unit: determines the peripheral access request issued by the routing unit according to the unlocking signal output by the locking unit and the isolation unit configuration request issued by the routing unit. Once the access type matches, the isolation unit will not issue the peripheral access request to the arbitration unit, and at the same time, generates filtering request information; The recording unit: saves the filtering request information sent by the isolation unit, and sends the available depth information to the scoreboard unit; The arbitration unit: arbitrates the requests passing through the isolation unit and the unfinished requests. If there are unfinished requests in the arbitration unit, the current request enters the cache of the arbitration unit, and the unfinished request is preferentially sent to the corresponding peripheral device; Otherwise, the current request is directly sent to the corresponding peripheral; The scoreboard unit generates a record full interrupt flag according to the available depth information sent by the recording unit in each bypass component, and sends it to the interrupt controller; the interrupt controller generates a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing.

2. A bus access control system based on bypass configuration according to claim 1, characterized in that: The CPU's bus requests include access requests to various peripherals, configuration requests to the locking units and isolation units in various bypass components, and access requests to the recording units in the bypass components.

3. A bus access control system based on bypass configuration according to claim 1, characterized in that: Before configuring the isolation unit, you need to configure the locking unit, output a valid unlocking signal, and complete unlocking the isolation unit. After unlocking, the isolation unit can be configured; after completing the expected operation, you can configure the locking unit again and output an invalid unlocking signal to complete locking the isolation unit. At this time, the isolation unit cannot be configured.

4. A bus access control system based on bypass configuration according to claim 1, characterized in that: The depth of the record unit is set to 128. Every time a group of filtered bus requests is received, the available depth of the record unit is reduced by 1. When the available depth of the record unit is 0, a record full interrupt flag is generated to the interrupt controller.

5. A bus access control method based on bypass configuration, using a bus access control system based on bypass configuration as claimed in any one of claims 1 to 4, characterized in that: The steps include: (1) The CPU configures the locking unit in a bypass component through the bus interface, thereby generating an unlocking signal effective for the isolation unit in the bypass component; The isolation unit is configured to specify the access requests that need to be filtered out; the locking unit is then configured to invalidate the unlocking signal, and the isolation unit cannot be configured any more at this time; the effect after the configuration is completed is that the isolation unit in the bypass component is configured to filter the read request; (2) The CPU issues a read request to the peripheral corresponding to the bypass component through the bus interface; (3) The read request passes through the routing unit and reaches the isolation unit in the bypass component; (4) The isolation unit starts working, and the CPU's read request to the peripheral is filtered. At the same time, the recording unit in the bypass component records the filtered read request information and sends the available depth information to the scoreboard unit; (5) The arbitration unit in the bypass component will not receive any access request and will not work; (6) The peripheral corresponding to the bypass component will not receive access requests and will not work.

6. The bus access control method based on bypass configuration according to claim 5, characterized in that: When the available depth of a certain recording unit is 0, the scoreboard unit will generate a record full interrupt flag and send it to the interrupt controller. The interrupt controller will generate a trigger signal to the CPU, triggering the CPU to run the corresponding interrupt service program in the storage for processing.

7. The bus access control method based on bypass configuration according to claim 5, characterized in that: When there are no requests that need to be filtered in the system, the CPU does not configure the locking unit and the isolation unit, and the bypass component does not filter the access requests, and all requests can reach the peripherals.

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