Integrated accounting device

Abstract

An embodiment of the present application provides a storage-computing integrated device, comprising at least one system on chip, a logic chip, and multiple stacked DRAM units; the logic chip comprises: multiple first-class interfaces, interconnected with at least one system on chip; multiple storage-computing integrated modules, corresponding to and interconnected with one first-class interface; multiple DRAM control logics, corresponding to multiple storage-computing integrated modules; multiple second-class interfaces, corresponding to multiple DRAM control logics; each DRAM control logic is interconnected with at least one DRAM unit through multiple second-class interfaces; arbitration logic, corresponding to and interconnected with one first-class interface, and interconnected with multiple storage-computing integrated modules and multiple DRAM control logics; at least one system on chip is configured to access at least one of the corresponding multiple storage-computing integrated modules through at least one first-class interface; and / or access at least one of the corresponding multiple DRAM control logics through at least one first-class interface and the corresponding arbitration logic.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and is related to, but not limited to, a storage and computing integrated device. Background Art

[0002] Processing in Memory (PIM) technology is a hot topic in the industry and a development trend in artificial intelligence (AI). The demand for AI computing power is driving the need for ultra-high computing power and energy efficiency in PIM devices, necessitating large capacity, high performance, and high integration. Summary of the Invention

[0003] In view of this, an embodiment of the present application provides a storage and computing integrated device.

[0004] In a first aspect, an embodiment of the present application provides a storage-computing integrated device, which includes at least one system on chip, a logic chip interconnected with at least one system on chip, and multiple DRAM units stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes: multiple first-class interfaces, interconnected with at least one system on chip; multiple storage-computing integrated modules, corresponding to and interconnected with one first-class interface; multiple DRAM control logics, corresponding to multiple storage-computing integrated modules; multiple second-class interfaces, corresponding to multiple DRAM control logics; each DRAM control logic is interconnected with at least one DRAM unit through multiple second-class interfaces; arbitration logic, corresponding to and interconnected with one first-class interface, and interconnected with multiple storage-computing integrated modules and multiple DRAM control logics; at least one system on chip is configured to access at least one of the corresponding multiple storage-computing integrated modules through at least one first-class interface; and / or access at least one of the corresponding multiple DRAM control logics through at least one first-class interface and corresponding arbitration logic.

[0005] In some embodiments, the logic chip also includes an inter-interface interconnection connecting multiple first-class interfaces; at least one system on chip is configured to connect to at least another first-class interface through a first-class interface and an inter-interface interconnection, and access at least one of the multiple storage and computing modules corresponding to at least another first-class interface and / or at least one of the multiple DRAM control logics.

[0006] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage-computing modules through a first-class interface, or to access at least one of the multiple storage-computing modules corresponding to another first-class interface through a first-class interface and another first-class interface interconnected between interfaces; at least one of the multiple storage-computing modules accessed is configured as a cache device; or is configured as a computing device, accessing at least one of the multiple DRAM control logics through arbitration logic.

[0007] In some embodiments, at least one system on chip is configured to: access a first-class interface; decode the corresponding first-class interface based on the address transmitted by the at least one system on chip; select at least one of the corresponding multiple storage and computing modules through the corresponding first-class interface for command and data transmission, or select at least one of the multiple storage and computing modules corresponding to the other first-class interface through the corresponding first-class interface and the interface interconnection to connect another first-class interface for command and data transmission; at least one of the multiple storage and computing modules accessed starts calculation after receiving the command and data; during the calculation, access at least one of the multiple DRAM control logics through the arbitration logic, or decode to the corresponding first-class interface, access at least one of the multiple DRAM control logics corresponding to the other first-class interface through the corresponding first-class interface and the interface interconnection to connect another first-class interface; after the calculation is completed, return the result and status to at least one system on chip through the original path.

[0008] In some embodiments, at least one system on chip is configured to access at least one of a plurality of DRAM control logics through a first-class interface and corresponding arbitration logic, or to access at least one of a plurality of DRAM control logics through a first-class interface and another first-class interface corresponding to an inter-interface interconnection connection, and through another first-class interface and another corresponding arbitration logic; at least one of the plurality of DRAM control logics accessed is configured to access at least one corresponding DRAM unit.

[0009] In some embodiments, at least one system on chip is configured to: access a first-class interface; a corresponding first-class interface decodes based on an address transmitted by at least one system on chip; selects at least one of the corresponding multiple DRAM control logics through a corresponding first-class interface to transmit commands and data, or, through a corresponding first-class interface and another first-class interface connected to an interface interconnection, selects at least one of the multiple DRAM control logics corresponding to another first-class interface to transmit commands and data; at least one of the multiple DRAM control logics accessed receives the command and data, and sends it to the corresponding multiple second-class interfaces after scheduling; the corresponding multiple second-class interfaces transmit the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after at least one of the multiple DRAM control logics accessed completes the command, it returns the result and status to at least one system on chip through the original path.

[0010] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage and computing modules through a first-class interface, or to access at least one of the multiple storage and computing modules corresponding to another first-class interface through a first-class interface and another first-class interface connected by an interconnection between interfaces; at least one of the multiple storage and computing modules accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through arbitration logic; at least one system on chip is configured to access at least one of the multiple DRAM control logics through a first-class interface and the corresponding arbitration logic, or to access at least one of the multiple DRAM control logics through a first-class interface and another first-class interface corresponding to the interconnection between interfaces, and through another first-class interface and another corresponding arbitration logic; wherein the arbitration logic is configured to select at least one of the multiple storage and computing modules or at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configured static selection.

[0011] In some embodiments, at least one system on chip is configured to: access a first-class interface; the corresponding first-class interface decodes based on the address transmitted by the at least one system on chip; through the corresponding first-class interface, select at least one of the corresponding multiple storage and computing modules and at least one of the corresponding multiple DRAM control logics for command and data transmission, or, through the corresponding first-class interface and another first-class interface interconnected between interfaces, select at least one of the multiple storage and computing modules corresponding to the other first-class interface and at least one of the corresponding multiple DRAM control logics for command and data transmission; at least one of the multiple storage and computing modules accessed and at least one of the multiple DRAM control logics accessed select at least one of the multiple storage and computing modules or at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configuration static selection when passing through the corresponding arbitration logic; after receiving the command and data, at least one of the multiple DRAM control logics accessed sends it to the corresponding multiple second-class interfaces after scheduling; the corresponding multiple second-class interfaces transmit the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after at least one of the multiple DRAM control logics accessed completes the command, it returns the result and status to at least one system on chip through the original path.

[0012] In some embodiments, the logic chip further includes a three-dimensional interface, a two-dimensional / 2.5-dimensional interface, and a path selection circuit; at least one system on chip is configured to: connect the three-dimensional interface to a first path of a first type of interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system on chip; or, connect the two-dimensional / 2.5-dimensional interface to a second path of the first type of interface through the path selection circuit; the second path is used for two-dimensional / 2.5-dimensional interconnection between the logic chip and the system on chip.

[0013] In some embodiments, the logic chip is configured to: initialize and complete chip configuration; the chip configuration includes defining a first path or a second path, selecting the system on chip to connect to the corresponding first type interface, and allowing the system on chip to access the corresponding first type interface through the first path or the second path.

[0014] In some embodiments, the logic chip further includes a miscellaneous device / miscellaneous device dimension interface.

[0015] In a second aspect, an embodiment of the present application provides a storage-computing integrated device, which includes at least one stacked system on chip, a logic chip interconnected with at least one system on chip, and multiple DRAM units stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes: multiple first-class interfaces, interconnected with at least one system on chip; multiple storage-computing integrated modules, corresponding to and interconnected with one first-class interface; multiple DRAM control logics, corresponding to multiple storage-computing integrated modules; multiple second-class interfaces, corresponding to multiple DRAM control logics; each DRAM control logic is interconnected with at least one DRAM unit through multiple second-class interfaces; arbitration logic, corresponding to and interconnected with one first-class interface, and interconnected with multiple storage-computing integrated modules and multiple DRAM control logics; wherein, multiple storage-computing integrated modules, multiple DRAM control logics and arbitration logic corresponding to one first-class interface are arranged flatly; at least one system on chip is configured to access at least one of the corresponding multiple storage-computing integrated modules through at least one first-class interface; and / or access at least one of the corresponding multiple DRAM control logics through at least one first-class interface and corresponding arbitration logic.

[0016] In some embodiments, the logic chip also includes an inter-interface interconnection connecting multiple first-class interfaces; at least one system on chip is configured to connect to at least another first-class interface through a first-class interface and an inter-interface interconnection, and access at least one of the multiple storage and computing modules corresponding to at least another first-class interface and / or at least one of the multiple DRAM control logics.

[0017] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage-computing modules through a first-class interface, or to access at least one of the multiple storage-computing modules corresponding to another first-class interface through a first-class interface and another first-class interface interconnected between interfaces; at least one of the multiple storage-computing modules accessed is configured as a cache device; or is configured as a computing device, accessing at least one of the multiple DRAM control logics through arbitration logic.

[0018] In some embodiments, at least one system on chip is configured to access at least one of a plurality of DRAM control logics through a first-class interface and corresponding arbitration logic, or to access at least one of a plurality of DRAM control logics through a first-class interface and another first-class interface corresponding to an inter-interface interconnection connection, and through another first-class interface and another corresponding arbitration logic; at least one of the plurality of DRAM control logics accessed is configured to access at least one corresponding DRAM unit.

[0019] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage and computing modules through a first-class interface, or to access at least one of the multiple storage and computing modules corresponding to another first-class interface through a first-class interface and another first-class interface connected by an interconnection between interfaces; at least one of the multiple storage and computing modules accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through arbitration logic; at least one system on chip is configured to access at least one of the multiple DRAM control logics through a first-class interface and the corresponding arbitration logic, or to access at least one of the multiple DRAM control logics through a first-class interface and another first-class interface corresponding to the interconnection between interfaces, and through another first-class interface and another corresponding arbitration logic; wherein the arbitration logic is configured to select at least one of the multiple storage and computing modules or at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configured static selection.

[0020] In some embodiments, the logic chip further includes a three-dimensional interface, a two-dimensional / 2.5-dimensional interface, and a path selection circuit; at least one system on chip is configured to: connect the three-dimensional interface to a first path of a first type of interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system on chip; or, connect the two-dimensional / 2.5-dimensional interface to a second path of the first type of interface through the path selection circuit; the second path is used for two-dimensional / 2.5-dimensional interconnection between the logic chip and the system on chip.

[0021] In each embodiment of the present application, a three-dimensional stacking of a logic chip and a plurality of DRAM units is realized, and the space occupied is reduced while having little impact on the performance of the storage-computing integrated device. The storage-computing integrated module is a computing unit (including a storage space), and the storage-computing integrated module realizes a high-capacity, short-distance connection through a DRAM controller and a DRAM unit to complete the storage-computing integrated calculation. At the same time, the DRAM unit can be used by the storage-computing integrated module, or the system on chip can use it as DRAM alone through the first type of interface (SOC interface) or perform data interaction through the DRAM unit and the storage-computing integrated module. The system on chip can also access the storage space in the storage-computing integrated module through the SOC interface and interact directly with the storage-computing integrated module. In other words, the logic chip includes the storage-computing integrated module, and is interconnected with the DRAM unit in three dimensions to realize the acceleration effect of the storage-computing integrated module; the system on chip accesses the DRAM unit through the logic chip, and the computing integrated module is used as a DRAM unit; the logic chip contains DRAM control logic to simplify the sharing of DRAM units by the system on chip and the storage-computing integrated module; and the large capacity, high performance and high integration of the storage-computing integrated device are realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A This is one of the cross-sectional schematic diagrams of the stacked storage and computing integrated device according to various embodiments of the present application;

[0023] Figure 1B This is a second cross-sectional schematic diagram of a stacked storage and computing integrated device according to various embodiments of the present application;

[0024] Figure 2 This is a third cross-sectional schematic diagram of a stacked storage and computing integrated device according to various embodiments of the present application;

[0025] Figure 3 This is a fourth cross-sectional schematic diagram of a stacked storage and computing integrated device according to various embodiments of the present application;

[0026] Figure 4 This is one of the schematic block diagrams of various modules of the logic chip of the storage and computing integrated device according to various embodiments of the present application;

[0027] Figure 5 This is a second schematic block diagram of various modules of the logic chip of the storage-computing integrated device according to various embodiments of the present application;

[0028] Figure 6 This is the third schematic block diagram of each module of the logic chip of the storage and computing integrated device according to each embodiment of the present application. DETAILED DESCRIPTION

[0029] The following is a clear and complete description of the technical solutions in the embodiments of this application in conjunction with the embodiments of this application and the accompanying drawings. The described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0036] refer to Figure 1A and Figure 4 , Figure 2 and Figure 4 ,or Figure 3 and Figure 4 In a first aspect, an embodiment of the present application provides a storage-computing integrated device, which includes at least one system on chip 100, a logic chip 200 interconnected with the at least one system on chip, and a plurality of DRAM units 300 stacked on the logic chip and interconnected with the logic chip; wherein the logic chip 200 includes: a plurality of first-class interfaces interconnected with at least one system on chip; a plurality of storage-computing integrated modules corresponding to and interconnected with one first-class interface; a plurality of DRAM control logics corresponding to the plurality of storage-computing integrated modules; a plurality of second-class interfaces corresponding to the plurality of DRAM control logics; each DRAM control logic is interconnected with at least one DRAM unit through a plurality of second-class interfaces; an arbitration logic corresponding to and interconnected with one first-class interface, and is interconnected with the plurality of storage-computing integrated modules and the plurality of DRAM control logics; the at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through at least one first-class interface; and / or access at least one of the corresponding plurality of DRAM control logics through at least one first-class interface and the corresponding arbitration logic.

[0037] For ease of description of this application, in each embodiment of this application, the first and second directions are represented as two orthogonal directions extending from the top / bottom surfaces of a DRAM (Dynamic Random Access Memory) cell, and can also be understood as two orthogonal directions parallel to the top / bottom surfaces of a DRAM cell. The third direction is a direction perpendicular to the top / bottom surfaces of a DRAM cell, and can be understood as the stacking direction of multiple DRAM cells. The first direction is represented as the X direction in the drawings; the second direction is represented as the Y direction in the drawings; and the third direction is represented as the Z direction in the drawings.

[0038] To facilitate the description of this application, the terms in the embodiments of this application, such as "first-class interface", "second-class interface", "storage and computing integrated module", "DRAM control logic", and "arbitration logic" can also be understood by referring to the "SOC interface", "DRAM interface", "PIM", "DMC", and "Arb" shown in the accompanying drawings respectively.

[0039] At least one system-on-chip (SOC) can access multiple DRAM units in a substantially simultaneous or non-simultaneous manner through at least one of the plurality of first-type interfaces 201, 202, 203, and 204. In some embodiments, the at least one SOC can access the multiple DRAM units in a substantially simultaneous manner through at least a plurality of the plurality of first-type interfaces 201, 202, 203, and 204 in parallel. In some embodiments, the at least one SOC can include multiple stacked SOCs.

[0040] The plurality of DRAM cells may include four stacked layers, and may support a capacity of 12 gigabytes (GB) to 16 GB, but the capacity is not limited to this range and may be less than 12 GB or greater than 16 GB. The plurality of DRAM cells may also include any number of stacked layers less than or greater than four layers.

[0041] The DRAM Memory Controller (DMC) controls DRAM cells, such as write operations, read operations, and refresh operations on DRAM cells. The DRAM control logic is configured to store data in a DRAM cell, read data stored in a DRAM cell, or refresh data stored in a DRAM cell.

[0042] The arbitration logic includes a multiplexer (MUX) for accessing the plurality of DRAM cells in a substantially simultaneous / asynchronous manner by dynamically / statically selecting at least one of the plurality of DRAM control logics.

[0043] The first type of interface may include a three-dimensional (3D) interface, such as a through-silicon via (TSV) or a hybrid bonding structure having a vertical conductive channel; or the first type of interface may include a two-dimensional (2D) / two-and-a-half-dimensional (2.5D) interface, such as a physical layer (PHY) and a controller (CTRL). The number of the first type of interface may be 4, or any number lower or higher than 4, for example, referring to Figure 1A 、 Figure 2 or Figure 3 , schematically, the number of first-type interfaces is 4.

[0044] The second type of interface can include a 3D interface with a vertical conductive channel (TSV) or a hybrid bonding structure. The 3D interface allows signals to pass through the layers of the logic chip 200 and multiple DRAM cells. In some embodiments, the TSV or hybrid bonding structure 3D interface can pass through the logic chip or not to achieve interconnection between the DRAM and logic chips.

[0045] refer to Figure 1A In some embodiments, the storage and computing integrated device includes at least one system on chip, a logic chip located on the at least one system on chip and interconnected with the at least one system on chip, and a plurality of DRAM units stacked on the logic chip and interconnected with the logic chip.

[0046] refer to Figure 1B In other embodiments, at least one system-on-chip (SoC) includes a logic chip interconnected with the system-on-chip, multiple DRAM units stacked on the logic chip and interconnected with the logic chip, and a system-on-chip located on the multiple DRAM units and interconnected with the logic chip. This can facilitate heat dissipation of the SOC in certain scenarios.

[0047] In the following description, reference is made to Figure 1A The storage and computing integrated device constructed in the stacking manner shown is described in detail, but is not used to limit the embodiments of the present application.

[0048] In some embodiments, DRAM controllers connected to multiple first-class interfaces on a system-on-chip can access all DRAM units in the corresponding physical space. For example, if the multiple DRAM units are stacked in multiple layers, the DRAM controller can access one layer of DRAM units in the corresponding physical space, or multiple layers of DRAM units.

[0049] Schematically, multiple DRAM cells are stacked in two layers; each layer of DRAM cells includes 16 cell areas, corresponding to 16 DRAM control logics and 16 storage-computing modules. Exemplarily, each cell area can be a DRAM accessible device (macro) or a storage bank (BANK) (including multiple macros) of a minimum unit of a DRAM cell, and one storage bank corresponds to one DRAM control logic and one storage-computing module. Schematically, at least one system on chip 100 is interconnected with a logic chip 200 through four first-class interfaces 201, 202, 203, and 204, and the logic chip 200 is interconnected with two layers of DRAM cells through 16 second-class interfaces. Schematically, each of the four first-class interfaces 201, 202, 203, and 204 corresponds to an arbitration logic, four DRAM control logics, and four storage-computing modules, respectively. Each of the four DRAM control logics corresponds to two cell areas, and the two cell areas are respectively located in two layers of DRAM cells.

[0050] It should be noted that the number of first-class interfaces and the number of second-class interfaces are used to generally describe the number of signal paths and are not associated with the specific number of pins. For example, if at least one system-on-chip is interconnected with a logic chip via four first-class interfaces 201, 202, 203, and 204, it can be said that at least one system-on-chip is interconnected with the logic chip via four paths (which can be four-way parallel interconnections), but it does not mean that at least one system-on-chip is interconnected with the logic chip via four pins. For another example, if a DRAM control logic is interconnected with a DRAM unit via two second-class interfaces, it can be said that the DRAM control logic is interconnected with the DRAM unit via two paths (which can be two-way parallel interconnections), but it does not mean that the DRAM control logic is interconnected with the DRAM unit via two pins.

[0051] In an embodiment of the present application, large capacity is achieved. For example, multiple DRAM units include 4 stacked layers, and the capacity can support 12GB to 16GB. The capacity is not limited to this range and can also be less than 12GB or greater than 16GB, for example, up to tens of terabytes (TB), to meet capacity requirements, replacing, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), which can remove the physical layer or reduce the power consumption of the physical layer, greatly improving the performance used by customers and reducing customer power consumption.

[0052] In some embodiments, at least one system on chip accesses a corresponding first-class interface 202; a corresponding first-class interface 202 decodes based on the address transmitted by at least one system on chip; and through a corresponding first-class interface 202, accesses at least one of the multiple storage-computing modules and / or at least one of the multiple DRAM control logics corresponding to the first-class interface 202 to perform command and data transmission.

[0053] refer to Figure 5 In some embodiments, the logic chip 200 further includes an inter-interface interconnection connecting multiple first-class interfaces; at least one system on chip is configured to connect to at least another first-class interface through a first-class interface and an inter-interface interconnection, and access at least one of the multiple storage-computing modules and / or at least one of the multiple DRAM control logics corresponding to the at least another first-class interface.

[0054] In some embodiments, the inter-interface interconnect 206 may decode commands between system-on-chip interfaces and access commands from a corresponding first-type interface 202 to another first-type interface 204 .

[0055] Exemplarily, at least one system on chip accesses a corresponding first-class interface 202; a corresponding first-class interface 202 is decoded based on an address transmitted by at least one system on chip; another first-class interface 204 is connected through a corresponding first-class interface 202 and an inter-interface interconnection 206, and the other first-class interface 204 is decoded based on the address transmitted by the inter-interface interconnection, and accesses at least one of the multiple storage and computing modules and / or at least one of the multiple DRAM control logics corresponding to the other first-class interface 204 to perform command and data transmission.

[0056] refer to Figure 5 In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage and computing modules through a first-class interface 202, or to access at least one of the multiple storage and computing modules corresponding to another first-class interface 204 by connecting another first-class interface 204 through a first-class interface 202 and an inter-interface interconnection 206; at least one of the multiple storage and computing modules accessed is configured as a cache device; or is configured as a computing device, and accesses at least one of the multiple DRAM control logics through arbitration logic.

[0057] In some embodiments, at least one system on chip may use one of the corresponding multiple storage and computing modules as a cache device or a computing device.

[0058] Exemplarily, at least one system on chip accesses the corresponding storage-computing module 221 through a corresponding first-class interface 202; the accessed storage-computing module 221 can be used as a cache device, and after the cache device completes the command, it returns the result and status to at least one system on chip through the original path; or, the accessed storage-computing module 221 can be used as a computing device, and after the computing device completes the command, it returns the result and status to at least one system on chip through the original path; wherein, the process of the computing device completing the command will be described in detail later and will not be repeated here.

[0059] Exemplarily, at least one system on chip connects to another first-class interface 204 through a corresponding first-class interface 202 and an inter-interface interconnection 206, and accesses the storage-computing module 241 corresponding to the other first-class interface 204. The process of the accessed storage-computing module 241 completing the command can refer to the process of the accessed storage-computing module 221 completing the command.

[0060] refer to Figure 5In some embodiments, at least one system on chip is configured to: access a first-class interface 202; a corresponding first-class interface 202 is decoded based on an address transmitted by at least one system on chip; at least one of the corresponding multiple storage-computing modules (for example, the storage-computing module 221) is selected through the corresponding first-class interface 202 for command and data transmission, or, another first-class interface 204 is connected through the corresponding first-class interface 202 and the inter-interface interconnection 206, and at least one of the multiple storage-computing modules corresponding to the other first-class interface 204 (for example, the storage-computing module 241) is selected for command and data transmission; after receiving the command and data, at least one of the accessed multiple storage-computing modules starts the operation; during the operation, at least one of the multiple DRAM control logics is accessed through the arbitration logic, or, after decoding to the corresponding first-class interface, another first-class interface is connected through the corresponding first-class interface and the inter-interface interconnection, and at least one of the multiple DRAM control logics corresponding to the other first-class interface is accessed; after the operation is completed, the result and status are returned to at least one system on chip through the original path.

[0061] Exemplarily, the accessed storage-computing module takes the storage-computing module 221 as an example. After receiving the command and data, the storage-computing module 221 starts the calculation; during the calculation, the storage-computing module 221 can access the DRAM control logic 222 through the arbitration logic 229; after the DRAM control logic 222 receives the command and data, it sends it to the corresponding DRAM interface after scheduling; the corresponding DRAM interface transmits the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after the DRAM control logic 222 completes the command, it returns the result and status to the storage-computing module 221 through the original path; after the calculation is completed, the storage-computing module 221 returns the result and status to at least one on-chip system through the original path.

[0062] Exemplarily, the accessed storage-computing module takes the storage-computing module 221 as an example. After receiving the command and data, the storage-computing module 221 starts the calculation; during the calculation, the storage-computing module 221 can also decode to a corresponding first-class interface 202, connect to another first-class interface 204 through a corresponding first-class interface 202 and the interface interconnection 206, and access the DRAM control logic 242 through the arbitration logic 249 corresponding to the other first-class interface 204; after the DRAM control logic 242 receives the command and data, it sends it to the corresponding DRAM interface after scheduling; the corresponding DRAM interface transmits the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after the DRAM control logic 242 completes the command, it returns the result and status to the storage-computing module 221 through the original path; after the calculation is completed, the storage-computing module 221 returns the result and status to at least one on-chip system through the original path.

[0063] refer to Figure 5 In some embodiments, at least one system on chip is configured to access at least one of the multiple DRAM control logics through a first-type interface 202 and a corresponding arbitration logic 229, or to access at least one of the multiple DRAM control logics through a first-type interface 202 and an inter-interface interconnect 206 connected to a corresponding another first-type interface 204, and through another first-type interface 204 and a corresponding another arbitration logic 249; at least one of the multiple DRAM control logics accessed is configured to access at least one corresponding DRAM unit.

[0064] Exemplarily, at least one system on chip accesses the corresponding DRAM control logic 222 through a corresponding first-class interface 202 and the corresponding arbitration logic 229; the DRAM control logic 222 is accessed; after the DRAM control logic 222 receives the command and data, it sends them to the corresponding DRAM interface after scheduling; the corresponding DRAM interface transmits the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after the DRAM control logic 222 completes the command, it returns the result and status to at least one system on chip through the original path.

[0065] Exemplarily, at least one system on chip is connected to another first-class interface 204 through a corresponding first-class interface 202 and an inter-interface interconnection 206, and accesses the corresponding DRAM control logic 242 through another first-class interface 204 and the corresponding arbitration logic 249. The process of the accessed storage-computing module 241 completing the command can refer to the process of the accessed storage-computing module 221 completing the command.

[0066] refer to Figure 5In some embodiments, at least one system on chip is configured to: access a first-type interface 202; decode the corresponding first-type interface 202 based on the address transmitted by the at least one system on chip; select at least one of the corresponding multiple DRAM control logics (e.g., DRAM control logic 222) through the corresponding first-type interface 202 to transmit commands and data, or connect another first-type interface 204 through the corresponding first-type interface 202 and the inter-interface interconnect 206, and select at least one of the multiple DRAM control logics corresponding to the other first-type interface 204 (e.g., DRAM control logic 242) to transmit commands and data; after receiving the command and data, at least one of the accessed multiple DRAM control logics (e.g., DRAM control logic 222 / DRAM control logic 242) schedules and sends the command and data to the corresponding multiple second-type interfaces; the corresponding multiple second-type interfaces transmit the command and data to at least one DRAM unit; the at least one DRAM unit performs the corresponding function; after completing the command, at least one of the accessed multiple DRAM control logics returns the result and status to the at least one system on chip through the original path.

[0067] refer to Figure 5 In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage and computing modules through a first-class interface, or to access at least one of the multiple storage and computing modules corresponding to another first-class interface through a first-class interface and another first-class interface connected by an interconnection between interfaces; at least one of the multiple storage and computing modules accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through arbitration logic; at least one system on chip is configured to access at least one of the multiple DRAM control logics through a first-class interface and a corresponding arbitration logic, or to access at least one of the multiple DRAM control logics through a first-class interface and another first-class interface connected by an interconnection between interfaces, and through another first-class interface and another corresponding arbitration logic; wherein the arbitration logic is configured to select at least one of the multiple storage and computing modules or at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software-configured static selection.

[0068] In some embodiments, the arbitration logic can judge or select the commands of the first-class interface and the commands of the storage-computing module. For example, the commands of the first-class interface and the commands of the storage-computing module can be accessed at the same time, and the arbitration logic can dynamically select through arbitration or statically select through software configuration. For example, the arbitration logic can act as a multiplexer (MUX), and statically select the access of the commands of the first-class interface and the commands of the storage-computing module through software configuration of the multiplexer.

[0069] In some embodiments, the first type of interface can judge or select multiple commands of the storage and computing module. For example, multiple commands of the storage and computing module can be accessed simultaneously, and the first type of interface can be dynamically selected through arbitration or statically selected through software configuration.

[0070] refer to Figure 5 In some embodiments, at least one system on chip is configured to: access a first-class interface 202; a corresponding first-class interface 202 decodes based on an address transmitted by at least one system on chip; selects at least one of the corresponding multiple storage-computing modules and at least one of the corresponding multiple DRAM control logics through a corresponding first-class interface 202 to transmit commands and data, or connects another first-class interface 204 through a corresponding first-class interface 202 and an inter-interface interconnection 206, selects at least one of the multiple storage-computing modules corresponding to the other first-class interface 204 and at least one of the corresponding multiple DRAM control logics to transmit commands and data; the multiple storage-computing modules accessed At least one of the modules and at least one of the multiple DRAM control logics being accessed, when passing through the corresponding arbitration logic, is dynamically selected by arbitration / statically selected by software configuration, and one of the multiple storage-computing modules being accessed or at least one on-chip system accesses at least one of the multiple DRAM control logics; after receiving the command and data, at least one of the multiple DRAM control logics being accessed sends it to the corresponding multiple second-type interfaces after scheduling; the corresponding multiple second-type interfaces transmit the command and data to at least one DRAM unit; at least one DRAM unit completes the corresponding function; after completing the command, at least one of the multiple DRAM control logics being accessed returns the result and status to at least one on-chip system through the original path.

[0071] Exemplarily, at least one system on chip selects the corresponding storage-computing integrated module 221 and the corresponding DRAM control logic 222 through a corresponding first-class interface 202 to transmit commands and data; wherein, the accessed storage-computing integrated module 221 accesses the DRAM control logic 222 through the arbitration logic 229 to transmit commands and data, and the first-class interface 202 corresponding to at least one system on chip also accesses the DRAM control logic 222 through the arbitration logic 229 to transmit commands and data; when passing through the corresponding arbitration logic 229, the arbitration logic 229 can judge or select the commands of the first-class interface and the commands of the storage-computing integrated module, and the arbitration dynamically selects / the software configures the static selection of the commands of the first-class interface or the commands of the storage-computing integrated module to access the DRAM control logic 222 for command and data transmission.

[0072] Exemplarily, at least one system on chip selects the corresponding storage and computing module 221 and the corresponding DRAM control logic 222 through a corresponding first-class interface 202 to transmit commands and data; wherein, the storage and computing module 221 is decoded to a corresponding first-class interface 202, and connected to another first-class interface 204 through a corresponding first-class interface 202 and the inter-interface interconnection 206 to transmit commands and data, and at least one system on chip also transmits commands and data through the corresponding first-class interface 202; when passing through the corresponding first-class interface 202, the first-class interface 202 can judge or select the commands of the storage and computing module and the commands of at least one system on chip, and arbitrate dynamically select / software configures static selection of the commands of the storage and computing module or the commands of at least one system on chip for command and data transmission.

[0073] refer to Figure 6 In some embodiments, the logic chip further includes a three-dimensional interface, a two-dimensional / 2.5-dimensional interface, and a path selection circuit; at least one system-on-chip is configured to: connect the three-dimensional interface to a first path of a first-type interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system-on-chip; or, connect the two-dimensional / 2.5-dimensional interface to a second path of the first-type interface through the path selection circuit; the second path is used for two-dimensional / 2.5-dimensional interconnection between the logic chip and the system-on-chip.

[0074] refer to Figure 1A and Figure 6 In some embodiments, a 3D interface is used for 3D interconnection between the logic chip 200 and the system-on-chip 100, supporting a relatively high bandwidth. The 3D interface serves as a buffer interface for the system-on-chip 100. The 3D interface can be fixed in position, number, and size, and can be used as a standard interface or a coprocessor interface, enabling rapid integration of different systems-on-chips.

[0075] refer to Figure 2 and Figure 6 In some embodiments, the 2D / 2.5D interface is used for 2D / 2.5D interconnection between the logic chip 200 and the system on chip 100 .

[0076] refer to Figure 3 and Figure 6In some embodiments, the 3D interface is used for 3D interconnection between the logic chip 200 and the SoC 100, and the 2D / 2.5D interface is used for 2D / 2.5D interconnection between the logic chip 200 and the external SoC 400, supporting compatibility between the 3D and 2D / 2.5D interfaces. The 3D interface is used as a buffer interface for the SoC 100; the 2D / 2.5D interface is used for interfacing with a 2D / 2.5D external SoC 400. For example, if the external SoC 400 includes an external buffer or a coprocessor, the 2D / 2.5D interface can be used as an interface for the external buffer of the 2D / 2.5D SoC or as an interface for the coprocessor of a storage and computing module.

[0077] refer to Figure 6 In some embodiments, the path selection circuit includes a multiplexer; a first input end of the multiplexer is connected to the 3D interface, a second input end is connected to the 2D / 2.5D interface, an output end is connected to the SOC interface, and a control end receives a selection signal Sel to form a first path connecting the 3D interface to the first type interface or a second path connecting the 2D / 2.5D interface to the first type interface.

[0078] The SOC interface can be understood as the system-on-chip convergence port for 2D / 2.5D and 3D interfaces. The select signal sel selects the actual path for different product forms, such as connecting a 3D interface to the first path of the first type interface; or connecting a 2D / 2.5D interface to the second path of the first type interface. The SOC interface can access DRAM control logic or the integrated storage and computing module. The SOC interface can also access register space.

[0079] In some embodiments, the 3D interface may include a TSV or hybrid bonding structure having vertical conductive channels. The 3D interface enables signals to pass through various layers of the logic chip 200 and the plurality of DRAM cells.

[0080] In some embodiments, the 2D / 2.5D interface may include a physical layer, a controller (CTRL).

[0081] refer to Figure 6 In some embodiments, the logic chip 200 is configured to: initialize and complete chip configuration; the chip configuration includes defining a first path or a second path, selecting the system on chip to connect to the corresponding first type interface, and allowing the system on chip to access the corresponding first type interface through the first path or the second path.

[0082] Exemplarily, the logic chip 200 is initialized, chip configuration is completed, a 2D / 2.5D or 3D path is defined, and the SOC interface path is selected (which can be understood as selecting the first path or the second path).

[0083] After selecting the 2D / 2.5D interface or the 3D interface, the system on chip 100 accesses the SOC interface through the corresponding first path or second path, so that the SOC interface performs decoding based on the address transmitted by the system on chip 100 .

[0084] refer to Figure 6 In some embodiments, the logic chip further includes a miscellaneous device\miscellaneous device dimension interface Misc.

[0085] In each embodiment of the present application, a 3D stacking of a logic chip and a plurality of DRAM units is achieved. By integrating a specific memory capacity and a capacity-sensitive computing acceleration unit in the logic chip, the unit and the DRAM unit are 3D stacked to form a storage-computing module acceleration. When the storage-computing module acceleration is not in use, the capacity of the storage-computing module can be used as DRAM for the system on chip, or when the storage-computing module acceleration is used, part of the capacity of the storage-computing module can be used for the system on chip. The multiple DRAM units included in the logic chip can be used as a cache for the system on chip, replacing, for example, DDR SDRAM, which can remove the physical layer or reduce the power consumption of the physical layer, thereby achieving large capacity, high performance, and high integration of the storage-computing device.

[0086] In a second aspect, an embodiment of the present application provides another storage-computing integrated device, which includes at least one stacked system on chip, a logic chip interconnected with at least one system on chip, and a plurality of DRAM units stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes: a plurality of first-class interfaces, interconnected with at least one system on chip; a plurality of storage-computing integrated modules, corresponding to and interconnected with one first-class interface; a plurality of DRAM control logics, corresponding to a plurality of storage-computing integrated modules; a plurality of second-class interfaces, corresponding to a plurality of DRAM control logics; each DRAM control logic is interconnected with at least one DRAM unit through a plurality of second-class interfaces; an arbitration logic, corresponding to and interconnected with one first-class interface, and interconnected with a plurality of storage-computing integrated modules and a plurality of DRAM control logics; wherein a plurality of storage-computing integrated modules, a plurality of DRAM control logics and an arbitration logic corresponding to a first-class interface are arranged flatly; at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through at least one first-class interface; and / or to access at least one of the corresponding plurality of DRAM control logics through at least one first-class interface and a corresponding arbitration logic.

[0087] In some embodiments, the logic chip also includes an inter-interface interconnection connecting multiple first-class interfaces; at least one system on chip is configured to connect to at least another first-class interface through a first-class interface and an inter-interface interconnection, and access at least one of the multiple storage and computing modules corresponding to at least another first-class interface and / or at least one of the multiple DRAM control logics.

[0088] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage-computing modules through a first-class interface, or to access at least one of the multiple storage-computing modules corresponding to another first-class interface through a first-class interface and another first-class interface interconnected between interfaces; at least one of the multiple storage-computing modules accessed is configured as a cache device; or is configured as a computing device, accessing at least one of the multiple DRAM control logics through arbitration logic.

[0089] In some embodiments, at least one system on chip is configured to access at least one of a plurality of DRAM control logics through a first-class interface and corresponding arbitration logic, or to access at least one of a plurality of DRAM control logics through a first-class interface and another first-class interface corresponding to an inter-interface interconnection connection, and through another first-class interface and another corresponding arbitration logic; at least one of the plurality of DRAM control logics accessed is configured to access at least one corresponding DRAM unit.

[0090] In some embodiments, at least one system on chip is configured to access at least one of the corresponding multiple storage and computing modules through a first-class interface, or to access at least one of the multiple storage and computing modules corresponding to another first-class interface through a first-class interface and another first-class interface connected by an interconnection between interfaces; at least one of the multiple storage and computing modules accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through arbitration logic; at least one system on chip is configured to access at least one of the multiple DRAM control logics through a first-class interface and the corresponding arbitration logic, or to access at least one of the multiple DRAM control logics through a first-class interface and another first-class interface corresponding to the interconnection between interfaces, and through another first-class interface and another corresponding arbitration logic; wherein the arbitration logic is configured to select at least one of the multiple storage and computing modules or at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configured static selection.

[0091] In some embodiments, the logic chip further includes a three-dimensional interface, a two-dimensional / 2.5-dimensional interface, and a path selection circuit; at least one system on chip is configured to: connect the three-dimensional interface to a first path of a first type of interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system on chip; or, connect the two-dimensional / 2.5-dimensional interface to a second path of the first type of interface through the path selection circuit; the second path is used for two-dimensional / 2.5-dimensional interconnection between the logic chip and the system on chip.

[0092] The other identical / similar parts of the storage-computing integrated device provided in each embodiment of the second aspect of this application refer to the storage-computing integrated device provided in each embodiment of the first aspect above. For the technical features not fully disclosed in the embodiments of the second aspect of this application, please refer to the above embodiments for understanding, and no further details will be given here.

[0093] In each embodiment of the present application, 3D integration of a system on chip, a logic chip, and multiple DRAM units is achieved, and space occupancy is reduced with little impact on the performance of the storage-computing integrated device. The multiple storage-computing integrated modules included in the logic chip can be used as caches for the system on chip, replacing, for example, DDR SDRAM, and can remove the physical layer or reduce the power consumption of the physical layer, thereby achieving large capacity, high performance, and high integration of the storage-computing integrated device; 3D integration of the system on chip, a logic chip, and multiple DRAM units is achieved, a 3D interface is defined, and standard parts are made; the storage-computing integrated module can support a terabyte (TB) level capacity and can be used for AI large model calculations; the logic chip supports through-silicon via or micro-bump output, and is integrated with the system on chip for AXI protocol, with a capacity support of, for example, 400GB, and face-to-face (F2F) packaging; support is provided for enabling or disabling at least one of multiple storage-computing integrated modules; and support compatibility between 3D interfaces and 2D / 2.5D interfaces.

[0094] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0095] The above description is only a preferred embodiment of the present application and does not limit the scope of protection of the present application. All equivalent structural transformations made based on the contents of the present application description and drawings, or direct / indirect application in other related technical fields, are included in the scope of protection of the present application.

Claims

1. A storage and computing integrated device, characterized in that: The invention comprises at least one system on chip, a logic chip interconnected with the at least one system on chip, and a plurality of DRAM units stacked on the logic chip and interconnected with the logic chip; wherein the logic chip comprises: a plurality of first-type interfaces interconnected with the at least one system-on-chip; Multiple storage and computing modules corresponding to and interconnected with one of the first-type interfaces; Multiple DRAM control logics corresponding to the multiple storage and computing modules; A plurality of second-type interfaces corresponding to the plurality of DRAM control logics; each of the DRAM control logics is interconnected with at least one of the DRAM units via the plurality of second-type interfaces; Arbitration logic, corresponding to and interconnected with one of the first-type interfaces, and interconnected with the multiple storage-computing modules and the multiple DRAM control logics; The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing modules through at least one first-type interface; and / or access at least one of the corresponding plurality of DRAM control logics through at least one first-type interface and the corresponding arbitration logic; The logic chip further includes an inter-interface interconnection connecting the plurality of first-type interfaces; The at least one system on chip is also configured to access at least one of the multiple storage and computing modules and / or at least one of the multiple DRAM control logics corresponding to at least another first-class interface through one of the first-class interfaces and the interconnection between the interfaces.

2. The storage and computing integrated device according to claim 1, characterized in that: The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through one of the first-type interfaces, or to access at least one of the plurality of storage-computing integrated modules corresponding to another of the first-type interfaces through one of the first-type interfaces and the inter-interface interconnection; At least one of the accessed plurality of integrated storage and computing modules is configured as a cache device; Alternatively, the device is configured as a computing device and accesses at least one of the plurality of DRAM control logics through the arbitration logic.

3. The storage and computing integrated device according to claim 2, characterized in that: The at least one system on chip is configured to: Accessing an interface of the first type; A corresponding one of the first-type interfaces decodes based on an address transmitted by the at least one system-on-chip; Selecting at least one of the plurality of storage-computing integrated modules to transmit commands and data through a corresponding one of the first-type interfaces, or connecting another first-class interface through a corresponding one of the first-class interfaces and the interconnection between the interfaces, and selecting at least one of the multiple storage-computing integrated modules corresponding to the other first-class interface to transmit commands and data; After receiving the command and data, at least one of the accessed multiple storage and computing modules starts computing; When the operation is performed, at least one of the plurality of DRAM control logics is accessed through the arbitration logic, or, after decoding to a corresponding first-type interface, another first-type interface is connected through the corresponding first-type interface and the inter-interface interconnection to access at least one of the plurality of DRAM control logics corresponding to the other first-type interface; After the operation is completed, the result and status are returned to the at least one system on chip through the original path.

4. The storage and computing integrated device according to claim 1, characterized in that: The at least one system on chip is configured to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and the corresponding arbitration logic, or to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and another of the first-type interfaces corresponding to the inter-interface interconnection and through another of the first-type interfaces and another of the corresponding arbitration logic; At least one of the accessed plurality of DRAM control logics is configured to access the corresponding at least one DRAM cell.

5. The storage and computing integrated device according to claim 4, characterized in that: The at least one system on chip is configured to: Accessing an interface of the first type; A corresponding one of the first-type interfaces decodes based on an address transmitted by the at least one system-on-chip; Selecting at least one of the corresponding plurality of DRAM control logics to transmit commands and data through a corresponding one of the first-type interfaces, or, connecting another first-type interface through a corresponding one of the first-type interfaces and the inter-interface interconnection, and selecting at least one of the plurality of DRAM control logics corresponding to the other first-type interface to transmit commands and data; At least one of the accessed plurality of DRAM control logics receives the command and data, schedules the received command and data, and sends the data to the corresponding plurality of second-type interfaces; The corresponding plurality of second-type interfaces transmit commands and data to at least one of the DRAM units; and at least one of the DRAM units performs a corresponding function; After completing a command, at least one of the accessed plurality of DRAM control logics returns a result and a status to the at least one system on chip through an original path.

6. The storage and computing integrated device according to claim 1, characterized in that: The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through one of the first-type interfaces, or to access at least one of the plurality of storage-computing integrated modules corresponding to another of the first-type interfaces through one of the first-type interfaces and the inter-interface interconnection; At least one of the multiple storage-computing modules being accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through the arbitration logic; The at least one system on chip is configured to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and the corresponding arbitration logic, or to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and another of the first-type interfaces corresponding to the inter-interface interconnection and through another of the first-type interfaces and another of the corresponding arbitration logic; The arbitration logic is configured to select at least one of the multiple storage-computing modules or at least one on-chip system to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configuration static selection.

7. The storage and computing integrated device according to claim 6, characterized in that: The at least one system on chip is configured to: Accessing an interface of the first type; A corresponding one of the first-type interfaces decodes based on an address transmitted by the at least one system-on-chip; Selecting at least one of the plurality of storage-computing modules and at least one of the plurality of DRAM control logics to transmit commands and data through a corresponding one of the first-type interfaces, or connecting another first-class interface through a corresponding one of the first-class interfaces and the inter-interface interconnection, selecting at least one of the multiple storage-computing modules and at least one of the corresponding multiple DRAM control logics corresponding to the other first-class interface to transmit commands and data; At least one of the multiple storage-computing integrated modules being accessed and at least one of the multiple DRAM control logics being accessed selects at least one of the multiple storage-computing integrated modules or the at least one system on chip to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software-configured static selection when passing through the corresponding arbitration logic; At least one of the accessed plurality of DRAM control logics receives the command and data, schedules the received command and data, and sends the data to the corresponding plurality of second-type interfaces; The corresponding plurality of second-type interfaces transmit commands and data to at least one of the DRAM units; and at least one of the DRAM units performs a corresponding function; After completing a command, at least one of the accessed plurality of DRAM control logics returns a result and a status to the at least one system on chip through an original path.

8. The storage and computing integrated device according to claim 1, characterized in that: The logic chip further includes a three-dimensional interface, a two-dimensional / two-and-a-half-dimensional interface, and a path selection circuit; and the at least one system on chip is configured as follows: Connecting the three-dimensional interface to a first path of the first type of interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system on chip; or, The two-dimensional / two-and-a-half-dimensional interface is connected to a second path of the first type of interface through the path selection circuit; the second path is used for two-dimensional / two-and-a-half-dimensional interconnection between the logic chip and the system on chip.

9. The storage and computing integrated device according to claim 8, characterized in that: The logic chip is configured as follows: Initialization completes chip configuration; the chip configuration includes defining the first path or the second path, selecting the system on chip to connect to the corresponding first type interface, for the system on chip to access the corresponding first type interface through the first path or the second path.

10. The storage and computing integrated device according to claim 8, characterized in that: The logic chip also includes miscellaneous device / miscellaneous device dimension interfaces.

11. A storage and computing integrated device, characterized in that: The invention comprises at least one stacked system on chip, a logic chip interconnected with the at least one system on chip, and a plurality of DRAM units stacked on and interconnected with the logic chip; wherein the logic chip comprises: a plurality of first-type interfaces interconnected with the at least one system-on-chip; Multiple storage and computing modules corresponding to and interconnected with one of the first-type interfaces; Multiple DRAM control logics corresponding to the multiple storage and computing modules; A plurality of second-type interfaces corresponding to the plurality of DRAM control logics; each of the DRAM control logics is interconnected with at least one of the DRAM units via the plurality of second-type interfaces; Arbitration logic, corresponding to and interconnected with one of the first-type interfaces, and interconnected with the multiple storage-computing modules and the multiple DRAM control logics; The plurality of storage-computing integrated modules, the plurality of DRAM control logics, and the arbitration logic corresponding to one of the first-type interfaces are arranged in a flat pattern; The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing modules through at least one first-type interface; and / or access at least one of the corresponding plurality of DRAM control logics through at least one first-type interface and the corresponding arbitration logic; The logic chip further includes an inter-interface interconnection connecting the plurality of first-type interfaces; The at least one system on chip is also configured to access at least one of the multiple storage and computing modules and / or at least one of the multiple DRAM control logics corresponding to at least another first-class interface through one of the first-class interfaces and the interconnection between the interfaces.

12. The storage and computing integrated device according to claim 11, characterized in that: The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through one of the first-type interfaces, or to access at least one of the plurality of storage-computing integrated modules corresponding to another of the first-type interfaces through one of the first-type interfaces and the inter-interface interconnection; At least one of the accessed plurality of integrated storage and computing modules is configured as a cache device; Alternatively, the device is configured as a computing device and accesses at least one of the plurality of DRAM control logics through the arbitration logic.

13. The storage and computing integrated device according to claim 11, characterized in that: The at least one system on chip is configured to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and the corresponding arbitration logic, or to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and another of the first-type interfaces corresponding to the inter-interface interconnection and through another of the first-type interfaces and another of the corresponding arbitration logic; At least one of the accessed plurality of DRAM control logics is configured to access the corresponding at least one DRAM cell.

14. The storage and computing integrated device according to claim 11, characterized in that: The at least one system on chip is configured to access at least one of the corresponding plurality of storage-computing integrated modules through one of the first-type interfaces, or to access at least one of the plurality of storage-computing integrated modules corresponding to another of the first-type interfaces through one of the first-type interfaces and the inter-interface interconnection; At least one of the multiple storage-computing modules being accessed is configured as a computing device, and accesses at least one of the multiple DRAM control logics through the arbitration logic; The at least one system on chip is configured to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and the corresponding arbitration logic, or to access at least one of the plurality of DRAM control logics through one of the first-type interfaces and another of the first-type interfaces corresponding to the inter-interface interconnection and through another of the first-type interfaces and another of the corresponding arbitration logic; The arbitration logic is configured to select at least one of the multiple storage-computing modules or at least one on-chip system to access at least one of the multiple DRAM control logics through arbitration dynamic selection / software configuration static selection.

15. The storage and computing integrated device according to claim 11, characterized in that: The logic chip further includes a three-dimensional interface, a two-dimensional / two-and-a-half-dimensional interface, and a path selection circuit; and the at least one system on chip is configured as follows: Connecting the three-dimensional interface to a first path of the first type of interface through the path selection circuit; the first path is used for three-dimensional interconnection between the logic chip and the system on chip; or, The two-dimensional / two-and-a-half-dimensional interface is connected to a second path of the first type of interface through the path selection circuit; the second path is used for two-dimensional / two-and-a-half-dimensional interconnection between the logic chip and the system on chip.

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