Semiconductor device and method for manufacturing the same

Abstract

The present embodiment discloses a semiconductor device and a method for manufacturing the same, the method comprising providing a silicon carbide body; forming a first groove extending from a first surface of the silicon carbide body into the silicon carbide body; forming a first isolation layer and a first polysilicon in the first groove, the first isolation layer being located between the first polysilicon and the bottom of the first groove, and between the first polysilicon and two side walls of the first groove; forming a second polysilicon and a second isolation layer in the first groove, the second isolation layer being located between the second polysilicon and two side walls of the first groove, and the second isolation layer and the first isolation layer completely covering the first polysilicon; forming a second groove extending from the second polysilicon to the bottom of the first groove, the second groove at least exposing a portion of the bottom of the first groove; and oxidizing a portion of the first polysilicon and a portion of the second polysilicon at a high temperature to form a third isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer completely cover the first polysilicon and the second polysilicon.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, is considered to be one of the main materials for making semiconductor chips in the future due to its excellent physical properties, such as high bandgap width, high electrical conductivity and high thermal conductivity. These characteristics make SiC devices show significant advantages in application scenarios such as high voltage, high current, high temperature, high frequency and low loss.

[0003] SiC trench gate structure can reduce the cell size, and thus reduce the chip size. Therefore, SiC trench gate structure has become a research hotspot. How to reduce the on-resistance of trench gate SiC power devices and alleviate the electric field concentration phenomenon at the bottom of the trench, and solve the high risk of leakage and breakdown of silicon carbide diodes are technical problems that need to be solved urgently. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure are intended to provide a semiconductor device and a method for manufacturing the same; the technical problems in the prior art that silicon carbide diodes have a high risk of leakage and breakdown, and a high process difficulty.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a silicon carbide body;

[0008] forming a first trench extending from a first surface of the silicon carbide body into the silicon carbide body;

[0009] forming a first isolation layer and a first polysilicon in the first trench, wherein the first isolation layer is located between the first polysilicon and the bottom of the first trench, and between the first polysilicon and two sidewalls of the first trench;

[0010] forming a second polysilicon and a second isolation layer in the first trench, wherein the second isolation layer is located between the second polysilicon and two sidewalls of the first trench, and the second isolation layer and the first isolation layer completely cover the first polysilicon;

[0011] forming a second trench extending from the second polysilicon to the bottom of the first trench, wherein the second trench at least exposes a portion of the bottom of the first trench;

[0012] A third isolation layer is formed by oxidizing a portion of the first polysilicon and a portion of the second polysilicon at high temperature, so that the first isolation layer, the second isolation layer and the third isolation layer completely cover the first polysilicon and the second polysilicon.

[0013] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0014] Silicon carbide body;

[0015] a first trench extending from a first surface of the silicon carbide body into the silicon carbide body;

[0016] A first polysilicon and a first isolation layer, wherein the first isolation layer is located between the first polysilicon and the bottom of the first trench, and between the first polysilicon and two sidewalls of the first trench;

[0017] a second polysilicon and a second isolation layer, wherein the second isolation layer is located between the second polysilicon and two sidewalls of the first trench, and the second isolation layer and the first isolation layer completely cover the first polysilicon;

[0018] a second trench extending from the second polysilicon to the bottom of the first trench, wherein the second trench at least exposes a portion of the bottom of the first trench;

[0019] The third isolation layer is formed by high-temperature oxidation of part of the first polysilicon and part of the second polysilicon, and the first isolation layer, the second isolation layer and the third isolation layer completely cover the first polysilicon and the second polysilicon.

[0020] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof; by forming a first isolation layer and a first polysilicon, as well as a second polysilicon and a second isolation layer in a first trench, more effective electrical isolation can be achieved. This structure helps to reduce the risk of leakage and breakdown, and improves the reliability and stability of the device. The arrangement of the first polysilicon and the second polysilicon helps to optimize the electric field distribution inside the device, and can reduce the on-resistance of the semiconductor device. By accurately controlling the position and thickness of the polysilicon layer, the electric field concentration area can be reduced, thereby improving the voltage resistance and reliability of the device. The high electron saturation velocity and low resistivity of the silicon carbide material itself help to reduce the conduction loss of the device. The arrangement of the first polysilicon and the second polysilicon can further optimize the conductive path and improve the power conversion efficiency; the high thermal conductivity of silicon carbide helps to better manage the heat generated when the device is running. The arrangement of the first polysilicon and the second polysilicon can help heat conduction, reduce the heat dissipation demand, and help to achieve miniaturization and lightweight of the device. Secondly, the third isolation layer is generated by high-temperature oxidation of polysilicon, which can reduce the process difficulty and the difficulty of filling the hole size, which is conducive to filling the hole of a small-size chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0022] Figure 2 A vertical cross-sectional schematic diagram of a silicon carbide body provided in an embodiment of the present disclosure.

[0023] Figure 3 A vertical cross-sectional schematic diagram of a semiconductor device after a first trench is formed according to an embodiment of the present disclosure.

[0024] Figure 4 A vertical cross-sectional schematic diagram of a semiconductor device after silicon dioxide is formed provided in an embodiment of the present disclosure.

[0025] Figure 5 A vertical cross-sectional schematic diagram of a semiconductor device after polysilicon is formed according to an embodiment of the present disclosure.

[0026] Figure 6 A vertical cross-sectional schematic diagram of a semiconductor device after forming a first polysilicon layer and a first isolation layer is provided in an embodiment of the present disclosure.

[0027] Figure 7 A vertical cross-sectional schematic diagram of a semiconductor device after a second isolation layer is formed according to an embodiment of the present disclosure.

[0028] Figure 8 A vertical cross-sectional schematic diagram of a semiconductor device after forming a second polysilicon is provided in an embodiment of the present disclosure.

[0029] Fig. 9 A vertical cross-sectional schematic diagram of a semiconductor device after a second trench is formed according to an embodiment of the present disclosure.

[0030] Fig.10 A vertical cross-sectional schematic diagram of a semiconductor device after a third isolation layer is formed according to an embodiment of the present disclosure.

[0031] Fig.11 A vertical cross-sectional schematic diagram of a semiconductor device after a first shielding region is formed according to an embodiment of the present disclosure.

[0032] Fig.12 A vertical cross-sectional schematic diagram of a semiconductor device after a first current-carrying region is formed according to an embodiment of the present disclosure.

[0033] Fig.13 A vertical cross-sectional schematic diagram of a semiconductor device after a second shielding region is formed according to an embodiment of the present disclosure.

[0034] Fig.14A vertical cross-sectional schematic diagram of a semiconductor device after a second current-carrying region is formed according to an embodiment of the present disclosure.

[0035] Fig.15 A vertical cross-sectional schematic diagram of a semiconductor device after a first current spreading layer is formed, provided in an embodiment of the present disclosure.

[0036] Fig.16 A vertical cross-sectional schematic diagram of a semiconductor device after forming a second current spreading layer, a body region, and a heavily doped region is provided in an embodiment of the present disclosure.

[0037] Fig.17 A vertical cross-sectional schematic diagram after a second shielding area is formed on a silicon carbide body provided in an embodiment of the present disclosure.

[0038] Fig.18 Another vertical cross-sectional schematic diagram of a semiconductor device after forming a first current spreading layer is provided in an embodiment of the present disclosure.

[0039] Fig.19 A vertical cross-sectional schematic diagram of another semiconductor device after forming a heavily doped region provided in an embodiment of the present disclosure.

[0040] Fig. 20 A vertical cross-sectional schematic diagram of another semiconductor device after forming a body region provided in an embodiment of the present disclosure.

[0041] Fig.21 Another vertical cross-sectional schematic diagram of a semiconductor device after forming a first trench is provided in an embodiment of the present disclosure.

[0042] Fig. 22 Another vertical cross-sectional schematic diagram of a semiconductor device after forming a first current-carrying region is provided in an embodiment of the present disclosure.

[0043] Fig.23 A vertical cross-sectional schematic diagram of another semiconductor device after silicon dioxide is formed according to an embodiment of the present disclosure.

[0044] Fig.24 Another vertical cross-sectional schematic diagram of a semiconductor device after polysilicon is formed is provided in an embodiment of the present disclosure.

[0045] Fig.25 Another vertical cross-sectional schematic diagram of a semiconductor device after forming a first polysilicon layer and a first isolation layer is provided in an embodiment of the present disclosure.

[0046] Fig.26 Another vertical cross-sectional schematic diagram of a semiconductor device after forming a second isolation layer is provided in an embodiment of the present disclosure.

[0047] Fig. 27Another vertical cross-sectional schematic diagram of a semiconductor device after forming a second polysilicon is provided in an embodiment of the present disclosure.

[0048] Fig.28 A vertical cross-sectional schematic diagram of another semiconductor device after forming a second trench provided in an embodiment of the present disclosure.

[0049] Fig.29 A vertical cross-sectional schematic diagram of a semiconductor device after a metal electrode is formed according to an embodiment of the present disclosure.

[0050] Fig.30 A vertical cross-sectional schematic diagram of a semiconductor device formed on a substrate provided in an embodiment of the present disclosure.

[0051] List of reference numerals:

[0052] 1. Silicon carbide body; 11. First groove; 12. Second groove; 13. First shielding area; 14. First current-carrying area; 15. Second shielding area; 16. Second current-carrying area; 171. First current spreading layer; 172. Second current spreading layer; 18. Heavily doped area; 19. Body area; 21. First isolation layer; 22. Second isolation layer; 23. Third isolation layer; 31. First polysilicon; 32. Second polysilicon; 4. Metal electrode; 5. Substrate.

[0053] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0054] In the detailed description that follows, reference is made to the accompanying drawings, which form a part hereof, and in which specific embodiments in which silicon carbide devices may be implemented are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements in different drawings are represented by the same reference symbols.

[0055] The terms "having," "comprising," "including," and "comprising" and the like are open ended, and the terms indicate the presence of stated structures, elements, or features but do not exclude the presence of additional elements or features. The quantifiers and pronouns "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0056] Ohmic contact is a non-rectifying electrical junction with linear or almost linear current-voltage characteristics. Schottky junction, i.e. Schottky contact, is a metal-semiconductor junction with rectifying characteristics, in which the work function of the metal and the dopant concentration in the semiconductor material are selected so that a depletion zone is formed in the semiconductor material along the metal-semiconductor junction in the absence of an externally applied electric field. In the case of Schottky contact, the term "metal-semiconductor junction" can also refer to a junction between a metalloid semiconductor and a semiconductor, wherein the junction has the same characteristics as a metal-semiconductor junction. For example, it may be possible to form a Schottky contact between polysilicon and silicon carbide. If two components (e.g., two regions) form an ohmic contact or a Schottky contact, respectively, this may mean that there is an ohmic contact or a Schottky contact between the two components. In both cases, it may be possible for the two regions to be directly adjacent to each other. However, it may also be possible that a further component is located between the two components.

[0057] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doping regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0058] The main components of a layer or structure from a chemical composition or alloy are the elements whose atoms form the chemical composition or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper-aluminum alloy.

[0059] As a wide bandgap semiconductor material, due to the particularity of silicon carbide materials, traditional isolation technology may not provide sufficient isolation characteristics, resulting in leakage and breakdown problems. Traditional silicon carbide devices may have high conduction and switching losses, affecting the efficiency and performance of the device.

[0060] Based on this, the present disclosure first provides a method for manufacturing a semiconductor device, referring to Figure 1 , the method for manufacturing a semiconductor device may include steps S110 to S160.

[0061] In step S110 , a silicon carbide body is provided.

[0062] In some examples of the present disclosure, reference Figure 2 First, a silicon carbide body 1 may be provided. By way of example, the silicon carbide body 1 may be of the polytype 15R-SiC, 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body 1 may also include dopant atoms, such as nitrogen N, phosphorus P, beryllium Be, boron B, aluminum Al and / or gallium Ga. Further, the silicon carbide body 1 may include unwanted impurities, such as hydrogen and / or oxygen. The silicon carbide body 1 may include a first surface 1A at the front side and an opposite second surface 1B at the back side.

[0063] It should be noted that the conductivity type of the silicon carbide body 1 may be a first conductivity type, the first conductivity type may be n-type, and the second conductivity type may be p-type. Here and below, the conductivity type of the silicon carbide body 1 is named as the first conductivity type.

[0064] It should be noted that the first conductivity type and the second conductivity type in the present disclosure are used to distinguish between n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type.

[0065] In this exemplary embodiment, the silicon carbide body 1 is of the first conductivity type, and the first conductivity type is n-type.

[0066] In step S120 , a first trench extending from a first surface of the silicon carbide body into the silicon carbide body is formed.

[0067] In an exemplary embodiment of the present disclosure, referring to Figure 3 , a first trench 11 extending from the first surface 1A into the silicon carbide body 1 may be formed on the silicon carbide body 1 .

[0068] Specifically, when forming the first groove 11, a mask etching process can be used to etch the first groove 11 on the silicon carbide body 1, and the formed first groove 11 has sidewalls and a bottom. The specific position of the first groove 11 can be customized based on user needs and will not be repeated in this exemplary embodiment.

[0069] In step S130 , a first isolation layer and a first polysilicon are formed in the first trench, wherein the first isolation layer is located between the first polysilicon and the bottom of the first trench, and between the first polysilicon and two sidewalls of the first trench.

[0070] In some example embodiments of the present disclosure, after forming the first trench 11, a first isolation layer 21 and a first polysilicon 31 may be formed in the first trench 11. Specifically, the first isolation layer 21 and the first polysilicon 31 may be first deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. Figure 4 The silicon dioxide is formed on the first surface 1A and the sidewalls and bottom of the first trench 11. Then, a silicon dioxide such as Figure 5 The polysilicon shown in the figure fills the first surface 1A and the first trench 11. After the deposition is completed, the silicon dioxide and the polysilicon are etched to form a Figure 6 The first polysilicon 31 and the first isolation layer 21 shown fill part of the first trench 11, and the first polysilicon 31 and the first isolation layer 21 form a planarization layer in the first trench 11. The etching method can be customized according to user needs and will not be described in detail in this exemplary embodiment.

[0071] In step S140, a second polysilicon and a second isolation layer are formed in the first trench, the second isolation layer is located between the second polysilicon and two sidewalls of the first trench, and the second isolation layer and the first isolation layer completely cover the first polysilicon.

[0072] In an exemplary embodiment of the present disclosure, after forming the first polysilicon 31 and the first isolation layer 21, a second polysilicon 32 and a second isolation layer 22 may be formed in the first trench 11. Specifically, a planarization layer formed by the first polysilicon 31 and the first isolation layer 21 and a portion of the first surface 1A close to the first trench 11 may be formed as follows: Figure 7 The second isolation layer 22 is then formed by deposition. Figure 8 The second polysilicon 32 is shown, wherein the first polysilicon 31 , the second polysilicon 32 , the first isolation layer 21 , and the second isolation layer 22 completely fill the first trench 11 , wherein the second isolation layer 22 covers a portion of the first surface 1A.

[0073] Optionally, the first isolation layer 21 and the second isolation layer 22 are both made of silicon dioxide. After the second polysilicon 32 is formed, a side of the second polysilicon 32 away from the bottom of the first trench 11 is located on the same surface as the first surface 1A.

[0074] In step S150 , a second trench extending from the second polysilicon to the bottom of the first trench is formed, and the second trench at least exposes a portion of the bottom of the first trench.

[0075] In some examples, reference Fig. 9 After forming the second polysilicon 32, a second trench 12 may be formed on the second polysilicon 32 in the first trench 11, wherein the second trench 12 extends from the surface of the second polysilicon 32 on the side away from the bottom of the first trench 11 to the bottom of the first trench 11, and at least partially exposes the bottom of the first trench 11. The second trench 12 may be formed in the same manner as the first trench 11, both of which are formed by mask etching. The specific formation method may also be customized according to user needs, and will not be described in detail in this exemplary embodiment.

[0076] After the second trench 12 is formed, portions of the first polysilicon 31 and the second polysilicon 32 are exposed on both sidewalls of the second trench 12 .

[0077] In step S160 , a third isolation layer is formed by oxidizing a portion of the first polysilicon and a portion of the second polysilicon at a high temperature, so that the first isolation layer, the second isolation layer and the third isolation layer completely cover the first polysilicon and the second polysilicon.

[0078] After the second trench 12 is formed, Fig.10 The second polysilicon 32 in the same plane as the first surface 1A and the portions of the first polysilicon 31 and the second polysilicon 32 exposed on the two side walls of the second trench 12 can be oxidized by high-temperature oxidation to form a third isolation layer 23, wherein the first polysilicon 31 and the second polysilicon 32 are completely covered by the first isolation layer 21, the second isolation layer 22 and the third isolation layer 23.

[0079] The method for manufacturing a semiconductor device provided by an embodiment of the present disclosure can achieve more effective electrical isolation by forming a first isolation layer 21 and a first polysilicon 31, as well as a second polysilicon 32 and a second isolation layer 22 in a first trench 11. This structure helps to reduce the risk of leakage and breakdown, and improve the reliability and stability of the device. The arrangement of the first polysilicon 31 and the second polysilicon 32 helps to optimize the electric field distribution inside the device. By precisely controlling the position and thickness of the polysilicon layer, the area of ​​electric field concentration can be reduced, thereby improving the voltage resistance and reliability of the device. The high electron saturation velocity and low resistivity of the silicon carbide material itself help to reduce the conduction loss of the device. The arrangement of the first polysilicon 31 and the second polysilicon 32 can further optimize the conductive path and improve the power conversion efficiency; the high thermal conductivity of silicon carbide helps to better manage the heat generated when the device is running. The arrangement of the first polysilicon 31 and the second polysilicon 32 can facilitate heat conduction, reduce heat dissipation requirements, and help achieve miniaturization and lightweight of the device. Secondly, generating the third isolation layer 23 by high-temperature oxidation of polysilicon can reduce process difficulty and the difficulty of filling hole size, which is beneficial for filling holes in small-size chips.

[0080] In some examples, reference Fig.11 After forming the first trench 11 and before forming the first isolation layer 21 and the first polysilicon 31, the bottom of the first trench 11 can also be extended to the first shielding area 13 in the silicon carbide body 1, and the second trench 12 at least exposes part of the first shielding area 13 to improve the problem of concentrated electric field distribution in the first trench 11. The second trench 12 exposes the first shielding area 13 so that the metal electrode can be directly connected to the first shielding area 13. The first shielding area 13 is a heavily doped area 18 of the second conductivity type, and has better conductivity after forming ohmic contact with the metal electrode.

[0081] In some examples, reference Fig.12 Before forming the first trench 11, a first current-carrying region 14 may be formed at the bottom of the first trench 11, wherein the first current-carrying region 14 extends from the bottom of the first trench 11 to the silicon carbide body 1, and the first shielding region 13 runs through the first current-carrying region 14 and does not completely cover the first current-carrying region 14, and the first current-carrying region 14 can effectively alleviate the electric field concentration effect at the bottom of the trench. The first current-carrying region 14 is of the second conductivity type, and the doping concentration of the second current-carrying region 16 is less than the doping concentration of the body region 19.

[0082] In some examples, reference Fig.13 At least one second shielding region 15 may be formed, and the number of optional second shielding regions 15 is two, which are respectively arranged on both sides of the first trench 11. The doping concentration of the second shielding region 15 may be the same as that of the first shielding region 13, and both are of the second conductivity type.

[0083] In some examples, reference Fig.14 After forming the second shielding region 15 , a second current-carrying region 16 may be further formed. The second current-carrying region 16 is disposed on a side of the second shielding region 15 away from the first surface 1A.

[0084] The first current-carrying region 14 and the second current-carrying region 16 have the same conductivity type, which is the second conductivity type.

[0085] Reference Fig.15 Before forming the first trench 11, a second current spreading layer 172 may be formed in the silicon carbide body 1. The extension direction of the second current spreading layer 172 is the same as that of the first plane and is arranged parallel to the first plane.

[0086] Reference Fig.16 A first current spreading layer 171 may also be formed in the silicon carbide body 1, the first current spreading layer 171 is arranged in parallel with the second current source spreading layer 172, and the first current spreading layer 171 is connected to the second current carrying region 16. Fig.15 , a body region 19 and a heavily doped region 18 can also be formed, wherein the heavily doped region 18 extends from the first surface 1A into the silicon carbide body 1, and the body region 19 is located between the heavily doped region 18 and the above-mentioned silicon carbide body 1, wherein the conductivity type of the heavily doped region 18 is the first conductivity type, and the conductivity type of the body region 19 is the second conductivity type, and the body region 19 and the heavily doped region 18 form a reverse PN junction.

[0087] The current spreading layer can improve the distribution of current and help to distribute heat more evenly, reduce hot spots and lower the thermal resistance of the device. By reducing current crowding and improving thermal management, the current spreading layer helps to improve the reliability and life of semiconductor devices. The current spreading layer helps to transfer current more evenly from the electrode to the active area of ​​the diode laterally, reducing current crowding, thereby improving the optoelectronic performance of the device. By optimizing the distribution of current, the current spreading layer can reduce energy losses in the electrode and contact area and improve the overall energy efficiency of the device.

[0088] In some examples, the reverse recovery performance of the diode can be improved by the cooperation between the first shielding region 13, the first current carrying region 14 and the second current carrying region 16. At the same time, the second current carrying region 16 forms a PN junction with the first current spreading layer 171 to avoid leakage in the cell region.

[0089] The manufacturing method of the semiconductor device is described in detail below by using a specific example implementation. First, referring to Fig.17 , a second shielding region 15 may be first formed on the silicon carbide body 1, wherein the second shielding region 15 is disposed at both ends of the silicon carbide body 1, referring to Fig.18A shallowly injected second current spreading layer 172 is formed between the two second shielding regions 15 by high-temperature ion implantation of nitrogen / phosphorus elements, and a first current spreading layer 171 is formed in the above-mentioned silicon carbide body 1 by ion implantation of nitrogen / phosphorus elements, wherein the injection junction depth of the second current spreading layer 172 is less than the injection junction depth of the first current spreading layer 171.

[0090] Then, refer to Fig.19 , nitrogen / phosphorus elements are ion implanted from the first surface 1A at high temperature to form a heavily doped region 18, wherein the heavily doped region 18 has the same conductivity type as the first current spreading layer 171 and the second current spreading layer 172, both of which are the first conductivity type, and the doping concentration of the heavily doped region 18 is greater than the doping concentration of the first current spreading layer 171, and the doping concentrations of the first current spreading layer 171 and the second current spreading layer 172 can be the same within a threshold range.

[0091] Reference Fig. 20 The body region 19 can be formed by high temperature injection of aluminum ions, wherein the body region 19 is located between the silicon carbide body 1 and the heavily doped region 18. After the heavily doped region 18 is formed, Fig.21 A second current carrying region 16 is formed by high temperature aluminum ion implantation. The second current carrying region 16 is located on a side of the first shielding region 13 away from the first surface 1A, and an implantation junction depth of the second current carrying region 16 is greater than an implantation junction depth of the second shielding region 15 .

[0092] Then, a first groove 11 extending toward the silicon carbide body 1 is formed in the heavily doped region 18 of the first surface 1A. Specifically, the first groove 11 is formed by etching, and then Fig. 22 A first current-carrying region 14 is formed at the bottom of the first trench 11 , which is also formed by high-temperature aluminum ion implantation, and then a first shielding region 13 is formed at the bottom of the first trench 11 . The first shielding region 13 extends from the bottom of the first trench 11 into the silicon carbide body 1 , and the first shielding region 13 runs through the first current-carrying region 14 .

[0093] After forming the first shielding region 13, a first polysilicon 31 and a first isolation layer 21 may be formed in the first trench 11. Specifically, a first layer such as a silicon layer 21 may be deposited on the bottom, two sidewalls, and the first surface 1A of the first trench 11. Fig.23 Then, polysilicon is formed on the side of the silicon dioxide away from the silicon carbide body 1, and the polysilicon completely fills the first trench 11 and covers the first surface 1A. Fig.24 Then, by etching, a Fig.25 The first isolation layer 21 and the first polysilicon 31 are shown.

[0094] After the first polysilicon 31 and the first isolation layer 21 are formed, the second polysilicon 32 and the second isolation layer 22 may be formed. Specifically, the second polysilicon 32 and the second isolation layer 22 may be formed in the first trench 11. Specifically, the planarization layer formed by the first polysilicon 31 and the first isolation layer 21 and the portion of the first surface 1A close to the first trench 11 may be formed as follows: Fig.26 The second isolation layer 22 is then formed by deposition. Fig. 27 The second polysilicon 32 is shown, wherein the first polysilicon 31 , the second polysilicon 32 , the first isolation layer 21 , and the second isolation layer 22 completely fill the first trench 11 , wherein the second isolation layer 22 covers a portion of the first surface 1A.

[0095] Optionally, the first isolation layer 21 and the second isolation layer 22 are both made of silicon dioxide. After the second polysilicon 32 is formed, a side of the second polysilicon 32 away from the bottom of the first trench 11 is located on the same surface as the first surface 1A.

[0096] Reference Fig.28 After forming the second polysilicon 32, a second trench 12 may be formed on the second polysilicon 32 in the first trench 11, wherein the second trench 12 extends from the surface of the second polysilicon 32 on the side away from the bottom of the first trench 11 to the bottom of the first trench 11, and at least partially exposes the bottom of the first trench 11. The second trench 12 may be formed in the same manner as the first trench 11, both of which are formed by mask etching. The specific formation method may also be customized according to user needs, and will not be described in detail in this exemplary embodiment.

[0097] After the second trench 12 is formed, portions of the first polysilicon 31 and the second polysilicon 32 are exposed on both sidewalls of the second trench 12 .

[0098] After the second trench 12 is formed, Fig.16 The second polysilicon 32 in the same plane as the first surface 1A and the portions of the first polysilicon 31 and the second polysilicon 32 exposed on the two side walls of the second trench 12 can be oxidized by high-temperature oxidation to form a third isolation layer 23, wherein the first polysilicon 31 and the second polysilicon 32 are completely covered by the first isolation layer 21, the second isolation layer 22 and the third isolation layer 23.

[0099] In some examples, after the formation of the second trench 12 is completed, referring to Fig.29, a metal electrode 4 can be formed, the metal electrode 4 completely fills the above-mentioned second groove 12 and covers the first surface 1A, wherein the metal electrode 4 forms a good ohmic contact with the first shielding area 13 and the second shielding area 15, the first shielding area 13 forms a PN junction with the silicon carbide body 1, the second shielding area 15 forms a PN junction with the silicon carbide body 1, the first current spreading layer 171 and the second current spreading layer 172 can both form a PN junction with the silicon carbide body 1, and the first current spreading layer 171 can also form a PN junction with the above-mentioned second current carrying area 16, and the first current carrying area 14 can also form a PN junction with the above-mentioned silicon carbide body 1.

[0100] In some examples, reference Fig.30 Before providing the silicon carbide body 1, a silicon carbide substrate 5 may be provided first. The conductivity type of the silicon carbide substrate 5 is the same as that of the silicon carbide body 1, but the doping concentration of the silicon carbide substrate 5 is higher than that of the silicon carbide body 1. The silicon carbide body 1 is formed on one side of the silicon carbide substrate 5, that is, the second surface 1B of the silicon carbide body 1 is in contact with the silicon carbide substrate 5.

[0101] It should be noted that when the silicon carbide body 1 is formed, the silicon carbide body 1 is formed on the silicon carbide substrate 5 by depositing a silicon carbide epitaxial layer.

[0102] The manufacturing method of the semiconductor device disclosed in the present invention significantly improves the performance of the silicon carbide device through innovative structural design. First, by forming a first trench 11 in the silicon carbide body 1, and arranging a first isolation layer 21 and a first polysilicon 31, as well as a second polysilicon 32 and a second isolation layer 22 therein, more effective electrical isolation is achieved. This structural design helps to reduce the risk of leakage and breakdown, and improve the reliability and stability of the device.

[0103] In addition, the method optimizes the electric field distribution inside the device and reduces the area of ​​electric field concentration by precisely controlling the position and thickness of the polysilicon layer, thereby improving the voltage resistance and reliability of the device. The high electron saturation velocity and low resistivity of the silicon carbide material itself help to reduce the conduction loss of the device. The setting of the first polysilicon 31 and the second polysilicon 32 can further optimize the conductive path and improve the power conversion efficiency; the high thermal conductivity of silicon carbide helps to better manage the heat generated during the operation of the device. The setting of the first polysilicon 31 and the second polysilicon 32 can facilitate heat conduction, reduce the need for heat dissipation, and help to achieve miniaturization and lightweight of the device. Secondly, the third isolation layer 23 is generated by high-temperature oxidation of polysilicon, which can reduce the process difficulty and reduce the difficulty of filling the hole size, which is conducive to filling holes in small-size chips.

[0104] In some examples, the reverse recovery performance of the diode can be improved by the mutual cooperation of the first shielding region 13, the first current-carrying region 14 and the second current-carrying region 16. At the same time, the second current-carrying region 16 forms a PN junction with the first current spreading layer 171 to avoid leakage in the cell region. The current spreading layer can improve the distribution of current and help to distribute heat more evenly, reduce hot spots and reduce the thermal resistance of the device. By reducing current crowding and improving thermal management, the current spreading layer helps to improve the reliability and life of semiconductor devices; the current spreading layer helps to more evenly transfer current from the electrode to the active area of ​​the diode, reducing current crowding, thereby improving the optoelectronic performance of the device. By optimizing the distribution of current, the current spreading layer can reduce the power loss in the electrode and contact area and improve the overall energy efficiency of the device.

[0105] Furthermore, the present disclosure also provides a semiconductor device, referring to Fig.10 The semiconductor device may include a silicon carbide body 1 , a first trench 11 , a first polysilicon 31 and a first isolation layer 21 , a second polysilicon 32 and a second isolation layer 22 , a second trench 12 , and a third isolation layer 23 . The first trench 11 extends from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1; the first isolation layer 21 is located between the first polysilicon 31 and the bottom of the first trench 11, and between the first polysilicon 31 and the two side walls of the first trench 11; the second isolation layer 22 is located between the second polysilicon 32 and the two side walls of the first trench 11, and the second isolation layer 22 and the first isolation layer 21 completely cover the first polysilicon 31; the second trench 12 extends from the second polysilicon 32 to the bottom of the first trench 11, and the second trench 12 at least exposes a portion of the bottom of the first trench 11; the third isolation layer 23 is formed by high-temperature oxidation of a portion of the first polysilicon 31 and a portion of the second polysilicon 32, and the first isolation layer 21, the second isolation layer 22 and the third isolation layer 23 completely cover the first polysilicon 31 and the second polysilicon 32.

[0106] In some examples, reference Fig.11 The semiconductor device further includes a first shielding region 13 , which extends from the bottom of the first trench 11 into the silicon carbide body 1 , and the second trench 12 at least exposes a portion of the first shielding region 13 .

[0107] In some examples, reference Fig.13 The semiconductor device further includes at least one second shielding region 15 , which extends from the first surface 1A into the silicon carbide body 1 .

[0108] In some examples, reference Fig.12 The semiconductor device further includes a first current-carrying region 14 , which extends from the bottom of the first trench 11 into the silicon carbide body 1 , and the second shielding region 15 does not completely cover the first current-carrying region 14 .

[0109] In some examples, reference Fig.14 The semiconductor device further includes a second current-carrying region 16 , and the second current-carrying region 16 is located at a side of the second shielding region 15 away from the first surface 1A.

[0110] In some examples, reference Fig.16 The semiconductor device further includes a first current spreading layer 171 , the first shielding region 13 penetrates the first current spreading layer 171 , and the first current spreading layer 171 contacts the second current carrying region 16 .

[0111] In some examples, reference Fig.16 The semiconductor device further includes a second current spreading layer 172 , the second current spreading layer 172 is in contact with the second shielding region 15 , and the first trench 11 penetrates the second current spreading layer 172 .

[0112] In some examples, reference Fig.16 The semiconductor device further includes a body region 19 and a heavily doped region 18 . The heavily doped region 18 is located between the body region 19 and the first surface 1A. The first trench 11 penetrates the body region 19 and the heavily doped region 18 .

[0113] It should be noted that the specific structure of the semiconductor device can refer to the manufacturing method of the semiconductor device, which will not be elaborated here.

[0114] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the inventions claimed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not claimed in the present disclosure.

[0116] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a silicon carbide body (1); forming a first groove (11) extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1); forming a first isolation layer (21) and a first polysilicon (31) in the first trench (11), wherein the first isolation layer (21) is located between the first polysilicon (31) and the bottom of the first trench (11), and between the first polysilicon (31) and two side walls of the first trench (11); forming a second polysilicon (32) and a second isolation layer (22) in the first trench (11), wherein the second isolation layer (22) is located between the second polysilicon (32) and two side walls of the first trench (11), and the second isolation layer (22) and the first isolation layer (21) completely cover the first polysilicon (31); forming a second trench (12) extending from the second polysilicon (32) to the bottom of the first trench (11), wherein the second trench (12) at least exposes a portion of the bottom of the first trench (11); A third isolation layer (23) is formed by oxidizing a portion of the first polysilicon (31) and a portion of the second polysilicon (32) at high temperature, so that the first isolation layer (21), the second isolation layer (22) and the third isolation layer (23) completely cover the first polysilicon (31) and the second polysilicon (32).

2. The manufacturing method according to claim 1, characterized in that: The method further comprises: forming a first shielding region (13) extending from the bottom of the first trench (11) into the silicon carbide body (1); The second groove (12) exposes at least a portion of the first shielding area (13).

3. The manufacturing method according to claim 2, characterized in that: The method further comprises: At least one second shielding region (15) is formed extending from the first surface (1A) into the silicon carbide body (1).

4. The manufacturing method according to claim 3, characterized in that: Before forming the first shielding area (13), the method further comprises: forming a first current-carrying region (14) extending from the bottom of the first trench (11) into the silicon carbide body (1); After the first shielding region (13) is formed, the first shielding region (13) does not completely cover the first current-carrying region (14).

5. The manufacturing method according to claim 3, characterized in that: The method further comprises: A second current-carrying region (16) is formed, wherein the second current-carrying region (16) is located on a side of the second shielding region (15) away from the first surface (1A).

6. The manufacturing method according to claim 5, characterized in that: Before forming the first shielding area (13), the method further comprises: A first current spreading layer (171) is formed, the first shielding region (13) penetrates the first current spreading layer (171), and the first current spreading layer (171) is in contact with the second current carrying region (16).

7. The manufacturing method according to claim 3, characterized in that: Before forming the first groove (11), the method further comprises: A second current spreading layer (172) is formed, wherein the second current spreading layer (172) is in contact with the second shielding region (15), and the first groove (11) penetrates the second current spreading layer (172).

8. The manufacturing method according to claim 1, characterized in that: Before forming the first groove (11), the method further comprises: A body region (19) and a heavily doped region (18) are formed, wherein the heavily doped region (18) is located between the body region (19) and the first surface (1A), and the first trench (11) penetrates the body region (19) and the heavily doped region (18).

9. A semiconductor device, characterized in that: include: Silicon carbide body (1); A first groove (11) extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1); A first polysilicon (31) and a first isolation layer (21), wherein the first isolation layer (21) is located between the first polysilicon (31) and the bottom of the first trench (11), and between the first polysilicon (31) and two side walls of the first trench (11); a second polysilicon (32) and a second isolation layer (22), wherein the second isolation layer (22) is located between the second polysilicon (32) and two side walls of the first trench (11), and the second isolation layer (22) and the first isolation layer (21) completely cover the first polysilicon (31); a second trench (12), extending from the second polysilicon (32) to the bottom of the first trench (11), the second trench (12) exposing at least a portion of the bottom of the first trench (11); The third isolation layer (23) is formed by high-temperature oxidation of part of the first polysilicon (31) and part of the second polysilicon (32), and the first isolation layer (21), the second isolation layer (22) and the third isolation layer (23) completely cover the first polysilicon (31) and the second polysilicon (32).

10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises: A first shielding region (13), the first shielding region (13) extending from the bottom of the first trench (11) into the silicon carbide body (1), and the second trench (12) at least exposes a portion of the first shielding region (13).

11. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises: At least one second shielding region (15) extends from the first surface (1A) into the silicon carbide body (1).

12. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: The first current-carrying region (14) extends from the bottom of the first trench (11) into the silicon carbide body (1), and the second shielding region (15) does not completely cover the first current-carrying region (14).

13. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: A second current-carrying region (16), the second current-carrying region (16) being located on a side of the second shielding region (15) away from the first surface (1A).

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: A first current spreading layer (171), the first shielding region (13) penetrates the first current spreading layer (171), and the first current spreading layer (171) is in contact with the second current carrying region (16).

15. The semiconductor device according to claim 11, wherein: The semiconductor device further comprises: The second current spreading layer (172) is in contact with the second shielding area (15), and the first groove (11) runs through the second current spreading layer (172).

16. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises: A body region (19) and a heavily doped region (18), wherein the heavily doped region (18) is located between the body region (19) and the first surface (1A), and the first trench (11) runs through the body region (19) and the heavily doped region (18).

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