Integrated passive device, preparation method thereof and electronic equipment

Abstract

The invention provides an integrated passive device, a preparation method thereof and electronic equipment, and belongs to the technical field of passive devices. The integrated passive device disclosed by the invention comprises a dielectric substrate, at least two conductive layers arranged on the dielectric substrate, and an interlayer dielectric layer positioned between the two adjacent conductive layers, one of any two adjacent conductive layers close to the dielectric substrate is a first conductive layer, and the other one is a second conductive layer; wherein the first conductive layer comprises a first conductive structure, and the second conductive layer comprises a second conductive structure; and the second conductive structure and the first conductive structure are electrically connected through a connecting hole at least penetrating through the interlayer dielectric layer between the second conductive structure and the first conductive structure.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of passive devices, and in particular relates to an integrated passive device and a preparation method thereof, and an electronic device. Background Art

[0002] In the contemporary era, the consumer electronics industry is developing rapidly. Mobile communication terminals represented by mobile phones, especially 5G mobile phones, are developing rapidly. Mobile phones need to process more and more signal frequency bands, and the number of RF chips required is also rising. The mobile phone forms favored by consumers are constantly developing towards miniaturization, lightness, and long battery life. In traditional mobile phones, there are a large number of discrete devices such as resistors, capacitors, inductors, filters, etc. on the RF PCB board. They have the disadvantages of large size, high power consumption, many solder joints, and large changes in parasitic parameters, which makes it difficult to meet future needs. The interconnection and matching between RF chips require integrated passive devices (IPDs) with small area, high performance, and good consistency. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides an integrated passive device and a preparation method thereof, and an electronic device.

[0004] In a first aspect, an embodiment of the present disclosure provides an integrated passive device, comprising a dielectric substrate, at least two conductive layers arranged on the dielectric substrate, and an interlayer dielectric layer located between two adjacent conductive layers; for any two adjacent conductive layers, one close to the dielectric substrate is a first conductive layer, and the other is a second conductive layer; wherein the first conductive layer includes a first conductive structure, and the second conductive layer includes a second conductive structure; the second conductive structure and the first conductive structure are electrically connected via a connection hole that at least penetrates the interlayer dielectric layer between the two.

[0005] The connecting hole includes a first sub-hole and a second sub-hole that are interconnected; the first sub-hole penetrates the interlayer dielectric layer, and the second sub-hole penetrates at least a portion of the thickness of the first conductive structure.

[0006] The first opening of the first sub-hole is connected to the second opening of the second sub-hole, and the orthographic projections of the first opening and the second opening on the dielectric substrate coincide.

[0007] The first opening of the first sub-hole is connected to the second opening of the second sub-hole, and the orthographic projection of the second opening on the dielectric substrate covers the orthographic projection of the first opening on the dielectric substrate.

[0008] Wherein, the shape of the orthographic projection of the second sub-hole on the dielectric substrate includes a circle or a square.

[0009] Wherein, the inner wall of the connecting hole is stepped.

[0010] The connecting hole comprises a plurality of interconnected sub-holes, and the adjacent sub-holes define a step at the connecting position, and the maximum aperture of the sub-hole relatively close to the dielectric substrate is smaller than the minimum aperture of the sub-hole relatively far from the dielectric substrate.

[0011] Wherein, the connection hole only passes through the interlayer dielectric layer.

[0012] Wherein, the first conductive structure includes a first main structure and a first protruding structure connected to a side of the first main structure close to the interlayer dielectric layer; and / or,

[0013] The second conductive structure includes a second main body structure and a second protruding structure connected to a side of the second main body structure close to the interlayer dielectric layer.

[0014] Wherein, when the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the first main structure and the second main structure are connected through the connecting hole.

[0015] Wherein, when the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the orthographic projections of the first protruding structure and the second protruding structure on the dielectric substrate are alternately arranged.

[0016] Wherein, when the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the first protruding structure and the second protruding structure are arranged in a one-to-one correspondence.

[0017] The interlayer dielectric layer includes a third main structure, a third protruding structure connected to a side of the third main structure close to the first conductive structure, and a fourth protruding structure connected to a side of the third main structure close to the second conductive structure.

[0018] Wherein, the material of the interlayer dielectric layer includes polyimide.

[0019] The embodiment of the present disclosure also provides a method for preparing an integrated passive device, wherein a dielectric substrate is provided, at least two conductive layers are sequentially formed on the dielectric substrate, and an interlayer dielectric layer is formed between two adjacent conductive layers; one of any two adjacent conductive layers close to the dielectric substrate is a first conductive layer, and the other is a second conductive layer; wherein,

[0020] Forming the first conductive layer includes forming a first conductive structure, and forming the second conductive layer includes forming a second conductive structure. The second conductive structure and the first conductive structure are electrically connected via a connection hole that at least penetrates the interlayer dielectric layer therebetween.

[0021] Wherein, forming the connecting via comprises:

[0022] Before forming the interlayer dielectric layer, patterning the first conductive pattern to form a second sub-hole penetrating at least a portion of the thickness of the first conductive pattern;

[0023] After forming the interlayer dielectric layer, a first sub-hole penetrating the interlayer dielectric layer is formed, and the first sub-hole and the second sub-hole are connected to each other to form the connection hole.

[0024] The interlayer dielectric layer includes first sub-interlayer dielectric layers stacked in sequence in a direction away from the dielectric substrate; the first sub-interlayer dielectric layer has sub-holes, and the sub-holes of the first sub-interlayer dielectric layers are interconnected to form the connecting holes; the adjacent sub-holes define a step at the connecting position, and the maximum aperture of the sub-hole relatively close to the dielectric substrate is smaller than the minimum aperture of the sub-hole relatively far from the dielectric substrate.

[0025] Wherein, the first conductive structure includes a first main structure and a first protruding structure connected to a side of the first main structure close to the interlayer dielectric layer; and / or,

[0026] The second conductive structure includes a second main body structure and a second protruding structure connected to a side of the second main body structure close to the interlayer dielectric layer.

[0027] Wherein, the conductive layer is formed by an electroplating process.

[0028] In a second aspect, an embodiment of the present disclosure provides an electronic device, which includes any of the integrated passive devices described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A partial cross-sectional view of an integrated passive device according to an embodiment of the present disclosure.

[0030] Figure 2 for Figure 1 A cross-sectional view of a connecting via of an integrated passive device is shown.

[0031] Figure 3 It is a partial cross-sectional view of an integrated passive device of a first example of an embodiment of the present disclosure.

[0032] Figure 4a for Figure 3A cross-sectional view of a connecting via of an integrated passive device is shown.

[0033] Figure 4b for Figure 3 A cross-sectional view of a connecting via of an integrated passive device is shown.

[0034] Figure 5 A partial cross-sectional view of an integrated passive device including three conductive layers according to a first example of an embodiment of the present disclosure.

[0035] Figure 6 The present invention is a flowchart of a method for preparing an integrated passive device according to a first example of an embodiment of the present invention.

[0036] Figure 7 A partial cross-sectional view of an integrated passive device according to a second example of an embodiment of the present disclosure.

[0037] Figure 8 for Figure 7 A cross-sectional view of a connecting via of an integrated passive device is shown.

[0038] Fig. 9 A partial cross-sectional view of an integrated passive device including three conductive layers according to a second example of an embodiment of the present disclosure.

[0039] Fig.10 The present invention is a flowchart of a method for preparing an integrated passive device according to a second example of an embodiment of the present invention.

[0040] Fig.11 A partial cross-sectional view of an integrated passive device according to a third example of an embodiment of the present disclosure.

[0041] Fig.12 A partial cross-sectional view of another integrated passive device according to a third example of an embodiment of the present disclosure.

[0042] Fig.13 A partial cross-sectional view of an integrated passive device including three conductive layers according to a third example of an embodiment of the present disclosure.

[0043] Fig.14 The present invention is a flowchart of a method for preparing an integrated passive device according to a third example of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] First, Figure 1 is a partial cross-sectional view of an integrated passive device according to an embodiment of the present disclosure; Figure 2 for Figure 1 A cross-sectional view of a connecting via of an integrated passive device as shown; Figure 1 and 2 As shown, an embodiment of the present disclosure provides an integrated passive device, which includes but is not limited to an inductor. The device includes a dielectric substrate 1, at least two conductive layers arranged on the dielectric substrate 1, and an interlayer dielectric layer 4 located between adjacent conductive layers. In the embodiment of the present disclosure, for any two adjacent conductive layers, the one close to the dielectric substrate 1 is called the first conductive layer 2, and the other is called the second conductive layer 3. The first conductive layer 2 includes a first conductive structure 21, and the second conductive layer 3 includes a second conductive structure 31. The first conductive structure 21 and the second conductive structure 31 are electrically connected through a connection hole 41 that at least penetrates the interlayer dielectric layer 4 between the first conductive structure 21 and the second conductive structure 31.

[0047] It should be noted that when the integrated passive device is an inductor, the first conductive structure 21 and the second conductive structure 31 are coil structures of the inductor, and the number of conductive layers determines the number of turns of the inductor coil structure.

[0048] In the embodiment of the present disclosure, the material of the conductive layer is generally a metal material, and the material of the interlayer dielectric layer 4 includes but is not limited to polyimide PI. In the embodiment of the present disclosure, only the interlayer dielectric layer 4 using polyimide is used as an example for explanation. Since the thermal expansion coefficients of the conductive layer and the interlayer dielectric layer 4 are quite different, when the film layer is heated and expanded, the interlayer dielectric layer 4 will expand laterally (parallel to the plane where the dielectric substrate 1 is located), causing the first conductive structure 21 and the second conductive structure 31, which were originally electrically connected, to separate (peeling) at the connection position. The following technical solutions are provided in the embodiment of the present disclosure to improve this problem.

[0049] Before describing the following examples, it should be noted that the following examples mainly take the electrical connection of two adjacent conductive layers as an example, but it should be understood that the integrated passive device can have more conductive layers, which are not listed here one by one.

[0050] First example: Figure 3 A partial cross-sectional view of an integrated passive device according to a first example of an embodiment of the present disclosure; Figure 4a for Figure 3 A cross-sectional view of a connecting via of an integrated passive device as shown; Figure 3 and 4a As shown, the integrated passive device includes a dielectric substrate 1, a first conductive layer 2, an interlayer dielectric layer 4, and a second conductive layer 3 arranged on the dielectric substrate 1 in sequence. The first conductive layer 2 includes a first conductive structure 21, the second conductive layer 3 includes a second conductive structure 31, and the first conductive structure 21 and the second conductive structure 31 are electrically connected through a connecting hole 41 that at least penetrates the interlayer dielectric layer 4 therebetween. In this example, the connecting hole 41 includes a first sub-hole 401 and a second sub-hole 402 that are interconnected; the first sub-hole 401 penetrates the interlayer dielectric layer 4, and the second sub-hole 402 penetrates at least a portion of the thickness of the first conductive structure 21. That is, the connecting hole 41 not only penetrates the interlayer dielectric layer 4, but also penetrates at least a portion of the thickness of the first conductive structure 21. In this case, when the second conductive structure 31 is connected to the first conductive structure 21, the connection position between the second conductive structure 31 and the first conductive structure 21 is limited within the second sub-hole 402. In this way, even if the interlayer dielectric layer 4 expands laterally, the connection position between the second conductive structure 31 and the first conductive structure 21 is limited within the second hole on the first conductive structure 21, which can effectively improve the problem of separation of the connection position between the second conductive structure 31 and the first conductive structure 21.

[0051] In some examples, the first opening of the first sub-hole 401 is connected to the second opening of the second sub-hole 402, and the orthographic projections of the first opening and the second opening on the dielectric substrate 1 completely overlap. At this time, the connection position of the second conductive structure 31 and the first conductive structure 21 is just completely wrapped by the second hole, which can ensure that the second conductive structure 31 and the first conductive structure 21 are stably connected. It should be noted that in the embodiment of the present disclosure, the first opening of the first sub-hole 401 refers to the one of the two openings of the first sub-hole 401 that is close to the dielectric substrate 1, and the second opening of the second sub-hole 402 refers to the one of the two openings of the second sub-hole 402 that is far from the dielectric substrate 1. In this case, the orthographic projection shapes of the first sub-hole 401 and the second sub-hole 402 on the dielectric substrate 1 are exactly the same. For example, if the orthographic projection shape of the first sub-hole 401 on the dielectric substrate 1 is a circle, the orthographic projection shape of the second sub-hole 402 on the dielectric substrate 1 is also a circle.

[0052] In some examples, Figure 4b for Figure 3 A cross-sectional view of a connecting via of an integrated passive device as shown; Figure 4b As shown, the first opening of the first sub-hole 401 is connected to the second opening of the second sub-hole 402, and the orthographic projection of the second opening on the dielectric substrate 1 covers the orthographic projection of the first opening on the dielectric substrate 1. In this case, the aperture of the second sub-hole 402 is larger than that of the first sub-hole 401. In this case, the orthographic projection shapes of the first sub-hole 401 and the second sub-hole 402 on the dielectric substrate 1 can be completely the same or different. For example: if the shape of the orthographic projection of the first sub-hole 401 on the dielectric substrate 1 is circular, the shape of the orthographic projection of the second sub-hole 402 on the dielectric substrate 1 is also circular. For another example: if the shape of the orthographic projection of the first sub-hole 401 on the dielectric substrate 1 is circular, the shape of the orthographic projection of the second sub-hole 402 on the dielectric substrate 1 is also square.

[0053] It should be noted that Figure 5 A partial cross-sectional view of an integrated passive device including three conductive layers according to a first example of an embodiment of the present disclosure; Figure 5 As shown, based on the above example, the integrated passive device can be expanded to include more conductive layers. In this case, the depth, shape and size of the second hole formed on each conductive layer can be the same or different, which is not limited in the embodiments of the present disclosure.

[0054] For the integrated passive device of the first example, a method for preparing the integrated passive device is also provided in this example. Figure 6 Flow chart of a method for preparing an integrated passive device according to a first example of an embodiment of the present disclosure; Figure 6 As shown, the following steps may be specifically included:

[0055] S11, providing a dielectric substrate 1.

[0056] In some examples, a dielectric substrate 1 with a thickness of 0.15 to 2 mm and a mass production size is prepared according to the requirements of the process equipment. The material of the dielectric substrate 1 can be selected from glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. In step S11, a cleaning process before preparation of the dielectric substrate 1 may be included, and ultrasonic cleaning is performed in sequence with organic solvents such as deionized water, ethanol, isopropanol, etc., and the ultrasonic time is at least 15 minutes. After ultrasonic cleaning, it is dried in an oven, and can be dried at 75°C for a certain time according to the last cleaning solvent.

[0057] S12, forming a first conductive layer 2 on the dielectric substrate 1, wherein the first conductive layer 2 includes a first conductive structure 21, and the first conductive structure 21 includes a second sub-hole 402 penetrating at least a portion of the thickness thereof.

[0058] In some examples, the first conductive layer 2 in step S12 can be formed by additive electroplating or by subtractive electroplating. The following specifically describes step S12 by taking the additive electroplating method to form the first conductive layer 2 as an example.

[0059] Specifically, step S12 may include forming a first auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a first conductive film layer, and using the first conductive film layer as a first seed layer. Next, a first photoresist layer is formed on a side of the first seed layer away from the dielectric substrate 1, and the first photoresist layer is exposed, developed, and etched to form a first conductive pattern. The first conductive pattern is electroplated to form a first conductive structure 21 to be patterned. A second photoresist layer is formed on the first conductive structure 21 to be patterned, and the second photoresist layer is exposed, developed, and etched to form a first conductive structure 21 having a second sub-hole 402.

[0060] The first auxiliary film layer is used to increase the adhesion of the first conductive film layer. The material of the first auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu. The first photoresist layer and the second photoresist layer can both use ordinary photosensitive photoresists, and positive photoresists or negative photoresists can be selected.

[0061] S13 , forming an interlayer dielectric layer 4 on a side of the first conductive structure 21 away from the dielectric substrate 1 , wherein the interlayer dielectric layer 4 has a first sub-hole 401 penetrating the thickness thereof, and the first sub-hole 401 is connected to the second sub-hole 402 to form a connecting hole 41 .

[0062] In some examples, the material of the interlayer dielectric layer 4 includes, for example, resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc. In the embodiment of the present disclosure, the material of the interlayer dielectric layer 4 is polyimide as an example. Step S13 may include coating to form the interlayer dielectric layer 4 to be patterned, then exposing, developing and etching to form the first sub-hole 401 that penetrates the interlayer dielectric layer 4, and finally curing.

[0063] S14 , forming a second conductive layer 3 on a side of the interlayer dielectric layer 4 away from the dielectric substrate 1 , wherein the second conductive layer 3 includes a second conductive structure 31 , and the second conductive structure 31 is electrically connected to the first conductive structure 21 through the first sub-hole 401 and the second sub-hole 402 .

[0064] In some examples, the second conductive layer 3 in step S14 can be formed by additive electroplating or by subtractive electroplating. The following specifically describes step S14 by taking the additive electroplating method to form the second conductive layer 3 as an example.

[0065] Specifically, step S14 may include forming a second auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a second conductive film layer, and using the second conductive film layer as a second seed layer. Next, a third photoresist layer is formed on a side of the second seed layer away from the dielectric substrate 1, and the third photoresist layer is exposed, developed, and etched to form a second conductive pattern. The second conductive pattern is electroplated to form a second conductive structure 31.

[0066] The second auxiliary film layer is used to increase the adhesion of the second conductive film layer. The material of the second auxiliary film layer includes but is not limited to titanium Ti, and the material of the second conductive film layer includes but is not limited to Cu. The third photoresist layer can be made of ordinary photosensitive photoresist, and positive photoresist or negative photoresist can be selected.

[0067] Second example: Figure 7 A partial cross-sectional view of an integrated passive device according to a second example of an embodiment of the present disclosure; Figure 8 for Figure 7 A cross-sectional view of a connecting via of an integrated passive device as shown; Figure 7 and 8As shown, the integrated passive device includes a dielectric substrate 1, a first conductive layer 2, an interlayer dielectric layer 4, and a second conductive layer 3 arranged on the dielectric substrate 1 in sequence. The first conductive layer 2 includes a first conductive structure 21, the second conductive layer 3 includes a second conductive structure 31, and the first conductive structure 21 and the second conductive structure 31 are electrically connected through a connecting hole 41 that penetrates the interlayer dielectric layer 4. The inner wall of the connecting hole 41 is stepped. In this example, the inner wall of the connecting hole 41 is designed to be stepped, thereby increasing the contact area between the second conductive structure 31 and the interlayer dielectric layer 4. At this time, under the condition of the same amount of heat, the stress generated by the expansion of the film layer is constant, the contact area between the film layers is increased, the force per unit area is reduced, and it is more difficult for the film layers to separate. At the same time, the heat dissipation area of ​​the device is increased to avoid the accumulation of heat in local positions.

[0068] In some embodiments, the connection hole 41 includes a plurality of interconnected sub-holes 403 , and adjacent sub-holes 403 define a step at the connection position, and the maximum aperture of the sub-hole 403 relatively close to the dielectric substrate 1 is smaller than the minimum aperture of the sub-hole 403 relatively far from the dielectric substrate 1 .

[0069] Specifically, the interlayer dielectric layer 4 may include a first sub-interlayer dielectric layer 40 stacked in multiple layers, each of the first sub-interlayer dielectric layers 40 has a sub-hole 403, and the multiple sub-holes 403 are connected to form a connection hole 41. It should be noted that in this example, only the connection hole 41 includes two sub-holes 403, that is, the interlayer dielectric layer 4 includes only two layers of first sub-interlayer dielectric layers 40. However, it should be understood that the number of sub-holes 403 can be specifically set according to the actual product, and will not be listed one by one here.

[0070] It should be noted that Fig. 9 FIG. 1 is a partial cross-sectional view of an integrated passive device including three conductive layers according to a second example of an embodiment of the present disclosure; Fig. 9 As shown, based on the above example, the integrated passive device can be expanded to include more conductive layers. In this case, the depth, shape and size of the connection holes 41 formed on each interlayer dielectric layer 4 can be the same or different, which is not limited in the embodiments of the present disclosure.

[0071] For the integrated passive device of the second example, a method for preparing the integrated passive device is also provided in this example. Fig.10 Flow chart of a method for preparing an integrated passive device according to a second example of an embodiment of the present disclosure; Fig.10 As shown, the following steps may be specifically included:

[0072] S21, providing two dielectric substrates 1.

[0073] In some examples, a dielectric substrate 1 with a thickness of 0.15 to 2 mm and a mass production size is prepared according to the requirements of the process equipment. The material of the dielectric substrate 1 can be selected from glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. In step S21, a cleaning process before preparation of the dielectric substrate 1 may be included, and ultrasonic cleaning is performed in sequence with organic solvents such as deionized water, ethanol, isopropanol, etc., and the ultrasonic time is at least 15 minutes. After ultrasonic cleaning, it is dried in an oven, and can be dried at 75°C for a certain time according to the last cleaning solvent.

[0074] S22 , forming a first conductive layer 2 on the dielectric substrate 1 , wherein the first conductive layer 2 includes a first conductive structure 21 .

[0075] In some examples, the first conductive layer 2 in step S22 can be formed by additive electroplating or by subtractive electroplating. The following specifically describes step S22 by taking the additive electroplating method to form the first conductive layer 2 as an example.

[0076] Specifically, step S22 may include forming a first auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a first conductive film layer, and using the first conductive film layer as a first seed layer. Next, a first photoresist layer is formed on a side of the first seed layer away from the dielectric substrate 1, and the first photoresist layer is exposed, developed, and etched to form a first conductive pattern. The first conductive pattern is electroplated to form a first conductive structure 21.

[0077] The first auxiliary film layer is used to increase the adhesion of the first conductive film layer. The material of the first auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu. The first photoresist layer and the second photoresist layer can both use ordinary photosensitive photoresists, and positive photoresists or negative photoresists can be selected.

[0078] S23. An interlayer dielectric layer 4 is formed on a side of the first conductive structure 21 away from the dielectric substrate 1. The interlayer dielectric layer 4 has a connection hole 41 that penetrates through the thickness thereof. The connection hole 41 includes a plurality of sub-holes 403 that are interconnected. The adjacent sub-holes 403 define a step at a connection position. The maximum aperture of the sub-hole 403 that is relatively close to the dielectric substrate 1 is smaller than the minimum aperture of the sub-hole 403 that is relatively far from the dielectric substrate 1.

[0079] In some examples, the interlayer dielectric layer 4 may include a first sub-interlayer dielectric layer 40 stacked in multiple layers, each of which has a sub-hole 403, and a plurality of sub-holes 403 are connected to form a connection hole 41. The material of the first sub-interlayer dielectric layer 40 includes, for example, polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For another example, the organic insulating material includes an elastic material, for example, urethane, thermoplastic polyurethane (TPU) and the like.

[0080] In the embodiment of the present disclosure, the material of the first intersub-layer dielectric layer 40 is polyimide as an example. Step S23 may include coating to form a first intersub-layer dielectric layer 40 to be patterned, then exposing, developing, and etching to form a sub-hole 403 penetrating the first intersub-layer dielectric layer 40, and finally curing. After that, coating is continued to form a second intersub-layer dielectric layer 40 to be patterned, then exposing, developing, and etching to form a sub-hole 403 penetrating the second intersub-layer dielectric layer 40, and finally curing, at this time, a connecting hole 41 is formed.

[0081] S24 , forming a second conductive layer 3 on a side of the interlayer dielectric layer 4 away from the dielectric substrate 1 , wherein the second conductive layer 3 includes a second conductive structure 31 , and the second conductive structure 31 is electrically connected to the first conductive structure 21 through the first sub-hole 401 and the second sub-hole 402 .

[0082] In some examples, the second conductive layer 3 in step S24 can be formed by additive electroplating or by subtractive electroplating. The following takes the formation of the second conductive layer 3 by additive electroplating as an example to specifically describe step S24.

[0083] Specifically, step S24 may include forming a second auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a second conductive film layer, and using the second conductive film layer as a second seed layer. Next, a third photoresist layer is formed on a side of the second seed layer away from the dielectric substrate 1, and the third photoresist layer is exposed, developed, and etched to form a second conductive pattern. The second conductive pattern is electroplated to form a second conductive structure 31.

[0084] The second auxiliary film layer is used to increase the adhesion of the second conductive film layer. The material of the second auxiliary film layer includes but is not limited to titanium Ti, and the material of the second conductive film layer includes but is not limited to Cu. The third photoresist layer can be made of ordinary photosensitive photoresist, and positive photoresist or negative photoresist can be selected.

[0085] The third example: Fig.11 FIG. 1 is a partial cross-sectional view of an integrated passive device of a third example of an embodiment of the present disclosure; Fig.11As shown, the integrated passive device includes a dielectric substrate 1, a first conductive layer 2, an interlayer dielectric layer 4, and a second conductive layer 3 sequentially arranged on the dielectric substrate 1. Among them, the first conductive layer 2 includes a first conductive structure 21, the second conductive layer 3 includes a second conductive structure 31, and the first conductive structure 21 and the second conductive structure 31 are electrically connected through a connection hole 41 that at least penetrates the interlayer dielectric layer 4 between the first conductive structure 21 and the second conductive structure 31. In this example, the first conductive structure 21 includes a first main structure 211 and a plurality of first protruding structures 212 connected to the first main structure 211 on a side close to the interlayer dielectric layer 4, and / or the second conductive structure 31 includes a second main structure 311 and a plurality of second protruding structures 312 connected to the second main structure 311 on a side close to the interlayer dielectric layer 4. In the embodiment of the present disclosure, only the example that the first conductive structure 21 includes the first main structure 211 and the first protruding structure 212, and the second conductive structure 31 includes the second main structure 311 and the second protruding structure 312 is used for description. In this case, the first main structure 211 and the second main structure 311 are electrically connected through the connection hole 41 that penetrates the interlayer dielectric layer 4. The first protruding structure 212 and the second protruding structure 312 both extend into the film layer of the interlayer dielectric layer 4, and the interlayer dielectric layer 4 also extends between the first protruding structures 212 and the second protruding structures 312. Under the same heat condition, the stress generated by the expansion of the film layer is constant, the contact area between the film layers is increased, the force per unit area is reduced, the film layers are more difficult to separate, and the heat dissipation area of ​​the device is increased to avoid the accumulation of heat in local positions.

[0086] In some examples, the orthographic projections of the first protruding structures 212 and the second protruding structures 312 on the dielectric substrate 1 may be arranged alternately, or the first protruding structures 212 and the second protruding structures 312 may be arranged one-to-one. Any arrangement can alleviate the problem of separation between film layers.

[0087] Fig.12 FIG. 1 is a partial cross-sectional view of another integrated passive device according to a third example of an embodiment of the present disclosure; Fig.12 As shown, similar to the above example, the interlayer dielectric layer 4 of the integrated passive device may include a third main structure 42, a third protruding structure 43 connected to the third main structure 42 on a side close to the first conductive structure 21, and a fourth protruding structure 44 arranged on a side connected to the third main structure 42 close to the second conductive structure 31. It should be understood that a second receiving groove may be arranged on the first conductive structure 21, and a third receiving groove may be arranged on the second conductive structure 31. In this case, the second receiving groove and the third protruding structure 43 are arranged in a one-to-one correspondence, and the third protruding structure 43 is arranged in the corresponding second receiving groove, and the third receiving groove and the fourth protruding structure 44 are arranged in a one-to-one correspondence, and the fourth protruding structure 44 is arranged in the corresponding third receiving groove.

[0088] It should be noted that Fig.13 FIG. 1 is a partial cross-sectional view of an integrated passive device including three conductive layers according to a third example of an embodiment of the present disclosure; Fig.13 As shown, based on the above example, the integrated passive device can be expanded to include more conductive layers. In this case, the height, shape and size of the protruding structure formed on each conductive layer can be the same or different, which is not limited in the embodiments of the present disclosure.

[0089] For the integrated passive device of the third example, a method for preparing the integrated passive device is also provided in this example. Fig.14 Flow chart of a method for preparing an integrated passive device according to a third example of an embodiment of the present disclosure; Fig.14 As shown, the following steps may be specifically included:

[0090] S31, providing a dielectric substrate 1.

[0091] In some examples, a dielectric substrate 1 with a thickness of 0.15 to 2 mm for mass production is prepared according to the requirements of the process equipment. The material of the dielectric substrate 1 can be selected from glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. In step S31, a cleaning process before preparation of the dielectric substrate 1 may be included, and ultrasonic cleaning is performed in sequence with organic solvents such as deionized water, ethanol, isopropanol, etc., and the ultrasonic time is at least 15 minutes. After ultrasonic cleaning, it is dried in an oven, and can be dried at 75°C for a certain time according to the last cleaning solvent.

[0092] S32 , forming a first conductive layer 2 on the dielectric substrate 1 , wherein the first conductive layer 2 includes a first conductive structure 21 ; the first conductive structure 21 includes a first main body structure 211 and a first protruding structure 212 .

[0093] In some examples, the first conductive layer 2 in step S32 can be formed by additive electroplating or by subtractive electroplating. The following specifically describes step S32 by taking the additive electroplating method to form the first conductive layer 2 as an example.

[0094] Specifically, step S32 may include forming a first auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a first conductive film layer, and using the first conductive film layer as a first seed layer. Next, a first photoresist layer is formed on the side of the first seed layer away from the dielectric substrate 1, and the first photoresist layer is exposed, developed, and etched to form a first conductive pattern. The first conductive pattern is electroplated to form a first main structure 211 to be patterned. A second photoresist layer is formed on the first main structure 211, and the second photoresist layer is exposed, developed, and etched to expose a position on the first main structure 211 where a first protruding structure 212 is to be formed, and the first main structure 211 at this position is used as a seed layer, and electroplating is performed to form the first protruding structure 212.

[0095] The first auxiliary film layer is used to increase the adhesion of the first conductive film layer. The material of the first auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu. The first photoresist layer and the second photoresist layer can both use ordinary photosensitive photoresists, and positive photoresists or negative photoresists can be selected.

[0096] S33 , forming an interlayer dielectric layer 4 on a side of the first conductive structure 21 away from the dielectric substrate 1 , wherein the interlayer dielectric layer 4 has a connection hole 41 penetrating the thickness thereof, and a first receiving groove 404 penetrating a portion of the thickness of the interlayer dielectric layer 4 .

[0097] In some examples, the material of the interlayer dielectric layer 4 includes, for example, resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc. In the embodiment of the present disclosure, the material of the interlayer dielectric layer 4 is polyimide as an example. Step S33 may include coating to form the interlayer dielectric layer 4 to be patterned, then forming a connection hole 41 that penetrates the interlayer dielectric layer 4 by exposure, development and etching, and finally curing.

[0098] S34. A second conductive layer 3 is formed on a side of the interlayer dielectric layer 4 facing away from the dielectric substrate 1. The second conductive layer 3 includes a second conductive structure 31. The second conductive structure 31 includes a second main body structure 311 and a second protruding structure 312. The second main body structure 311 is electrically connected to the first main body structure 211 through the connecting hole 41. The second protruding structure 312 is arranged in a one-to-one correspondence with the first receiving groove 404, and the second protruding structure 312 is filled in the corresponding first receiving groove 404.

[0099] In some examples, the second conductive layer 3 in step S34 can be formed by additive electroplating or by subtractive electroplating. The following specifically describes step S34 by taking the additive electroplating method to form the second conductive layer 3 as an example.

[0100] Specifically, step S34 may include forming a second auxiliary film layer by a method including but not limited to magnetron sputtering, and then continuously sputtering a second conductive film layer, and using the second conductive film layer as a second seed layer. Next, a third photoresist layer is formed on a side of the second seed layer away from the dielectric substrate 1, and the third photoresist layer is exposed, developed, and etched to form a second conductive pattern. The second conductive pattern is electroplated to form a second conductive structure 31.

[0101] The second auxiliary film layer is used to increase the adhesion of the second conductive film layer. The material of the second auxiliary film layer includes but is not limited to titanium Ti, and the material of the second conductive film layer includes but is not limited to Cu. The third photoresist layer can be made of ordinary photosensitive photoresist, and positive photoresist or negative photoresist can be selected.

[0102] In a second aspect, an embodiment of the present disclosure provides an electronic device, which includes any of the above-mentioned integrated passive devices.

[0103] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An integrated passive device, comprising a dielectric substrate, at least two conductive layers arranged on the dielectric substrate, and an interlayer dielectric layer located between two adjacent conductive layers; one of any two adjacent conductive layers close to the dielectric substrate is a first conductive layer, and the other is a second conductive layer; wherein, The first conductive layer includes a first conductive structure, and the second conductive layer includes a second conductive structure; the second conductive structure and the first conductive structure are electrically connected via a connection hole that at least penetrates the interlayer dielectric layer therebetween.

2. The integrated passive device according to claim 1, wherein: The connecting hole includes a first sub-hole and a second sub-hole that are interconnected; the first sub-hole penetrates the interlayer dielectric layer, and the second sub-hole penetrates at least a portion of the thickness of the first conductive structure.

3. The integrated passive device according to claim 2, wherein: A first opening of the first sub-hole is connected to a second opening of the second sub-hole, and the orthographic projections of the first opening and the second opening on the dielectric substrate coincide.

4. The integrated passive device according to claim 2, wherein: The first opening of the first sub-hole is connected to the second opening of the second sub-hole, and the orthographic projection of the second opening on the dielectric substrate covers the orthographic projection of the first opening on the dielectric substrate.

5. The integrated passive device according to any one of claims 2 to 4, wherein: The shape of the orthographic projection of the second sub-hole on the dielectric substrate includes a circle or a square.

6. The integrated passive device according to claim 1, wherein: The inner wall of the connecting hole is stepped.

7. The integrated passive device according to claim 6, wherein: The connection hole includes a plurality of interconnected sub-holes, and the adjacent sub-holes define a step at the connection position, and the maximum aperture of the sub-hole relatively close to the dielectric substrate is smaller than the minimum aperture of the sub-hole relatively far from the dielectric substrate.

8. The integrated passive device according to claim 6 or 7, wherein: The connection hole only penetrates the interlayer dielectric layer.

9. The integrated passive device according to claim 1, wherein: The first conductive structure includes a first main structure and a first protruding structure connected to a side of the first main structure close to the interlayer dielectric layer; and / or, The second conductive structure includes a second main body structure and a second protruding structure connected to a side of the second main body structure close to the interlayer dielectric layer.

10. The integrated passive device according to claim 9, wherein: When the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the first main structure and the second main structure are connected through the connecting hole.

11. The integrated passive device according to claim 9, wherein: When the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the orthographic projections of the first protruding structure and the second protruding structure on the dielectric substrate are alternately arranged.

12. The integrated passive device according to claim 9, wherein: When the first conductive structure includes the first main structure and the first protruding structure, and the second conductive structure includes the second main structure and the second protruding structure, the first protruding structure and the second protruding structure are arranged in a one-to-one correspondence.

13. The integrated passive device according to claim 1, wherein: The interlayer dielectric layer includes a third main body structure, a third protruding structure connected to a side of the third main body structure close to the first conductive structure, and a fourth protruding structure connected to a side of the third main body structure close to the second conductive structure.

14. The integrated passive device according to claim 1, wherein: The material of the interlayer dielectric layer includes polyimide.

15. A method for preparing an integrated passive device, wherein: A dielectric substrate is provided, on which at least two conductive layers are sequentially formed, and an interlayer dielectric layer is formed between two adjacent conductive layers; of any two adjacent conductive layers, one close to the dielectric substrate is a first conductive layer, and the other is a second conductive layer; wherein, Forming the first conductive layer includes forming a first conductive structure, and forming the second conductive layer includes forming a second conductive structure. The second conductive structure and the first conductive structure are electrically connected via a connection hole that at least penetrates the interlayer dielectric layer therebetween.

16. The method for preparing an integrated passive device according to claim 15, wherein: Forming the connecting via comprises: Before forming the interlayer dielectric layer, patterning the first conductive pattern to form a second sub-hole penetrating at least a portion of the thickness of the first conductive pattern; After forming the interlayer dielectric layer, a first sub-hole penetrating the interlayer dielectric layer is formed, and the first sub-hole and the second sub-hole are connected to each other to form the connection hole.

17. The method for preparing an integrated passive device according to claim 15, wherein: The interlayer dielectric layer includes first sub-interlayer dielectric layers stacked in sequence in a direction away from the dielectric substrate; the first sub-interlayer dielectric layer has sub-holes, and the sub-holes of each of the first sub-interlayer dielectric layers are interconnected to form the connecting hole; the adjacent sub-holes define a step at the connecting position, and the maximum aperture of the sub-hole relatively close to the dielectric substrate is smaller than the minimum aperture of the sub-hole relatively far from the dielectric substrate.

18. The method for preparing an integrated passive device according to claim 15, wherein: The first conductive structure includes a first main structure and a first protruding structure connected to a side of the first main structure close to the interlayer dielectric layer; and / or, The second conductive structure includes a second main body structure and a second protruding structure connected to a side of the second main body structure close to the interlayer dielectric layer.

19. The method for preparing an integrated passive device according to any one of claims 15 to 18, wherein: The conductive layer is formed by an electroplating process.

20. An electronic device comprising the integrated passive device according to any one of claims 1 to 14.

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