Power switch device

Abstract

The invention discloses a power switch device which comprises a substrate layer, an epitaxial layer, a gate structure, a first field plate structure and a second field plate structure. On the first surface of the power switch device, the first field plate structure and the second field plate structure are different in size or depth. According to the invention, the field plate structures with different sizes or depths are designed in the cellular region, and the breakdown region is led to the cellular region, so that the terminal region of the device is prevented from being broken down, and the UIS (Unclamped Inductive Switch) capability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power switch device and a structure thereof. Background Art

[0002] Field effect controlled power switching devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) are widely used as switches in power equipment such as power supplies and power converters.

[0003] The field effect control power switch device includes a surface with various functional areas. The surface can be divided into a cell area and a terminal area surrounding the cell area. Generally speaking, the cell area includes multiple cells of the same structure and size. The terminal area is used to provide protection for the cell area and improve the withstand voltage of the device. However, in order to reduce the area of ​​the device and improve the integration of the device, the area of ​​the terminal area is limited. When the terminal area is broken down, due to its limited area, the device's ability to withstand UIS (Unclamped Inductive Switching) will be very poor. Summary of the invention

[0004] The present application provides a power switch device, which leads the breakdown region to the cell region by designing a field plate structure with inconsistent size or depth in the cell region, thereby avoiding the breakdown of the terminal region of the device and improving the UIS capability of the device.

[0005] According to one embodiment of the present invention, a power switch device is provided, comprising: a substrate layer; an epitaxial layer located on the substrate layer; a gate structure; a first field plate structure, comprising a first field plate groove, a first field plate electrode and a first field plate insulating layer, wherein the first field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the first field plate electrode is located in the first field plate groove, the first field plate insulating layer covers the inner surface of the first field plate groove, and isolates the first field plate electrode from the first field plate groove; and a second field plate structure, comprising a second field plate groove, a second field plate electrode and a second field plate insulating layer, wherein the second field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the second field plate electrode is located in the second field plate groove, the second field plate insulating layer covers the inner surface of the second field plate groove, and isolates the second field plate electrode from the second field plate groove; wherein on a plane parallel to the first surface of the power switch device, the first field plate structure and the first field plate structure have different spacings in the same direction therein.

[0006] According to an embodiment of the present invention, a power switch device is provided, comprising: a substrate layer; an epitaxial layer located on the substrate layer; a gate structure; a first field plate structure, comprising a first field plate groove, a first field plate electrode and a first field plate insulating layer, wherein the first field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the first field plate electrode is located in the first field plate groove, the first field plate insulating layer covers the inner surface of the first field plate groove, and isolates the first field plate electrode from the first field plate groove; and a second field plate structure, comprising a second field plate groove, a second field plate electrode and a second field plate insulating layer, wherein the second field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the second field plate electrode is located in the second field plate groove, the second field plate insulating layer covers the inner surface of the second field plate groove, and isolates the second field plate electrode from the second field plate groove; wherein in a direction perpendicular to the first surface of the power switch device, the first field plate groove has a first depth, the second field plate groove has a second depth, and the first depth is greater than the second depth.

[0007] According to an embodiment of the present invention, the aforementioned power switching device, wherein: the gate structure is strip-shaped on a plane parallel to the first surface of the power switching device; and the first field plate structure and the second field plate structure are arranged in strips and distributed on both sides of each gate structure.

[0008] According to an embodiment of the present invention, in the aforementioned power switch device, the gate structure is a planar gate structure, and the gate structure is located on the epitaxial layer.

[0009] According to one embodiment of the present invention, the aforementioned power switching device, wherein: the gate structure is a trench gate structure, the gate structure includes a gate trench, a gate electrode and a gate insulation layer, the gate trench extends vertically from the first surface of the power switching device to the inside of the epitaxial layer, the gate electrode is located in the gate trench, and the gate insulation layer covers the inner surface of the gate trench to isolate the gate electrode from the gate trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0011] Figure 1 is a schematic structural diagram of a partial cell region of a power switch device 100 according to an embodiment of the present invention;

[0012] Figure 2 According to an embodiment of the present invention, Figure 1The schematic diagram of the cross-sectional structure of a part of the cell area of ​​the power switch device 100 along the AA line is shown;

[0013] Figure 3 is a schematic structural diagram of a partial cell region of a power switch device 300 according to an embodiment of the present invention;

[0014] Figure 4 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 400 according to an embodiment of the present invention;

[0015] Figure 5 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 500 according to an embodiment of the present invention;

[0016] Figure 6 is a schematic structural diagram of a partial cell region of a power switch device 600 according to an embodiment of the present invention;

[0017] Figure 7 According to an embodiment of the present invention, Figure 6 The schematic diagram of the cross-sectional structure of a part of the cell region of the power switch device 600 along the BB line is shown;

[0018] Figure 8 is a schematic structural diagram of a partial cell region of a power switch device 800 according to an embodiment of the present invention;

[0019] Fig. 9 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 900 according to an embodiment of the present invention;

[0020] Fig.10 FIG. 1 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 1000 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0022] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0023] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0024] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0025] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0026] In this document, relative doping concentrations are described by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means that the doping concentration is lower than the doping concentration of an "n"-doped region, while the "n"-doped region has a higher doping concentration than the "n-"-doped region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations.

[0027] In an embodiment of the present invention, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus and arsenic. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, and gallium.

[0028] Figure 1 FIG. 1 is a schematic structural diagram of a partial cell region of a power switch device 100 according to an embodiment of the present invention.

[0029] The power switch device 100 may be or include an insulated gate field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power switch device 100 may also include other power semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor).

[0030] like Figure 1 As shown, the power switch device 100 includes a gate structure 101, a first field plate structure 102 and a second field plate structure 103. The gate structure 101 is a planar gate structure, distributed in strips, and each gate structure 101 is parallel to each other. The first field plate structure 102 and the second field plate structure 103 are arranged in strips and distributed on both sides of each gate structure 101.

[0031] It should be understood that Figure 1 FIG. 1 shows one surface of the power switch device 100. On this surface, in addition to the gate structure 101, the first field plate structure 102 and the second field plate structure 103, there are other regions, such as source regions and / or body regions. For the sake of clarity of the example, other regions except the gate structure 101, the first field plate structure 102 and the second field plate structure 103 are not shown. Figure 1 Shown in.

[0032] exist Figure 1In the embodiment, the gate structure 101 is in a strip shape, the first field plate structure 102 and the second field plate structure 103 are distributed on a straight line parallel to the length direction of the gate structure 101, and the first field plate structure 102 and the second field plate structure 103 are distributed at intervals. That is, in a direction parallel to the length direction of the gate structure 101, a second field plate structure 103 is distributed between every two adjacent first field plate structures 102, and a first field plate structure 102 is distributed between every two adjacent second field plate structures 103.

[0033] exist Figure 1 In the embodiment, the first field plate structure 102 and the second field plate structure 103 both have an octagonal shape in a plane. Two opposite and parallel sides of the octagonal first field plate structure 102 are parallel to the length direction of the gate structure 101, and the distance between the two sides is defined as a first spacing W1. Two opposite and parallel sides of the octagonal second field plate structure 103 are parallel to the length direction of the gate structure 101, and the distance between the two sides is defined as a second spacing W2. The first spacing W1 and the second spacing W2 are perpendicular to the length direction of the gate structure 101 in a horizontal plane. Figure 1 In an embodiment, the first spacing W1 is greater than the second spacing W2. In some embodiments, the second spacing W2 is between 80% and 100% of the first spacing W1. In one embodiment, the second spacing W2 is 95% of the first spacing W1.

[0034] In some embodiments, the first spacing W1 is in a range of 0.2-2 μm, and the second spacing W2 is smaller than the first spacing W1 and is between 80% and 100% of the first spacing W1 .

[0035] exist Figure 1 In the embodiment, the first field plate structure 102 and the second field plate structure 103 are in an octagonal shape. In some embodiments, in order to make the electric field uniformly distributed, each corner of the octagon is passivated to be in an arc shape.

[0036] Figure 2 According to an embodiment of the present invention, Figure 1 The schematic diagram of the cross-sectional structure of a partial cell region of the power switch device 100 along the AA line is shown.

[0037] like Figure 2 As shown, the power switch device 100 has a first surface 104 and a second surface 105. The first surface 104 is Figure 1The plane of the power switch device 100 shown. The first surface 104 and the second surface 105 are parallel and face opposite directions in a vertical direction. The distance between the first surface 104 and the second surface 105 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 104 and the second surface 105 is called a horizontal plane, and the direction perpendicular to the first surface 104 and the second surface 105 is called a vertical direction.

[0038] like Figure 2 As shown, the power switch device 100 includes a substrate 106 and an epitaxial layer 107. The epitaxial layer 107 is located on the substrate 106. The first surface 104 is not only a surface of the power switch device 100, but also a surface of the epitaxial layer 107. The other surface of the epitaxial layer 107 is parallel to and opposite to the first surface 104, and is connected to the substrate 106. The second surface 105 is not only a surface of the power switch device 100, but also a surface of the substrate 106. The other surface of the substrate 106 is parallel to and opposite to the second surface 105, and is connected to the epitaxial layer 107.

[0039] In some embodiments, other semiconductor layers are further included between the substrate 106 and the epitaxial layer 107 .

[0040] In one embodiment, the substrate 106 and the epitaxial layer 107 have a first conductivity type, and the doping concentration of the substrate 106 is greater than the doping concentration of the epitaxial layer 107. In one embodiment, the substrate layer 106 and the epitaxial layer 107 are both n-type semiconductor layers, and the substrate 106 of the power switch device 100 can be made of any suitable semiconductor material such as silicon, silicon carbide, germanium, silicon germanium, gallium nitride, gallium arsenide, etc.

[0041] For clarity of illustration, Figure 2 The metal contact structures or polysilicon contact structures corresponding to the regions on the first surface 104 are not shown. A person skilled in the art should understand that, in order for the power switch device 100 to work properly, the regions on the horizontal plane of the power switch device 100 will also be connected to corresponding potentials through conductive contact structures.

[0042] Combination Figure 1 and 2 As shown, the gate structure 101 included in the power switch device 100 is a planar gate structure and is located on the epitaxial layer 107 , that is, located on the first surface 104 .

[0043] The first field plate structure 102 includes a first field plate groove 102a, a first field plate electrode 102b and a first field plate insulating layer 102c. The first field plate groove 102a extends vertically inward from the first surface 104 of the power switch device 100, that is, extends into the epitaxial layer 107. The bottom of the first field plate groove 102a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the first field plate groove 102a, that is, the inside of the groove, is covered by the first field plate insulating layer 102c. The first field plate electrode 102b is located in the first field plate groove 102a, and is isolated from the first field plate groove 102a by the first field plate insulating layer 102c, which is equivalent to being isolated from the epitaxial layer 107. The material of the first field plate electrode 102b can be metal or polysilicon. The material of the first field plate insulating layer 102c can be silicon oxide, silicon nitride, or a combination of the two, etc., and is formed by thermal oxygen growth or deposition. In one embodiment, the first field plate insulating layer 102 c is uniformly wrapped around the first field plate electrode 102 b .

[0044] The second field plate structure 103 includes a second field plate groove 103a, a second field plate electrode 103b and a second field plate insulating layer 103c. The second field plate groove 103a extends vertically inward from the first surface 104 of the power switch device 100, that is, extends into the epitaxial layer 107. The bottom of the second field plate groove 103a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the second field plate groove 103a, that is, the inside of the groove, is covered by the second field plate insulating layer 103c. The second field plate electrode 103b is located in the second field plate groove 103a, and is isolated from the second field plate groove 103a by the second field plate insulating layer 103c, which is equivalent to being isolated from the epitaxial layer 107. The material of the second field plate electrode 103b can be metal or polysilicon. The material of the second field plate insulating layer 103c can be silicon oxide, silicon nitride or a combination of the two, etc., and is formed by thermal oxygen growth or deposition. In one embodiment, the second field plate insulating layer 103 c is uniformly wrapped around the second field plate electrode 103 b .

[0045] In one embodiment, the first field plate insulating layer 102c and the second field plate insulating layer 103c have the same thickness and material, and are manufactured in the same process step.

[0046] exist Figure 2In the embodiment, the power switch device 100 further includes a body region 108 and a source region 109. The body region 108 is located in the epitaxial layer 107, exposed to the first surface 104 of the power switch device 100, and distributed on both sides of the corresponding gate structure 101. One side wall of the body region 108 is located below the corresponding gate structure 101, and the other side wall is connected to the side wall of the adjacent first field plate structure 102 or the second field plate structure 103. The source region 109 is located in the body region 108 and exposed to the first surface 104 of the power switch device 100. One side wall of the source region 109 is located below the corresponding gate structure 101, and the other side wall has a certain distance from the side wall of the adjacent first field plate structure 102 or the second field plate structure 103, that is, it is not connected.

[0047] In one embodiment, the source region 109 has a first conductivity type, and the body region 108 has a second conductivity type. In one embodiment, the source region 109 is an n-type semiconductor, and the body region 108 is a p-type semiconductor. In one embodiment, the doping concentration of the source region 109 is greater than the doping concentration of the body region 108.

[0048] exist Figure 2 In the embodiment, all gate structures 101 are connected to the gate potential G, and all first field plate electrodes 102 b , second field plate electrodes 103 b and source regions 109 are connected to the source potential S.

[0049] like Figure 2 As shown, the first field plate trench 102a has a first depth H1 in a direction perpendicular to the first surface 104 of the power switch device 100, and the second field plate trench 103a has a second depth H2 in a direction perpendicular to the first surface 104 of the power switch device 100. Figure 2 In the embodiment, the first depth H1 is substantially the same as the second depth H2. In an actual power switch device, due to possible errors in the manufacturing process, the first depth H1 may be slightly greater than the second depth H2. In one embodiment, the first depth H1 and the second depth H2 range from 0.8 μm to 1.5 μm.

[0050] The power switch device 100 shown in the embodiment of the present invention has field plate structures of different sizes in the cell region, thereby introducing uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 100 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0051] exist Figure 2In an embodiment, the number ratio of the first field plate structures 102 and the second field plate structures 103 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 102 and the second field plate structures 103 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 102 and the second field plate structures 103 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 102 and the second field plate structures 103 is 2:1, and on a straight line parallel to the length direction of the gate structure 101, two first field plate structures 102 are distributed between every two adjacent second field plate structures 103. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 102 and the second field plate structures 103.

[0052] Figure 3 FIG. 4 is a schematic structural diagram of a partial cell region of a power switch device 300 according to an embodiment of the present invention.

[0053] The power switch device 300 may be or include an insulated gate field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power switch device 300 may also include other power semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor).

[0054] like Figure 3 As shown, the power switch device 300 includes a gate structure 301, a first field plate structure 302 and a second field plate structure 303. The gate structure 301 is a planar gate structure, which is distributed in a strip shape on a horizontal plane, and each gate structure 301 is parallel to each other. The first field plate structure 302 and the second field plate structure 303 are arranged in a strip shape and distributed on both sides of each gate structure 301.

[0055] and Figure 1 Compared with the power switch device 100 shown in FIG. 1 , the shapes of the first field plate structure 302 and the second field plate structure 303 on the horizontal plane are different from the first field plate structure 102 and the second field plate structure 103. Figure 3 As shown, the first field plate structure 302 and the second field plate structure 303 are circular in shape on the horizontal plane. The first field plate structure 302 and the second field plate structure 303 have different diameters on the horizontal plane. Specifically, the diameter of the first field plate structure 302 is greater than the diameter of the second field plate structure 303.

[0056] It should be understood that in other embodiments of the present invention, on the horizontal plane of the power switch device, the first field plate structure and the second field plate structure may also have other shapes, such as a hexagon, a square, etc. Moreover, the first field plate structure and the second field plate structure do not necessarily have to be the same shape, for example, the first field plate structure may be designed as a hexagon, and the second field plate structure may be designed as a circle.

[0057] Figure 4 FIG. 4 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 400 according to an embodiment of the present invention.

[0058] like Figure 4 As shown, the power switch device 400 has a first surface 404 and a second surface 405. The first surface 404 is one of the surfaces of the power switch device 400. The first surface 404 and the second surface 405 are parallel and face opposite directions in a vertical direction. The distance between the first surface 404 and the second surface 405 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 404 and the second surface 405 is called a horizontal plane, and the direction perpendicular to the first surface 404 and the second surface 405 is called a vertical direction.

[0059] like Figure 4 As shown, the power switch device 400 includes a substrate 106 and an epitaxial layer 107 located on the substrate. The first surface 404 is both a surface of the power switch device 400 and a surface of the epitaxial layer 107. The other surface of the epitaxial layer 107 is parallel to and opposite to the first surface 404, and is connected to the substrate 106. The second surface 405 is both a surface of the power switch device 400 and a surface of the substrate 406. The other surface of the substrate 406 is parallel to and opposite to the second surface 405, and is connected to the epitaxial layer 107.

[0060] In some embodiments, other semiconductor layers are further included between the substrate 106 and the epitaxial layer 107 .

[0061] In one embodiment, the substrate 106 and the epitaxial layer 107 have a first conductivity type, and the doping concentration of the substrate 106 is greater than the doping concentration of the epitaxial layer 107. In one embodiment, the substrate layer 106 and the epitaxial layer 107 are both n-type semiconductor layers, and the substrate 106 of the power switch device 100 can be made of any suitable semiconductor material such as silicon, silicon carbide, germanium, silicon germanium, gallium nitride, gallium arsenide, etc.

[0062] For clarity of illustration, Figure 4The metal contact structures or polysilicon contact structures corresponding to the regions on the first surface 404 are not shown. A person skilled in the art should understand that, in order for the power switch device 400 to work properly, the regions on the horizontal plane of the power switch device 400 will also be connected to corresponding potentials through conductive contact structures.

[0063] like Figure 4 As shown, the gate structure 401 included in the power switch device 400 is a planar gate structure and is located on the epitaxial layer 107 , that is, located on the first surface 404 .

[0064] The first field plate structure 402 includes a first field plate groove 402a, a first field plate electrode 402b and a first field plate insulating layer 402c. The first field plate groove 402a extends vertically inward from the first surface 404 of the power switch device 400, that is, extends into the epitaxial layer 107. The bottom of the first field plate groove 402a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the first field plate groove 402a, that is, the inside of the groove, is covered by the first field plate insulating layer 402c. The first field plate electrode 402b is located in the first field plate groove 402a, and is isolated from the first field plate groove 402a by the first field plate insulating layer 402c, which is equivalent to being isolated from the epitaxial layer 107. The material of the first field plate electrode 402b can be metal or polysilicon. The material of the first field plate insulating layer 402c can be silicon oxide, silicon nitride, or a combination of the two, etc., and is formed by thermal oxygen growth or deposition. In one embodiment, the first field plate insulating layer 402 c is uniformly wrapped around the first field plate electrode 402 b .

[0065] The second field plate structure 403 includes a second field plate groove 403a, a second field plate electrode 403b and a second field plate insulating layer 403c. The second field plate groove 403a extends vertically inward from the first surface 404 of the power switch device 400, that is, extends into the epitaxial layer 107. The bottom of the second field plate groove 403a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the second field plate groove 403a, that is, the inside of the groove, is covered by the second field plate insulating layer 403c. The second field plate electrode 403b is located in the second field plate groove 403a, and is isolated from the second field plate groove 403a by the second field plate insulating layer 403c, which is equivalent to being isolated from the epitaxial layer 107. The material of the second field plate electrode 403b can be metal or polysilicon. The material of the second field plate insulating layer 403c can be silicon oxide, silicon nitride, or a combination of the two, etc., formed by thermal oxygen growth or deposition. In one embodiment, the second field plate insulating layer 403 c is uniformly wrapped around the second field plate electrode 403 b .

[0066] In one embodiment, the first field plate insulating layer 402 c and the second field plate insulating layer 403 c have the same thickness and material, and are manufactured in the same process step.

[0067] exist Figure 4 In the embodiment, the power switch device 400 further includes a body region 408 and a source region 409. The body region 408 is located in the epitaxial layer 407, exposed to the first surface 404 of the power switch device 400, and distributed on both sides of the corresponding gate structure 401. One side wall of the body region 408 is located below the corresponding gate structure 401, and the other side wall is connected to the side wall of the adjacent first field plate structure 402 or the second field plate structure 403. The source region 409 is located in the body region 408 and exposed to the first surface 404 of the power switch device 400. One side wall of the source region 409 is located below the corresponding gate structure 401, and the other side wall has a certain distance from the side wall of the adjacent first field plate structure 402 or the second field plate structure 403, that is, it is not connected.

[0068] In one embodiment, the source region 409 has a first conductivity type, and the body region 408 has a second conductivity type. In one embodiment, the source region 409 is an n-type semiconductor, and the body region 408 is a p-type semiconductor. In one embodiment, the doping concentration of the source region 409 is greater than the doping concentration of the body region 408.

[0069] exist Figure 4 In the embodiment, all gate structures 401 are connected to the gate potential G, and all first field plate electrodes 402 b , second field plate electrodes 403 b and source regions 409 are connected to the source potential S.

[0070] exist Figure 4 In the embodiment, the first field plate structure 402 and the second field plate structure 403 have structures of the same shape and size on the horizontal plane. On the horizontal plane, and in a direction perpendicular to the length direction of the gate structure 401, the first field plate structure 402 has a third spacing W3, and the second field plate structure 403 has a fourth spacing W4. The third spacing W3 is substantially the same as the fourth spacing W4.

[0071] like Figure 4 As shown, the first field plate trench 402a has a third depth H3 in a direction perpendicular to the first surface 404 of the power switch device 400, and the second field plate trench 403a has a fourth depth H4 in a direction perpendicular to the first surface 404 of the power switch device 400. Figure 4 In an embodiment, the third depth H3 is greater than the fourth depth H4. In an embodiment, the third depth H3 and the fourth depth H4 have a value range of 1 μm-10 μm. In an embodiment, there is a depth difference H5 between the third depth H3 and the fourth depth H4, and the depth difference H5 is within 10% of the third depth H3.

[0072] The power switch device 400 shown in the embodiment of the present invention has a field plate structure with different depths in the cell region, thereby introducing an uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 400 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0073] exist Figure 4 In an embodiment, the number ratio of the first field plate structures 402 and the second field plate structures 403 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 402 and the second field plate structures 403 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 402 and the second field plate structures 403 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 402 and the second field plate structures 403 is 2:1, and on a straight line parallel to the length direction of the gate structure 401, two first field plate structures 402 are distributed between every two adjacent second field plate structures 403. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 402 and the second field plate structures 403.

[0074] Figure 5 FIG. 5 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 500 according to an embodiment of the present invention.

[0075] like Figure 5 As shown, the power switch device 500 has a first surface 504 and a second surface 505. The first surface 504 is one of the surfaces of the power switch device 500. The first surface 504 and the second surface 505 are parallel and face opposite directions in a vertical direction. The distance between the first surface 504 and the second surface 505 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 504 and the second surface 505 is called a horizontal plane, and the direction perpendicular to the first surface 504 and the second surface 505 is called a vertical direction.

[0076] like Figure 5As shown, the power switch device 500 includes a substrate 106 and an epitaxial layer 107 located on the substrate. The first surface 504 is both a surface of the power switch device 500 and a surface of the epitaxial layer 107. The other surface of the epitaxial layer 107 is parallel to and opposite to the first surface 504, and is connected to the substrate 106. The second surface 505 is both a surface of the power switch device 500 and a surface of the substrate 506. The other surface of the substrate 506 is parallel to and opposite to the second surface 505, and is connected to the epitaxial layer 107.

[0077] In some embodiments, other semiconductor layers are further included between the substrate 106 and the epitaxial layer 107 .

[0078] In one embodiment, the substrate 106 and the epitaxial layer 107 have a first conductivity type, and the doping concentration of the substrate 106 is greater than the doping concentration of the epitaxial layer 107. In one embodiment, the substrate layer 106 and the epitaxial layer 107 are both n-type semiconductor layers, and the substrate 106 of the power switch device 100 can be made of any suitable semiconductor material such as silicon, silicon carbide, germanium, silicon germanium, gallium nitride, gallium arsenide, etc.

[0079] For clarity of illustration, Figure 5 The metal contact structures or polysilicon contact structures corresponding to the regions on the first surface 504 are not shown. A person skilled in the art should understand that, in order for the power switch device 500 to work properly, the regions on the horizontal plane of the power switch device 500 will also be connected to corresponding potentials through conductive contact structures.

[0080] like Figure 5 As shown, the gate structure 501 included in the power switch device 500 is a planar gate structure and is located on the epitaxial layer 107 , that is, located on the first surface 504 .

[0081] The first field plate structure 502 includes a first field plate groove 502a, a first field plate electrode 502b and a first field plate insulating layer 502c. The first field plate groove 502a extends vertically inward from the first surface 504 of the power switch device 500, that is, extends into the epitaxial layer 107. The bottom of the first field plate groove 502a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the first field plate groove 502a, that is, the inside of the groove, is covered by the first field plate insulating layer 502c. The first field plate electrode 502b is located in the first field plate groove 502a, and is isolated from the first field plate groove 502a by the first field plate insulating layer 502c, which is equivalent to being isolated from the epitaxial layer 107. The material of the first field plate electrode 502b can be metal or polysilicon. The material of the first field plate insulating layer 502c can be silicon oxide, silicon nitride, or a combination of the two, etc., and is formed by thermal oxygen growth or deposition. In one embodiment, the first field plate insulating layer 502 c is uniformly wrapped around the first field plate electrode 502 b .

[0082] The second field plate structure 503 includes a second field plate groove 503a, a second field plate electrode 503b and a second field plate insulating layer 503c. The second field plate groove 503a extends vertically inward from the first surface 504 of the power switch device 500, that is, extends into the epitaxial layer 107. The bottom of the second field plate groove 503a is located in the epitaxial layer 107 and does not reach the substrate layer 106. The inner surface of the second field plate groove 503a, that is, the inside of the groove, is covered by the second field plate insulating layer 503c. The second field plate electrode 503b is located in the second field plate groove 503a, and is isolated from the second field plate groove 503a by the second field plate insulating layer 503c, which is equivalent to being isolated from the epitaxial layer 107. The material of the second field plate electrode 503b can be metal or polysilicon. The material of the second field plate insulating layer 503c can be silicon oxide, silicon nitride or a combination of the two, etc., formed by thermal oxygen growth or deposition. In one embodiment, the second field plate insulating layer 503 c is uniformly wrapped around the second field plate electrode 503 b .

[0083] In one embodiment, the first field plate insulating layer 502c and the second field plate insulating layer 503c have the same thickness and material, and are manufactured in the same process step.

[0084] exist Figure 5In the embodiment, the power switch device 500 further includes a body region 408 and a source region 509. The body region 508 is located in the epitaxial layer 507, exposed to the first surface 504 of the power switch device 500, and distributed on both sides of the corresponding gate structure 501. One side wall of the body region 508 is located below the corresponding gate structure 501, and the other side wall is connected to the side wall of the adjacent first field plate structure 502 or the second field plate structure 503. The source region 509 is located in the body region 508 and exposed to the first surface 504 of the power switch device 500. One side wall of the source region 509 is located below the corresponding gate structure 501, and the other side wall has a certain distance from the side wall of the adjacent first field plate structure 502 or the second field plate structure 503, that is, it is not connected.

[0085] In one embodiment, the source region 509 has a first conductivity type, and the body region 508 has a second conductivity type. In one embodiment, the source region 509 is an n-type semiconductor, and the body region 508 is a p-type semiconductor. In one embodiment, the doping concentration of the source region 509 is greater than the doping concentration of the body region 508.

[0086] exist Figure 5 In the embodiment, all gate structures 501 are connected to the gate potential G, and all first field plate electrodes 502 b , second field plate electrodes 503 b and source regions 509 are connected to the source potential S.

[0087] exist Figure 5 In the embodiment, on a horizontal plane and in a direction perpendicular to the length direction of the gate structure 501, the first field plate structure 502 has a fifth spacing W5, and the second field plate structure 503 has a sixth spacing W6. Figure 5 In an embodiment, the fifth spacing W5 is greater than the sixth spacing W6. In some embodiments, the sixth spacing W6 is between 80% and 100% of the fifth spacing W5. In one embodiment, the sixth spacing W6 is 95% of the fifth spacing W5.

[0088] like Figure 5 As shown, the first field plate trench 502a has a sixth depth H6 in a direction perpendicular to the first surface 504 of the power switch device 500, and the second field plate trench 503a has a seventh depth H7 in a direction perpendicular to the first surface 504 of the power switch device 500. Figure 5 In an embodiment, the seventh depth H7 is greater than the sixth depth H6. In an embodiment, the sixth depth H6 and the seventh depth H7 have a value range of 1 μm-10 μm. In an embodiment, there is a depth difference H8 between the sixth depth H6 and the seventh depth H7, and the depth difference H8 is within 10% of the sixth depth H6.

[0089] The power switch device 500 shown in the embodiment of the present invention has a field plate structure with different depths and spacings in the cell region, thereby introducing an uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 500 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0090] exist Figure 5 In the embodiment, the first field plate grooves 502a have a wider spacing on the horizontal plane and a deeper depth in the direction perpendicular to the horizontal plane. In other embodiments, the first field plate grooves may also be arranged to have a wider spacing on the horizontal plane than the second field plate grooves, and a shallower depth in the direction perpendicular to the horizontal plane than the second field plate grooves.

[0091] exist Figure 5 In an embodiment, the number ratio of the first field plate structures 502 and the second field plate structures 503 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 502 and the second field plate structures 503 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 502 and the second field plate structures 503 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 502 and the second field plate structures 503 is 2:1, and on a straight line parallel to the length direction of the gate structure 501, two first field plate structures 502 are distributed between every two adjacent second field plate structures 503. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 502 and the second field plate structures 503.

[0092] Figure 6 FIG. 4 is a schematic structural diagram of a partial cell region of a power switch device 600 according to an embodiment of the present invention.

[0093] The power switch device 600 may be or include an insulated gate field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power switch device 600 may also include other power semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor).

[0094] like Figure 6As shown, the power switch device 600 includes a gate structure 601, a first field plate structure 602 and a second field plate structure 603. The gate structure 601 is a trench gate structure, distributed in strips, and each gate structure 601 is parallel to each other. The first field plate structure 602 and the second field plate structure 603 are arranged in strips and distributed on both sides of each gate structure 601.

[0095] It should be understood that Figure 6 FIG. 1 shows one surface of a power switch device 600. On this surface, in addition to the gate structure 601, the first field plate structure 602 and the second field plate structure 603, there are other regions, such as a source region and / or a body region. For the sake of clarity of the example, other regions except the gate structure 601, the first field plate structure 602 and the second field plate structure 603 are not shown. Figure 6 Shown in.

[0096] exist Figure 6 In the embodiment, the gate structure 601 is in a strip shape, the first field plate structure 602 and the second field plate structure 603 are distributed on a straight line parallel to the length direction of the gate structure 601, and the first field plate structure 602 and the second field plate structure 603 are distributed at intervals. That is, in a direction parallel to the length direction of the gate structure 601, a second field plate structure 603 is distributed between every two adjacent first field plate structures 602, and a first field plate structure 602 is distributed between every two adjacent second field plate structures 603.

[0097] exist Figure 6 In the embodiment, the first field plate structure 602 and the second field plate structure 603 both have an octagonal shape in a plane. Two opposite and parallel sides of the octagonal first field plate structure 602 are parallel to the length direction of the gate structure 601, and the distance between the two sides is defined as a seventh spacing W7. Two opposite and parallel sides of the octagonal second field plate structure 603 are parallel to the length direction of the gate structure 601, and the distance between the two sides is defined as an eighth spacing W8. The seventh spacing W7 and the eighth spacing W8 are perpendicular to the length direction of the gate structure 601 in a horizontal plane. Figure 6 In an embodiment, the seventh spacing W7 is greater than the eighth spacing W8. In some embodiments, the eighth spacing W8 is between 80% and 100% of the seventh spacing W7. In one embodiment, the eighth spacing W8 is 95% of the seventh spacing W7.

[0098] In some embodiments, the seventh pitch W7 is in a range of 0.3-2 μm, and the eighth pitch W8 is smaller than the seventh pitch W7 and is between 80% and 100% of the seventh pitch W7 .

[0099] exist Figure 6In the embodiment, the first field plate structure 602 and the second field plate structure 603 are in an octagonal shape. In some embodiments, in order to make the electric field uniformly distributed, each corner of the octagon is passivated to be in an arc shape.

[0100] Figure 7 According to an embodiment of the present invention, Figure 6 The schematic diagram of the cross-sectional structure of a partial cell region of the power switch device 600 along line BB is shown.

[0101] like Figure 7 As shown, the power switch device 600 has a first surface 604 and a second surface 605. The first surface 604 is Figure 6 The plane of the power switch device 600 shown in FIG. The first surface 604 and the second surface 605 are parallel and face opposite directions in a vertical direction. The distance between the first surface 604 and the second surface 605 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 604 and the second surface 605 is called a horizontal plane, and the direction perpendicular to the first surface 604 and the second surface 605 is called a vertical direction.

[0102] like Figure 7 As shown, the power switch device 600 includes a substrate 606 and an epitaxial layer 607. The epitaxial layer 607 is located on the substrate 606. The first surface 604 is not only a surface of the power switch device 600, but also a surface of the epitaxial layer 607. The other surface of the epitaxial layer 607 is parallel to and opposite to the first surface 604, and is connected to the substrate 606. The second surface 605 is not only a surface of the power switch device 600, but also a surface of the substrate 606. The other surface of the substrate 606 is parallel to and opposite to the second surface 605, and is connected to the epitaxial layer 607.

[0103] In some embodiments, other semiconductor layers are further included between the substrate 606 and the epitaxial layer 607 .

[0104] In one embodiment, the substrate 606 and the epitaxial layer 607 have a first conductivity type, and the doping concentration of the substrate 606 is greater than the doping concentration of the epitaxial layer 607. In one embodiment, the substrate layer 606 and the epitaxial layer 607 are both n-type semiconductor layers, and the substrate 606 of the power switch device 600 can be made of any suitable semiconductor material such as silicon, silicon carbide, germanium, silicon germanium, gallium nitride, gallium arsenide, etc.

[0105] For clarity of illustration, Figure 7The metal contact structures or polysilicon contact structures corresponding to the regions on the first surface 604 are not shown. A person skilled in the art should understand that, in order for the power switch device 600 to work properly, the regions on the horizontal plane of the power switch device 600 will also be connected to corresponding potentials through conductive contact structures.

[0106] Combination Figure 6 and 7 As shown, the gate structure 601 included in the power switch device 600 is a trench gate structure. The gate structure 601 includes a gate plate trench 601a, a gate electrode 601b and a gate insulating layer 601c. The gate trench 601a extends inward from the first surface 604 of the power switch device 600, that is, extends into the epitaxial layer 607. The bottom of the gate trench 601a is located in the epitaxial layer 607 and does not reach the substrate layer 606. The inner surface of the gate trench 601a, that is, the inside of the trench, is covered by the gate insulating layer. The gate electrode 601b is located in the gate trench 601a, and is isolated from the gate trench 601a by the gate insulating layer 601c, which is equivalent to being isolated from the epitaxial layer 607. The material of the gate electrode 601b can be metal or polysilicon. The material of the gate insulating layer 601c can be silicon oxide, silicon nitride or a combination of the two, etc., formed by thermal oxygen growth or deposition. In one embodiment, the gate insulating layer 601c is uniformly wrapped around the gate electrode 601b.

[0107] The first field plate structure 602 includes a first field plate trench 602a, a first field plate electrode 602b, and a first field plate insulating layer 602c. Figure 2 The structure and material of the first field plate structure 102 of the embodiment are similar, and for the sake of clarity, they will not be described in detail here.

[0108] The second field plate structure 603 includes a second field plate trench 603a, a second field plate electrode 603b, and a second field plate insulating layer 603c. Figure 2 The structure and material of the second field plate structure 602 of the embodiment are similar, and for the sake of clarity, the description is not repeated here.

[0109] exist Figure 7In the embodiment, the power switch device 600 further includes a body region 608 and a source region 609. The body region 608 is located in the epitaxial layer 607 and is distributed on both sides of the corresponding gate structure 601. One side wall of the body region 608 is connected to the side wall of the adjacent gate structure 601, and the other side wall is connected to the side wall of the adjacent first field plate structure 602 or the second field plate structure 603. The source region 609 is located in the body region 608 and is exposed to the first surface 604 of the power switch device 600. One side wall of the source region 609 is connected to the side wall of the adjacent gate structure 101, and the other side wall is connected to the side wall of the adjacent first field plate structure 602 or the second field plate structure 603.

[0110] In one embodiment, the source region 609 has a first conductivity type, and the body region 608 has a second conductivity type. In one embodiment, the source region 609 is an n-type semiconductor, and the body region 608 is a p-type semiconductor. In one embodiment, the doping concentration of the source region 609 is greater than the doping concentration of the body region 608.

[0111] exist Figure 7 In the embodiment, all gate electrodes 601 b are connected to the gate potential G, and all first field plate electrodes 602 b , second field plate electrodes 603 b and source regions 609 are connected to the source potential S.

[0112] like Figure 7 As shown, the first field plate trench 602a has a ninth depth H9 in a direction perpendicular to the first surface 604 of the power switch device 600, and the second field plate trench 603a has a tenth depth H10 in a direction perpendicular to the first surface 604 of the power switch device 600. Figure 7 In the embodiment, the ninth depth H9 is substantially the same as the tenth depth H10. In an actual power switch device, due to possible errors in the manufacturing process, the ninth depth H9 may be slightly greater than the tenth depth H10. In an embodiment, the ninth depth H9 and the tenth depth H10 have a value range of 0.8 μm-1.5 μm.

[0113] The power switch device 600 shown in the embodiment of the present invention has field plate structures of different sizes in the cell region, thereby introducing uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 600 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0114] exist Figure 6In an embodiment, the number ratio of the first field plate structures 602 and the second field plate structures 603 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 602 and the second field plate structures 603 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 602 and the second field plate structures 603 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 602 and the second field plate structures 603 is 2:1, and on a straight line parallel to the length direction of the gate structure 601, two first field plate structures 602 are distributed between every two adjacent second field plate structures 603. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 602 and the second field plate structures 603.

[0115] Figure 8 FIG. 8 is a schematic structural diagram of a partial cell region of a power switch device 800 according to an embodiment of the present invention.

[0116] The power switch device 800 may be or include an insulated gate field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power switch device 800 may also include other power semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor).

[0117] like Figure 8 As shown, the power switch device 800 includes a gate structure 801, a first field plate structure 802 and a second field plate structure 803. The gate structure 801 is a trench gate structure, which is distributed in a strip shape on a horizontal plane, and each gate structure 801 is parallel to each other. The first field plate structure 802 and the second field plate structure 803 are arranged in a strip shape and distributed on both sides of each gate structure 801.

[0118] and Figure 6 Compared with the power switch device 600 shown in FIG. 1 , the shapes of the first field plate structure 802 and the second field plate structure 803 on the horizontal plane are different from the first field plate structure 602 and the second field plate structure 603. Figure 8 As shown, the first field plate structure 802 and the second field plate structure 803 are circular in shape on the horizontal plane, and the first field plate structure 802 and the second field plate structure 803 have different diameters on the horizontal plane. Specifically, the diameter of the first field plate structure 802 is greater than the diameter of the second field plate structure 803.

[0119] It should be understood that in other embodiments of the present invention, on the horizontal plane of the power switch device, the first field plate structure and the second field plate structure may also have other shapes, such as a hexagon, a square, etc. Moreover, the first field plate structure and the second field plate structure do not necessarily have to be the same shape, for example, the first field plate structure may be designed as a hexagon, and the second field plate structure may be designed as a circle.

[0120] Fig. 9 FIG. 1 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 900 according to an embodiment of the present invention.

[0121] like Fig. 9 As shown, the power switch device 900 has a first surface 904 and a second surface 905. The first surface 904 is one of the surfaces of the power switch device 900. The first surface 904 and the second surface 905 are parallel and face opposite directions in a vertical direction. The distance between the first surface 904 and the second surface 905 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 904 and the second surface 905 is called a horizontal plane, and the direction perpendicular to the first surface 904 and the second surface 905 is called a vertical direction.

[0122] like Fig. 9 As shown, the power switch device 900 includes a gate structure 901, a first field plate structure 902 and a second field plate structure 903. The gate structure 901 is a trench gate structure, including a gate trench 901a, a gate electrode 901b and a gate insulating layer 901c. Figure 7 The gate structure 601 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0123] The first field plate structure 902 includes a first field plate trench 902a, a first field plate electrode 902b, and a first field plate insulating layer 902c. Figure 7 The first field plate structure 602 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0124] The second field plate structure 903 includes a second field plate trench 903a, a second field plate electrode 903b, and a second field plate insulating layer 903c. Figure 7 The second field plate structure 603 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0125] exist Fig. 9 In the embodiment, the power switch device 900 further includes a body region 908 and a source region 909. The body region 908 and the source region 909 are respectively Figure 7The structure, position and material of the body region 608 and the source region 609 in the embodiment are similar, and for the sake of clarity, they will not be described in detail here.

[0126] exist Fig. 9 In the embodiment, the first field plate structure 902 and the second field plate structure 903 have structures of the same shape and size on the horizontal plane. On the horizontal plane, and in a direction perpendicular to the length direction of the gate structure 901, the first field plate structure 902 has a ninth spacing W9, and the second field plate structure 903 has a tenth spacing W10. The ninth spacing W9 is substantially the same as the tenth spacing W10.

[0127] like Fig. 9 As shown, the first field plate trench 902a has an eleventh depth H11 in a direction perpendicular to the first surface 904 of the power switch device 900, and the second field plate trench 903a has a twelfth depth H12 in a direction perpendicular to the first surface 904 of the power switch device 900. Fig. 9 In an embodiment, the eleventh depth H11 is greater than the twelfth depth H12. In an embodiment, the eleventh depth H11 and the twelfth depth H12 have a value range of 1 μm-10 μm. In an embodiment, there is a depth difference H13 between the eleventh depth H11 and the twelfth depth H12, and the depth difference H13 is within 10% of the eleventh depth H11.

[0128] The power switch device 900 shown in the embodiment of the present invention has a field plate structure with different depths in the cell region, thereby introducing an uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 900 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0129] exist Fig. 9 In an embodiment, the number ratio of the first field plate structures 902 and the second field plate structures 903 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 902 and the second field plate structures 903 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 902 and the second field plate structures 903 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 902 and the second field plate structures 903 is 2:1, and on a straight line parallel to the length direction of the gate structure 901, two first field plate structures 902 are distributed between every two adjacent second field plate structures 903. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 902 and the second field plate structures 903.

[0130] Fig.10FIG. 1 is a schematic cross-sectional structure diagram of a partial cell region of a power switch device 1000 according to an embodiment of the present invention.

[0131] like Fig.10 As shown, the power switch device 1000 has a first surface 1004 and a second surface 1005. The first surface 1004 is one of the surfaces of the power switch device 1000. The first surface 1004 and the second surface 1005 are parallel and face opposite directions in a vertical direction. The distance between the first surface 1004 and the second surface 1005 may be between tens of microns and hundreds of microns according to design requirements. In the embodiment of the present invention, the plane parallel to the first surface 1004 and the second surface 1005 is called a horizontal plane, and the direction perpendicular to the first surface 1004 and the second surface 1005 is called a vertical direction.

[0132] like Fig.10 As shown, the power switch device 1000 includes a gate structure 1001, a first field plate structure 1002 and a second field plate structure 1003. The gate structure 1001 is a trench gate structure, including a gate trench 1001a, a gate electrode 1001b and a gate insulating layer 1001c. Figure 7 The gate structure 601 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0133] The first field plate structure 1002 includes a first field plate trench 1002a, a first field plate electrode 1002b, and a first field plate insulating layer 1002c. Figure 7 The first field plate structure 602 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0134] The second field plate structure 1003 includes a second field plate trench 1003a, a second field plate electrode 1003b, and a second field plate insulating layer 1003c. Figure 7 The second field plate structure 603 of the embodiment is similar, and for the sake of clarity, it will not be described in detail here.

[0135] exist Fig.10 In the embodiment, the power switch device 1000 further includes a body region 1008 and a source region 1009. The body region 1008 and the source region 1009 are respectively Figure 7 The structure, position and material of the body region 608 and the source region 609 in the embodiment are similar, and for the sake of clarity, they will not be described in detail here.

[0136] exist Fig.10 In the embodiment, on a horizontal plane and in a direction perpendicular to the length direction of the gate structure 1001, the first field plate structure 1002 has an eleventh spacing W11, and the second field plate structure 1003 has a twelfth spacing W12. Fig.10 In an embodiment, the eleventh pitch W11 is greater than the twelfth pitch W12. In some embodiments, the twelfth pitch W12 is between 80% and 100% of the eleventh pitch W11. In one embodiment, the twelfth pitch W12 is 95% of the eleventh pitch W11.

[0137] like Fig.10 As shown, the first field plate trench 1002a has a fourteenth depth H14 in a direction perpendicular to the first surface 1004 of the power switch device 1000, and the second field plate trench 1003a has a fifteenth depth H15 in a direction perpendicular to the first surface 1004 of the power switch device 1000. Fig.10 In an embodiment, the fifteenth depth H15 is greater than the fourteenth depth H14. In an embodiment, the fourteenth depth H14 and the fifteenth depth H15 have a value range of 1 μm-10 μm. In an embodiment, there is a depth difference H16 between the fourteenth depth H14 and the fifteenth depth H15, and the depth difference H16 is within 10% of the fourteenth depth H14.

[0138] The power switch device 1000 shown in the embodiment of the present invention has a field plate structure with different depths and spacings in the cell region, thereby introducing an uneven electric field distribution in the cell region, reducing the breakdown voltage of the cell region, so that when the power switch device 1000 is broken down, the cell region is broken down before the terminal region. Because the area of ​​the cell region is larger than the area of ​​the terminal region, when the breakdown occurs in the cell region rather than the terminal region, the device's ability to withstand UIS is improved.

[0139] exist Fig.10 In the embodiment, the first field plate grooves 1002a have a wider spacing on the horizontal plane and a deeper depth in the direction perpendicular to the horizontal plane. In other embodiments, the first field plate grooves may also be arranged to have a wider spacing on the horizontal plane than the second field plate grooves, and a shallower depth in the direction perpendicular to the horizontal plane than the second field plate grooves.

[0140] exist Fig.10In an embodiment, the number ratio of the first field plate structures 1002 and the second field plate structures 1003 of different sizes is 1:1, and they are distributed at intervals on the horizontal plane. In other embodiments, the first field plate structures 1002 and the second field plate structures 1003 may also be distributed in other number ratios, for example, the number ratio of the first field plate structures 1002 and the second field plate structures 1003 may be N:1, and N may be any natural number greater than or equal to 1. In one embodiment, the number ratio of the first field plate structures 1002 and the second field plate structures 1003 is 2:1, and on a straight line parallel to the length direction of the gate structure 1001, two first field plate structures 1002 are distributed between every two adjacent second field plate structures 1003. The embodiment of the present invention does not limit the number ratio and arrangement of the first field plate structures 1002 and the second field plate structures 1003.

[0141] In some of the aforementioned embodiments, the first field plate structure and the second field plate structure are arranged to have different spacings in a direction perpendicular to the length direction of the gate structure on a horizontal plane to illustrate the principle of the present invention. It should be understood that the principle of the present invention is not limited thereto. In some embodiments, the first field plate structure and the second field plate structure may also be arranged to have different spacings in a direction parallel to the length direction of the gate structure on a horizontal plane. In some embodiments, the first field plate structure and the second field plate structure may also be arranged to have different spacings in any parallel direction on a horizontal plane.

[0142] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A power switching device, comprising: substrate layer; an epitaxial layer, located on the substrate layer; Gate structure; A first field plate structure, comprising a first field plate groove, a first field plate electrode and a first field plate insulating layer, wherein the first field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the first field plate electrode is located in the first field plate groove, and the first field plate insulating layer covers the inner surface of the first field plate groove to isolate the first field plate electrode from the first field plate groove; as well as A second field plate structure, comprising a second field plate groove, a second field plate electrode and a second field plate insulating layer, wherein the second field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the second field plate electrode is located in the second field plate groove, and the second field plate insulating layer covers the inner surface of the second field plate groove to isolate the second field plate electrode from the second field plate groove; In a plane parallel to the first surface of the power switch device, the first field plate structures have different spacings from the first field plate structures in the same direction.

2. The power switch device according to claim 1, wherein: The gate structure is in a strip shape on a plane parallel to the first surface of the power switch device; and The first field plate structure and the second field plate structure are arranged in strips and distributed on both sides of each gate structure.

3. The power switch device according to claim 2, wherein: The gate structure is a planar gate structure, and the gate structure is located on the epitaxial layer.

4. The power switch device according to claim 3, further comprising: a body region located in the epitaxial layer, exposed to the first surface of the power switch device, and distributed on both sides of each gate structure, wherein one side wall of the body region is located below the gate structure, and the other side wall is connected to the side wall of the adjacent first field plate structure or the second field plate structure; and The source region is located in the body region and exposed to the first surface of the power switching device, wherein one side wall of the source region is located below the gate structure, and the other side wall is at a certain distance from the side wall of the adjacent first field plate structure or the second field plate structure.

5. The power switch device according to claim 2, wherein: The gate structure is a trench gate structure, which includes a gate trench, a gate electrode and a gate insulating layer. The gate trench extends vertically from the first surface of the power switching device to the inside of the epitaxial layer. The gate electrode is located in the gate trench. The gate insulating layer covers the inner surface of the gate trench to isolate the gate electrode from the gate trench.

6. The power switch device according to claim 5, further comprising: a body region located in the epitaxial layer and distributed on both sides of each gate structure, wherein one side wall of the body region is connected to a side wall of an adjacent gate structure, and the other side wall is connected to a side wall of an adjacent first field plate structure or a second field plate structure; and The source region is located in the body region and exposed to the first surface of the power switch device, wherein one side wall of the source region is connected to the side wall of the adjacent gate structure, and the other side wall is connected to the side wall of the adjacent first field plate structure or the second field plate structure. 7 . The power switch device of claim 1 , wherein the first field plate structure and the second field plate structure are spaced apart and distributed along a length direction of the gate structure.

8. The power switching device as described in claim 1, wherein the first field plate structure and the second field plate structure are distributed on a straight line parallel to the length direction of the gate structure, and a second field plate structure is distributed for every N isolated first field plate structures, wherein N is a natural number greater than 1. 9 . The power switch device of claim 1 , wherein on a plane parallel to the first surface of the power switch device, a maximum spacing of the second field plate structure is more than 80% of a maximum spacing of the first field plate structure. 10 . The power switch device of claim 1 , wherein on a plane parallel to the first surface of the power switch device, a maximum pitch of the second field plate structure is 95% of a maximum pitch of the first field plate structure.

11. The power switch device according to claim 1, wherein: The first field plate trench has a first depth in a direction perpendicular to the first surface of the power switch device, the second field plate trench has a second depth in a direction perpendicular to the first surface of the power switch device, and the first depth is substantially the same as the second depth.

12. The power switch device according to claim 1, wherein: The first field plate trench has a first depth in a direction perpendicular to a first surface of the power switch device, the second field plate trench has a second depth in a direction perpendicular to the first surface of the power switch device, and the first depth is greater than the second depth.

13. The power switch device according to claim 1, wherein: The first field plate trench has a first depth in a direction perpendicular to the first surface of the power switch device, the second field plate trench has a second depth in a direction perpendicular to the first surface of the power switch device, and the second depth is between 80% and 100% of the first depth. 14 . The power switch device of claim 1 , wherein on a plane parallel to a first surface of the power switch device, the first field plate structure and the second field plate structure have different spacings in a direction perpendicular to a length direction of the gate structure. 15 . The power switch device of claim 1 , wherein on a plane parallel to a first surface of the power switch device, the first field plate structure and the second field plate structure have different spacings in a direction parallel to a length direction of a gate structure.

16. A power switching device, comprising: substrate layer; an epitaxial layer, located on the substrate layer; Gate structure; A first field plate structure, comprising a first field plate groove, a first field plate electrode and a first field plate insulating layer, wherein the first field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the first field plate electrode is located in the first field plate groove, and the first field plate insulating layer covers the inner surface of the first field plate groove to isolate the first field plate electrode from the first field plate groove; as well as A second field plate structure, comprising a second field plate groove, a second field plate electrode and a second field plate insulating layer, wherein the second field plate groove vertically extends from the first surface of the power switch device to the inside of the epitaxial layer, the second field plate electrode is located in the second field plate groove, and the second field plate insulating layer covers the inner surface of the second field plate groove to isolate the second field plate electrode from the second field plate groove; In a direction perpendicular to the first surface of the power switch device, the first field plate trench has a first depth, the second field plate trench has a second depth, and the first depth is greater than the second depth.

17. The power switch device according to claim 16, wherein: The gate structure is in a strip shape on a plane parallel to the first surface of the power switch device; and The first field plate structure and the second field plate structure are arranged in strips and distributed on both sides of each gate structure.

18. The power switch device according to claim 17, wherein: The gate structure is a planar gate structure, and the gate structure is located on the epitaxial layer.

19. The power switch device according to claim 18, further comprising: a body region located in the epitaxial layer, exposed to the first surface of the power switch device, and distributed on both sides of each gate structure, wherein one side wall of the body region is located below the gate structure, and the other side wall is connected to the side wall of the adjacent first field plate structure or the second field plate structure; and The source region is located in the body region and exposed to the first surface of the power switching device, wherein one side wall of the source region is located below the gate structure, and the other side wall is at a certain distance from the side wall of the adjacent first field plate structure or the second field plate structure.

20. The power switch device of claim 17, wherein: The gate structure is a trench gate structure, which includes a gate trench, a gate electrode and a gate insulating layer. The gate trench extends vertically from the first surface of the power switching device to the inside of the epitaxial layer. The gate electrode is located in the gate trench. The gate insulating layer covers the inner surface of the gate trench to isolate the gate electrode from the gate trench.

21. The power switch device according to claim 20, further comprising: a body region located in the epitaxial layer and distributed on both sides of each gate structure, wherein one side wall of the body region is connected to a side wall of an adjacent gate structure, and the other side wall is connected to a side wall of an adjacent first field plate structure or a second field plate structure; and The source region is located in the body region and exposed to the first surface of the power switch device, wherein one side wall of the source region is connected to the side wall of the adjacent gate structure, and the other side wall is connected to the side wall of the adjacent first field plate structure or the second field plate structure. 22 . The power switch device of claim 16 , wherein the first field plate structure and the second field plate structure are spaced apart from each other along a length direction of the gate structure.

23. The power switching device as described in claim 16, wherein the first field plate structure and the second field plate structure are distributed on a straight line parallel to the length direction of the gate structure, and a first field plate structure is distributed between every two adjacent second field plate structures, wherein N is a natural number greater than 1. 24 . The power switch device of claim 16 , wherein in a plane parallel to the first surface of the power switch device, in one direction, a pitch of the second field plate structure is more than 80% of a pitch of the first field plate structure.

25. The power switch device of claim 16, wherein: The second depth is between 80% and 100% of the first depth.

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