Preparation method of heterojunction solar cell and solar cell

Abstract

The invention provides a preparation method of a heterojunction solar cell and the solar cell, and relates to the technical field of solar cells. The preparation method of the solar cell comprises the steps of preparing at least one first passivation layer, at least one n-type doped layer and at least one first transparent conductive layer on one side of a silicon substrate, preparing at least one second passivation layer, at least one p-type doped layer and at least one second transparent conductive layer on the other side of the silicon substrate, and preparing at least one second transparent conductive layer on the other side of the silicon substrate. At least one of the first transparent conductive layer and the second transparent conductive layer is formed by cadmium oxide, the cadmium oxide is deposited through a plasma evaporation deposition method, the deposition of the cadmium oxide through plasma evaporation does not need high temperature, elements are ionized more sufficiently, the mobility of the prepared thin film is higher, and the conversion efficiency of the cell is high.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Heterojunction cells are a new hot topic in the photovoltaic field, with many advantages such as high open-circuit voltage, high conversion efficiency, and low temperature coefficient.

[0003] The current preparation method for heterojunction cells can be described as follows: the silicon wafer is textured to form a pyramid-shaped texture surface, the cleaning process removes surface impurities, the plasma enhanced vapor chemical deposition process (PECVD) deposits amorphous silicon films on the upper and lower surfaces of the silicon wafer respectively, and magnetron sputtering (PVD) deposits a 70-90nm first transparent conductive layer (TCO) and a second transparent conductive layer on the upper and lower surfaces of the silicon wafer. After the transparent conductive film is deposited, the battery is screen-printed or copper-plated to prepare metal electrodes.

[0004] At present, the first transparent conductive layer and the second transparent conductive layer of the commonly used heterojunction battery are made of indium oxide-based materials (referred to as ITO or VTTO). The method for preparing transparent conductive materials is magnetron sputtering. The mobility of the prepared ITO material is 20-80cm 2 / V·s. Since indium in indium-based materials is a rare metal, its reserves are limited. In addition, in order to reduce battery costs, a few heterojunction batteries also use zinc oxide-based materials, such as zinc oxide doped with aluminum (AZO) or tin oxide-based materials, such as tantalum doped with tin oxide (TTO). However, the performance of zinc oxide and tin oxide-based TCO materials is biased, and the mobility of the prepared thin film is low, which is difficult to exceed 30cm 2 / V·s, which seriously affects the conversion efficiency of the battery.

[0005] Cadmium oxide semiconductor materials (CdO) have excellent photoelectric properties and good chemical stability in air, but are unstable in acidic or alkaline solutions. Common preparation methods (such as radio frequency magnetron sputtering, spray pyrolysis, metal chemical vapor deposition (MOCVD), sol-gel method and thermal evaporation method) can be used to prepare CdO films. These films have broad application prospects in optoelectronic devices, transparent conductive films and gas sensors.

[0006] However, the properties of CdO-based materials prepared by conventional preparation methods are not good enough. Moreover, after preparing CdO, high-temperature annealing is required to improve the performance of CdO to a better level. The entire process of heterojunction batteries is a low-temperature process, and the high-temperature annealing process is not very compatible with the low-temperature process of heterojunction batteries. Therefore, cadmium oxide materials prepared by conventional methods are difficult to apply to heterojunction batteries. Summary of the invention

[0007] An object of the first aspect of the present invention is to provide a method for preparing a solar cell, so as to solve the problem of low efficiency of the solar cell prepared in the prior art.

[0008] The second aspect of the present invention aims to provide a solar cell prepared by the above-mentioned method for preparing a solar cell.

[0009] In particular, the present invention also provides a method for preparing a heterojunction solar cell, the method comprising:

[0010] Providing a silicon substrate;

[0011] Depositing at least one first passivation layer and at least one n-type doped layer on the front surface of the silicon substrate, and depositing at least one second passivation layer and at least one p-type doped layer on the back surface of the silicon substrate;

[0012] Depositing at least one first transparent conductive layer on the n-type doped layer, and depositing at least one second transparent conductive layer on the p-type doped layer; wherein at least one of the first transparent conductive layer and the second transparent conductive layer is a cadmium oxide transparent conductive layer, and the cadmium oxide transparent conductive layer is deposited by plasma evaporation deposition;

[0013] A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

[0014] Optionally, the material of the cadmium oxide transparent conductive layer is doped cadmium oxide, and the doped elements in the doped cadmium oxide are selected from: one or more of yttrium, ytterbium, indium, lanthanum, beryllium, samarium, manganese, magnesium, gallium, strontium, bromine, iron, copper, zinc, molybdenum, praseodymium, tin, aluminum, chromium, gadolinium, iron and potassium; and the doped elements are doped into the cadmium oxide in the form of oxides;

[0015] Optionally, the mass proportion of the oxide in the cadmium oxide material is 0.1% to 20%;

[0016] Optionally, the band gap of the oxide is 2.5 eV to 10 eV.

[0017] Optionally, the step of preparing the cadmium oxide transparent conductive layer by plasma evaporation deposition method comprises:

[0018] Placing cadmium oxide or doped cadmium oxide material in a crucible in a plasma evaporation deposition device;

[0019] Introducing argon and oxygen into the plasma evaporation deposition device, wherein the volume ratio of oxygen to argon is 0 to 80%;

[0020] The parameters of the plasma evaporation deposition equipment are adjusted to perform plasma evaporation deposition; wherein the parameters include a pressure of 0.1-2 Pa, a current of 100-250 A, a crucible coil current of 10-100 A, a deflection coil current of 5-50 A, and a plasma gun coil current of 5-80 A.

[0021] Optionally, after introducing argon and oxygen into the plasma evaporation deposition equipment, the method further comprises:

[0022] Hydrogen is introduced into the plasma evaporation deposition equipment, wherein the hydrogen accounts for 0% to 10% of the total gas volume.

[0023] Optionally, before depositing at least one first transparent conductive layer on the n-type doped layer and depositing at least one second transparent conductive layer on the p-type doped layer, the method further comprises:

[0024] A buffer layer is prepared on at least one of the n-type doping layer and the p-type doping layer.

[0025] Optionally, the material of the buffer layer is selected from indium oxide, indium tin oxide or indium oxide doped with one or more transition metals;

[0026] Optionally, the buffer layer has a thickness of 0.5 nm to 70 nm.

[0027] Optionally, after depositing at least one first transparent conductive layer on the n-type doped layer and depositing at least one second transparent conductive layer on the p-type doped layer, the method further comprises:

[0028] A protective layer is formed on at least one of the first transparent conductive layer and the second transparent conductive layer.

[0029] Optionally, the material of the protective layer is selected from indium oxide film, tin oxide film, titanium oxide film, aluminum oxide film or indium tin oxide film;

[0030] Optionally, the protective layer has a thickness of 0.5 nm to 40 nm;

[0031] Optionally, the refractive index of the protective layer is 1.3-2.2.

[0032] Optionally, the indium oxide film, the tin oxide film, the titanium oxide film, and the aluminum oxide film are all formed by atomic layer deposition.

[0033] Optionally, the indium tin oxide thin film is formed by alternately depositing indium oxide thin films and tin oxide thin films.

[0034] Optionally, after forming the protective layer, the method further comprises:

[0035] The conductive layer is cut, and the conductive layer includes a first transparent conductive layer, a second transparent conductive layer, the buffer layer and the protective layer.

[0036] Optionally, the conductive layer is cut by laser film removal, and the laser is irradiated onto the conductive layer in a direction that is at a certain angle to the vertical direction;

[0037] Optionally, the direction of the laser is completely parallel to the edge of the silicon substrate, and an insulating region is formed on the conductive layer close to the side region of the silicon substrate, and the cutting width is 20 to 300 μm.

[0038] Optionally, the carrier used in the process of preparing at least one of the first transparent conductive layer, the second transparent conductive layer and the buffer layer is a maskless carrier; the maskless carrier supports the silicon substrate by means of four-corner supports or suspensions.

[0039] Optionally, the protective layer is patterned by laser etching to form through holes on the protective layer that match the first electrode and the second electrode, so that the first electrode directly contacts the first transparent conductive layer, and the second electrode directly contacts the second transparent conductive layer.

[0040] Optionally, the laser is a short-wavelength laser, and the laser is vertically emitted into the protective layer.

[0041] In particular, the present invention also provides a heterojunction solar cell, which is prepared according to the above-mentioned method for preparing a heterojunction solar cell.

[0042] In the preparation method of the present scheme, at least one first passivation layer, at least one n-type doped layer and at least one first transparent conductive layer are prepared on one side of the silicon substrate, and at least one second passivation layer, at least one p-type doped layer and at least one second transparent conductive layer are prepared on the other side of the silicon substrate. In addition, at least one of the first transparent conductive layer and the second transparent conductive layer is formed of cadmium oxide, and the cadmium oxide is deposited by plasma evaporation deposition. The deposition of cadmium oxide by plasma evaporation does not require high temperature, and the elements are more fully ionized, so the mobility of the prepared thin film is higher and the conversion efficiency of the battery is high.

[0043] In the present scheme, hydrogen can be introduced during the preparation of the cadmium oxide transparent conductive layer. The introduction of hydrogen can break bonds with weaker bond energy, passivate defects of the transparent conductive layer, and improve the crystallization performance and conductivity of the transparent conductive layer.

[0044] In this solution, a buffer layer is formed between the n-type doped layer and the first transparent conductive layer, or between the p-type doped layer and the second transparent conductive layer, or between the n-type doped layer and the first transparent conductive layer and between the p-type doped layer and the second transparent conductive layer. The buffer layer mainly improves the contact problem between the n-type doped layer and the first transparent conductive layer, and / or improves the contact problem between the p-type doped layer and the second transparent conductive layer, reduces the contact resistance between the transparent conductive layer and the doped layer, improves the contact performance between the transparent conductive layer and the doped layer (specific factors affecting efficiency include current, series resistance, open voltage, filling), and thus improves the overall performance of the battery.

[0045] In this solution, a protective layer can be formed on the first transparent conductive layer, or a protective layer can be formed on the second transparent conductive layer, or a protective layer can be formed on both the first transparent conductive layer and the second transparent conductive layer. Due to the existence of the protective layer, the first transparent conductive layer and the second transparent conductive layer are covered by the protective layer, so that the stability of the first transparent conductive layer and the second transparent conductive layer can be improved, and the diffusion of toxicity of the first transparent conductive layer and the second transparent conductive layer can be prevented, thereby improving the stability and environmental friendliness of the entire battery.

[0046] When this solution uses a laser to cut the transparent conductive layer, buffer layer and protective layer, the laser hits the product at a certain angle, which can remove the transparent conductive layer, buffer layer and protective layer on one side and the side of the silicon substrate, but will not remove the transparent conductive layer, buffer layer and protective layer on the other side of the silicon substrate, thereby avoiding a short circuit caused by the connection between the positive and negative poles of the battery and affecting the open circuit voltage, thereby maximizing the battery conversion efficiency.

[0047] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0049] Figure 1 is a schematic flow chart of a method for preparing a solar cell according to a specific embodiment of the present invention;

[0050] Figure 2 according to Figure 1 A schematic structural diagram of a solar cell prepared by the preparation method;

[0051] Figure 3is a schematic flow chart of steps for preparing a cadmium oxide transparent conductive layer by a plasma evaporation deposition method according to a specific embodiment of the present invention;

[0052] Figure 4 is a schematic flow chart of steps for preparing a cadmium oxide transparent conductive layer by a plasma evaporation deposition method according to another specific embodiment of the present invention;

[0053] Figure 5 is a schematic flow chart of a method for preparing a solar cell according to another specific embodiment of the present invention;

[0054] Figure 6 is in accordance with Figure 5 A schematic structural diagram of a solar cell prepared by the preparation method;

[0055] Figure 7 is a schematic flow chart of a method for preparing a solar cell according to another specific embodiment of the present invention;

[0056] Figure 8 is in accordance with Figure 7 A schematic structural diagram of a solar cell prepared by the preparation method;

[0057] Fig. 9 is a schematic flow chart of a method for preparing a solar cell according to another specific embodiment of the present invention;

[0058] Fig.10 is in accordance with Fig. 9 A schematic structural diagram of a solar cell prepared by the preparation method;

[0059] Fig.11 is a schematic structural diagram of a solar cell being film-removed by laser in a preparation method according to the present invention in one embodiment;

[0060] Fig.12 is in accordance with Fig.11 Schematic structure diagram obtained after the solar cell is stripped by the laser at an angle in FIG.

[0061] Fig.13 This is a schematic diagram of the structure of a solar cell before it is cut;

[0062] Fig.14 is a schematic structural diagram of a solar cell being film-removed by laser in a preparation method according to the present invention in another embodiment;

[0063] Fig.15 is in accordance with Fig.14 Schematic structure diagram obtained after the solar cell is stripped by the laser at an angle in FIG.

[0064] Fig.16It is a schematic diagram of the structure of a solar cell in which the protective layer is removed by laser and then the electrode is prepared;

[0065] Fig.17 It is a schematic diagram showing the relationship between the absorptivity of short-wavelength light and wavelength of transparent conductive materials and microcrystalline silicon / microcrystalline silicon;

[0066] Fig.18 It is a schematic diagram showing the relationship between the absorption rate of transparent conductive materials and microcrystalline silicon / microcrystalline silicon to long-wavelength light and wavelength.

[0067] Description of reference numerals:

[0068] Silicon substrate-101; first passivation layer-102; second passivation layer-103; n-type doped layer-104; p-type doped layer-105; first transparent conductive layer-106; second transparent conductive layer-107; first electrode-108; second electrode-109; first buffer layer-1062; second buffer layer-1072; first protective layer-1063; second protective layer-1073; insulating region-120. DETAILED DESCRIPTION

[0069] In the description of this embodiment, it should be understood that the terms "length", "width", "height", "up", "down", "left", "right", "vertical", "horizontal", "bottom", "inside" and "outside" etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0070] As a specific embodiment of the present invention, Figure 1 As shown, this embodiment provides a method for preparing a heterojunction solar cell, and the method for preparing a heterojunction solar cell may include:

[0071] Step S100, providing a silicon substrate 101;

[0072] Step S200, depositing at least one first passivation layer 102 and at least one n-type doped layer 104 on the first passivation layer 102 on the front surface of the silicon substrate 101, and depositing at least one second passivation layer 103 and at least one p-type doped layer 105 on the second passivation layer 103 on the back surface of the silicon substrate 101;

[0073] Step S300, depositing at least one first transparent conductive layer 106 on the n-type doped layer 104, and depositing at least one second transparent conductive layer 107 on the p-type doped layer 105; wherein at least one of the first transparent conductive layer 106 and the second transparent conductive layer 107 is a cadmium oxide transparent conductive layer, and the cadmium oxide transparent conductive layer is deposited by plasma evaporation deposition;

[0074] In step S400 , a first electrode 108 is formed on the first transparent conductive layer 106 , and a second electrode 109 is formed on the second transparent conductive layer 107 .

[0075] Specifically, the structural schematic diagram of the prepared solar cell is as follows Figure 2 As shown, in this embodiment, at least one first passivation layer 102, at least one n-type doped layer 104 and at least one first transparent conductive layer 106 are prepared on one side of the silicon substrate 101, and at least one second passivation layer 103, at least one p-type doped layer 105 and at least one second transparent conductive layer 107 are prepared on the other side of the silicon substrate 101, and at least one of the first transparent conductive layer 106 and the second transparent conductive layer 107 is formed of cadmium oxide, and the cadmium oxide is deposited by plasma evaporation deposition. The deposition of cadmium oxide by plasma evaporation does not require high temperature, and the elements are more fully ionized, the mobility of the prepared thin film is higher, the conversion efficiency of the battery is high, the properties are more stable, and it can be used in the low-temperature heterojunction battery preparation process flow, and it is more environmentally friendly.

[0076] Specifically, the deposition order of the first passivation layer 102, the n-type doped layer 104, the second passivation layer 103, and the p-type doped layer 105 in the present embodiment can be the order of the front first passivation layer 102-the front n-type doped layer 104-the back second passivation layer 103-the back p-type doped layer 105, or the order of the front first passivation layer 102-the back second passivation layer 103-the front n-type doped layer 104-the back p-type doped layer 105, or the order of the back second passivation layer 103-the front first passivation layer 102-the front n-type doped layer 104-the back p-type doped layer 105, etc. The specific deposition order can be adjusted according to actual conditions and is not limited here.

[0077] Specifically, in this embodiment, the first electrode 108 and the second electrode 109 can be formed by electroplating or screen printing.

[0078] As a specific embodiment of the present invention, the material of the cadmium oxide transparent conductive layer in this embodiment is doped cadmium oxide, and the doped elements in the doped cadmium oxide are selected from: one or more of yttrium, ytterbium, indium, lanthanum, beryllium, samarium, manganese, magnesium, gallium, strontium, bromine, iron, copper, zinc, molybdenum, praseodymium, tin, aluminum, chromium, gadolinium, iron and potassium. And the doped elements are doped into the cadmium oxide in the form of oxides, the mass ratio of the oxides is 0.1% to 20%; the band gap size of the oxides is 2.5eV to 10eV.

[0079] Specifically, the cadmium oxide transparent conductive layer in this embodiment is doped with cadmium oxide, which can improve the performance of the first transparent conductive layer 106 and / or the second transparent conductive layer 107. By doping with an oxide having a band gap width greater than that of cadmium oxide, the band gap width of the transparent conductive layer finally prepared can be increased, thereby improving the transmittance of light in the short-wave band, improving the overall transmittance of the transparent conductive layer, and thereby improving the performance of the battery; by doping with alkali metal elements, it can be used as a donor impurity to increase the number of free electrons, thereby improving the conductivity of n-type CdO; by doping, the crystal quality of cadmium oxide can be improved, lattice defects can be reduced, thereby improving its device performance; by doping, the interface characteristics can be improved, interface defects can be reduced, and the carrier transmission efficiency can be improved.

[0080] Specifically, the present embodiment adopts a plasma evaporation deposition method (PED), and the PED device includes one or more high-density plasma excitation systems (generating a large number of electrons, exciting more positively charged Ar+ ions and negatively charged electrons), a magnetic field control system, a deflection system, a cooling system, a crucible and other components. Each plasma excitation system may include a tantalum tube, lanthanum hexaboride, a molybdenum ring, and a magnetic field control system. Each plasma system corresponds to a crucible.

[0081] As a specific embodiment of the present invention, Figure 3 As shown, the steps of preparing the cadmium oxide transparent conductive layer by the plasma evaporation deposition method of this embodiment may include:

[0082] Step F100, placing cadmium oxide or doped cadmium oxide material in a crucible in a plasma evaporation deposition device;

[0083] Step F200, introducing argon and oxygen into a plasma evaporation deposition device, wherein the volume ratio of oxygen to argon is 0 to 80%;

[0084] Step F300, adjusting the parameters of the plasma evaporation deposition equipment to perform plasma evaporation deposition; wherein the parameters include pressure 0.1-2 Pa, current 100-250 A, crucible coil current 10-100 A, deflection coil current 5-50 A, plasma gun coil current 5-80 A.

[0085] By using the above method, a cadmium oxide transparent conductive layer can be prepared at room temperature without high temperature, and the prepared film has a higher mobility.

[0086] As a specific embodiment of the present invention, Figure 4 As shown, in step F200 of this embodiment, the step of introducing argon and oxygen into the plasma evaporation deposition equipment further includes:

[0087] Step F400, introducing hydrogen into the plasma evaporation deposition equipment; wherein the proportion of hydrogen in the entire gas volume is 0% to 10%.

[0088] In the process of preparing the cadmium oxide transparent conductive layer, hydrogen can be introduced. The introduction of hydrogen can break bonds with weaker bond energy, passivate the defects of the transparent conductive layer, and improve the crystallization performance and conductivity of the transparent conductive layer.

[0089] Specifically, attached Figure 4 There is no order between step F200 and step F400, and hydrogen can be introduced at the same time as argon and oxygen. As a specific embodiment of the present invention, Figure 5 and Figure 6 As shown, step S300 of this embodiment further includes: depositing at least one first transparent conductive layer 106 on the n-type doped layer 104 and depositing at least one second transparent conductive layer 107 on the p-type doped layer 105;

[0090] Step S500, preparing a buffer layer (1062, 1072) on at least one of the n-type doping layer 104 and the p-type doping layer 105. Specifically, in this embodiment, the buffer layer 1062 is formed between the n-type doping layer 104 and the first transparent conductive layer 106, or the buffer layer 1072 is formed between the p-type doping layer 105 and the second transparent conductive layer 107, or the buffer (1062, 1072) is formed between the n-type doping layer 104 and the first transparent conductive layer 106 and the p-type doping layer 105 and the second transparent conductive layer 107. Preferably, the buffer layer (1062, 1072) is formed between the n-type doping layer 104 and the first transparent conductive layer 106 and the p-type doping layer 105 and the second transparent conductive layer 107. The buffer layer (1062, 1072) of this embodiment is mainly used to improve the contact between the n-type doped layer 104 and the first transparent conductive layer 106, and / or to improve the contact between the p-type doped layer 105 and the second transparent conductive layer 107, thereby reducing the contact resistance between the transparent conductive layer and the doped layer, and improving the contact performance between the transparent conductive layer and the doped layer (specific factors affecting efficiency include current, series resistance, opening voltage, and filling), thereby improving the overall performance of the battery.

[0091] Specifically, the material of the buffer layer of this embodiment is selected from indium oxide, indium tin oxide or indium oxide doped with one or more transition metals. The thickness of the buffer layer is 0.5nm to 70nm. For example, the thickness of the buffer layer can be 0.5nm, 10nm, 20nm, 50nm or 70nm.

[0092] As a specific embodiment of the present invention, Figure 7 and Figure 8 As shown, after step S300 of this embodiment deposits at least one first transparent conductive layer 106 on the n-type doped layer 104 and at least one second transparent conductive layer 107 on the p-type doped layer 105, the following steps may be further included:

[0093] Step S600, forming a protective layer (1063, 1073) on at least one of the first transparent conductive layer 106 and the second transparent conductive layer 107;

[0094] Step S700, preparing a first electrode and a second electrode on the protective layer (1063, 1073).

[0095] Specifically, in this embodiment, a protective layer 1063 may be formed on the first transparent conductive layer 106, or a protective layer 1073 may be formed on the second transparent conductive layer 107, or protective layers (1063, 1073) may be formed on both the first transparent conductive layer 106 and the second transparent conductive layer 107. Preferably, protective layers (1063, 1073) are formed on both the first transparent conductive layer 106 and the second transparent conductive layer 107. In this embodiment, due to the presence of the protective layers (1063, 1073), the first transparent conductive layer 106 and the second transparent conductive layer 107 are covered by the protective layers (1063, 1073), so that the stability of the first transparent conductive layer 106 and the second transparent conductive layer 107 can be improved, and the diffusion of the toxicity of the first transparent conductive layer 106 and the second transparent conductive layer 107 formed by the cadmium oxide material can be prevented, thereby improving the stability and environmental friendliness of the entire battery.

[0096] Specifically, the material of the protective layer (1063, 1073) is selected from indium oxide film, tin oxide film, titanium oxide film, aluminum oxide film or indium tin oxide film. In this embodiment, the material of the protective layer is preferably indium tin oxide film.

[0097] Specifically, the indium oxide film, the tin oxide film, the titanium oxide film, and the aluminum oxide film in the protective layer (1063, 1073) in this embodiment are all formed by atomic layer deposition.

[0098] Specifically, when it is necessary to deposit a protective layer (1063, 1073), the product to be prepared is vertically inserted into the basket, the required gas source is introduced, and the protective layers (1063, 1073) are deposited on both sides of the silicon wafer. Specifically, the indium oxide film, the tin oxide film, the titanium oxide film, and the aluminum oxide film are all prepared by introducing the corresponding separate metal gas source and oxidant. The indium source used to prepare the indium oxide film is trimethylindium (In(CH 3 ) 3 ), the oxidant is water (H 2 O) or ozone (O 3 The tin source used to prepare the tin oxide (SnO2) film can be tetraethyltin (Sn(C 2 H 5 ) 4 ), the oxidant can be water (H 2 O) or ozone (O 3 The titanium source used to prepare the titanium oxide (TiO2) film can be tetraisopropoxytitanium (Ti(OCH(CH 3 ) 2 ) 4 ) or titanium tetrachloride (TiCl 4 ), the oxidant can be water (H 2 O) or ozone (O 3 )]. The aluminum source used to prepare the aluminum oxide (Al2O3) film can be trimethylaluminum (Al(CH 3 ) 3 ), the oxidant can be water (H 2 O) or ozone (O 3 ).

[0099] Specifically, the indium tin oxide film is formed by alternately depositing an indium oxide film and a tin oxide film, that is, by alternately introducing an indium source for preparing the indium oxide film and a tin source and an oxidant for preparing the tin oxide film.

[0100] Specifically, the thickness of the protective layer (1063, 1073) of this embodiment is 0.5nm-40nm, for example, the thickness can be 0.5nm, 10nm, 20nm, 30nm or 40nm. The refractive index of the protective layer (1063, 1073) is 1.3-2.2. For example, the refractive index can be 1.3, 1.8, 2 or 2.2.

[0101] As another specific embodiment of the present invention, this embodiment Fig. 9 and Fig.10As shown, buffer layers (1062, 1072) are deposited inside the first transparent conductive layer 106 and the second transparent conductive layer 107, and protective layers (1063, 1073) are deposited outside the first transparent conductive layer 106 and the second transparent conductive layer 107, so that the product can improve the contact performance between the first transparent conductive layer 106 and the second transparent conductive layer 107 and the doping layer (104, 105) through the buffer layer (1062, 1072), and prevent the diffusion of toxicity of the first transparent conductive layer 106 and the second transparent conductive layer 107 composed of cadmium oxide materials through the protective layer (1063, 1073), thereby improving the stability and environmental friendliness of the entire battery.

[0102] As a specific embodiment of the present invention, in this embodiment, the conductive layer formed on the side wall of the substrate is cut by stripping, and the conductive layer may include a first transparent conductive layer 106, a second transparent conductive layer 107, and at least one of a buffer layer (1062, 1072) and a protective layer (1063, 1073).

[0103] As one example, Fig.10 As shown, in this embodiment, a mask carrier can be used when forming the second transparent conductive layer 107 and the buffer layer 1072 located in the second transparent conductive layer 107, so that the prepared second transparent conductive layer 107 has a certain distance from the edge of the silicon substrate 101, thereby forming a disconnected state. If the protective layer (1063, 1073) is not prepared at this time, then due to the existence of the mask carrier, the film on both sides of the silicon substrate 101 already has an insulating area 120, and no further cutting is required. If it is necessary to further prepare the protective layer (1063, 1073) at this time, since the preparation method of the protective layer (1063, 1073) is to vertically insert the product into the basket for preparation, the protective layers (1063, 1073) on both sides of the silicon substrate 102 are inevitably overlapped with each other, and the product structure formed is as follows: Fig.11 As shown, it is necessary to use laser to cut the protective layer (1063, 1073) on the back of the silicon substrate 101 (as shown in FIG. Fig.10 and Fig.11 As shown), thereby preventing the prepared battery cell from short-circuiting.

[0104] Generally speaking, in a carrier with a mask, the width of the mask is generally 0.5mm or even wider, which means that the effective light absorption area of ​​the cell becomes smaller after cutting, resulting in a decrease in the performance of the cell.

[0105] As another embodiment, this embodiment uses a maskless carrier when forming the buffer layer (1062, 1072) and the transparent conductive layer (106, 107), and the maskless carrier supports the silicon substrate 101 in a four-corner support or suspension manner. If the protective layer (1063, 1073) is not prepared at this time, since the buffer layer (1062, 1072) and the transparent conductive layer (106, 107) are prepared using a maskless carrier, the buffer layer (1062, 1072) and the transparent conductive layer (106, 107) on both sides of the silicon substrate 101 overlap each other, and laser removal is required to avoid short circuit of the battery cell. If the protective layer (1063, 1073) is further prepared later, since the protective layer (1063, 1073) is prepared by vertically inserting the product into the flower basket, the protective layer (1063, 1073) is prepared. Therefore, in the product after the protective layers (1063, 1073) are prepared, the protective layers (1063, 1073) on both sides of the silicon substrate 101 will overlap (e.g. Fig.13 As shown), the product can be cut by laser after the protective layer (1063, 1073) is prepared (as shown). Fig.14 and Fig.15 As shown), the buffer layers (1062, 1072) located on both sides of the silicon substrate 101 are prevented from being electrically conductive to each other, the first transparent conductive layer 106 and the second transparent conductive layer 107 located on both sides of the silicon substrate 101 are prevented from being electrically conductive to each other, and the protective layers (1063, 1073) located on both sides of the silicon substrate 101 are prevented from being electrically conductive to each other.

[0106] As a specific embodiment of the present invention, the present embodiment uses laser film removal to cut the transparent conductive layer (including the buffer layer, the transparent conductive layer and the protective layer) to form an insulating region 120. The width of the insulating region 120 can be 20 to 300 μm. Specifically, the laser of the present embodiment irradiates the conductive layer (such as Fig.11 and Fig.14 ), and the direction of the laser is completely parallel to the edge of the silicon substrate 101, and an insulating region 120 is formed on the conductive layer near the side region of the silicon substrate 101. Specifically, in this embodiment, long wavelength (1200nm-2000nm) light is used for irradiation, so that the conductive layer can be stripped without damaging the microcrystalline silicon or amorphous silicon.

[0107] Specifically, in this embodiment, the angle of the laser can be in the direction shown by arrow a in the figure to remove the film of the product. In this way, the back and side of the battery cell can be cut, and the front side will not be affected, thereby meeting the cutting requirements while not affecting the light absorption area of ​​the front side of the battery, thereby maximizing the battery conversion efficiency.

[0108] As one of the embodiments of the present invention, Fig.16As shown, in this embodiment, after preparing a protective layer on the first transparent conductive layer 106 and the second transparent conductive layer 107, before preparing the first electrode 108 and the second electrode 109, the protective layer can be patterned by laser to expose the portion of the printed electrode in the first transparent conductive layer 106 and the second transparent conductive layer 107, so that the subsequent electrode can directly contact the first transparent conductive layer 106 and the second transparent conductive layer 107, thereby reducing the contact resistance between the electrode and the transparent conductive layer and improving the contact characteristics between the electrode and the transparent conductive layer.

[0109] Specifically, in this embodiment, a short wavelength (355 nm, pulse width 10 ps) laser is used to remove the protective layer.

[0110] As a specific embodiment of the present invention, this embodiment also provides a solar cell, which is prepared according to the above method for preparing a solar cell.

[0111] The following is a detailed description with reference to specific embodiments.

[0112] Comparative Example 1

[0113] 1) After the n-type single crystal silicon wafer is texturized and cleaned, it is placed in a PECVD chamber, and a second passivation layer 103 is sequentially deposited on the second surface of the n-type single crystal silicon wafer by chemical vapor deposition. A first passivation layer 102 and an n-type doping layer 104 are deposited on the first surface of the n-type single crystal silicon wafer. A p-type doping layer 105 is deposited on the second passivation layer 103 on the second surface of the n-type single crystal silicon wafer.

[0114] 2) Argon and oxygen are introduced at room temperature, the gas flow ratio of argon to oxygen is set at 50:1, the chamber pressure is maintained at 0.7 Pa, and a first transparent conductive layer 106 is deposited on the n-type doped layer 104, and a second transparent conductive layer 107 is deposited on the p-type doped layer 105 by magnetron sputtering.

[0115] The transparent conductive material used in this comparative example is the most mainstream ITO material in the industry, wherein the mass ratio of indium oxide to tin oxide is 90:10, and the thickness of the prepared first transparent conductive layer 106 and the second transparent conductive layer 107 is 80nm. When depositing the first transparent conductive layer 106 and the second transparent conductive layer 107, the transparent conductive layer material can not only be deposited on the first surface and the second surface of the silicon wafer, but also a little deposited on the side of the silicon wafer, causing the first surface of the battery (battery negative electrode) and the second surface of the battery (battery positive electrode) to overlap and form a short circuit. In order to avoid this situation, it is necessary to use a mask carrier to support the silicon wafer for coating when preparing the second transparent conductive layer 107. The mask carrier can cover the four sides of the silicon wafer to prevent the area from being deposited on the second transparent conductive layer 107. Therefore, after preparing the second transparent conductive layer 107, a closed physical insulation area is formed at the edge of the second surface of the silicon wafer. The width of the physical insulation area formed by this method can generally be controlled at about 0.5mm.

[0116] 3) The first electrode 108 and the second electrode 109 are respectively prepared by screen printing on the first transparent conductive layer 106 and the second transparent conductive layer 107, wherein the first electrode 108 and the second electrode 109 are silver electrodes or silver-copper electrodes. After the battery is formed, it is subsequently subjected to an LED process and a battery conversion efficiency test is performed.

[0117] Comparative Example 2

[0118] Step 1) and step 3) are the same as those in Comparative Example 1;

[0119] Step 2) Argon gas is introduced at room temperature, the chamber pressure is maintained at 0.5 Pa, and a first transparent conductive layer 106 is deposited on the n-type doped layer 104 and a second transparent conductive layer 107 is deposited on the p-type doped layer 105 by magnetron sputtering.

[0120] The transparent conductive material used in this comparative example is cadmium oxide material, and the thickness of the prepared first and second transparent conductive layers 107 is 80nm. When preparing the second transparent conductive layer 107, a mask carrier is used, and the width of the physical insulation area at the edge of the silicon wafer is 0.5mm.

[0121] Example 1

[0122] Specific structure such as Figure 2 As shown, the specific preparation steps include:

[0123] Step 1) and step 3) are the same as those in Comparative Example 1;

[0124] Step 2) PED coating method is used to deposit a first transparent conductive layer 106 on the n-type doped layer 104 and a second transparent conductive layer 107 on the p-type doped layer 105 at room temperature. The material type of the first transparent conductive layer 106 and the second transparent conductive layer 107 is cadmium oxide material, and the material thickness is 80nm. The PED plasma system current is set to 150A, the crucible coil current is set to 25A, the deflection coil current is set to 15A, the plasma gun coil current is set to 15A, the process pressure is set to 0.5Pa, and the gas introduced is argon and oxygen. When preparing the second transparent conductive layer 107, a mask carrier is used, and the width of the physical insulation area at the edge of the silicon wafer is 0.5mm.

[0125] Example 2

[0126] Specific structure such as Figure 2 As shown, the specific preparation steps include:

[0127] Step 1) and step 3) are the same as those in Comparative Example 1.

[0128] Step 2) PED coating is used to deposit a first transparent conductive layer 106 on the n-type doped layer 104 and a second transparent conductive layer 107 on the p-type doped layer 105 at room temperature. The first transparent conductive layer 106 and the second transparent conductive layer 107 are made of cadmium oxide with a thickness of 80 nm. The PED plasma system current is set to 150 A, the crucible coil current is set to 25 A, the deflection coil current is set to 15 A, the plasma gun coil current is set to 15 A, and the process pressure is set to 0.5 Pa.

[0129] In addition, this example also verifies the influence of other factors on the properties of the prepared film.

[0130] In some embodiments, hydrogen gas is introduced into the PED plasma system to verify the effect of hydrogen gas introduction on material properties.

[0131] In order to increase the band gap of the material and improve the short-wave transmittance of the transparent conductive film, in some embodiments, the type of target material is changed to verify the influence of different element doping on the properties of the prepared material and the influence of applying this type of material to heterojunction batteries on the battery performance.

[0132] In this example, yttrium-doped cadmium oxide (Y 2 O 3 :CdO, Wt% = 3:97, Wt%), beryllium-doped cadmium oxide (BeO:CdO, Wt% = 5:95, Wt%), samarium-doped cadmium oxide (Sm 2 O 3 :CdO,Wt%=10:90,Wt%), yttrium-magnesium co-doped cadmium oxide (Y2 O 3 :MgO:CdO, Wt%=3:4:93, Wt%), gallium-beryllium-zinc co-doped cadmium oxide (Ga2O3:BeO:ZnO:CdO, Wt%=1:2:5:92, Wt%) and other materials.

[0133] Example 3

[0134] The structural schematic diagram of the SHJ heterojunction battery in this embodiment is as follows Figure 6 As shown. From top to bottom, it includes the first electrode 108, the first transparent conductive layer 106 (i.e., the first cadmium oxide-based TCO main layer), the first buffer layer 1062, the n-type doped layer 104, the first passivation layer 102, the n-type single crystal silicon wafer 101, the second passivation layer 103, the p-type doped layer 105, the second buffer layer 1072, the second transparent conductive layer 107 (i.e., the second cadmium oxide-based TCO main layer), and the second electrode 109. It further includes a physical insulation region 120 to prevent the first transparent conductive layer 106 and the second transparent conductive layer 107 from overlapping and short-circuiting.

[0135] The specific preparation method of the heterojunction solar cell in this embodiment includes the following steps:

[0136] Step 1) and step 3) are the same as those in Comparative Example 1;

[0137] Step 2) A first buffer layer 1062 is also prepared inside the first transparent conductive layer 106. Preferably, the first buffer layer 1062 has a thickness of 20 nm, is ITO, and is located between the first transparent conductive layer 106 (first cadmium oxide-based TCO main layer) and the n-type doped layer 104. The first buffer layer 1062 is used to improve the contact problem between the n-type doped layer 104 and the first transparent conductive layer 106. The first buffer layer 1062 is coated by PED coating. The first buffer layer 1062 and the first transparent conductive layer 106 (first cadmium oxide-based TCO main layer) are completed in the same cavity without leaving the cavity in the middle, reducing the impact of the cavity breaking and the experimental process on the battery efficiency. The total thickness of the first buffer layer 1062 and the first transparent conductive layer 106 is 80 nm.

[0138] And / or, the second transparent conductive layer 107 (i.e., the second cadmium oxide-based TCO main layer) also includes a second buffer layer 1072. Preferably, the second buffer layer 1072 has a thickness of 20 nm, is ITO, and is located between the second transparent conductive layer 107 and the p-type doped layer 105. The second buffer layer 1072 is used to improve the contact problem between the p-type doped layer 105 and the second transparent conductive layer 107. The second buffer layer 1072 is coated by PED, and the second buffer layer 1072 and the second transparent conductive layer 107 are completed in the same cavity without leaving the cavity in the middle, thereby reducing the impact of the cavity breaking and the experimental process on the battery efficiency. The thickness of the second buffer layer 1072 and the total thickness of the second transparent conductive layer 107 are 80 nm. When preparing the second buffer layer 1072 and the second transparent conductive layer 107 materials, a mask carrier is used, and the width of the physical insulation area at the edge of the silicon wafer is 0.5 mm.

[0139] Example 4

[0140] The structural schematic diagram of the heterojunction battery in this embodiment is as follows Figure 8 As shown. In this embodiment, the SHJ heterojunction battery includes, from top to bottom, a first electrode 108, a first protective layer 1063, a first transparent conductive layer 106 (a first cadmium oxide-based TCO main layer), an n-type doped layer 104, a first passivation layer 102, an n-type single crystal silicon wafer 101, a second passivation layer 103, a p-type doped layer 105, a second transparent conductive layer 107, a second protective layer 1073, and a second electrode 109. It further includes a physical insulation region 120 to prevent the first transparent conductive layer 106 and the second transparent conductive layer 107 from overlapping and short-circuiting.

[0141] The specific preparation method of the heterojunction solar cell in this embodiment includes the following steps:

[0142] Step 1) and step 3) are the same as those in Comparative Example 1;

[0143] Step 2) The first transparent conductive layer 106 includes a first protective layer 1063. Preferably, the first protective layer 1063 has a thickness of 2 nm, the material of the first protective layer 1063 is ITO, the refractive index of the first protective layer 1063 is 2, and the first protective layer 1063 is located between the first transparent conductive layer 106 and the first electrode 108. The first protective layer 1063 is a dense oxide, which is used to improve device performance and stability and prevent the diffusion of toxic cadmium. The total thickness of the first protective layer 1063 and the first transparent conductive layer 106 is 80 nm. The first protective layer 1063 is coated by ALD preparation method, and the ALD coating has high density and good protection.

[0144] And / or, a second protective layer 1073 is prepared outside the second transparent conductive layer 107. Preferably, the second protective layer 1073 has a thickness of 2nm, the material of the second protective layer 1073 is ITO, the refractive index of the second protective layer 1073 is 2, and the second protective layer 1073 is located between the second transparent conductive layer 107 and the second electrode 109. The second protective layer 1073 is a dense oxide, which is used to improve the performance and stability of the device and prevent the diffusion of toxic cadmium. The thickness of the second protective layer 1073 and the total thickness of the second transparent conductive layer 107 are 80nm. The second protective layer 1073 is coated by ALD preparation method, and the ALD coating has high density and good protection.

[0145] During the experiment, the silicon wafer is vertically inserted into the flower basket, the required gas source is introduced, and the required protective dielectric material is deposited on both sides of the silicon wafer.

[0146] Example 5

[0147] The structural schematic diagram of the heterojunction battery in this embodiment is as follows Fig.10 As shown. From top to bottom, it includes the first electrode 108, the first protective layer 1063, the first transparent conductive layer 106 (the first cadmium oxide TCO main layer 106), the first buffer layer 1062, the n-type doped layer 104, the first passivation layer 102, the n-type single crystal silicon wafer 101, the second passivation layer 103, the p-type doped layer 105, the second buffer layer 1072, the second transparent conductive layer 107 (i.e., the second cadmium oxide TCO main layer 107), the second protective layer 1073, and the second electrode 109. It further includes a physical insulation region 120 to prevent the conductive layers from overlapping and short-circuiting each other.

[0148] The specific preparation method of the heterojunction solar cell in this embodiment includes the following steps:

[0149] Step 1) and step 3) are the same as those in Comparative Example 1;

[0150] Step 2) The first buffer layer 1062 is located between the n-type doped layer 104 and the first transparent conductive layer 106 (the first cadmium oxide based TCO main layer), the first transparent conductive layer 106 is located between the first buffer layer 1062 and the first protective layer 1063, and the first protective layer 1063 is located between the first cadmium oxide based TCO main layer and the first electrode 108.

[0151] The thickness of the first buffer layer 1062 is 20 nm, the thickness of the first protective layer 1063 is 2 nm, and the total thickness of the first buffer layer 1062 , the first cadmium oxide based TCO main layer 106 , and the first protective layer 1063 is 80 nm.

[0152] The first buffer layer 1062 is ITO, the first cadmium oxide based TCO main layer 106 is cadmium oxide, both indium oxide and cadmium oxide are coated by PED, without leaving the cavity, and the entire coating process is completed in the same cavity, reducing the impact of cavity rupture and experimental process on battery efficiency; the first protective layer 1063 is ITO, coated by ALD.

[0153] The first buffer layer 1062 is used to improve the contact problem between the n-type doped layer 104 and the first transparent conductive layer 106. The first protective layer 1063 is a dense oxide, which is used to improve the device performance and stability and prevent the diffusion of toxic cadmium.

[0154] And / or, the second buffer layer 1072 is located between the p-type doped layer 104 and the second transparent conductive layer 107 (i.e., the second cadmium oxide based TCO main layer), the second cadmium oxide based TCO main layer 107 is located between the second buffer layer 1072 and the second protective layer 1073, and the second protective layer 1073 is located between the second cadmium oxide based TCO main layer 107 and the second electrode 109.

[0155] The thickness of the second buffer layer 1072 is 20 nm, the thickness of the second protective medium 1073 is 2 nm, and the total thickness of the second buffer layer 1072 , the second cadmium oxide based TCO main layer 107 and the second protective layer 1073 is 80 nm.

[0156] The second buffer layer 1072 is ITO, the second cadmium oxide TCO main layer 107 is cadmium oxide, indium oxide and cadmium oxide are both PED coated, without cavity exit, the entire coating process is completed in the same cavity, reducing the impact of cavity breakage and experimental process on battery efficiency. The second protective layer is ITO using ALD coating.

[0157] The second buffer layer 1072 is used to improve the contact problem between the p-type doping layer 105 and the TCO. The second protective layer 1073 is a dense oxide, which is used to improve the device performance and stability and prevent the diffusion of toxic cadmium.

[0158] Example 6

[0159] The structural schematic diagram of the heterojunction battery in this embodiment is as follows Fig.10As shown. From top to bottom, it includes the first electrode 108, the first protective layer 1063, the first transparent conductive layer 106 (the first cadmium oxide TCO main layer 106), the first buffer layer 1062, the n-type doping layer 104, the first passivation layer 102, the n-type single crystal silicon wafer 101, the second passivation layer 103, the p-type doping layer 105, the second buffer layer 1072, the second transparent conductive layer 107 (i.e., the second cadmium oxide TCO main layer 107), the second protective layer 1073, and the second electrode 109. In this embodiment, a mask carrier with a width of 0.5 mm is used when preparing the conductive layer. Since the conductive layers on both sides of the silicon substrate are prepared simultaneously, a closed physical insulation area (such as Fig.11 shown).

[0160] The specific preparation method of the heterojunction solar cell in this embodiment includes the following steps:

[0161] Step 1) and step 3) are the same as those in Comparative Example 1;

[0162] Step 2-1) is the same as step 2) in Example 5;

[0163] Step 2-2) Use a pulsed long-wave laser with a wavelength of 1200 nm and an incident angle of α = arctan (a / b) = 45°, where b is 100 microns and a is the thickness of the silicon wafer (100 microns), to scan the second surface of the silicon wafer around the periphery to form the desired laser insulation area. The shape of the product formed after laser cutting is as follows: Fig.12 shown.

[0164] Example 7

[0165] The structural schematic diagram of the heterojunction battery in this embodiment is as follows Fig.14 As shown. From top to bottom, it may include a first electrode 108, a first protective layer 1063, a first transparent conductive layer 106 (a first cadmium oxide TCO main layer 106), a first buffer layer 1062, an n-type doped layer 104, a first passivation layer 102, an n-type single crystal silicon wafer 101, a second passivation layer 103, a p-type doped layer 105, a second buffer layer 1072, a second transparent conductive layer 107 (i.e., a second cadmium oxide TCO main layer 107), a second protective layer 1073, and a second electrode 109. In the present embodiment, a double-sided maskless carrier is used when preparing the conductive layer (the four corners of the silicon wafer are point-contacted and lifted up and placed in the coating chamber). Since the conductive layers of the silicon substrate are prepared twice simultaneously, the edge of the second surface of the silicon wafer is the same as the edge of the first surface, and there is no physical insulation area (such as Fig.14 shown).

[0166] The specific preparation method of the heterojunction solar cell in this embodiment includes the following steps:

[0167] Step 1) and step 3) are the same as those in Comparative Example 1;

[0168] Step 2-1) is the same as step 2) in Example 5;

[0169] Step 2-2), such as Fig.17 and Fig.18 As shown, from Fig.17 and Fig.18 It can be seen that microcrystalline silicon or amorphous silicon (n-type doped layer and p-type doped layer) does not absorb light in the long-wave band, but absorbs light in the short-wave band, and transparent conductive materials absorb light in the long-wave band. Therefore, in this embodiment, a pulsed long-wave laser is used as a film removal laser. At this time, the conductive layers on both sides of the silicon substrate 101 can be removed without damaging materials at other locations. Specifically, Fig.14 As shown, the wavelength of the laser used in this embodiment is 1200nm. According to the incident angle α=arctan(a / b)=45°, where b is 100 microns and a is the thickness of the silicon wafer (100 microns), the second surface of the silicon wafer is scanned along the four sides of the silicon wafer to form the required laser insulation area. This method can completely remove the TCO material on the second surface and the side, and keep the passivation layer and doping layer in the area intact. The size of the required laser insulation area can be achieved by tilting the angle α to obtain a precisely controllable laser insulation area width b. The final product after laser film removal is as follows Fig.12 and Fig.15 shown.

[0170] Example 8

[0171] The structural schematic diagram of the heterojunction battery in this embodiment is shown in FIG. Fig.14 As shown. From top to bottom, it includes the first electrode 108, the first protective layer 1063, the first transparent conductive layer 106 (the first cadmium oxide TCO main layer 106), the first buffer layer 1062, the n-type doping layer 104, the first passivation layer 102, the n-type single crystal silicon wafer 101, the second passivation layer 103, the p-type doping layer 105, the second buffer layer 1072, the second transparent conductive layer 107 (i.e., the second cadmium oxide TCO main layer 107), the second protective layer 1073, and the second electrode 109. In this embodiment, a double-sided maskless carrier is used when preparing the first transparent conductive layer 106 and the second transparent conductive layer 107 (the four corners of the silicon wafer are point-contacted and lifted up to be placed in the coating cavity).

[0172] The specific preparation method of the SHJ heterojunction solar cell in this embodiment includes the following steps:

[0173] Step 1) and step 3) are the same as those in Comparative Example 1;

[0174] Step 2-1) is the same as step 2) in Example 5;

[0175] Step 2-2) is the same as step 2-2) in Example 7;

[0176] Step 2-3), using a pulsed short-wave laser, wherein the wavelength of the laser is 532nm, in a direction perpendicular to the first surface or the second surface, the laser is used to remove the area where the first electrode 108 is to be made on the first protective layer or the second electrode 109 is to be made on the second protective layer. Among them, the band gap of the protective layer ITO is 3.5eV, and the band gap of the cadmium oxide-based TCO main layer is 3eV. The pulsed short-wave laser can process ITO to a greater extent, and the structure of the solar cell finally obtained is as follows Fig.15 and Fig.16 shown.

[0177] The main preparation conditions and product efficiency of the above examples are shown in Table 1 below.

[0178] Table 1

[0179]

[0180] It can be seen from the above table:

[0181] Compared with Comparative Example 1 and Comparative Example 2, in Example 1, the CdO transparent conductive layer is prepared by using PED, which can greatly improve the battery efficiency.

[0182] Compared with Example 1, when hydrogen is introduced during the preparation process, Example 2 can reduce the defects of the transparent conductive layer, inhibit the recombination of electrons and holes, and improve the battery mobility.

[0183] Compared with Example 2, Example 3 introduces a buffer layer, which can effectively improve the contact performance between the transparent conductive layer and the doping layer, thereby improving the conversion efficiency of the battery.

[0184] Compared with Example 2, Example 4 introduces a protective layer, which prevents the toxic diffusion of CdO. At the same time, the performance improvement caused by the protective layer and the short circuit caused by the protective layer cause the performance of the entire battery to decline.

[0185] Compared with Example 4, Example 5 introduces a buffer layer, and its performance is improved. Compared with Example 3, Example 5 introduces a protective layer, which, as can be seen from the above analysis, causes a decrease in performance.

[0186] Compared with Example 5, Example 6 uses a mask carrier to form a partition area when preparing the transparent conductive layer and the buffer layer, and uses a laser to cut the protective layer. In this way, the conductive layers on both sides of the silicon substrate 101 are disconnected from each other, so that the battery will not be short-circuited, thereby improving the efficiency of the battery.

[0187] Compared with Example 6, Example 7 uses a maskless carrier for the preparation of the transparent conductive layer and the buffer layer. After the preparation of the protective layer is completed, the transparent conductive layer, the buffer layer and the protective layer are cut by laser. Compared with the mask carrier cutting method, the laser cutting has a smaller cutting area, thereby improving the efficiency of the battery.

[0188] Compared with Example 7, after the transparent conductive layer, the buffer layer and the protective layer are cut, Example 8 is subjected to laser stripping on the protective layer to form holes for preparing electrodes, so that the electrodes are in direct contact with the transparent conductive layer, thereby increasing the contact performance between the electrodes and the transparent conductive layer and improving the efficiency of the battery.

[0189] At this point, those skilled in the art should recognize that, although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived based on the content disclosed in the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and recognized as covering all these other variations or modifications.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: The method comprises: Providing a silicon substrate; Depositing at least one first passivation layer and at least one n-type doped layer on the front surface of the silicon substrate, and depositing at least one second passivation layer and at least one p-type doped layer on the back surface of the silicon substrate; Depositing at least one first transparent conductive layer on the n-type doped layer, and depositing at least one second transparent conductive layer on the p-type doped layer; wherein at least one of the first transparent conductive layer and the second transparent conductive layer is a cadmium oxide transparent conductive layer, and the cadmium oxide transparent conductive layer is deposited by plasma evaporation deposition; A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

2. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The material of the cadmium oxide transparent conductive layer is doped cadmium oxide, and the doped elements in the doped cadmium oxide are selected from: one or more of yttrium, ytterbium, indium, lanthanum, beryllium, samarium, manganese, magnesium, gallium, strontium, bromine, iron, copper, zinc, molybdenum, praseodymium, tin, aluminum, chromium, gadolinium, iron and potassium; and the doped elements are doped into the cadmium oxide in the form of oxides; Optionally, the mass proportion of the oxide in the cadmium oxide material is 0.1% to 20%; Optionally, the band gap of the oxide is 2.5 eV to 10 eV.

3. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The steps of preparing the cadmium oxide transparent conductive layer by plasma evaporation deposition method include: placing cadmium oxide or doped cadmium oxide material in a crucible in a plasma evaporation deposition device; Introducing argon and oxygen into the plasma evaporation deposition device, wherein the volume ratio of oxygen to argon is 0 to 80%; The parameters of the plasma evaporation deposition equipment are adjusted to perform plasma evaporation deposition; wherein the parameters include a pressure of 0.1-2 Pa, a current of 100-250 A, a crucible coil current of 10-100 A, a deflection coil current of 5-50 A, and a plasma gun coil current of 5-80 A.

4. The method for preparing a heterojunction solar cell according to claim 3, characterized in that: After introducing argon and oxygen into the plasma evaporation deposition equipment, the method further comprises: Hydrogen is introduced into the plasma evaporation deposition equipment, wherein the hydrogen accounts for 0% to 10% of the total gas volume.

5. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: Before depositing at least one first transparent conductive layer on the n-type doped layer and depositing at least one second transparent conductive layer on the p-type doped layer, the method further comprises: A buffer layer is prepared on at least one of the n-type doping layer and the p-type doping layer.

6. The method for preparing a heterojunction solar cell according to claim 5, characterized in that: The material of the buffer layer is selected from indium oxide, indium tin oxide or indium oxide doped with one or more transition metals; Optionally, the buffer layer has a thickness of 0.5 nm to 70 nm.

7. The method for preparing a heterojunction solar cell according to claim 5, characterized in that: After depositing at least one first transparent conductive layer on the n-type doped layer and at least one second transparent conductive layer on the p-type doped layer, the method further comprises: A protective layer is prepared on at least one of the first transparent conductive layer and the second transparent conductive layer.

8. The method for preparing a heterojunction solar cell according to claim 7, characterized in that: The material of the protective layer is selected from indium oxide film, tin oxide film, titanium oxide film, aluminum oxide film or indium tin oxide film; Optionally, the protective layer has a thickness of 0.5 nm to 40 nm; Optionally, the refractive index of the protective layer is 1.3-2.

2.

9. The method for preparing a heterojunction solar cell according to claim 8, characterized in that: The indium oxide film, tin oxide film, titanium oxide film and aluminum oxide film are all formed by atomic layer deposition.

10. The method for preparing a heterojunction solar cell according to claim 9, characterized in that: The indium tin oxide thin film is formed by alternately depositing an indium oxide thin film and a tin oxide thin film.

11. The method for preparing a heterojunction solar cell according to any one of claims 7 to 10, characterized in that: After forming the protective layer, the method further comprises: The conductive layer is cut to form an insulating region, wherein the width of the insulating region is 20 to 300 μm, wherein the conductive layer includes at least one of a first transparent conductive layer, a second transparent conductive layer, the buffer layer and the protective layer.

12. The method for preparing a heterojunction solar cell according to claim 11, characterized in that: The conductive layer is cut by laser stripping, and the laser is irradiated onto the conductive layer on the second surface of the silicon substrate in a direction at a certain angle to the vertical direction, and the direction of the laser is completely parallel to the edge of the silicon substrate, forming the insulating area on the conductive layer close to the side area of ​​the silicon substrate.

13. The method for preparing a heterojunction solar cell according to claim 7, characterized in that: The carrier used in the process of preparing at least one of the first transparent conductive layer, the second transparent conductive layer and the buffer layer is a maskless carrier; The maskless carrier supports the silicon substrate in a four-corner support or suspension manner.

14. The method for preparing a heterojunction solar cell according to claim 7, characterized in that: The protective layer is patterned by laser stripping to form through holes on the protective layer that match the first electrode and the second electrode, so that the first electrode directly contacts the first transparent conductive layer, and the second electrode directly contacts the second transparent conductive layer.

15. The method for preparing a heterojunction solar cell according to claim 14, characterized in that: The laser light is a short-wavelength laser light, and the laser light is vertically incident on the protective layer.

16. A heterojunction solar cell, characterized in that: The heterojunction solar cell is prepared according to the method for preparing the heterojunction solar cell according to any one of claims 1 to 15.

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