Transistor X-ray detector and preparation method thereof

Abstract

The invention provides a transistor X-ray detector and a preparation method thereof. The transistor X-ray detector comprises a transistor, wherein the transistor comprises a grid electrode, a grid dielectric layer, a heterojunction layer, a source electrode and a drain electrode; the gate dielectric layer is arranged between the gate electrode and the heterojunction layer, the heterojunction layer comprises an interface passivation layer and a channel layer, the channel layer is a gallium oxide channel layer, the interface passivation layer and the channel layer form a heterojunction, the interface passivation layer is arranged between the gate dielectric layer and the channel layer in a stacked mode, the source electrode and the drain electrode are electrically connected with the channel layer, and the source electrode and the drain electrode are spaced. Compared with the prior art, the transistor X-ray detector has obviously higher detection sensitivity, and the service life of the X-ray detector can be effectively prolonged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a transistor X-ray detector and a preparation method thereof. Background Art

[0002] X-ray dosimeters are used to detect the dose of X-rays and are widely used in modern industry, transportation logistics, medical and other industries. Currently, the commonly used X-ray dosimeters include Geiger counters, scintillator detectors and semiconductor detectors.

[0003] At present, the core components of semiconductor detectors are mostly field effect transistors based on silicon semiconductor materials. The material of the channel layer in the field effect transistor is single crystal silicon, and the material of the gate dielectric layer is silicon dioxide. Its working principle is: high-energy radiation generates electrons in the gate dielectric layer through ionization excitation. The electrons are accelerated by the electric field and swept out of the gate dielectric layer and leave positively charged ionization defects, causing the threshold voltage of the transistor to shift. The irradiation dose can be obtained by the offset of the threshold voltage. Semiconductor detectors have the advantages of high energy resolution, small size, and short resolution time. However, the detection sensitivity of this semiconductor detector needs to be further improved. Summary of the invention

[0004] Based on this, it is necessary to provide a transistor X-ray detector to address the problems in the above-mentioned background technology, so as to improve the detection sensitivity while ensuring the service life of the detector.

[0005] According to some embodiments of the present disclosure, there is provided a transistor X-ray detector, which includes a transistor, wherein the transistor includes: a gate, a gate dielectric layer, a heterojunction layer, a source electrode, and a drain electrode;

[0006] The gate dielectric layer is arranged between the gate and the heterojunction layer, the heterojunction layer includes an interface passivation layer and a channel layer, the channel layer is a gallium oxide channel layer, the interface passivation layer and the channel layer form a heterojunction, the interface passivation layer is stacked between the gate dielectric layer and the channel layer, the source and the drain are electrically connected to the channel layer, and the source and the drain are spaced apart.

[0007] In some embodiments of the present disclosure, the carrier concentration of the interface passivation layer is higher than the carrier concentration of the channel layer.

[0008] In some embodiments of the present disclosure, the carrier concentration of the interface passivation layer is 1×10 18 cm -3 ~1×10 23 cm -3 .

[0009] In some embodiments of the present disclosure, a substrate is further included; the gate is arranged on the substrate, the gate dielectric layer is stacked on the gate, the interface passivation layer, the source and the drain are all arranged on the gate dielectric layer, and the channel layer is arranged on the interface passivation layer.

[0010] In some embodiments of the present disclosure, the carrier concentration of the channel layer is 1×10 13 cm -3 ~1×10 18 cm -3 .

[0011] In some embodiments of the present disclosure, the thickness of the interface passivation layer is 1 nm to 6 nm.

[0012] In some embodiments of the present disclosure, the thickness of the channel layer is 15 nm to 60 nm.

[0013] In some embodiments of the present disclosure, the thickness of the gate dielectric layer is ≤100 nm.

[0014] In some embodiments of the present disclosure, a threshold voltage detection mechanism is further included. The threshold voltage detection mechanism is electrically connected to the transistor, and the threshold voltage detection mechanism is used to measure the threshold voltage of the transistor.

[0015] In some embodiments of the present disclosure, the material of the interface passivation layer is selected from one or more of indium gallium zinc oxide, indium zinc oxide and indium tin oxide.

[0016] According to some further embodiments of the present disclosure, there is also provided a method for preparing the transistor X-ray detector according to the above embodiment, which comprises the following steps:

[0017] Preparing the gate and the gate dielectric layer on a substrate;

[0018] Depositing the material of the interface passivation layer and the material of the channel layer on the gate dielectric layer to form the heterojunction layer;

[0019] The source electrode and the drain electrode are prepared on the heterojunction layer.

[0020] In some embodiments of the present disclosure, depositing the material of the interface passivation layer includes: depositing the material of the interface passivation layer in a gas environment free of oxygen by physical vapor deposition.

[0021] In some embodiments of the present disclosure, depositing the material of the channel layer includes: depositing the material of the channel layer in a gas environment free of oxygen by physical vapor deposition.

[0022] In some embodiments of the present disclosure, after depositing the material of the channel layer, the method further includes: annealing the deposited material of the channel layer in an oxidizing gas environment containing oxygen atoms to reduce oxygen vacancy defects therein.

[0023] In some embodiments of the present disclosure, the temperature during the annealing process is controlled to be 200° C. to 500° C.

[0024] In some embodiments of the present disclosure, the time during the annealing process is controlled to be 10 min to 120 min.

[0025] The transistor X-ray detector provided by the present disclosure is significantly different from the traditional transistor X-ray detector in that a heterojunction layer is introduced into the heterojunction layer, which includes an interface passivation layer and a channel layer. The channel layer is made of gallium oxide material. The oxygen vacancy defects of the gallium oxide material will increase under the irradiation of X-rays, and the electrical properties of the channel layer will change accordingly, which causes the threshold voltage of the device to shift. Experiments show that compared with traditional technologies, the transistor X-ray detector has significantly higher detection sensitivity, and because its main principle of detecting X-rays is based on the change of oxygen vacancy defects in the heterojunction layer rather than ionization damage in the gate dielectric layer, it can also effectively improve the service life of the X-ray detector.

[0026] The interface defects between the gallium oxide channel layer and the gate dielectric layer can cause the threshold voltage of the transistor to be unstable. The present invention introduces an interface passivation layer between the channel layer and the gate dielectric layer, and the interface passivation layer and the gallium oxide layer form a heterojunction layer, which can improve the problem of unstable threshold voltage of the transistor when gallium oxide is used as the channel layer, and greatly improves the measurement stability of the transistor before and after irradiation.

[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of the structure of a transistor X-ray detector provided by the present disclosure;

[0030] Figure 2 For preparation Figure 1The schematic diagram of the steps of the transistor X-ray detector shown;

[0031] Figure 3 A schematic diagram of the structure of a substrate provided by the present disclosure;

[0032] Figure 4 For Figure 3 A schematic diagram of a structure for preparing a gate based on the structure shown;

[0033] Figure 5 For Figure 4 A schematic diagram of a structure for preparing a dielectric material layer, a passivation material layer and a channel material layer based on the structure shown;

[0034] Figure 6 For Figure 5 A schematic diagram of a structure in which a dielectric material layer, a passivation material layer and a channel material layer are etched on the basis of the structure shown to form a gate dielectric layer, an interface passivation layer and a channel layer respectively;

[0035] Figure 7 The drain current-gate-source voltage curves of the transistor of Example 1 are measured multiple times before and after irradiation;

[0036] Figure 8 1 is a drain current-gate-source voltage curve of the transistor of Example 1 before irradiation and after each irradiation;

[0037] Fig. 9 Based on Figure 8 The relationship curves between threshold voltage and irradiation dose, and threshold voltage offset and irradiation dose are drawn based on the threshold voltage results in the experiment;

[0038] Fig.10 The drain current-gate-source voltage curves of the transistor of Example 1 before irradiation, after irradiation for 5 minutes, after irradiation for 10 minutes, and after irradiation for 15 minutes when a 0V bias voltage is applied to the gate;

[0039] Fig.11 The drain current-gate-source voltage curves of the transistor of Example 1 before irradiation and after irradiation for 5 minutes when a 10V bias voltage is applied to the gate;

[0040] Fig.12 The drain current-gate-source voltage curves of the transistor of Example 1 before irradiation and after irradiation for 5 minutes when a -10V bias voltage is applied to the gate;

[0041] Fig.13 The drain current-gate-source voltage curves of the transistor of Comparative Example 2 before irradiation, after 2 minutes of irradiation, after 4 minutes of irradiation, and after 6 minutes of irradiation;

[0042] Fig.14The drain current-gate-source voltage curves of the transistor of Comparative Example 2 are obtained by three measurements after irradiation for 6 minutes.

[0043] The reference numerals and their meanings are as follows:

[0044] 100, substrate; 110, gate; 120, gate dielectric layer; 121, dielectric material layer; 130, interface passivation layer; 131, passivation material layer; 140, channel layer; 141, channel material layer; 150, source; 160, drain. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0047] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0048] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] The disclosed embodiments are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing, and the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0051] The present disclosure provides a transistor X-ray detector, which includes a transistor, and the transistor includes: a gate, a gate dielectric layer, a heterojunction layer, a source electrode and a drain electrode. The gate dielectric layer is arranged between the gate and the heterojunction layer, the heterojunction layer includes an interface passivation layer and a channel layer, the material of the channel layer includes gallium oxide, the interface passivation layer is stacked and arranged between the gate dielectric layer and the channel layer, the source electrode and the drain electrode are electrically connected to the channel layer, and the source electrode and the drain electrode are spaced apart.

[0052] It can be understood that the components included in the transistor X-ray detector provided in the present disclosure can together form a transistor, and the X-ray detector in the present disclosure refers to an X-ray detector that uses the transistor as a functional component for detecting X-rays.

[0053] The working principle of traditional X-ray detectors is: when X-rays irradiate the transistor, ionization excitation occurs in the gate dielectric layer and causes ionization defects in the gate dielectric layer, which causes the threshold voltage of the transistor to shift. By measuring the shift of its threshold voltage, its irradiation dose can be obtained. However, traditional transistors mostly use silicon dioxide as the material of the gate dielectric layer and silicon as the material of the channel layer, and the detection sensitivity of the transistor is low. In addition, high-energy irradiation will also leave more permanent ionization damage in the gate dielectric layer and the channel layer, which greatly affects the service life of the device.

[0054] The sensitivity of the transistor X-ray detector refers to: the threshold voltage offset under a unit irradiation dose. The sensitivity of the transistor X-ray detector can be obtained by calculating the ratio of the threshold voltage offset to the irradiation dose.

[0055] The transistor X-ray detector provided by the present disclosure is significantly different from the traditional transistor X-ray detector in that a heterojunction layer is introduced into the heterojunction layer, which includes an interface passivation layer and a channel layer. The channel layer is made of gallium oxide material. The oxygen vacancy defects of the gallium oxide material will increase under the irradiation of X-rays, and the electrical properties of the channel layer will change accordingly, which causes the threshold voltage of the device to shift. Experiments show that compared with traditional technologies, the transistor X-ray detector has significantly higher detection sensitivity, and because its main principle of detecting X-rays is based on the change of oxygen vacancy defects in the heterojunction layer rather than ionization damage in the gate dielectric layer, it can also effectively improve the service life of the X-ray detector.

[0056] However, the interface defects between the gallium oxide material and the gate dielectric layer can cause the threshold voltage of the transistor to be unstable. The present invention introduces an interface passivation layer between the channel layer and the gate dielectric layer, and forms a heterojunction layer with the gallium oxide layer through the interface passivation layer and passivates the interface defects, thereby improving the problem of unstable threshold voltage of the transistor when a single layer of gallium oxide is used as the channel layer, and greatly improving the measurement stability of the transistor before and after irradiation.

[0057] It can be understood that a heterojunction is formed between the interface passivation layer and the gallium oxide channel layer, and the interface passivation layer is in direct contact with the channel layer. Its main function is to passivate defects at the interface of the gate dielectric layer, thereby avoiding the problem of unstable threshold voltage generated when the gallium oxide channel layer is in direct contact with the gate dielectric layer.

[0058] It is understood that the material of the channel layer of the present disclosure includes gallium oxide, and the gallium oxide should be broadly understood on the basis of pure gallium oxide (Ga2O3). For example, the gallium oxide can be a pure gallium oxide material, or a gallium oxide material with certain doping elements, such as aluminum-doped gallium oxide material. This does not affect the implementation of the present disclosure.

[0059] In order to facilitate understanding of the transistor X-ray detector of the present disclosure, Figure 1 The specific structure of one of the transistor X-ray detectors is shown in FIG. Figure 1 As shown, the transistor X-ray detector includes: a substrate 100, a gate 110, a gate dielectric layer 120, a heterojunction layer, a source 150 and a drain 160. The gate dielectric layer 120 is disposed between the gate 110 and the heterojunction layer, the heterojunction layer includes an interface passivation layer 130 and a channel layer 140, the material of the channel layer 140 includes gallium oxide, the interface passivation layer 130 is stacked between the gate dielectric layer 120 and the channel layer 140, the source 150 and the drain 160 are electrically connected to the channel layer 140, and the source 150 and the drain 160 are spaced apart from each other.

[0060] Further, based on Figure 1 In the orientation shown, the gate 110 is disposed on the substrate 100, the gate dielectric layer 120 is stacked on the gate 110, the interface passivation layer 130 in the heterojunction layer is stacked on the gate dielectric layer 120, and the channel layer 140 in the heterojunction layer is stacked on the interface passivation layer 130. The source 150 is in direct contact with the channel layer 140 to achieve electrical connection, and the drain 160 is also in direct contact with the channel layer 140 to achieve electrical connection, and the source 150 and the drain 160 are spaced apart.

[0061] In this embodiment, the material of the channel layer 140 includes gallium oxide. Oxygen vacancy defects may exist in the gallium oxide channel layer 140 so that it has an appropriate carrier concentration.

[0062] In some examples of this embodiment, the carrier concentration of the interface passivation layer 130 is higher than that of the channel layer 140. Designing the interface passivation layer 130 with a higher carrier concentration produces a better passivation effect on the surface of the channel layer 140 close to the gate dielectric layer 120, thereby ensuring the long-term use stability of the transistor X-ray detector.

[0063] In some examples of this embodiment, in the heterojunction layer, the carrier concentration in the interface passivation layer 130 may be 1×10 18 cm -3 ~1×10 23 cm -3 Setting the carrier concentration within this range can effectively restrain the defects at the interface of the channel layer 140. Further, the carrier concentration in the interface passivation layer 130 can be 3×10 18 cm -3 ~5×10 20 cm -3 .

[0064] In some examples of this embodiment, in the heterojunction layer, the carrier concentration of the channel layer 140 may be 1×10 13 cm -3 ~1×10 18 cm -3 .

[0065] In some examples of this embodiment, the material of the interface passivation layer 130 may be selected from conductive metal oxides. For example, the material of the interface passivation layer 130 may be selected from one or more of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and indium tin oxide (ITO). In this embodiment, the material of the interface passivation layer 130 is indium gallium zinc oxide.

[0066] In some examples of this embodiment, the thickness of the interface passivation layer 130 is 1nm to 6nm. The interface passivation layer 130 is mainly used to passivate the interface of the gallium oxide channel layer 140. The thickness of the interface passivation layer 130 is controlled to be thin, which can ensure the passivation effect while avoiding the change of the electrical properties of the channel layer 140 caused by the introduction of the interface passivation layer 130 as much as possible. In a further example, the thickness of the interface passivation layer 130 can be 1nm to 3nm.

[0067] The thickness of the interface passivation layer 130 may be uniform. However, it is understood that, due to the actual preparation process, the thickness of the interface passivation layer 130 may be non-uniform, for example, the thickness of a part of the interface passivation layer 130 is thicker than that of other parts of the interface passivation layer 130, but the interface passivation layer 130 still has the function of interface passivation.

[0068] In some examples of this embodiment, the thickness of the channel layer 140 is 15nm to 60nm. When the transistor is irradiated by X-rays, the change in the concentration of oxygen vacancy defects in the channel layer 140 with a thickness of 15nm to 60nm can make the threshold voltage shift of the transistor more obvious and easier to observe.

[0069] In some examples of this embodiment, the substrate 100 may be a quartz substrate 100. In other embodiments, the substrate 100 may also be other materials as long as they can be used to support the transistor structure located on the substrate 100.

[0070] In some examples of this embodiment, the material of the gate 110 may be a conductive material, such as a metal material. In further examples, the metal material may be one or more of chromium, copper, tungsten, aluminum, and silver. In this embodiment, the material of the gate 110 may be chromium.

[0071] In some examples of this embodiment, the thickness of the gate 110 may be 10 nm to 100 nm. In a further example, in order to ensure the conductivity of the gate 110 while reducing the impact on other layers located above, the thickness of the gate 110 is 30 nm to 50 nm. In this embodiment, the thickness of the gate 110 may be 30 nm to 40 nm.

[0072] It can be understood that the gate dielectric layer 120 is used to insulate the gate 110 and the channel layer 140, so the material of the gate dielectric layer 120 is an insulating material. In some examples of this embodiment, the material of the gate dielectric layer 120 can be one or more of silicon oxide and aluminum oxide. In a further example, the material of the gate dielectric layer 120 can be aluminum oxide.

[0073] In some examples of this embodiment, the thickness of the gate dielectric layer 120 is ≤100nm. It is understood that when irradiated by X-rays, ionization defects will also be generated in the gate dielectric layer 120. Controlling the thickness of the gate dielectric layer 120 to be ≤100nm can reduce the ionization defects in the gate dielectric layer 120 and minimize the contribution of the ionization defects of the gate dielectric layer 120 to the threshold voltage shift. In a further example, the thickness of the gate dielectric layer 120 is 30nm to 100nm. In this embodiment, the thickness of the gate dielectric layer 120 can be 60nm.

[0074] In some examples of this embodiment, the material of the source 150 and the drain 160 may be a conductive material, such as a metal material. In further examples, the metal material may be one or more of titanium, tungsten, aluminum, silver, and gold. In this embodiment, the material of the source 150 and the drain 160 may be a stacked film of titanium and gold.

[0075] In some examples of this embodiment, the thickness of the source 150 and the drain 160 may be 30nm to 100nm, respectively. In further examples, the thickness of the source 150 and the drain 160 is 30nm to 60nm. In this embodiment, the thickness of the source 150 and the drain 160 may be 50nm. For example, the source 150 and the drain 160 may include a gold film layer with a thickness of 20nm and a titanium film layer with a thickness of 30nm.

[0076] Understandably, Figure 1 The structure of the transistor X-ray detector shown actually has the structure of a thin film transistor, which can be obtained by depositing a thin film and etching it, and its preparation method is relatively simple. In other embodiments, the transistor X-ray detector can also have other forms of transistor structures, which will not be described in detail here.

[0077] In some examples of this embodiment, the transistor X-ray detector further includes a threshold voltage detection mechanism, the threshold voltage detection mechanism is electrically connected to the transistor, and the threshold voltage detection mechanism is used to measure the threshold voltage of the transistor.

[0078] The present disclosure also provides a preparation Figure 1 The transistor X-ray detector method is shown. Figure 2 The schematic diagram of the steps of the preparation method is shown, referring to Figure 2 As shown, the preparation method includes steps S1 to S6.

[0079] Step S1, providing a substrate 100.

[0080] Figure 3 A schematic structural diagram of a provided substrate 100 is shown.

[0081] In some examples of this embodiment, the substrate 100 may be a quartz substrate 100. In other embodiments, the substrate 100 may also be other materials as long as it can be used for preparing other structures located thereon in the subsequent process.

[0082] In this embodiment, the step of providing the substrate 100 also includes the step of ultrasonically cleaning the substrate 100. For example, acetone and isopropanol are used to ultrasonically clean the substrate 100. In a further example, after cleaning the substrate 100, nitrogen is used to blow dry the substrate 100 to obtain a substrate 100 that is as clean as possible.

[0083] Step S2 , forming a gate 110 on the surface of the substrate 100 .

[0084] Figure 4 Shown in Figure 3 The schematic diagram of the structure of the gate 110 is prepared based on the structure shown in FIG. Figure 4 As shown, the gate 110 is stacked on the substrate 100 .

[0085] In some examples of this embodiment, the material of the gate 110 may be chromium. The step of preparing the gate 110 includes: depositing a chromium film on the substrate 100 , and then patterning the deposited chromium film by etching to form the gate 110 .

[0086] The chromium film may be deposited on the substrate 100 by physical vapor deposition, such as evaporation or sputtering.

[0087] In the step of patterning the deposited chromium film, a layer of photoresist may be first prepared on the surface of the chromium film, and then the photoresist may be exposed and developed to obtain a patterned photoresist, and then the chromium film prepared by photoresist etching may be used to form the gate 110 .

[0088] In some examples of this embodiment, when preparing the gate 110 , the thickness of the chromium film can be controlled to be 30 nm to 40 nm.

[0089] Step S3 , sequentially preparing a dielectric material layer 121 , a passivation material layer 131 and a channel material layer 141 on the substrate 100 .

[0090] Figure 5 Shown in Figure 4 A schematic diagram of a structure in which a dielectric material layer 121, a passivation material layer 131 and a channel material layer 141 are prepared based on the structure shown in FIG. Figure 5 As shown, the dielectric material layer 121 , the passivation material layer 131 and the channel material layer 141 are sequentially stacked on the substrate 100 from bottom to top.

[0091] In this embodiment, the material of the dielectric material layer 121 may be aluminum oxide. The dielectric material layer 121 may be prepared by atomic layer deposition.

[0092] In this embodiment, the thickness of the dielectric material layer 121 may be ≤100 nm. For example, the thickness of the dielectric material layer 121 is 100 nm.

[0093] Reference Figure 5 As shown, since the gate 110 is patterned, part of the substrate 100 is not covered by the gate 110. In this step, a dielectric material layer 121 may be prepared on the substrate 100 not covered by the gate 110.

[0094] In this embodiment, the material of the passivation material layer 131 may be indium gallium zinc oxide. The passivation material layer 131 may be prepared by physical vapor deposition. Further, the passivation material layer 131 may be prepared by radio frequency magnetron sputtering.

[0095] In some examples of this embodiment, the passivation material layer 131 is deposited in a gas environment without oxygen, so that the passivation material layer 131 contains oxygen vacancy defects and thus increases its carrier concentration. The gas environment without oxygen can be a vacuum or a protective gas without oxygen. For example, the passivation material layer 131 can be deposited in a gas environment of pure argon.

[0096] In this embodiment, the thickness of the passivation material layer 131 may be 1 nm to 3 nm.

[0097] In this embodiment, the material of the channel material layer 141 may be gallium oxide. The channel material layer 141 may be prepared by physical vapor deposition. Further, the passivation material layer 131 may be prepared by radio frequency magnetron sputtering.

[0098] In some examples of this embodiment, the channel material layer 141 is deposited in a gas environment without oxygen, so that oxygen defects are contained in the channel material layer 141. The gas environment without oxygen can be a vacuum or a protective gas without oxygen. For example, the channel material layer 141 can be deposited in a gas environment of pure argon.

[0099] In this embodiment, the thickness of the channel material layer 141 may be 15 nm to 60 nm. Further, in this embodiment, the thickness of the channel material layer 141 is 30 nm.

[0100] In some examples of this embodiment, the materials in the prepared passivation material layer 131 and the channel material layer 141 are amorphous materials. For example, the material of the passivation material layer 131 is amorphous indium gallium zinc oxide, and the material of the channel material layer 141 is amorphous gallium oxide. Amorphous materials do not have clear grain boundaries, which facilitates the migration of oxygen vacancy defects and carriers, and has a higher defect tolerance, thereby obtaining better device performance than crystalline materials.

[0101] Step S4, etching the dielectric material layer 121, the passivation material layer 131 and the channel material layer 141 in sequence.

[0102] Figure 6 Shown in Figure 5 A schematic structural diagram of etching the dielectric material layer 121, the passivation material layer 131 and the channel material layer 141 on the basis of the structure shown in the figure to form a gate dielectric layer 120, an interface passivation layer 130 and a channel layer 140 respectively.

[0103] In some examples of this embodiment, the etching of the channel material layer 141 and the passivation material layer 131 may be performed based on the same pattern. For example, a layer of photoresist is first prepared on the surface of the channel material layer 141, and then the photoresist is exposed and developed to obtain a patterned photoresist, and then the channel material layer 141 and the passivation material layer 131 are sequentially etched based on the photoresist to form the channel layer 140 and the interface passivation layer 130, respectively.

[0104] Furthermore, in the step of etching the channel material layer 141, a suitable etchant may be selected to stop etching on the passivation material layer 131 or the dielectric material layer 121. When etching the passivation material layer 131, a suitable etchant may be selected to stop etching on the dielectric material layer 121.

[0105] In some examples of this embodiment, an etchant including tetramethylammonium hydroxide is used to etch the channel material layer 141, an etchant including dilute hydrochloric acid is used to etch the passivation material layer 131, and an etchant including phosphoric acid is used to etch the dielectric material layer 121. Further, when etching the dielectric material layer 121, heating can be used to promote etching.

[0106] Step S5, preparing the source electrode 150 and the drain electrode 160.

[0107] The source electrode 150 and the drain electrode 160 are formed on the gate dielectric layer 120 and the channel layer 140 .

[0108] It is understood that the materials of the source electrode 150 and the drain electrode 160 can be the same, so there is no need to distinguish them in the actual preparation process. In some examples of this embodiment, a photoresist can be firstly spin-coated on the substrate 100 and patterned, and then a layer of source and drain material layer is deposited, and then the photoresist and the redundant source and drain material layer thereon are removed to form the source electrode 150 and the drain electrode 160 respectively.

[0109] In this embodiment, the source and drain material layer may include a stacked titanium film layer and a gold film layer. In the actual preparation process, the titanium film layer and the gold film layer may be deposited in sequence by radio frequency magnetron sputtering.

[0110] In this embodiment, the thickness of the titanium film layer can be controlled to be 20 nm, and the thickness of the gold film layer can be controlled to be 30 nm.

[0111] It can be understood that the process of preparing the source electrode 150 and the drain electrode 160 also includes a step of removing redundant structures (such as photoresist) on the substrate 100 to obtain the structure of the thin film transistor.

[0112] Step S6 , performing annealing treatment on the channel layer 140 .

[0113] It can be understood that since the channel layer 140 is prepared on the substrate 100 , in the actual preparation process, the substrate 100 together with the structure that has been prepared above the substrate 100 can be annealed.

[0114] In this embodiment, the step of annealing the channel layer 140 is performed in a gas environment containing oxygen atoms to reduce oxygen vacancy defects in the channel layer 140. It can be understood that the oxygen atoms in the gas environment should be able to enter the channel layer 140 during the annealing process so that the oxygen vacancy defects in the channel layer 140 are reduced.

[0115] In some examples of this embodiment, the gas environment containing oxygen atoms may be oxygen, air, or other suitable oxidizing gases.

[0116] In some examples of this embodiment, the temperature during the annealing process can be controlled to be 200°C to 500°C. Among them, controlling the annealing temperature to be above 200°C can ensure that the oxygen vacancy defects in the channel layer 140 are relatively fully repaired, which can not only ensure the normal on and off of the transistor device, but also help to improve the sensitivity of the transistor to X-ray irradiation. Controlling the annealing temperature to be below 500°C can avoid the crystallization of the channel layer 140 material as much as possible, and ensure the electrical properties and radiation resistance of the channel layer 140. In a further example, the temperature during the annealing process can be controlled to be 220°C to 400°C. Further, the temperature during the annealing process can be controlled to be 250°C to 400°C.

[0117] In some examples of this embodiment, the time during the annealing process can be controlled to be 10 minutes to 120 minutes. In further examples, the time during the annealing process can be controlled to be 30 minutes to 60 minutes.

[0118] It can be understood that through steps S1 to S6, the following can be prepared: Figure 1 The transistor X-ray detector shown.

[0119] Furthermore, the present disclosure also provides an X-ray detection method, which uses the transistor X-ray detector provided by the present disclosure for detection. During detection, the radiation dose received by the transistor X-ray detector is determined by monitoring the offset of the turn-on voltage of the transistor X-ray detector before and after detection.

[0120] Among them, since the detection principle of the present invention is based on the fact that X-rays will increase the threshold voltage of the transistor, and high-energy X-rays will increase the oxygen vacancy defects in the channel layer, if a bias voltage is applied to the gate during this process, it may cause a substantial increase in oxygen vacancy defects in the channel layer, and even cause the channel layer to fail. Therefore, no bias voltage may be applied to the gate during the irradiation process, that is, the gate is empty. By measuring the offset of the threshold voltage before and after irradiation, the irradiation dose of the X-ray can be obtained. If a certain bias voltage is applied during the detection process, the detection accuracy of the transistor X-ray detector will be reduced, and the service life will be greatly shortened. In addition, the use of the gate emptying method can also help reduce the energy consumption of the transistor X-ray detector.

[0121] It can be understood that there is a certain regularity between the offset of the threshold voltage of the transistor X-ray detector and the irradiation dose, such as a linear relationship. Before use, one of the transistors can be used for experiments to determine the relationship between the offset of the threshold voltage and the irradiation dose, i.e. calibration. The calibration results can be used for other transistors to determine the irradiation dose by the offset of the threshold voltage.

[0122] In order to facilitate the understanding of the transistor X-ray detector in the present disclosure, the present disclosure also provides the following embodiments and comparative examples to facilitate the understanding of the implementation and advantages of the transistor X-ray detector.

[0123] Example 1

[0124] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0125] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0126] The substrate is placed in an atomic layer deposition chamber to deposit an aluminum oxide film with a thickness of about 60 nm, and then transferred to a radio frequency magnetron sputtering chamber to deposit an indium gallium zinc oxide film with a thickness of about 2 nm and a gallium oxide film with a thickness of about 30 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon;

[0127] The gallium oxide film, the indium gallium zinc oxide film and the aluminum oxide film are patterned in sequence by etching to obtain a gallium oxide channel layer, an interface passivation layer and a gate dielectric layer respectively;

[0128] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20 nm and a gold film with a thickness of about 30 nm are sequentially deposited, and excess photoresist and metal materials are removed to obtain a source electrode and a drain electrode;

[0129] The substrate was transferred to a hot plate at 400°C and annealed for 30 min to obtain a transistor; the carrier concentration of the interface passivation layer was 10 20 cm -3 .

[0130] Example 2

[0131] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0132] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0133] The substrate is placed in an atomic layer deposition chamber to deposit an aluminum oxide film with a thickness of about 60 nm, and then transferred to a radio frequency magnetron sputtering chamber to deposit an indium gallium zinc oxide film with a thickness of about 2 nm and a gallium oxide film with a thickness of about 30 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon;

[0134] The gallium oxide film, the indium gallium zinc oxide film and the aluminum oxide film are patterned in sequence by etching to obtain a gallium oxide channel layer, an interface passivation layer and a gate dielectric layer respectively;

[0135] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20 nm and a gold film with a thickness of about 30 nm are sequentially deposited, and excess photoresist and metal materials are removed to obtain a source electrode and a drain electrode;

[0136] The substrate was transferred to a hot plate at 250°C and annealed for 30 min to obtain a transistor; the carrier concentration of the interface passivation layer was 10 19 cm -3 .

[0137] Example 3

[0138] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0139] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0140] The substrate is placed in an atomic layer deposition chamber to deposit an aluminum oxide film with a thickness of about 60 nm, and then transferred to a radio frequency magnetron sputtering chamber to deposit an indium zinc oxide film with a thickness of about 2 nm and a gallium oxide film with a thickness of about 30 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon;

[0141] The gallium oxide film, the indium zinc oxide film and the aluminum oxide film are patterned in sequence by etching to obtain a gallium oxide channel layer, an interface passivation layer and a gate dielectric layer respectively;

[0142] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20 nm and a gold film with a thickness of about 30 nm are sequentially deposited, and excess photoresist and metal materials are removed to obtain a source electrode and a drain electrode;

[0143] The substrate was transferred to a hot plate at 400°C and annealed for 30 min to obtain a transistor; the carrier concentration of the interface passivation layer was 10 21 cm -3 .

[0144] Comparative Example 1

[0145] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0146] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0147] An aluminum oxide film with a thickness of about 60 nm is deposited in an atomic layer deposition chamber on the substrate, and then transferred to a radio frequency magnetron sputtering chamber to deposit a gallium oxide film with a thickness of about 30 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon;

[0148] The gallium oxide film and the aluminum oxide film are patterned in sequence by etching to obtain a gallium oxide channel layer and a gate dielectric layer respectively;

[0149] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20nm and a gold film with a thickness of about 30nm are deposited in sequence, and the excess photoresist and metal material are removed to obtain the source and drain.

[0150] The threshold voltage of the transistor prepared in Comparative Example 1 is unstable. Even without irradiation, there is a significant deviation between the threshold voltages measured once and once, and the transistor cannot be used as a stable device.

[0151] Comparative Example 2

[0152] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0153] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0154] An aluminum oxide film with a thickness of about 60 nm is deposited in an atomic layer deposition chamber on the substrate, and then transferred to a radio frequency magnetron sputtering chamber to deposit a low-resistivity indium gallium zinc oxide film with a thickness of about 2 nm and a high-resistivity indium gallium zinc oxide film with a thickness of about 30 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon gas and an oxygen-argon mixed gas respectively;

[0155] The high-resistivity indium gallium zinc oxide film, the low-resistivity indium gallium zinc oxide film and the aluminum oxide film are patterned in sequence by etching to obtain a channel layer and a gate dielectric layer composed of high-resistivity and low-resistivity indium gallium zinc oxide, respectively;

[0156] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20 nm and a gold film with a thickness of about 30 nm are sequentially deposited, and excess photoresist and metal materials are removed to obtain a source electrode and a drain electrode;

[0157] The substrate was transferred to a hot plate at 200°C and annealed for 30 minutes to obtain a transistor; the carrier concentration of the low-resistivity indium gallium zinc oxide film was 10 20 cm -3 The carrier concentration of high resistivity InGaZnO thin film is 10 16 cm -3 .

[0158] Comparative Example 3

[0159] The quartz substrate was ultrasonically cleaned with acetone and isopropanol for 8 min, then dried with a nitrogen gun and placed in a radio frequency magnetron sputtering chamber;

[0160] A chromium film with a thickness of 30 nm is plated on the substrate and patterned by etching to obtain a gate;

[0161] An aluminum oxide film with a thickness of about 400 nm is deposited in an atomic layer deposition chamber on the substrate, and then transferred to a radio frequency magnetron sputtering chamber to deposit an indium gallium zinc oxide film with a thickness of about 32 nm. The gas environment in the radio frequency magnetron sputtering chamber is argon;

[0162] The indium gallium zinc oxide film and the aluminum oxide film are patterned in sequence by etching to obtain an indium gallium zinc oxide channel layer and a gate dielectric layer respectively;

[0163] A layer of photoresist is spin-coated on the substrate and patterned, and then a titanium film with a thickness of about 20 nm and a gold film with a thickness of about 30 nm are sequentially deposited, and excess photoresist and metal materials are removed to obtain a source electrode and a drain electrode;

[0164] The substrate was transferred to a hot plate at 400°C for annealing for 30 minutes to obtain a transistor; the carrier concentration of the indium gallium zinc oxide film was 10 17 cm -3 .

[0165] The transistors of the above embodiments and comparative examples were irradiated under X-rays. In the following tests, unless otherwise specified, the voltage of the X-ray source was 30 kV and the current was 200 μA.

[0166] Experiment 1: The transistor of Example 1 was used, the gate, source and drain were all empty, and placed under X-ray irradiation. A voltage of 1V was applied between the source and drain, and three measurements were performed before irradiation and three measurements were performed after irradiation. The change in the threshold voltage of the transistor was recorded for each measurement. The test results can be found in Figure 7 . Figure 7 The drain current-gate-source voltage curves of the transistor of Example 1 measured multiple times before and after irradiation are recorded in FIG.

[0167] Reference Figure 7 As shown in the figure, the characteristic curves of the transistor in the three measurements before irradiation are basically the same, and in the three measurements after irradiation, the characteristic curves are also basically the same. This shows that the threshold voltage of the device is very stable and there is basically no random drift.

[0168] Experiment 2: The transistor of Example 1 is used, the gate, source and drain are all empty, and the transistor is irradiated multiple times, each irradiation lasts for 120 seconds. A voltage of 1V is applied between the source and the drain, and the drain current-gate-source voltage curve is recorded before irradiation and after each irradiation, which can be seen in Figure 8 .tidy Figure 8 The threshold voltage results in the plots of threshold voltage vs. irradiation dose, and threshold voltage offset vs. irradiation dose, can be seen in Fig. 9 .

[0169] Reference Fig. 9 As shown in Figure 2, with the increase of irradiation dose, the threshold voltage offset of the transistor approximately presents two linear relationships. Fig. 9 Calculation shows that when the irradiation dose is approximately 0mGy to 24mGy, the sensitivity of the transistor is 102.9V / Gy; when the irradiation dose is approximately 24mGy to 65mGy, the sensitivity of the transistor is 45.9V / Gy. The sensitivity is obtained by calculating the ratio between the threshold voltage offset and the irradiation dose. The transistors of Examples 2 to 3 have similar sensitivities to the transistor of Example 1, which will not be described in detail.

[0170] Experiment 3: The three transistors of Example 3 were used to irradiate the transistors with X-rays. During the irradiation process, 0V bias voltage (empty), 10V bias voltage, and -10V bias voltage were applied to the gates of the three transistors. A voltage of 1V was applied between the source and the drain, and the drain current-gate-source voltage curves were recorded before irradiation, after 5 minutes of irradiation, after 10 minutes of irradiation, and after 15 minutes of irradiation. The results can be seen in Figure 10 to Figure 12 . Fig.10 For a transistor with a gate bias voltage of 0V applied, Fig.11 For a transistor with a gate bias voltage of 10V, Fig.12 Corresponds to a transistor with a -10V bias voltage applied to the gate.

[0171] Reference Fig.10 As shown in Figure 1, when a 0V bias voltage is applied to the gate, the threshold voltage shift of the transistor is 5V after 5 minutes of irradiation. Fig.11 As shown in Figure 2, when a 10V bias voltage is applied to the gate, the threshold voltage shift of the transistor is greater than 15V after 5 minutes of irradiation. Fig.12 As shown in Figure 2, when a -10V bias voltage is applied to the gate, the threshold voltage shift of the transistor is close to 10V after 5 minutes of irradiation. Figure 10 to Figure 12 It can be seen that during the test irradiation process, the gate voltage bias state can effectively change the response sensitivity of the transistor.

[0172] Experiment 4: The transistor of comparative example 2 was used, the gate was left blank, and it was placed under X-ray irradiation. A voltage of 1V was applied between the source and the drain, and the drain current-gate-source voltage curves of the transistor were recorded before irradiation, after 2 minutes of irradiation, after 4 minutes of irradiation, and after 6 minutes of irradiation. The results can be seen in Fig.13 In addition, the transistor drain current-gate source voltage curve was measured three times after 6 minutes of irradiation. The results can be seen in Fig.14 .

[0173] Reference Fig.13 As shown, the threshold voltage position of the transistor of Comparative Example 2 is basically unchanged after irradiation for 2 minutes, 4 minutes, and 6 minutes, and combined with Fig.14 As shown, there are large deviations between the threshold voltages of the transistor in the three additional tests performed after 6 minutes of irradiation, indicating that the transistor cannot quantitatively characterize the intensity of the irradiation dose.

[0174] Experiment 5: The sensitivity of the transistor of Comparative Example 3 was tested, and the result was about 1.2V / Gy. This is mainly because the indium gallium zinc oxide channel layer in the transistor of Comparative Example 3 is not suitable for measuring the irradiation intensity. Comparative Example 3 still uses the gate dielectric layer as the main response source for X-ray irradiation, and its detection sensitivity is significantly lower. The sensitivity of the transistor in Example 1 is 1 to 2 orders of magnitude higher than that of such a conventional transistor, indicating that the transistor X-ray detector provided by the present disclosure has a very significant improvement in sensitivity performance.

[0175] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0176] It should be understood that, unless otherwise specified herein, the execution of the steps of the preparation method is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps of the preparation method may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0177] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0178] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A transistor X-ray detector, characterized in that: A transistor is included, wherein the transistor includes: a gate, a gate dielectric layer, a heterojunction layer, a source electrode and a drain electrode; The gate dielectric layer is arranged between the gate and the heterojunction layer, the heterojunction layer includes an interface passivation layer and a channel layer, the channel layer is a gallium oxide channel layer, the interface passivation layer and the channel layer form a heterojunction, the interface passivation layer is stacked between the gate dielectric layer and the channel layer, the source and the drain are electrically connected to the channel layer, and the source and the drain are spaced apart.

2. The transistor X-ray detector according to claim 1, characterized in that: The carrier concentration of the interface passivation layer is higher than the carrier concentration of the channel layer.

3. The transistor X-ray detector according to claim 2, characterized in that: The carrier concentration of the interface passivation layer is 1×10 18 cm -3 ~1×10 23 cm -3 ; and / or, the carrier concentration of the channel layer is 1×10 13 cm -3 ~1×10 18 cm -3 .

4. The transistor X-ray detector according to any one of claims 1 to 3, characterized in that: It also includes a substrate; the gate is arranged on the substrate, the gate dielectric layer is stacked on the gate, the interface passivation layer, the source and the drain are all arranged on the gate dielectric layer, and the channel layer is arranged on the interface passivation layer.

5. The transistor X-ray detector according to claim 4, characterized in that: The thickness of the interface passivation layer is 1 nm to 6 nm; and / or, The thickness of the channel layer is 15nm to 60nm; and / or, The thickness of the gate dielectric layer is ≤100 nm.

6. The transistor X-ray detector according to claim 4, characterized in that: The material of the interface passivation layer is selected from one or more of indium gallium zinc oxide, indium zinc oxide and indium tin oxide.

7. The transistor X-ray detector according to any one of claims 1 to 3 and 5 to 6, characterized in that: It also includes a threshold voltage detection mechanism, which is electrically connected to the transistor and is used to measure the threshold voltage of the transistor.

8. The method for preparing a transistor X-ray detector according to any one of claims 1 to 7, characterized in that: The steps include: Preparing the gate and the gate dielectric layer on a substrate; Depositing the material of the interface passivation layer and the material of the channel layer on the gate dielectric layer to form the heterojunction layer; and, The source electrode and the drain electrode are prepared on the heterojunction layer.

9. The method for preparing a transistor X-ray detector according to claim 8, characterized in that: Depositing the material of the interface passivation layer comprises: depositing the material of the interface passivation layer in a gas environment free of oxygen by physical vapor deposition; and / or, Depositing the material of the channel layer comprises: depositing the material of the channel layer in a gas environment without oxygen by physical vapor deposition; After depositing the material of the channel layer, the method further includes: annealing the deposited material of the channel layer in an oxidizing gas environment containing oxygen atoms to reduce oxygen vacancy defects therein.

10. The method for preparing a transistor X-ray detector according to claim 9, characterized in that: Controlling the temperature during the annealing process to be 200° C. to 500° C.; and / or, The time during the annealing process is controlled to be 10 minutes to 120 minutes.

Images