Ultra-low clock power multi-bit flip-flop using unidirectional device

Abstract

The invention provides an ultra-low clock power multi-bit flip-flop using a unidirectional device. Embodiments herein relate to a multi-bit flip-flop circuit that uses unidirectional transistors to allow sharing of transistors between a set of flip-flops while avoiding charge sharing within or between flip-flops. Clock devices in a circuit may be shared to reduce clock transistor gate capacitance and associated power consumption. A shared transistor may provide a holder circuit and / or a tri-state inverter in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state holder sharing. Another example implementation uses a tri-state retainer and / or transfer gate sharing. Another example implementation uses transfer gate sharing without a holder.

Description

Technical Field

[0001] The present application relates generally to the field of flip-flops and, more particularly, to reducing power consumption in multi-bit flip-flop circuits. Background Art

[0002] Flip-flop circuits, also known as flip-flops, are the basic components of sequential logic circuits in computing devices. A flip-flop consists of one or more latches, each of which stores a bit of data in a storage node, where the value of the bit is represented by one of two stable states. The flip-flop also receives a clock signal that indicates when to latch and output data. However, reducing the power consumed by flip-flops has been a challenge. Summary of the invention

[0003] One aspect of the present disclosure provides an apparatus, comprising: a plurality of flip-flops, wherein each of the plurality of flip-flops comprises an internal device and a storage node; and a shared device shared by the plurality of flip-flops, wherein for each of the plurality of flip-flops, the internal device is coupled to the shared device, and the combination of the internal device and the shared device is part of a keeper circuit capable of maintaining a value in the storage node, wherein the internal device and the shared device comprise unidirectional transistors.

[0004] Another aspect of the present disclosure provides a trigger. The trigger includes: a storage node; and a first p-type FET connected in series with a first n-type field effect transistor (FET); wherein: the storage node is coupled to drain terminals of the first p-type FET and the first n-type FET; the first p-type FET is connected in series with a shared p-type FET, and the shared p-type FET is coupled to at least one other trigger; the first n-type FET is connected in series with a shared n-type FET, and the shared n-type FET is coupled to at least one other trigger; and the first p-type FET, the first n-type FET, and the shared p-type FET and the shared n-type FET include unidirectional transistors.

[0005] Another aspect of the present disclosure provides a trigger. The trigger includes: a first storage node; a second storage node; and a first p-type FET connected in series with a first n-type field effect transistor (FET); and a second p-type FET connected in series with a second n-type FET, wherein: an output node between the first p-type FET and the first n-type FET is coupled to the first storage node; the first p-type FET is connected in series with a first shared p-type FET coupled to at least one other trigger, and is connected in series with a first shared n-type FET coupled to at least one other trigger; an output node between the second p-type FET and the second n-type FET is coupled to the second storage node; and the second p-type FET is connected in series with a second shared p-type FET coupled to at least one other trigger, and is connected in series with a second shared n-type FET coupled to at least one other trigger.

[0006] Another aspect of the present disclosure provides a method, which includes receiving data bits at a plurality of flip-flops, wherein each flip-flop includes a storage node to store the respective data bits, and at the storage node of each flip-flop, strengthening the value of the data bit using an internal device of the flip-flop and a shared device shared by the plurality of flip-flops, wherein the internal device and the shared device include unidirectional transistors.

[0007] Another aspect of the present disclosure provides a non-transitory machine-readable storage medium, including machine-readable instructions. These instructions, when executed, cause a processor or other circuit or computing device to perform a method. The method includes: receiving data bits at a plurality of flip-flops, wherein each flip-flop includes a storage node to store each data bit; and at the storage node of each flip-flop, using an internal device of the flip-flop and a shared device shared by a plurality of flip-flops, to strengthen the value of the data bit, wherein the internal device and the shared device include unidirectional transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of the present disclosure will be more fully understood through the detailed description given below and through the drawings of various embodiments of the present disclosure, however the detailed description and drawings should not be understood as limiting the present disclosure to specific embodiments but are only for illustration and understanding.

[0009] Figure 1A An example multi-bit flip-flop circuit 100 using bidirectional field effect transistors (FETs) is depicted in accordance with various embodiments.

[0010] Figure 1B Depicted are various embodiments Figure 1A An example implementation of trigger 150 is provided.

[0011] Figure 2A Depicted are example configurations of bidirectional FETs where no charge sharing occurs, according to various embodiments.

[0012] Figure 2B Depicted are example configurations of bidirectional FETs in which charge sharing occurs in accordance with various embodiments.

[0013] Figure 2C Depicted are example configurations of unidirectional FETs where no charge sharing occurs, according to various embodiments.

[0014] Figure 3 An example multi-bit flip-flop circuit 300 using unidirectional FETs and with tri-state holder sharing is depicted in accordance with various embodiments.

[0015] Figure 4A Depicted is a schematic diagram of a circuit having tri-state holder sharing according to various embodiments. Figure 3An example implementation of trigger 350 is provided.

[0016] Figure 4B Depicted are various embodiments of Figure 4A An example first subset of consistent shared keeper devices.

[0017] Figure 4C Depicted are various embodiments of Figure 4A An example second subset of consistent shared keeper devices.

[0018] Figure 5 An example multi-bit flip-flop circuit 500 using unidirectional FETs and having tri-state holders and / or pass gate sharing is depicted in accordance with various embodiments.

[0019] Figure 6 Depicted is a schematic diagram of a circuit having tri-state holders and pass gate sharing according to various embodiments. Figure 5 An example implementation of trigger 550 is provided.

[0020] Figure 7 Depicted are various embodiments Figure 6 2 is an example configuration of a first tri-state inverter (TSI1) and a second tri-state inverter (TSI2) of a flip-flop 550.

[0021] Figure 8 Depicted are various embodiments of Figure 5 Another example implementation of flip-flop 550 is flip-flop 850 with transfer gate sharing and no keeper.

[0022] Fig. 9 Illustrations illustrate examples of components that may be present in a computing system 950 for implementing the techniques (eg, operations, processes, methods, and approaches) described herein. DETAILED DESCRIPTION

[0023] As mentioned at the outset, there are various challenges in reducing the power consumed by flip-flops in computing devices.

[0024] Triggers are ubiquitous in many types of computing devices, including power-constrained server / mobile microprocessors, discrete or integrated graphics processors, and artificial intelligence (AI) / machine learning accelerators. These processors / accelerators may be arranged, for example, in a system-in-package (SiP), system-on-a-chip (SoC), or stacked tile / chiplet design that includes multiple integrated circuits / chips in the same package. In these and other devices, clocking is one of the most important power contributors and limiters.

[0025] Reducing power in computing systems with tight power budgets improves performance by allowing the integration of more processor cores, memory, and other processing elements, and improves battery life in mobile and edge network devices.

[0026] Specifically, dynamic clocking power is the largest contributor to overall chip power dissipation and consumes up to 60% of it, most of which is loaded in the final flip-flop. The flip-flop is a basic circuit used in all digital synchronous systems and must be very low-power because it contributes the most to the clocking power. Typically, flip-flops utilize devices of the smallest size and cannot be further reduced in size to reduce power. In addition, as process technology scales, circuits are limited by variations to achieve low-voltage operation for high energy efficiency. This limits the minimum allowable device size, preventing any further dynamic power savings from being obtained through transistor size settings. Since performance, power, and area (PPA) benefits are slowing down as process technology scales to smaller sizes, circuit innovations are needed to improve PPA, specifically to reduce clocking power. In addition, with the strong demand for higher frequency central processing units (CPUs), graphics processors, and AI accelerators, deeper pipelines will only exacerbate the problem of clocking power consumption.

[0027] One potential solution to reduce power and improve power efficiency is to reduce the supply voltage. However, this will reduce performance due to the degradation of transistor on-current (Ion). Scaling the supply voltage and transistor threshold voltage (Vth) simultaneously can compensate for the reduction in Ion caused by the lower supply voltage. However, using such low-Vth transistors will significantly increase the leakage power component of the total power.

[0028] Another possible solution involves ultra-low temperature (ULT) operation, such as 0°C, -100°C or lower. ULT operation has attracted much attention in various fields such as cryogenic computing, quantum computing and space exploration, where low temperature can provide significant advantages. ULT operation provides the advantages of higher mobility and steeper subthreshold slope, thereby enhancing the transistor Ion / Ioff ratio. In addition, combining ULT with low Vth transistors at ultra-low voltage (ULV) (e.g., subthreshold voltage) results in a processor-voltage-temperature (PVT) angle, which can achieve the same or higher performance while significantly reducing dynamic / leakage power. However, ULT requires extremely low voltage operation / low power design to keep cooling cost overhead at a controllable level. Therefore, it is desirable to develop circuits / architectures that can achieve low supply voltage operation (Vmin), low power and high performance at such low temperatures.

[0029] Design opportunities for ULT / ULV include emerging applications such as quantum computing application-specific integrated circuits (ASICs). Quantum computing operates at extremely low temperatures, which creates new circuit design opportunities for exploiting design-technology co-optimization due to reduced leakage. In addition, accelerators operate at extremely low voltages and use keeper-free circuits to reduce area and power beyond traditional solutions.

[0030] In addition, emerging devices for post-silicon and more advanced complementary metal-oxide semiconductors (CMOS) can exhibit unidirectional (asymmetric) behavior, i.e., current can flow through the transistor in essentially only one direction. Such asymmetric devices include negative differential resistance MOSFETs, gated Gunn devices, asymmetric III-V metal-oxide-semiconductor field-effect transistors (MOSFETs), and tunnel field-effect transistors (TFETs). Unidirectional / asymmetric transistors generally only allow current to flow in one direction.

[0031] Negative differential resistance (NDR) is a phenomenon where the current decreases as the voltage increases. It is often associated with devices such as Gunn devices or tunnel diodes. It is also possible to achieve negative differential resistance behavior in MOSFETs by exploiting certain device structures or operating conditions. An example is the resonant-tunneling transistor (RTT), also known as the Esaki transistor. This is a specialized MOSFET that is designed to exhibit NDR characteristics. RTT operates based on quantum mechanical tunneling through a thin barrier within the transistor structure. By controlling the bias conditions and the geometry of the device, NDR can be achieved in the current-voltage characteristics of the RTT.

[0032] A gated Gunn device or transistor, also known as a Gunn diode transistor or transferred electron device (TED), is a semiconductor device that exhibits NDR characteristics. The device is based on the Gunn effect, a phenomenon in which the electron transit time in certain semiconductor materials oscillates. The Gunn effect occurs when a high electric field is applied to certain types of materials such as gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN).

[0033] Asymmetric III-V MOSFETs, also known as asymmetric heterojunction transistors, are a type of MOSFET that utilizes III-V compound semiconductors in its device structure. These transistors combine different III-V semiconductor materials with silicon or silicon dioxide to create a heterojunction, thereby achieving enhanced performance compared to traditional silicon MOSFETs. In an asymmetric III-V MOSFET, the channel region is formed using III-V semiconductor materials such as gallium arsenide (GaAs), indium phosphide (InP), or other compound semiconductors.

[0034] TFET is a transistor that operates based on the principle of quantum tunneling. It is an alternative to traditional MOSFET and offers potential advantages such as lower power consumption and better control of subthreshold leakage current. In TFET, current is achieved through band-to-band tunneling, which allows electrons to tunnel from the source of the transistor to the channel region through a thin barrier. Compared with traditional MOSFET, this tunneling mechanism enables TFET to operate at a lower voltage and exhibit steeper subthreshold characteristics. TFET usually uses materials with narrow band gaps, such as III-V compound semiconductors or two-dimensional materials, such as graphene or transition metal dichalcogenides. Narrow band gaps help to achieve efficient quantum tunneling.

[0035] From a circuit design perspective, unidirectional FETs allow for further optimizations that traditional bidirectional FETs cannot perform, thereby improving clock power in flip-flops. Additionally, due to these optimizations, key transistors in critical circuits can be shared to achieve an “effective” 1DG or Z1 device size, thereby reducing clock power and random variation effects. 1DG or Z1 refers to the smallest transistor width allowed by the process.

[0036] In addition, multi-bit flip-flops can be used to reduce clock power by enabling sharing of local clock inverters to reduce clock power. However, there are diminishing returns for using multi-bit flip-flops. For example, after combining eight or more flip-flops, the additional power / area savings that can be achieved are limited.

[0037] The solution provided herein solves the above problems and other problems. In one aspect, the solution utilizes unidirectional / asymmetric FETs to share devices in multi-bit flip-flop circuits to reduce power. Critical clock devices in the circuit can be shared to significantly reduce the gate capacitance of the clock transistor. For example, testing has demonstrated a reduction of more than 40%.

[0038] The solution can reduce clock power to meet the strict power budget of computing devices. The power benefit improvement brought by reducing clock power is beyond the scope of what can be provided by the process and traditional standard cell library. The standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. In addition, the solution is compatible with the most famous low-power multi-bit flip-flop strategy adopted in today's standard cell library.

[0039] In one example implementation, the solution provides a multi-bit flip-flop circuit using unidirectional FETs and tri-state keeper sharing.

[0040] In another example implementation, a solution provides a multi-bit flip-flop circuit using unidirectional FETs and tri-state holders and / or pass gate sharing.

[0041] In another example implementation, the solution provides a multi-bit flip-flop circuit that uses a unidirectional FET shared with a pass gate and does not use a keeper.

[0042] These and other features will become further apparent from the discussion below.

[0043] Figure 1AAn example multi-bit flip-flop circuit 100 using bidirectional field effect transistors (FETs) according to various embodiments is depicted. The circuit receives several shared or common inputs, including a clock signal (clk) on path 101, a scan data signal sd[n-1:0] on path 133, a scan select signal ssb on path 135, and a data signal d[n-1:0] on path 139. The circuit also includes a number of flip-flops FF[0] 150, ..., FF[n-1] 151 in a set of flip-flops 152, n>1. Each flip-flop (or flip-flop circuit) receives a shared input at a respective input terminal. For example, input terminals nc1[0], ..., nc1[n-1] receive clk after clk is inverted at inverter 102 and provided on paths 103 and 106. Input terminals nc2[0], ..., nc2[n-1] receive the signal on path 103 after the signal is inverted at inverter 104 and provided on path 105. Input terminals ssb[0],...,ssb[n-1] receive ssb. Input terminals sd[0],...,sd[n-1] receive corresponding bits from a set of n bits represented by sd[n-1:0]. After ssb is inverted at inverter 136 and output on path 137, input terminals ss[0],...,ss[n-1] receive signal ss, which is the complement or inverse of ssb. Input terminals d[0],...,d[n-1] receive corresponding bits from a set of n data bits represented by d[n-1:0]. Note that for clarity, only the d and ss input terminals are depicted here for FF[0]. In one embodiment, each flip-flop may have the same input and output terminals.

[0044] Each flip-flop includes internal components that are controlled by input signals to provide outputs at corresponding output terminals out[0], ..., out[n-1] on paths 153, ..., 154. The bits on paths 153, ..., 154 are combined at path 157 to provide the final output out[n-1:0].

[0045] In this example, inverters 102 and 104 are clock devices, eg, devices that receive a clock signal.

[0046] Figure 1B Depicted are various embodiments Figure 1A An example implementation of a flip-flop 150 of FIG. 1 is shown in FIG. 1 . In one example implementation, the flip-flop may be a D-type master-slave flip-flop. This type of flip-flop includes a master latch 170 connected in series with a slave latch 180, which receives a data bit from the master latch and provides it as an output under the control of a clock signal.

[0047] The flip-flop includes a multiplexer 160 that passes sd[0] on path 162 or d[0] on path 164 to node 168. The multiplexer includes tri-state inverters 165 and 167. The tri-state inverter, also known as a tri-state buffer, may include a high-active input connected to a first signal (e.g., ss[0]) via paths 163 and 166, and a low-active input connected to the complement of the first signal (e.g., ssb[0]) via path 161. If the signal represents an enabled state, the tri-state inverter passes and inverts the input bit to the output. When not enabled, the tri-state inverter has a high impedance state at its output and does not pass the input bit. In the data latching mode of the flip-flop, the tri-state inverter 167 inverts d[0] and passes it to node 168.

[0048] The master latch 170 inverts the data input at the inverter 171 and transfers the data to the storage node 175 when the transmission gate 172 (also referred to as the transfer gate) is enabled. The transfer gate has a non-inverting input coupled to the clock signal at the input terminal nc1[0] and an inverting input coupled to the clock signal at the input terminal nc2[0]. When the voltage at nc2[0] is low and the voltage at nc1[0] is high, the transmission gate 172 is enabled. The master latch includes a keeper circuit 176 (or generally referred to as a circuit), which includes a tri-state inverter 173 and an inverter 174. The keeper circuit helps to keep the data bit at the storage node 175, for example, in a low or high state. The data bit is inverted at the inverter 174, and the output of the inverter is input to the tri-state inverter 173. Based on the clock signal from nc2[0] at its non-inverting input and the clock signal from nc1[0] at its inverting input, tri-state inverter 173 passes its input to its output at storage node 175 to strengthen the voltage level of the stored data bit.

[0049] In addition, the data bit is output from the primary latch to the secondary latch at path 186. When the transmission gate 181 is enabled, the data bit is passed by it to the storage node 185, where the value of the data bit is maintained by the keeper circuit 187 including the inverter 182 and the tri-state inverter 183. When the voltage at nc1[0] is low and the voltage at nc2[0] is high, the transmission gate 181 is enabled. The data at the storage node 185 can be output to the output terminal out[0] via the inverter 184.

[0050] In this example, transmission gates 172 and 181 and tri-state inverters 173 and 183 are clock devices.

[0051] Note that in this and other figures, conductive paths that intersect generally do not connect at an intersection unless a black circle is shown at the intersection to indicate a connection.

[0052] A disadvantage of the flip-flop 150 is that a complete keeper circuit is provided within the flip-flop. The solution described below overcomes this disadvantage.

[0053] Figure 2A An example configuration of a bidirectional FET in which charge sharing does not occur according to various embodiments is depicted. FETs 200 and 201 connected in series receive 1 and 0 data bits at their control gates, respectively, while FETs 210 and 211 connected in series also receive 1 and 0 data bits at their control gates, respectively. In this example, a 1 bit represents a high voltage, which turns on the n-type FET (making it conductive). A 0 bit represents a low (0V) voltage, which turns off the n-type FET (making it non-conductive). The double-headed arrows indicate that the FET is bidirectional. Z1 represents the impedance of the transistor. Since FETs 200 and 210 are not coupled to each other, charge sharing does not occur between them.

[0054] Figure 2B Depicted is an example configuration of a bidirectional FET in which charge sharing occurs in accordance with various embodiments. In this example, FETs 220 and 222 are connected in parallel with each other and in series with FET 221. FETs 220 and 222 are turned on by a 1 bit at their control gates, while FET 221 is turned off by a 0 bit at its control gate. The dashed arrows indicate the charge sharing paths through which current can flow. The impedance of FET 221 is either Z1 or Z2. Therefore, the bidirectional FET results in a condition where charge sharing can occur between the two FETs. Since this may destroy the state node, many circuit topologies do not allow this.

[0055] Figure 2C Depicted are example configurations of unidirectional FETs in which charge sharing does not occur according to various embodiments. In the case of using unidirectional or asymmetric FETs, current can only flow in one direction, thereby realizing a new circuit topology with device (e.g., transistor) sharing, reducing capacitance and power consumption. In addition, device sharing enables the use of large-width transistors, which have a high tolerance for device variations. In this case, FETs 230 and 232 are connected in parallel to each other and are connected in series with FET 231. FETs 230 and 232 are turned on by a 1 bit at their control gates, while FET 231 is turned off by a 0 bit at its control gate. The impedance of FET 221 is Z1 or Z2. The downward arrow indicates the direction of current flow, i.e., from the power supply source at the top of the circuit to the ground.

[0056] The circled area indicates Figure 2A How the two off FETs in the circuit can be replaced by a single off FET.

[0057] In addition to the earlier discussion of various types of unidirectional devices, examples of ways to make unidirectional devices generally can include different modifications to the source and drain terminals of the transistor. The first modification technique involves differential doping. This results in a difference in the number of carriers (e.g., boron, phosphorus, arsenic, etc.) in the source and drain. The difference can range from a factor of more than 2. That is, the doping concentration of one terminal can be twice that of the other terminal. Typical carrier concentrations are ~1e20 to 1e21 carriers / cm3. Differential doping helps increase the carriers injected from one side while reducing the carrier injection on the other side.

[0058] The second technique involves doping type modulation. This can involve using different types of carriers on the source side and the drain side. An example includes a TFET (tunnel field effect transistor) device. A typical structure of this includes an n-type region near the source, a p-type channel, an n-type region at the edge of the channel near the drain, and p-type carriers at the drain (whereas conventional FETs typically have n-type regions near both the source and drain). This operates in a mode that modulates the pn junction under the gate. Having opposite types of carriers on the source and drain also makes the device highly unidirectional.

[0059] The third technique involves creating a Zener or Gunn or avalanche diode at the source or drain of the MOSFET. These diode types are introduced in the contact region below the gate edge. These diode structures achieve a high level of unidirectionality due to their respective operations. However, placing the junction of the diode near or below the gate ensures that undesirable effects on the drive current are minimized.

[0060] The above techniques can be further improved if the device is operated at low temperatures, but this is not a necessary criterion.

[0061] Figure 3 An example multi-bit flip-flop circuit 300 using unidirectional FETs and with tri-state holder sharing according to various embodiments is depicted. In order to exploit the unidirectional properties of transistors, clock devices are shared between multiple flip-flops in a multi-bit standard cell. This sharing enables significant reduction in clock power and reduced space requirements.

[0062] like Figure 1A As shown, a group of n flip-flops 352 is provided, including FF[0] 350, ..., FF[n-1] 351. The flip-flops include Figure 1AThe multi-bit flip-flop circuit 300 further includes an additional input terminal nc1p[0], ..., nc1p[n-1] coupled to the drain terminal of the p-type FET Pnc1p, an input terminal nc2p[0], ..., nc2p[n-1] coupled to the drain terminal of the p-type FET Pnc2p, an output terminal nc1n[0], ..., nc1n[n-1] coupled to the drain terminal of the n-type FET Nnc1n, and an output terminal nc2n[0], ..., nc2n[n-1] coupled to the drain terminal of the n-type FET Nnc2n. Pnc1p, Pnc2p, Nnc1n, and Nnc2n are shared or common devices / transistors that are coupled to each flip-flop in the multi-bit flip-flop circuit 300. They are shared between different flip-flops.

[0063] The circuit receives several shared or common inputs including a clock signal (clk) on path 301 , a scan data signal sd[n−1:0] on path 333 , a scan select signal ssb on path 335 , and a data signal d[n−1:0] on path 339 .

[0064] Each flip-flop receives a shared input at a respective input terminal. For example, input terminals nc1[0], ..., nc1[n-1] receive clk after clk is inverted at inverter 302 and provided on paths 303 and 330. Input terminals nc2[0], ..., nc2[n-1] receive the signal on path 303 after the signal is inverted at inverter 304 and provided on path 305. Input terminals nc1p[0], ..., nc1p[n-1] are coupled to drain terminal 313 of Pnc1p. The voltage at this drain terminal is a function of voltage nc1 on path 330 (which in turn is coupled to control gate 311) and power supply voltage Vdd at power supply terminal 310, which is coupled to source terminal 312. Specifically, when nc1 is low, the voltage at drain terminal 313 is high. Input terminals nc2p[0], ..., nc2p[n-1] are coupled to the drain terminal 323 of Pnc2p. The voltage at this drain terminal is a function of the voltage nc2 on path 305 (which in turn is coupled to the control gate 321) and the power supply voltage Vdd at the power supply terminal 320, which is coupled to the source terminal 322. Specifically, when nc2 is low, the voltage at the drain terminal 323 is high. Nc1 and Nc2 are complementary, so that when one is high, the other is low.

[0065] Furthermore, output terminals nc1n[0], ..., nc1n[n-1] are coupled to drain terminal 340 of Nnc1n. Signal nc1 on paths 303 and 331 is coupled to control gate 341 of this transistor. Terminals nc2n[0], ..., nc2n[n-1] are coupled to drain terminal 345 of Nnc2n. Signal nc2 on path 305 is coupled to control gate 346 of this transistor. Source 342 of Nnc1n is coupled to ground G1, and source 347 of Nnc2n is coupled to ground G2.

[0066] Input terminals ssb[0],...,ssb[n-1] receive ssb. Input terminals sd[0],...,sd[n-1] receive corresponding bits from a set of n bits represented by sd[n-1:0]. After ssb is inverted at inverter 336 and output on path 337, input terminals ss[0],...,ss[n-1] receive signal ss, which is the complement or inverse of ssb. Input terminals d[0],...,d[n-1] receive corresponding bits from a set of n data bits represented by d[n-1:0]. Note that for clarity, only the d and ss input terminals are depicted here for FF[0]. In one embodiment, each flip-flop may have the same input and output terminals. Each flip-flop includes internal components that are controlled by input signals to provide outputs at respective output terminals out[0], ..., out[n-1] on paths 353, ..., 354. The bits on paths 353, ..., 354 are combined at path 357 to provide a final multi-bit output out[n-1:0].

[0067] In this example, inverters 302 and 304 as well as Pnc1p, Pnc2p, Nnc1n, and Nnc2n are clock devices.

[0068] In some embodiments, the shared transistor is part of a keeper circuit that maintains the data in the storage node of the flip-flop. In one possible solution, the keeper can be provided as an inverted tri-state keeper, and the clock device is shared. As previously described, this solution can significantly reduce the clock transistor gate capacitance (excluding the local clock inverter).

[0069] Figure 4A Depicted is a schematic diagram of a circuit having tri-state holder sharing according to various embodiments. Figure 34. The trigger 350 of FIG. 4 is an example implementation of a trigger 350. The trigger includes a multiplexer 400, a main latch 410 and a sub-latch 425 arranged in series. The main latch and the sub-latch may also be referred to as a first latch and a second latch, or a main latch and a sub-latch, respectively. Each latch latches data in a respective storage node SN1 or SN2 before the data is output at the output terminal out[0].

[0070] The flip-flop includes a multiplexer 400, which passes sd[0] on path 402 or d[0] on path 404 to node 408. The multiplexer includes an inverter 405 and tri-state inverters 407 and 409. Tri-state inverter 407 can pass sd[0] based on ss[0] on node 408 and ssb[0] on path 401. Inverter 405 outputs ss[0] based on input of ssb[0] on input path 403. Tri-state inverter 409 can pass d[0] based on ssb[0] on path 406 and ss[0] on node 408. In the data latch mode of the flip-flop, tri-state inverter 409 inverts d[0] on path 404 and passes it to node 411.

[0071] In the master latch, the data bit is inverted at inverter 417 and provided to transmission gate 418. The inverting side of the transmission gate is coupled to the nc2[0] terminal via path 412, and the opposite non-inverting side of the transmission gate is coupled to the nc1[0] terminal via path 460. When transmission gate 418 is on, e.g., the signal at nc2[0] is low and the signal at nc1[0] is high, the inverted data bit is passed to SN1.

[0072] The first keeper circuit KP1 (or generally referred to as the first circuit) helps maintain the data at SN1. The keeper circuit includes a p-type transistor P1-1 and an n-type transistor N1-1 connected in series. P1-1 is coupled to Pnc1p via path 441 and terminal nc1p[0] and connected in series. N1-1 is coupled to Nnc2n via path 421 and output terminal nc2n[0] and connected in series. In the keeper operation, the data bit at SN1 is provided to the input 497 of the inverter 420. The inverted value is output at node 422, path 416 and node 419, which is coupled to the control gates 413 and 415 of P1-1 and N1-1 respectively. Node 498 represents the output from the pair of transistors. This output is provided back to SN1 via path 414 to strengthen the voltage at SN1. When Pnc1p and Nnc2n are in the on state, for example, when nc1 is low and nc2 is high, the keeper reinforcement of KP1 occurs.

[0073] The downward arrows associated with P1-1, N1-1, P2-1, and N2-1 indicate that they are unidirectional devices that are configured to flow current in the direction from a high voltage to a lower voltage (eg, ground). Shared transistors Pnc1p, Pnc2p, Nnc2n, and Nnc1n may be bidirectional or unidirectional.

[0074] In the secondary latch, when the transmission gate 432 is enabled, for example, when the signal at nc2[0] is high and the signal at nc1[0] is low, the data bit at node 422 is transferred to SN2 by the transmission gate 432. The inverting side of the transmission gate is coupled to the nc1[0] terminal via path 460, and the opposite in-phase side of the transmission gate is coupled to the nc2[0] terminal via path 427. The second retainer circuit KP2 (or generally referred to as the second circuit) helps maintain the data at SN2. The retainer circuit includes a p-type transistor P2-1 and an n-type transistor N2-1 connected in series. P2-1 is coupled to Pnc2p via path 426 and terminal nc2p[0] and connected in series. N2-1 is coupled to Nnc1n via path 435 and output terminal nc1n[0] and connected in series. In the retainer operation, the data bit at SN2 is provided to the input 501 of the inverter 434. The inverted value is output at path 431 and node 440, which is coupled to control gates 439 and 430 of P2-1 and N2-1, respectively. Node 499 represents the output from the pair of transistors. This output is provided back to SN2 via path 429 to reinforce the voltage at SN2. When Pnc2p and Nnc1n are in the on state, for example, when nc2 is low and nc1 is high, the keeper reinforcement of KP2 occurs.

[0075] The data at the storage node SN2 may be output to a path 438 and an output terminal out[0] via a path 437 and an inverter 436 .

[0076] Thus, each of the keeper circuits KP1 and KP2 is composed of a transistor (e.g., an internal transistor or other device) within each individual flip-flop and a shared transistor (e.g., an external transistor or other device) outside the flip-flop. In general, the keeper circuit may be composed of one or more internal transistors or other devices within each individual flip-flop and one or more shared transistors or other devices outside the flip-flop. Note that for ease of understanding, a shared external transistor is shown here.

[0077] In this example, transmission gates 418 and 432 are clock devices.

[0078] In one approach, each flip-flop in a multi-bit flip-flop circuit may have the same configuration.

[0079] P1-1, N1-1, P2-1, and N2-1 are examples of internal keeper devices (or generally referred to as internal devices), and Pnc1p, Pnc2p, Nnc2n, and Nnc1n are examples of shared keeper devices (or generally referred to as shared devices).

[0080] Figure 4B Depicted are various embodiments of Figure 4A An example first subset 490 of consistent shared keeper devices. The first subset includes a transistor Pnc1p receiving a clock signal nc1 at its control gate, and a transistor Nnc2n receiving a clock signal nc2 (complement of nc1) at its control gate. The first subset is associated with a master latch in one approach. For example, the first subset may represent a device shared by a master latch in each flip-flop of a multi-bit flip-flop circuit.

[0081] Figure 4C Depicted are various embodiments of Figure 4A An example second subset 491 of consistent shared keeper devices. The second subset includes a transistor Pnc2p receiving a clock signal nc2 at its control gate, and a transistor Nnc1n receiving a clock signal nc1 at its control gate. The second subset is associated with a secondary latch in one approach. For example, the second subset may represent a device shared by a secondary latch in each flip-flop of a multi-bit flip-flop circuit.

[0082] Figure 5 An example multi-bit flip-flop circuit 500 using unidirectional FETs and having tri-state holders and / or pass gate sharing according to various embodiments is depicted. This circuit is similar to Figure 3 Similar.

[0083] like Figure 3 As shown, a set of n flip-flops 552 is provided, including FF[0] 550, ..., FF[n-1] 551. In addition to nc1[0], ..., nc1[n-1] and nc2[0], ..., nc2[n-1], these flip-flops include Figure 3 As before, input terminals nc1p[0], ..., nc1p[n-1] are coupled to drain terminal 313 of Pnc1p, input terminals nc2p[0], ..., nc2p[n-1] are coupled to drain terminal 323 of Pnc2p, output terminals nc1n[0], ..., nc1n[n-1] are coupled to drain terminal 340 of Nnc1n, and output terminals nc2n[0], ..., nc2n[n-1] are coupled to drain terminal 345 of Nnc2n.

[0084] Circuit 500 receives several shared or common inputs including a clock signal (clk) on path 301 , a scan data signal sd[n−1:0] on path 333 , a scan select signal ssb on path 335 , and a data signal d[n−1:0] on path 339 .

[0085] Each flip-flop receives a shared input at a respective input terminal. For example, input terminals nc1[0], ..., nc1[n-1] receive clk after clk is inverted at inverter 302 and provided on paths 303 and 330. Input terminals nc2[0], ..., nc2[n-1] receive the signal on path 303 after the signal is inverted at inverter 304 and provided on path 305. Input terminals nc1p[0], ..., nc1p[n-1] are coupled to drain terminal 313 of Pnc1p. Input terminals nc2p[0], ..., nc2p[n-1] are coupled to drain terminal 313 of Pnc2p.

[0086] Furthermore, output terminals nc1n[0], ..., nc1n[n-1] are coupled to the drain terminal 340 of Nnc1n, and output terminals nc2n[0], ..., nc2n[n-1] are coupled to the drain terminal 345 of Nnc2n.

[0087] The signals sd[n-1:0], ssb and d[n-1:0] are as follows Figure 3 is entered as shown.

[0088] Figure 6 Depicted is a schematic diagram of a circuit having tri-state holders and pass gate sharing according to various embodiments. Figure 5 In this case, Figure 4A The transfer gates (transmission gates) 418 and 432 in are converted to reverse tri-state inverters, and the clock devices are shared. In order to maintain the same drive strength for the worst case switching, in one approach, the shared clock may not be scaled down. However, any clock width elimination of the keeper device may be achieved. Figure 4A In comparison, this topology reduces the clock transistor gate capacitance by an additional considerable amount (eg, by 11% in testing).

[0089] The flip-flop includes a multiplexer 400, a main latch 610, and a sub latch 625 arranged in series. Each latch latches data in a respective storage node SN1 or SN2 before the data is output at an output terminal out[0].

[0090] For example, multiplexer 400 passes d[0] to node 411, which is coupled to control gates 611 and 612 of p-type transistor P1-1a and n-type transistor N1-1a, respectively, which are coupled in series with each other. P1-1a is coupled to Pnc2p via paths 627 and 426 and terminal nc2p[0] and in series. N1-1a is coupled to Nnc1n via path 626 and output terminal nc1n[0] and in series. See also Figure 7 .

[0091] Node 613 at the drain terminal of these transistors provides an output signal / voltage to SN1. As before, the first keeper circuit KP1 helps maintain the data at SN1. The keeper circuit includes a p-type transistor P1-1 and an n-type transistor N1-1 connected in series. P1-1 is coupled to Pnc1p via path 441 and terminal nc1p[0] and connected in series. N1-1 is coupled to Nnc2n via path 421 and output terminal nc2n[0] and connected in series. In the keeper operation, the data bit at SN1 is provided to the input 497 of inverter 420. The inverted value is output at path 416 and node 419, which is coupled to the control gates 413 and 415 of P1-1 and N1-1, respectively. Node 498 represents the output from the pair of transistors. This output is provided back to SN1 via path 414 to strengthen the voltage at SN1. In one embodiment, each transistor represented by a downward arrow is unidirectional. As before, the shared transistors Pnc1p, Pnc2p, Nnc2n and Nnc1n can be bidirectional or unidirectional.

[0092] In the secondary latch, the data bit at SN1 is passed to the secondary latch on path 624. Path 624 is coupled to control gates 620 and 621 of p-type transistor P2-1a and n-type transistor N2-1a, which are coupled in series with each other. P2-1a is coupled to Pnc1p via paths 627 and 441 and terminal nc1p[0] and in series. N2-1a is coupled to Nnc2n via path 628 and output terminal nc2n[0] and in series. See also Figure 7 Node 622 represents the output from the pair of transistors. This output is provided to SN2.

[0093] The second keeper circuit KP2 helps maintain the data at SN2. The keeper circuit includes a p-type transistor P2-1 and an n-type transistor N2-1 connected in series. P2-1 is coupled to Pnc2p via path 426 and terminal nc2p[0] and connected in series. N2-1 is coupled to Nnc1n via path 435 and output terminal nc1n[0] and connected in series. In the keeper operation, the data bit at SN2 is provided to the input 501 of inverter 434. The inverted value is output at path 431 and node 440, which is coupled to control gates 439 and 430 of P2-1 and N2-1, respectively. Node 499 represents the output from the pair of transistors. This output is provided back to SN2 via path 429 to strengthen the voltage at SN2. The data at the storage node SN2 can be output to path 438 and output terminal out[0] via path 437 and inverter 436.

[0094] In this example, the flip-flop does not include an internal clock device. Instead, the clock device is a shared transistor Pnc1p, Pnc2p, Nnc2n, and Nnc1n, which are shared between the flip-flop groups of the multi-bit flip-flop circuit. The control gate of the clock transistor is connected to nc1 or nc2.

[0095] In one approach, each flip-flop in a multi-bit flip-flop circuit may have the same configuration.

[0096] P1-1, N1-1, P2-1, and N2-1 are examples of internal keeper devices, and Pnc1p, Pnc2p, Nnc2n, and Nnc1n are examples of shared keeper devices.

[0097] Figure 7 Depicted are various embodiments Figure 6 1 and 10 are exemplary configurations of a first tri-state inverter (TSI1) and a second tri-state inverter (TSI2) of a flip-flop 550. TSI1 includes Pnc2p, P1-1a, N1-1a, and Nnc1n connected in series. TSI2 includes Pnc1p, P2-1a, N2-1a, and Nnc2n connected in series. Figure 6 The flip-flops of thus share external devices Pnc2p, Nnc1n, Pnc1p and Nnc2n in two ways. First, they are shared to provide a keeper in the main latch and the sub-latch. Second, they are shared to provide a tri-state inverter in the main latch and the sub-latch. It can also be said that Pnc2p and Nnc1n are shared to provide a keeper and a tri-state inverter in the main latch, and Pnc1p and Nnc2n are shared to provide a keeper and a tri-state inverter in the sub-latch.

[0098] The output of the tri-state inverter is either the inverse of the input or high impedance (open circuit). The tri-state inverter also acts as a delay or buffer component. When Pnc2p and Nnc1n are in the on state, for example, when nc2 is low and nc1 is high, TSI1 provides an output. When Pnc1p and Nnc2n are in the on state, for example, when nc1 is low and nc2 is high, TSI2 provides an output.

[0099] Figure 8 Depicted are various embodiments of Figure 5 Another example implementation of flip-flop 550 is flip-flop 850 with transfer gate sharing and no keeper. This is an example of a keeperless flip-flop that may be suitable for ultra-low voltage and / or ultra-low temperature applications, for example. In this case, the additional data device and keeper are eliminated, thereby achieving data power reduction and smaller area usage.

[0100] Specifically, in the first three-state inverter TSI1a, the multiplexer 400, for example, passes d[0] to the node 411, which is coupled to the control gates 810 and 811 of the p-type transistor P1-1b and the n-type transistor N1-1b, which are coupled in series with each other. P1-1b is coupled to Pnc2p via the path 809 and the terminal nc2p[0] and is connected in series. N1-1b is coupled to Nnc1n via the path 808 and the output terminal nc1n[0] and is connected in series. The node 812 at the drain terminal of these transistors provides an output signal / voltage to the first sensing node SN1a.

[0101] SN1a is in turn coupled to a node 823 in a second tri-state inverter TSI2a. Node 823 is in turn coupled to control gates 820 and 821 of a p-type transistor P2-1b and an n-type transistor N2-1b, respectively, which are coupled in series with each other. P1-1b is coupled to Pnc1p via path 819 and terminal nc1p[0] and is in series. N2-1b is coupled to Nnc2n via path 818 and output terminal nc2n[0] and is in series. Node 822 at the drain terminals of these transistors provides an output signal / voltage to a second sensing node SN1b. The data at SN1a is in turn output to out[0] via inverter 850.

[0102] In this example, the number of transistors in the flip-flop is advantageously minimized.

[0103] Various alternative implementations are possible. For example, p-type transistors can be shared for both the main latch and the secondary latch, while n-type transistors are not shared. In another example, n-type transistors can be shared for both the main latch and the secondary latch, while p-type transistors are not shared. In another example, p-type and / or n-type transistors can be shared for the main latch but not for the secondary latch, or p-type and / or n-type transistors can be shared for the secondary latch but not for the main latch. The shared p-type transistor and the internal p-type transistor can be of the same type, or can be of different types. The shared n-type transistor and the internal n-type transistor can be of the same type, or can be of different types. For example, different types of unidirectional transistors can be used. In addition, the transistor can be a FET or other type of transistor. The transistor can also be replaced by other devices that provide similar functions.

[0104] Fig. 9 The diagram illustrates examples of components that may be present in a computing system 950 for implementing the techniques (e.g., operations, processes, methods, and approaches) described herein. A multi-bit flip-flop circuit may be provided in any circuit of the computing system 950, such as a contact Figures 3 to 8 For example, a multi-bit flip-flop circuit may be provided in at least one of the following.

[0105] For one embodiment, at least one processor 952 may be packaged with computing logic 982 and configured to implement aspects of the various example embodiments described herein to form a system-in-package (SiP), system-on-chip (SoC), or other circuit. The circuit may be part of a stacked tile / chiplet design that includes multiple integrated circuits / chips within the same package. The circuit may be considered a device, system, or circuit. Memory circuit 954 may store instructions, and processor circuit 952 may execute the instructions to perform the functions described herein.

[0106] The computing system 950 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof adapted in the computing system 950, or as components otherwise contained within a chassis of a larger system. For one embodiment, at least one processor 952 may be packaged together with computing logic 982 and configured to implement aspects of the various example embodiments described herein to form a system-in-package (SiP) or system-on-chip (SoC).

[0107] The system 950 includes a processor circuit in the form of one or more processors 952. The processor circuit 952 includes circuits such as (but not limited to) one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C or general programmable serial interface circuit, real time clock (RTC), timer-counter including interval and watchdog timer, general I / O, memory card controller such as secure digital / multi-media card (SD / MMC), interface, mobile industry processor interface (MIPI) interface and joint test access group (JTAG) test access port. In some implementations, the processor circuit 952 may include one or more hardware accelerators (e.g., the same or similar to the acceleration circuit 964), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, processor circuit 952 may include on-chip memory circuitry, which may include any suitable volatile and / or nonvolatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0108] The processor circuit 952 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing elements, or any suitable combination of these. The processor (or core) 952 may be coupled to or may include a memory / storage device, and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on the platform 950. The processor (or core) 952 is configured to operate application software to provide specific services to users of the platform 950. In some embodiments, the (one or more) processors 952 may be (or may be configured to) be (one or more) dedicated processors / controllers configured to operate according to various embodiments herein.

[0109] As an example, the processor(s) 952 may include Intel (Intel Architecture Core TM ) processors, such as i3, i5, i7, i9-based processors; Intel Microcontroller-based processors such as Quark TM 、Atom TM or other MCU-based processors; (one or more) Pentium Processor, (one or more) Xeon processors, or available from Intel in Santa Clara, California However, any number of other processors may be used, such as one or more of the following: Zen 1 from Advanced Micro Devices (AMD); Architecture, such as Ryzen(s) or EPYC Processor, Accelerated Processing Unit (APU), MxGPU, (one or more) Epyc Processors, etc.; from Apple (Apple ) company's A5-A12 and / or S1-S4 processors from Qualcomm (Qualcomm )Technology Company's Snapdragon(s) TM or Centriq TM Processor, Texas Instruments (Texas Instruments, Inc. ) OpenMultimedia Applications Platform (OMAP) TM Processors; MIPS-based designs from MIPS Technologies Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings plc, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; and processors manufactured by Cavium TM ThunderX2 provided by the company In some implementations, the processor(s) 952 may be part of a system on a chip (SoC), a system-in-Package (SiP), a multi-chip package (MCP), etc., where the processor(s) 952 and other components are formed as a single integrated circuit, or a single package, such as from Intel. Edison TM or Galileo TM SoC Board. Other examples of processor(s) 952 are mentioned elsewhere in this disclosure.

[0110] The system 950 may include or be coupled to an acceleration circuit 964, which may be implemented by one or more AI / ML accelerators, neural compute sticks, neuromorphic hardware, FPGAs, arrangements of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other forms of specialized processors or circuits designed to implement one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, reasoning, and classification operations), visual data processing, network data processing, object detection, rule analysis, and the like. In an FPGA-based implementation, the acceleration circuit 964 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and the like of the various embodiments discussed herein. In such an implementation, the acceleration circuit 964 may also include a memory unit (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a LUT, etc.

[0111] In some implementations, the processor circuit 952 and / or the acceleration circuit 964 may include hardware elements specifically customized for machine learning and / or artificial intelligence (AI) functions. In these implementations, the processor circuit 952 and / or the acceleration circuit 964 may be or may include an AI engine chip that, once loaded with appropriate weighting and training code, can run many different kinds of AI instruction sets. Additionally or alternatively, the processor circuit 952 and / or the acceleration circuit 964 may be or may include (one or more) AI accelerators, which may be one or more of the above-mentioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators may be a cluster of the following: artificial intelligence (AI) GPU, Google The company's tensor processing unit (TPU), AlphaICs Provided by Real AI Processor (RAP TM ),Intel Nervana provided by the company TM Neural Network Processor (NNP), Intel Movidius TM Myriad TM XVision Processing Unit (VPU), based on NVIDIA PX TM GPU, General Vision NM500 chip provided by Tesla (Tesla )Hardware 3, Adapteva Provided by Epiphany TM In some embodiments, the processor circuit 952 and / or the acceleration circuit 964 and / or the hardware accelerator circuit may be implemented as (one or more) AI acceleration coprocessors, such as Qualcomm Hexagon 685DSP provided by Changxiang Technology Co., Ltd. (Imagination TechnologiesLimited ) provided by PowerVR 2NX Neural Net Accelerator (NNA), Apple Neural Engine Core in A11 or A12 Bionic SoC, Huawei (Huawei ) provided by HiSilicon Kirin 970, etc. In some hardware-based implementations, individual subsystems of system 950 may be operated by individual AI acceleration coprocessors, AI GPUs, TPUs, or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., which are configured with appropriate logic blocks, (one or more) bitstreams, etc., to perform their respective functions.

[0112] The system 950 also includes a system memory 954. Any number of memory devices may be used to provide a fixed amount of system memory. As an example, the memory 954 may be or may include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), RAMBUS, or a combination thereof. Dynamic Random Access Memory (RAMBUS Dynamic Random Access Memory, RDRAM ), and / or any other desired type of volatile memory device. Additionally or alternatively, the memory 954 may be or may include a non-volatile memory, such as a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable (EEPROM), a flash memory, a non-volatile RAM, a ferroelectric RAM, a phase-change memory (PCM), a flash memory, and / or any other desired type of non-volatile memory device. Access to the memory 954 is controlled by a memory controller. Individual memory devices may have any number of different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (Q17P). Any number of other memory implementations may be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0113] The storage circuit 958 provides persistent storage of information such as data, applications, operating systems, etc. In one example, the storage device 958 can be implemented via a solid-state disk drive (SSDD) and / or a high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that can be used for the storage device 958 include flash memory cards, such as SD cards, microSD cards, XD picture cards, etc., and USB flash drives. In one example, the memory device may be or may include a memory device using chalcogenide glass, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM) memory including memristor technology, a phase change RAM (PRAM), a resistive memory including a metal oxide substrate, an oxygen vacancy substrate and a conductive bridge random access memory (CB-RAM), or a spin transfer torque (STT)-MRAM, a device based on a spin electronic magnetic junction memory, a device based on a magnetic tunneling junction (MTJ), a device based on a domain wall (DW) and a spin orbit transfer (SOT), a semiconductor thyristor-based memory device, a hard disk drive (HDD) drive, HDD), micro HDD, or a combination of these, or any other memory. Memory circuit 954 and / or storage circuit 958 may also include Intel and Micron Three-dimensional (3D) cross-point (XPOINT) memory.

[0114] The memory circuit 954 and / or the storage circuit 958 are configured to store computing logic 983 in the form of software, firmware, microcode or hardware level instructions to implement the techniques described herein. The computing logic 983 may be employed to store working copies and / or permanent copies of programming instructions, or data used to create programming instructions, for various components of the operating system 950 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of the system 950, one or more applications, and / or for implementing the embodiments discussed herein. The computing logic 983 may be stored or loaded into the memory circuit 954 as instructions 982 or data used to create instructions 982, and then accessed by the processor circuit 952 for execution to implement the functions described herein. The processor circuit 952 and / or the acceleration circuit 964 access the memory circuit 954 and / or the storage circuit 958 via the interconnect (IX) 956. The instructions 982 direct the processor circuit 952 to perform a specific sequence of actions or processes, for example, as described with reference to the (one or more) flow charts and (one or more) block diagrams of the operations and functions previously depicted. The various elements may be implemented by assembly instructions or a high-level language supported by processor circuit 952, which may be compiled into instructions 988, or data used to create instructions 988, for execution by processor circuit 952. A permanent copy of the programming instructions may be placed into a persistent storage device of storage circuit 958 at the factory or in the field, for example, via a distribution medium (not shown), via a communications interface (e.g., from a distribution server (not shown)), over the air (OTA), or any combination of these.

[0115] IX 956 couples processor 952 to communication circuitry 966 for communication with other devices, such as a remote server (not shown), etc. Communication circuitry 966 is a hardware element, or a collection of hardware elements, for communicating over one or more networks 963 and / or with other devices. In one example, communication circuitry 966 is or includes a transceiver circuit configured to implement wireless communication using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or its variants), IEEE 802.23.4, Bluetooth and / or Bluetooth Low Energy (Bluetooth low energy, BLE), ZigBee LoRaWAN TM(Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 966 is or includes one or more network interface controllers (NICs) to enable wired communications using, for example, an Ethernet connection, a Controller Area Network (CAN), a Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0116] IX 956 also couples processor 952 to interface circuitry 970 for connecting system 950 to one or more external devices 972. External devices 972 may include, for example, sensors, actuators, positioning circuits (e.g., global navigation satellite system (GNSS) / Global Positioning System (GPS) circuits), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuits (ICs) and / or the like), and / or other similar devices.

[0117] In some optional examples, various input / output (I / O) devices may be present in or connected to the system 950, and these devices are referred to as input circuits 986 and output circuits 984. Input circuits 986 and output circuits 984 include one or more user interfaces designed to enable a user to interact with the platform 950, and / or are designed to enable a peripheral component to interact with the platform 950. The input circuit 986 may include any physical or virtual device for accepting input, specifically including one or more physical or virtual buttons (e.g., reset button), physical keyboards, keypads, mice, touch pads, touch screens, microphones, scanners, headsets, and / or the like. The output circuit 984 may be included to show information or otherwise convey information, such as sensor readings, (one or more) actuator positions, or other similar information. Data and / or graphics may be displayed on one or more user interface components of the output circuit 984. Output circuitry 984 may include any number and / or combination of audio or visual displays, including, in particular, one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs, such as a display device or touch screen (e.g., a liquid crystal display (LCD)). The platform 950 may include a display, such as a display, such as a CrystalDisplay, LCD), LED display, quantum dot display, projector, etc.), where the output of characters, graphics, multimedia objects, etc. is generated or produced from the operation of the platform 950. The output circuit 984 may also include a speaker and / or other audio emitting device, (one or more) printers, and the like. Additionally or alternatively, (one or more) sensors may be used as input circuits 984 (e.g., image capture devices, motion capture devices, etc.) and one or more actuators may be used as output device circuits 984 (e.g., actuators to provide tactile feedback, etc.). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power supply interfaces, and the like. In some embodiments, in the context of the present system, the display or console hardware may be used to provide output and receive input to the edge computing system; manage components or services of the edge computing system; identify the status of edge computing components or services; or perform any other number of management or administrative functions or service use cases.

[0118] The components of system 950 may communicate via IX 956. IX 956 may include any number of technologies including ISA, extended ISA, I2C, SPI, point-to-point interface, power management bus (PMBus), PCI, PCIe, PCIx, Intel UPI, Intel Accelerator Link, Intel CXL, CAPI, OpenCAPI, Intel QPI, UPI, Intel OPA IX, RapidIO TM System IX, CCIX, Gen-Z Consortium IX, HyperTransport Interconnect, by NVIDIA NVLink, Time-Trigger Protocol (TTP) systems, FlexRay systems, PROFIBUS, and / or any number of other IX technologies provided. IX 956 can be a proprietary bus used, for example, in a SoC-based system.

[0119] The number, capabilities, and / or capacity of the elements of the system 950 may vary, depending on whether the computing system 950 is used as a fixed computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smart phone, a tablet computing device, a laptop computer, a gaming console, an IoT device, etc.). In various implementations, the computing device system 950 may include one or more components of a data center, a desktop computer, a workstation, a laptop computer, a smart phone, a tablet device, a digital camera, a smart appliance, a smart home hub, a network appliance, and / or any other device / system that processes data.

[0120] The techniques described herein may be performed in part or in whole by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions that implement any other process discussed herein). The instructions associated with the flow charts (and / or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.

[0121] The storage medium may be a tangible, non-transitory machine-readable medium, such as read only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROM), Digital Versatile Disk (DVD)), and the like.

[0122] The storage medium may be included in, for example, a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet device, a game console, a set-top box, an embedded system, a TV (television), or a personal desktop computer.

[0123] Some non-limiting examples of various embodiments are given below.

[0124] Example 1 includes a device comprising: a plurality of flip-flops, wherein each of the plurality of flip-flops includes an internal device and a storage node; and a shared device shared by the plurality of flip-flops, wherein for each of the plurality of flip-flops, the internal device is coupled to the shared device, and the internal device in combination with the shared device is part of a circuit capable of maintaining a value in the storage node, wherein the internal device includes a unidirectional transistor.

[0125] Example 2 includes an apparatus as described in Example 1, wherein: in each of the plurality of triggers, the internal device includes a p-type FET connected in series with an n-type field effect transistor (FET); and the shared device includes at least one of: a p-type FET connected in series with the p-type FET of the internal device, or an n-type FET connected in series with the n-type FET of the internal device.

[0126] Example 3 includes an apparatus as described in Example 1 or 2, wherein: in each of the plurality of triggers, the internal device includes a p-type FET connected in series with an n-type field effect transistor (FET); and the shared device includes a p-type FET connected in series with the p-type FET of the internal device and an n-type FET connected in series with the n-type FET of the internal device.

[0127] Example 4 includes an apparatus as described in any one of Examples 1-3, wherein: each of the multiple flip-flops includes a main latch coupled to a sub-latch; and in each of the multiple flip-flops, the internal device includes an internal device in the main latch and an internal device in the sub-latch, and the internal device in the main latch is coupled to a first subset of the shared devices and the internal device in the sub-latch is coupled to a second subset of the shared devices.

[0128] Example 5 includes an apparatus as described in Example 4, wherein: a first subset of the shared devices includes a p-type field effect transistor (FET) and an n-type FET; a second subset of the shared devices includes a p-type FET and an n-type FET; and for each trigger of the plurality of triggers: the internal devices in the master latch include a p-type FET and an n-type FET connected in series with the p-type FET and the n-type FET of the first subset; and the internal devices in the sub-latch include a p-type FET and an n-type FET connected in series with the p-type FET and the n-type FET of the second subset.

[0129] Example 6 includes an apparatus as described in any one of Examples 1-5, wherein, in each of the plurality of flip-flops: the internal device includes a p-type FET connected in series with an n-type field effect transistor (FET); the storage node is coupled to drain terminals of the p-type FET and the n-type FET and to an input of an inverter; and the output of the inverter is coupled to control gates of the p-type FET and the n-type FET.

[0130] Example 7 includes an apparatus as described in any of Examples 1-6, wherein each of the plurality of flip-flops includes a transmission gate coupled to the storage node, and the transmission gate passes a data bit to the storage node based on a complementary clock signal received by the transmission gate.

[0131] Example 8 includes the apparatus of any of Examples 1-7, wherein, for each flip-flop of the plurality of flip-flops, the internal device in combination with the shared device comprises a tri-state inverter.

[0132] Example 9 includes an apparatus as described in any of Examples 1-8, further including at least one of the following items in which the multiple triggers are provided: an integrated circuit, a system on a chip, a system-in-package, a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an interface circuit, an output circuit, an external device, or a computing device.

[0133] Example 10 includes a trigger comprising: a storage node; and a first p-type FET connected in series with a first n-type field effect transistor (FET), wherein: the storage node is coupled to drain terminals of the first p-type FET and the first n-type FET; the first p-type FET is connected in series with a shared p-type FET, and the shared p-type FET is coupled to at least one other trigger; the first n-type FET is connected in series with a shared n-type FET, and the shared n-type FET is coupled to the at least one other trigger; and the first p-type FET and the first n-type FET comprise unidirectional transistors.

[0134] Example 11 includes the flip-flop of Example 10, wherein the first p-type FET and the first n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a circuit capable of maintaining a value in the storage node.

[0135] Example 12 includes the flip-flop of Example 10, wherein the first p-type FET and the first n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a tri-state inverter.

[0136] Example 13 includes the flip-flop of Example 12, wherein the tri-state inverter transfers the data bit to the storage node based on a complementary clock signal received by the tri-state inverter.

[0137] Example 14 includes a trigger as described in any of Examples 10-13, further including a second p-type FET in series with a second n-type FET, wherein: the second p-type FET is in series with the shared p-type FET; the second n-type FET is in series with the shared n-type FET; the first p-type FET and the first n-type FET, in combination with the shared p-type FET and the shared n-type FET, are part of a circuit capable of maintaining the value in the storage node; and the second p-type FET and the second n-type FET, in combination with the shared p-type FET and the shared n-type FET, are part of a three-state inverter.

[0138] Example 15 includes a trigger as described in any of Examples 10-14, wherein: the drain terminal of the shared p-type FET is coupled to a power supply source; the source of the shared n-type FET is coupled to ground; and the unidirectional transistor enables current to flow from the power supply source to ground.

[0139] Example 16 includes a trigger comprising: a first storage node; a second storage node; and a first p-type FET connected in series with a first n-type field effect transistor (FET); and a second p-type FET connected in series with a second n-type FET, wherein: an output node between the first p-type FET and the first n-type FET is coupled to the first storage node; the first p-type FET is connected in series with a first shared p-type FET coupled to at least one other trigger, and in series with a first shared n-type FET coupled to the at least one other trigger; an output node between the second p-type FET and the second n-type FET is coupled to the second storage node; and the second p-type FET is connected in series with a second shared p-type FET coupled to the at least one other trigger, and in series with a second shared n-type FET coupled to the at least one other trigger.

[0140] Example 17 includes the flip-flop of Example 16, wherein the first p-type FET, the first n-type FET, the second p-type FET, and the second n-type FET are each unidirectional transistors.

[0141] Example 18 includes a trigger as described in Example 16 or 17, wherein: the first p-type FET and the first n-type FET combined with the first shared p-type FET and the first shared n-type FET are part of a first three-state inverter; and the second p-type FET and the second n-type FET combined with the second shared p-type FET and the second shared n-type FET are part of a second three-state inverter.

[0142] Example 19 includes the flip-flop of any of Examples 16-18, wherein the flip-flop is keeper-less.

[0143] Example 20 includes a trigger as described in any one of Examples 16-19, wherein: the first storage node, the first p-type FET and the first n-type FET are in a main latch; the second storage node, the second p-type FET and the second n-type FET are in a sub-latch; and the main latch is coupled in series with the sub-latch, and there is no inverter between the main latch and the sub-latch.

[0144] Example 21 includes a method comprising: receiving data bits at multiple flip-flops, wherein each flip-flop includes a storage node to store each data bit; and at the storage node of each flip-flop, utilizing an internal device of the flip-flop and a shared device shared by the multiple flip-flops to enhance the value of the data bit, wherein the internal device includes a unidirectional transistor.

[0145] Example 22 includes the method of Example 21, wherein the storage node is in a primary latch or a secondary latch of each flip-flop.

[0146] Example 23 includes a method as described in Example 21 or 22, wherein: in each of the plurality of triggers, the internal device includes a p-type FET connected in series with an n-type field effect transistor (FET); and the shared device includes a p-type FET connected in series with the p-type FET of the internal device and an n-type FET connected in series with the n-type FET of the internal device.

[0147] Example 24 includes a non-transitory machine-readable storage device including machine-readable instructions that, when executed, cause a processor or other circuit or computing device to implement a method as described in any of Examples 21-23.

[0148] Example 25 includes a computer program comprising instructions that, when executed by a computer, cause the computer to perform the method as described in any one of Examples 21-23.

[0149] In the detailed description herein, reference is made to the accompanying drawings, which form a part of this document, wherein like reference numerals designate like parts throughout, and in which embodiments that may be implemented are illustrated in the accompanying drawings. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0150] Various operations may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as meaning that these operations must be dependent on the order. Specifically, these operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0151] The terms "substantially," "close," "roughly," "approximately," and "about" generally refer to within + / -10% of a target value. Unless otherwise indicated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects simply indicates that different instances of similar objects are referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0152] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0153] The description may use the phrases "in one embodiment" or "in an embodiment", each of which may refer to one or more identical or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous.

[0154] As used herein, the term "circuitry" may refer to, be a part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. As used herein, a "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smart phone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0155] The terms "coupled," "communicatively coupled," and their derivatives are used herein. The term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, may mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and / or may mean that one or more other elements are coupled or connected between the elements allegedly coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact with each other. The term "communicatively coupled" may mean that two or more elements are in contact with each other by means of communication, including by wires or other interconnections, by wireless communication channels or links, and the like.

[0156] References in the specification to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" mean that the particular features, structures or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment", "one embodiment" or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure or characteristic "may", "might" or "could" be included, that particular component, feature, structure or characteristic is not required to be included. If the specification or claims refer to "a" or "an" element, it does not mean that there is only one of that element. If the specification or claims refer to "an additional" element, it does not exclude that there is more than one of that additional element.

[0157] In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any appropriate manner. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0158] Although the present disclosure has been described in conjunction with its specific embodiments, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications and variations falling within the broad scope of the appended claims.

[0159] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the given figures. In addition, the arrangement may be shown in block diagram form to avoid obscuring the present disclosure, and also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure is to be implemented (i.e., such specific details should be fully within the scope of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be clear to those skilled in the art that the present disclosure may be implemented without these specific details, or with variations of these specific details. The specification should therefore be considered illustrative, not restrictive.

[0160] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: a plurality of flip-flops, wherein each flip-flop of the plurality of flip-flops comprises an internal device and a storage node; as well as A shared device shared by the plurality of flip-flops, wherein for each of the plurality of flip-flops, the internal device is coupled to the shared device, and the combination of the internal device and the shared device is part of a keeper circuit capable of maintaining a value in the storage node, wherein the internal device and the shared device include unidirectional transistors.

2. The device of claim 1, wherein: In each of the plurality of flip-flops, the internal device comprises a p-type field effect transistor (FET) connected in series with an n-type FET; and The shared device includes at least one of: a p-type FET connected in series with a p-type FET of the internal device, or an n-type FET connected in series with an n-type FET of the internal device.

3. The device according to claim 1 or 2, wherein: In each of the plurality of flip-flops, the internal device comprises a p-type field effect transistor (FET) connected in series with an n-type FET; and The shared device includes a p-type FET connected in series with the p-type FET of the internal device and an n-type FET connected in series with the n-type FET of the internal device.

4. The device according to claim 1 or 2, wherein: Each flip-flop of the plurality of flip-flops includes a leader latch coupled to a follower latch; and In each of the plurality of flip-flops, the internal devices include an internal device in the leader latch and an internal device in the follower latch, the internal device in the leader latch being coupled to a first subset of the shared devices and the internal device in the follower latch being coupled to a second subset of the shared devices.

5. The device of claim 4, wherein: The first subset of shared devices includes p-type field effect transistors (FETs) and n-type FETs; The second subset of shared devices includes p-type FETs and n-type FETs; and For each trigger in the plurality of triggers: the internal devices in the leader latch include a p-type FET and an n-type FET connected in series with the p-type FET and the n-type FET of the first subset; and The internal devices in the follower latch include a series-connected p-type FET and an n-type FET in series with the p-type FET and the n-type FET of the second subset.

6. The device according to claim 1 or 2, wherein: In each of the plurality of triggers: The internal device includes a p-type field effect transistor (FET) connected in series with an n-type FET; The storage node is coupled to drain terminals of the p-type FET and the n-type FET and to an input of an inverter; and The output of the inverter is coupled to the control gates of the p-type FET and the n-type FET.

7. The device according to claim 1 or 2, wherein: Each of the plurality of flip-flops includes a transmission gate coupled to the storage node, and the transmission gate transfers a data bit to the storage node based on a complementary clock signal received by the transmission gate.

8. The device according to claim 1 or 2, wherein: For each flip-flop of the plurality of flip-flops, a combination of the internal device and the shared device comprises a tri-state inverter.

9. The apparatus of claim 1 or 2, further comprising at least one of the following in which the plurality of triggers and the shared device are provided: an integrated circuit, a system on a chip, a system in a package, a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an interface circuit, an output circuit, an external device, or a computing device.

10. A trigger, comprising: Storage nodes; as well as a first p-type field effect transistor (FET) connected in series with a first n-type FET; wherein: the storage node is coupled to drain terminals of the first p-type FET and the first n-type FET; The first p-type FET is connected in series with a shared p-type FET, and the shared p-type FET is coupled to at least one other trigger; the first n-type FET is in series with a shared n-type FET, the shared n-type FET being coupled to the at least one other flip-flop; and The first p-type FET, the first n-type FET, and the shared p-type FET and the shared n-type FET comprise unidirectional transistors.

11. The trigger as claimed in claim 10, wherein: The first p-type FET and the first n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a keeper circuit capable of maintaining a value in the storage node.

12. The trigger as claimed in claim 10, wherein: The first p-type FET and the first n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a tri-state inverter.

13. The trigger of claim 12, wherein: The tri-state inverter transfers a data bit to the storage node based on a complementary clock signal received by the tri-state inverter.

14. The trigger as claimed in claim 10 or 11, further comprising a second p-type FET connected in series with the second n-type FET, wherein: The second p-type FET is connected in series with the shared p-type FET; The second n-type FET is connected in series with the shared n-type FET; the first p-type FET and the first n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a keeper circuit capable of maintaining a value in the storage node; and The second p-type FET and the second n-type FET in combination with the shared p-type FET and the shared n-type FET are part of a tri-state inverter.

15. The trigger according to claim 10 or 11, wherein: A drain terminal of the shared p-type FET is coupled to a power supply source; The source of the shared n-type FET is coupled to ground; and The unidirectional transistor allows current to flow from the power supply to ground.

16. A trigger, comprising: A first storage node; The second storage node; as well as a first p-type field effect transistor (FET) connected in series with a first n-type FET; as well as A second p-type FET in series with a second n-type FET, wherein: An output node between the first p-type FET and the first n-type FET is coupled to the first storage node; the first p-type FET being in series with a first shared p-type FET coupled to at least one other flip-flop and in series with a first shared n-type FET coupled to the at least one other flip-flop; An output node between the second p-type FET and the second n-type FET is coupled to the second storage node; and The second p-type FET is connected in series with a second shared p-type FET coupled to the at least one other flip-flop, and in series with a second shared n-type FET coupled to the at least one other flip-flop.

17. The trigger of claim 16, wherein: Each FET is a unidirectional transistor.

18. A trigger as claimed in claim 16 or 17, wherein: The first p-type FET and the first n-type FET in combination with the first shared p-type FET and the first shared n-type FET are part of a first tri-state inverter; and The second p-type FET and the second n-type FET in combination with the second shared p-type FET and the second shared n-type FET are part of a second three-state inverter.

19. The trigger according to claim 16 or 17, wherein: The trigger is keeper-less.

20. The trigger of claim 16 or 17, wherein: The first storage node, the first p-type FET, and the first n-type FET are in a leader latch; The second storage node, the second p-type FET, and the second n-type FET are in a follower latch; and The leader latch is coupled in series with the follower latch without an inverter between the leader latch and the follower latch.

21. A method comprising: receiving data bits at a plurality of flip-flops, wherein each flip-flop includes a storage node to store a respective data bit; and At the storage node of each flip-flop, the value of the data bit is strengthened using an internal device of the flip-flop and a shared device shared by the plurality of flip-flops, wherein the internal device and the shared device include unidirectional transistors.

22. A non-transitory machine-readable storage medium comprising machine-readable instructions which, when executed, cause a processor or other circuit or computing device to perform a method comprising: receiving data bits at a plurality of flip-flops, wherein each flip-flop includes a storage node to store a respective data bit; and At the storage node of each flip-flop, the value of the data bit is strengthened using an internal device of the flip-flop and a shared device shared by the plurality of flip-flops, wherein the internal device and the shared device include unidirectional transistors.

23. The non-transitory machine-readable storage medium of claim 22, wherein: The storage node is a leader latch or a follower latch for each flip-flop.

24. The non-transitory machine-readable storage medium of claim 22 or 23, wherein: In each of the plurality of flip-flops, the internal device comprises a p-type field effect transistor (FET) connected in series with an n-type FET; and The shared device includes a p-type FET connected in series with the p-type FET of the internal device and an n-type FET connected in series with the n-type FET of the internal device.

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