Timing shutdown circuit and ATE test system

Abstract

The invention provides a timing power-off circuit and an ATE test system. The timing power-off circuit comprises a power-off button, a timing circuit and a power-down circuit which are connected in sequence. A movable end of the shutdown button is connected with a first power supply, and a fixed end of the shutdown button is connected with the timing circuit; the timing circuit comprises a second resistor, a first triode, a first capacitor, a second triode and a third triode; the power-down circuit comprises a relay and a contactor, a coil of the relay is connected with a collector electrode of the third triode, an auxiliary contact of the relay is connected between an auxiliary contact of the contactor and the coil, the auxiliary contact of the contactor is connected with a third power supply, and the coil is grounded. The timing circuit is constructed between the shutdown button and the power-down circuit by using the triode, the capacitor and other components, so that the timing power-down shutdown function of the equipment can be realized when the shutdown button is continuously pressed down, and the problem that the equipment is shut down by mistake due to the fact that the shutdown button is touched by mistake is prevented.

Description

Technical Field

[0001] The present application relates to the technical field of switch circuits, and in particular to a timed shutdown circuit and an ATE test system. Background Art

[0002] The shutdown button configured on ATE (Automatic Test Equipment) equipment is usually not used frequently, but it is inevitable that the user may accidentally press it. If the user accidentally presses it and causes the equipment to shut down, it may cause data loss and pipeline confusion. It may also cause program errors due to software power failure, thereby causing economic losses to the ATE equipment user.

[0003] In the prior art, there are some measures to prevent accidental touches of shutdown buttons of large industrial equipment, such as using passwords, double buttons, physical covers, etc. However, these methods may be complicated to operate, costly, or inflexible. Summary of the invention

[0004] In view of this, the present application proposes a timed shutdown circuit and an ATE test system. By utilizing components such as transistors and capacitors to construct a timing circuit between the shutdown button and the power-off circuit, the timed power-off shutdown function of the device can be realized when the shutdown button is pressed continuously, thereby preventing the device from shutting down accidentally due to accidentally touching the shutdown button.

[0005] In a first aspect, the present application provides a timed shutdown circuit, comprising a shutdown button, a timing circuit, and a power-off circuit connected in sequence;

[0006] One movable end of the shutdown button is connected to the first power supply, and the other movable end is grounded through a first resistor. The fixed end of the shutdown button is connected to the timing circuit, so as to transmit the first power supply signal to the timing circuit when the shutdown button is turned on.

[0007] The timing circuit comprises a second resistor, a first transistor, a first capacitor, a second transistor and a third transistor, one end of the second resistor is connected to the fixed end of the shutdown button, and the other end is connected to the emitter of the first transistor, the base of the first transistor is connected to the fixed end of the shutdown button, the collector is connected in series with the first capacitor and then grounded, the base of the second transistor is connected to the collector of the first transistor, the collector is connected to the second power supply through the third resistor, the emitter is grounded, the base of the third transistor is connected to the collector of the second transistor, the emitter is connected to the second power supply, and the collector is connected to the power-off circuit;

[0008] The power-off circuit includes a relay and a contactor, the coil of the relay is connected to the collector of the third transistor, the auxiliary contact is connected between the auxiliary contact of the contactor and the coil, the auxiliary contact of the contactor is connected to the third power supply, and the coil is grounded.

[0009] From the above, in the timing shutdown circuit provided by the present application, a timing circuit is set between the shutdown button and the power-off circuit to realize the function of timing power-off shutdown, wherein the timing circuit realizes the capacitor timing charging function through the second resistor, the first transistor and the first capacitor. When the shutdown button is continuously pressed, the first transistor is turned on, the first power supply charges the first capacitor through the second resistor and the first transistor, and connects the second transistor through the collector of the first transistor. When the voltage charged by the first capacitor reaches the turn-on voltage of the second transistor, the second transistor is turned on. At this time, the second power supply flows into the collector and emitter of the second transistor through the third resistor. The voltage drop generated at both ends of the third resistor provides a turn-on voltage for the third transistor. The third transistor is turned on, and the second power supply provides an electrical signal to the coil of the relay through the emitter and collector of the third transistor. The auxiliary contacts of the relay are disconnected, and the electrical signal provided by the third power supply to the coil of the contactor is disconnected, and the contactor loses power and disconnects, thereby realizing the power-off shutdown of the device. Through this application, the timed power-off shutdown function of the device can be realized when the shutdown button is pressed continuously, thereby preventing the device from shutting down accidentally due to accidentally touching the shutdown button.

[0010] Optionally, the timing circuit also includes a first diode, a photocoupler, a fourth resistor and a fifth resistor, the first diode and the input side of the photocoupler are connected in series between the fixed end of the shutdown button and the base of the first transistor, the fifth resistor is connected in series between the input side of the photocoupler and ground, the fourth resistor and the output side of the photocoupler are connected in series between a fourth power supply and ground, and when the photocoupler is turned on, its output side outputs a turn-on signal.

[0011] From the above, the software timed shutdown function can be realized through diodes, photocouplers and resistors, wherein one end of the first diode is connected to the fixed end of the shutdown button, and the other end is connected in series to the input side of the photocoupler and then connected to the base of the first transistor. One end of the output side of the photocoupler is connected to the fourth power supply through the fourth resistor, and the other end is grounded. When the shutdown button is continuously pressed, the electrical signal of the first power supply reaches the input side of the photocoupler after passing through the shutdown button and the first diode. The photocoupler is turned on, and the high-level signal provided by the fourth power supply to the output side is pulled down due to the conduction of the photocoupler. At this time, the output side of the photocoupler continuously outputs a low-level conduction signal, which can be sampled and timed by an external device, thereby realizing a timed shutdown at the software level. At the same time, a constant current source can also be formed by the first diode, the photocoupler, the second resistor and the fifth resistor, so that the first capacitor is charged by the constant current source, thereby realizing the function of precise timing and charging.

[0012] Optionally, a detection chip is further included, the detection chip is used to receive the conduction signal of the photoelectric coupler, and realize the software timed shutdown function according to the timing duration of the conduction signal;

[0013] The timing duration for implementing the software timed shutdown function is less than the charging duration of the first capacitor.

[0014] From the above, the low-level conduction signal output by the photocoupler is sampled and timed by the detection chip to execute the preset software timing power-off strategy according to the timing duration. The software timing duration is less than the hardware timing duration. Therefore, after the timing duration reaches the software timing duration, the software timing power-off strategy can be executed. Even if the software fails, the shutdown button can be continued to be pressed until the first capacitor is charged to the rated value, thereby driving the back-end circuit to be turned on, thereby realizing the hardware timing shutdown function.

[0015] Optionally, it also includes a voltage stabilizing circuit, which includes a sixth resistor and a voltage stabilizing diode connected in series between the fifth power supply and ground, and the connection node between the sixth resistor and the voltage stabilizing diode is connected to the emitter of the second transistor.

[0016] From the above, by setting a voltage stabilizing circuit consisting of a voltage stabilizing diode at the emitter of the second transistor, a stable reference voltage is provided for the emitter of the second transistor. When the voltage after charging the first capacitor rises to the rated voltage of the voltage stabilizing diode and the turn-on voltage of the second transistor, the second transistor can be turned on.

[0017] Optionally, the timing circuit also includes a second capacitor connected in series between the emitter of the second transistor and ground.

[0018] As described above, by setting the second capacitor between the emitter of the second transistor and the ground, it can be used to eliminate spike noise such as burrs in the current signal output by the emitter of the second transistor, which helps to maintain the stability of the second transistor.

[0019] Optionally, a power button is also included, and the power button is connected in parallel to both ends of the auxiliary contacts of the contactor.

[0020] From the above, by connecting the power button in parallel at both ends of the auxiliary contacts of the contactor, a power-on interlocking circuit is formed with the contactor. When the power button is pressed and released, the auxiliary contacts of the contactor are closed, and the third power supply normally supplies power to the equipment.

[0021] Optionally, the timing circuit further includes a second diode connected in series inversely to the fixed end of the shutdown button and the input end of the first capacitor.

[0022] From the above, in order to avoid the problem that the capacitor cannot be completely discharged due to frequent power on and off, resulting in the timing circuit being unable to accurately time, a second diode is set at the fixed end of the power-off button and the input end of the first capacitor. When the power-off button is released, the moving end of the power-off button is grounded through the first resistor. At this time, the second diode and the first resistor form a discharge circuit of the first capacitor. The first capacitor is completely discharged through the second diode and the first resistor, thereby effectively reducing the time interval required for the device to be turned on and off.

[0023] Optionally, the timing circuit further includes a third diode connected in series in reverse direction between the collector of the third transistor and the ground.

[0024] From the above, by setting a reverse diode between the collector and the ground of the third transistor, reverse protection is provided for the third transistor to prevent voltage fluctuations from causing damage to other components in the circuit.

[0025] Optionally, the first transistor and the third transistor are PNP transistors, and the second transistor is an NPN transistor.

[0026] From the above, through the first PNP-type transistor, when the first transistor is turned on, the base current is very small, and most of the current charges the first capacitor through the collector. When the charging voltage of the first capacitor reaches the turn-on voltage of the base and emitter of the second NPN-type transistor, the second transistor is turned on, and the voltage drop generated by the second power supply through the third resistor provides a turn-on voltage for the emitter and base of the third PNP-type transistor. The third transistor is turned on, and most of the current of the second power supply through the third transistor reaches the coil of the relay through the collector, so that the coil of the relay is energized and the auxiliary contact is driven to be disconnected.

[0027] In a second aspect, the present application provides an ATE test system, including a power cabinet, a test head, and a timed shutdown circuit as described above;

[0028] The timed shutdown circuit is connected between the power cabinet and the test head, and is used to implement power switch control from the power cabinet to the test head.

[0029] From the above, by setting the above-mentioned timed shutdown circuit between the power cabinet and the test head of the ATE test system, the timed power-off shutdown function of the ATE test system can be realized when the shutdown button is pressed continuously, thereby preventing the ATE test system from shutting down accidentally due to accidental pressing of the shutdown button.

[0030] These and other aspects of the present application will become more apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A schematic diagram of a module of a timed shutdown circuit provided in an embodiment of the present application;

[0032] Figure 2 A circuit diagram of a timer shutdown circuit in a powered-on state provided in an embodiment of the present application;

[0033] Figure 3 A circuit diagram of a timed shutdown circuit in shutdown mode provided in an embodiment of the present application;

[0034] Figure 4 A structural diagram of an ATE test system provided in an embodiment of the present application.

[0035] It should be understood that the size and shape of each block diagram in the above structural diagram are for reference only and should not constitute an exclusive interpretation of the embodiments of the present application. The relative positions and inclusion relationships between the blocks presented in the structural diagram are only schematic representations of the structural associations between the blocks, and do not limit the physical connection methods of the embodiments of the present application. DETAILED DESCRIPTION

[0036] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of the present application are mainly to illustrate the possible implementation methods of the technical solution of the present application and should not be interpreted as the only limitation on the technical solution of the present application. It is known to those of ordinary skill in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0038] The embodiment of the present application proposes a timed shutdown circuit and an ATE test system, wherein the timed shutdown circuit can realize hardware timed shutdown function and software timed shutdown function respectively, allowing the system to be powered off by software and hardware. The software power-off can be powered off according to the set timing sequence after the timing is completed, which is convenient for saving test data and resetting the test board; the hardware power-off avoids the main control freeze, logic errors and other problems that may occur in the software. The timing circuit is constructed and implemented only by low-cost components such as transistors and capacitors. When the shutdown button is pressed continuously, it can accurately calculate the power-off duration by controlling the capacitor charging current, realize the timed power-off shutdown function of the device, and prevent the device from shutting down by mistake due to the accidental touch of the shutdown button.

[0039] Refer to the following Figure 1-Figure 3 The circuit structure and working principle of a timed shutdown circuit provided in an embodiment of the present application are described in detail.

[0040] like Figure 1 As shown, a timed shutdown circuit provided in an embodiment of the present application includes a shutdown button 110, a timing circuit 120 and a power-off circuit 130 connected in sequence, wherein the input end of the shutdown button 110 is connected to a power supply, and by continuously pressing the shutdown button 110, the power signal passes through the shutdown button 110 to reach the timing circuit 120, and the pressing time of the shutdown button 110 is timed by the timing circuit 120, and when the specified time is reached, the back-end power-off circuit 130 is driven to power off and shut down the device, thereby realizing a software timed shutdown function or a hardware timed shutdown function, and preventing the device from shutting down accidentally due to accidentally touching the shutdown button.

[0041] like Figure 2 or Figure 3 As shown, one active end of the shutdown button S1 is connected to the power supply VCC_1, and the other active end is connected in series with a resistor R1 and then grounded. The fixed end of the power button S1 is connected to the timing circuit 120. Specifically, the fixed end of the power button S1 is connected in series with a resistor R3 and then connected to the emitter of a PNP transistor Q1. The base of the transistor Q1 is connected in series with a resistor R4 and then grounded. The collector is connected in series with a capacitor C1 and then grounded. The fixed end of the power button S1 is also connected in series with a diode D1 and an optocoupler U1. The input side (light emitting diode) is connected to the base of the transistor Q1 to provide a voltage drop for the emitter and base of the transistor Q1. When the shutdown button S1 is pressed continuously, the current signal output by the power supply VCC_1 flows to the resistor R4 through the resistor R3 and the emitter and base of the transistor Q1. The diode D1 connected in parallel to the resistor R3 and the emitter and base of the transistor Q1 and the input side of the photocoupler U1 provide a conduction voltage drop U for the emitter and base of the transistor Q1. D1 and U U1 Since the current flowing through the base of Q1 is very weak, it can be regarded as that all the current flows into the capacitor C1 and charges the capacitor C1. The resistor R4 needs to be set to a suitable resistance value so that the diode D1 and the input side of the photocoupler U1 can generate a suitable voltage drop, thereby generating a suitable current to charge the capacitor C1 through the voltage drop and the resistor R3. In this way, a constant current source for charging the capacitor C1 can be formed by the diode D1, the photocoupler U1, the resistor R3 and the resistor R4, thereby realizing the function of precise timing charging.

[0042] One end of the output side (photosensitive transistor) of the photocoupler U1 is connected to the pull-up power supply VCC_4 through the resistor R2, and the other end is grounded. When the photocoupler U1 is not turned on, the pull-up power supply VCC_4 outputs a high-level signal through the resistor R2. When the photocoupler U1 is turned on, the level signal output by the pull-up power supply VCC_4 through the resistor R2 is pulled low. At this time, the pull-up power supply VCC_4 outputs a low-level signal through the resistor R2. Therefore, by detecting the signal output by the pull-up power supply VCC_4 through the resistor R2 through a detection chip (such as an MCU chip or an FPGA chip), it can be determined whether the shutdown button S1 is pressed, and the low-level signal output by the pull-up power supply VCC_4 through the resistor R2 is timed by the detection chip, thereby executing the preset software timing power-off strategy according to the timing duration.

[0043] The collector of the transistor Q1 is connected to the base of the NPN transistor Q2, the collector of the transistor Q2 is connected to the pull-up power supply VCC_2 through the resistor R6, and the emitter is connected in series with the capacitor C2 and then grounded. The capacitor C2 can be used to eliminate spike noise such as burrs in the current signal output by the emitter of the transistor Q2, which helps to maintain the stability of the transistor Q2. In addition, the emitter of the transistor Q2 is also connected to a voltage stabilizing circuit composed of a resistor R5 and a voltage stabilizing diode D3. The resistor R5 and the voltage stabilizing diode D3 are connected in series between the power supply VCC_5 and the ground. The voltage stabilizing diode D3 stabilizes the voltage of the power supply VCC_5 at its rated voltage value, thereby providing a stable reference voltage for the emitter of the transistor Q2. When the voltage of the charged capacitor C1 rises to the rated voltage of the voltage stabilizing diode D3 and the conduction voltage required by the base and emitter of the transistor Q2, the transistor Q2 can be turned on. The collector of the transistor Q2 is connected to the base of the PNP-type transistor Q3, and the emitter of the transistor Q3 is connected to the pull-up power supply VCC_2. The collector is connected in series with a reverse diode D4 and then connected to When the transistor Q2 is turned on, the power supply VCC_2 drives the transistor Q3 to turn on through the voltage drop generated by the resistor R6, and the collector of the transistor Q3 is connected to the coil of the relay K1 of the power-off circuit 130, and the auxiliary contact of the relay K1 is connected in series between the auxiliary contact and the coil of the contactor K2, and the other end of the auxiliary contact of the contactor K2 is connected to the power supply VCC_3, and the other end of the coil of the contactor K2 is grounded. When the transistor Q3 is turned on, the current signal of the power supply VCC_2 reaches the coil of the relay K1 through the collector of the transistor Q3, driving the auxiliary contact of the relay K1 to disconnect, and the coil of the contactor K2 loses power, thereby causing the auxiliary contact of the contactor K2 to disconnect, and the power supply of the power supply VCC_3 to the device is disconnected.

[0044] A power button S2 is also connected to both ends of the auxiliary contacts of the contactor K2. The power button S2 can form a power-on interlocking circuit with the auxiliary contacts of the contactor K2. When the power button S2 is pressed and released, the auxiliary contacts of the contactor K2 are closed, and the power supply VCC_3 can normally power the device.

[0045] Since the embodiment of the present application uses a diode D1, a photocoupler U1 and a resistor R4 to form a constant current source for charging the capacitor C1, and the hardware timed shutdown function is realized by controlling the charging time of the capacitor C1, in order to avoid the problem that the capacitor C1 cannot be completely discharged due to frequent power on and off, resulting in the inability of the timing circuit to accurately time, a reverse diode D2 is provided at the fixed end of the shutdown button S1 and the input end of the capacitor C1. When the power on and off button S1 is released, the moving end of the shutdown button S1 is grounded through the resistor R1. At this time, the diode D2 and the resistor R1 form a discharge circuit of the capacitor C1. The capacitor C1 is completely discharged to the ground end through the diode D2 and the resistor R1, thereby effectively reducing the time interval required for the power on and off operations of the device.

[0046] Refer to the following Figure 2-Figure 3 The working principle of the timer shutdown circuit in the embodiment of the present application is described in detail.

[0047] When the shutdown button S1 is pressed, Figure 2 As shown, the active end of the shutdown button S1 is connected to the power supply VCC_1, and the current of the power supply VCC_1 flows to the resistor R4 through the resistor R3 and the emitter and base of the transistor Q1. The diode D1 connected in parallel to the resistor R3 and the emitter and base of the transistor Q1 and the input side of the photocoupler U1 provide a conduction voltage drop U for the emitter and base of the transistor Q1. D1 and U U1 , since the current flowing through the base of transistor Q1 is very weak, it can be regarded as that the current passing through resistor R3 all flows into capacitor C1 and charges capacitor C1. In addition, it should be noted that since the current flowing through the base of transistor Q1 is very weak, the value of resistor R4 will affect the voltage drop on the input side of diode D1 and photoelectric coupler U1. The specific voltage drop value can be obtained through the volt-ampere characteristic curve of diode D1 and photoelectric coupler U1. So far, the embodiment of the present application completes the circuit design of a constant current source charging capacitor C1 through diode D1, photoelectric coupler U1, resistor R3 and resistor R4, and the current output by the constant current source can be obtained according to the following formula:

[0048]

[0049] Among them, U D1 is the voltage drop across diode D1, U U1 is the voltage drop across the input side of the optocoupler U1, U Q1is the voltage drop across the emitter and base of transistor Q1, and R3 is the resistance value of resistor R3.

[0050] Afterwards, the Zener diode D3 is used as the main component to control the charging voltage of the capacitor C1. The current output by the power supply VCC_5 flows through the resistor R5 and then flows into the cathode of the Zener diode D3. The Zener diode D3 will stabilize the voltage at its rated voltage value. The capacitor C2 is used to eliminate spike noise such as burrs. When the voltage across the capacitor C1 rises to the sum of the rated voltage of the Zener diode D3 and the minimum conduction voltage of the base and emitter of the transistor Q2, the transistor Q2 is turned on. At this time, the voltage across the capacitor C1 tends to be stable. The charging time (t) of the capacitor C1 is the shutdown time set by the hardware timing circuit. The calculation formula is as follows:

[0051]

[0052] Among them, U D3 is the rated voltage value of the Zener diode D3, U Q2 is the voltage drop across the base and emitter of the transistor Q2, I is the output current of the constant current source mentioned above, C1 is the capacitance of the capacitor C1, and by selecting and changing the capacitance of the capacitor C1, the rated voltage value of the Zener diode D3, and the constant current source current I, the time required by the hardware timing circuit can be adjusted to meet different application conditions.

[0053] After transistor Q2 is turned on, the current output by the pull-up power supply VCC_2 flows into the collector and emitter of transistor Q2 through resistor R6. The voltage drop generated by the current in resistor R6 provides a conduction voltage for the emitter and base of transistor Q3. At this time, transistor Q3 is turned on, the coil of relay K1 is energized, and the auxiliary contacts are as follows: Figure 2 As shown, the coil of contactor K2 loses power and its auxiliary contacts are as follows Figure 2 The device is disconnected, thereby powering off the device.

[0054] After the above equipment loses power, that is, Figure 2 After pressing the shutdown button S1, Figure 3As shown, the power button S1 is released, and a reverse diode D2 is set at the fixed end of the power button S1 and the input end of the capacitor C1. When the power button S1 is released, the moving end of the power button S1 is grounded through the resistor R1. At this time, the diode D2 and the resistor R1 form a discharge circuit of the capacitor C1. The capacitor C1 is completely discharged to the ground end through the diode D2 and the resistor R1 when the device is powered off, thereby effectively reducing the time interval required for the device to be turned on and off. The problem that the capacitor C1 cannot be completely discharged due to frequent power on and off is avoided, resulting in the timing circuit being unable to accurately time. At this point, the design of the hardware timing circuit is completed. The embodiment of the present application also provides a software timing circuit. The software timing circuit is connected to a pull-up power supply VCC_4 after a resistor R2 is connected in series at one end of the output side of the optocoupler U1. The pull-up power supply VCC_4 is also connected to a detection chip (such as an MCU chip or an FPGA chip) through a resistor R2, and outputs a high level or a low level signal to the detection chip. As shown Figure 3 As shown, when the shutdown button S1 is not actuated, there is no current signal on the input side of the photocoupler U1, the photocoupler U1 remains disconnected, and the pull-up power supply VCC_4 outputs a high-level signal to the detection chip through the resistor R2. The detection chip can judge that the shutdown button S1 is not actuated based on the high-level signal. When the shutdown button S1 is pressed, the light-emitting diode on the input side of the photocoupler U1 is turned on, thereby turning on the photosensitive transistor on the output side of the photocoupler U1, and the pull-up power supply VCC_4 outputs a low-level signal to the detection chip through the resistor R2. The detection chip times the low-level signal, thereby executing the preset software timing power-off strategy according to the timing duration.

[0055] In addition, after the device is powered off, you can also power it back on by pressing the power button S2. Figure 3 As shown, the power button S2 and contactor K2 in the circuit together form a power-on interlock circuit. After the power button S2 is pressed and released, the auxiliary contact of the contactor K2 is closed, and the device is powered on normally.

[0056] It should be noted that the software timing duration set in the embodiment of the present application is less than the hardware timing duration, so that after the timing duration reaches the software timing duration, the software timing power-off strategy can be executed, allowing the device to be powered off in sequence according to the set power-off process execution order, thereby effectively avoiding the loss of test data and the problem that the system cannot be reset normally. When the software timing circuit fails, the shutdown button can also be continued to be pressed to continuously charge the capacitor C1 to reach a stable voltage, and then the transistors Q2 and Q3 at the back end are driven to conduct, thereby disconnecting the power-off circuit and completing the forced power-off of the device, and then realizing the normal shutdown operation without software through the hardware timing circuit, that is, avoiding the problem of being unable to shut down or abnormal shutdown caused by software crash, and supporting the anti-accidental touch power-off operation completed without software, effectively solving the economic loss or production line chaos caused by the current device accidentally touching the shutdown button.

[0057] To summarize, the timing shutdown circuit provided in the embodiment of the present application can respectively implement the hardware timing shutdown function and the software timing shutdown function, allowing the power-off operation of the device to be performed through software and hardware. When the user presses the shutdown button, the software timing circuit and the hardware timing circuit will start timing at the same time. Under normal use, the shutdown time set by the software timing circuit will be less than the shutdown time set by the hardware timing circuit. When the timing time reaches the shutdown time set by the software timing circuit, the software timing power-off strategy will be executed. If an accident or failure occurs in the software, the shutdown button that is continuously pressed will trigger the system shutdown control loop through the hardware timing circuit, thereby triggering the system shutdown main loop, and the system shutdown is completed, which avoids the problem of being unable to shut down or abnormal shutdown caused by software crashes, and supports the anti-accidental touch power-off operation completed in the absence of software, effectively solving the economic losses or production line chaos caused by the current equipment accidentally touching the shutdown button.

[0058] like Figure 4 As shown, the embodiment of the present application provides an ATE test system, referring to Figure 4 As shown, the system includes a power cabinet 210 , a timer shutdown circuit 220 and a test head 230 .

[0059] The timer shutdown circuit 220 is connected between the power cabinet 210 and the test head 230 , and is used to implement power switch control from the power cabinet 210 to the test head 230 .

[0060] It should be understood that the processing details of the timing shutdown circuit in the embodiment of the present application can be referred to Figure 1-Figure 3 The related descriptions of the illustrated embodiment and related extended embodiments will not be repeated in the embodiments of the present application.

[0061] It should be noted that the embodiments described in the present application are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application usually described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0062] The words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0063] In the above description, the numbers representing the steps involved do not necessarily mean that the steps will be executed. Intermediate steps may be included or replaced by other steps. The order of the previous and next steps may be interchanged or executed simultaneously if permitted.

[0064] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0065] The "one embodiment" or "embodiment" mentioned in this specification means that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present application. Therefore, the terms "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in the various embodiments of the present application, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment according to their inherent logical relationship.

[0066] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present application is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, all of which belong to the protection scope of the present invention.

Claims

1. A timer shutdown circuit, characterized in that: It includes a shutdown button, a timing circuit and a power-off circuit connected in sequence; One movable end of the shutdown button is connected to the first power supply, and the other movable end is grounded through a first resistor. The fixed end of the shutdown button is connected to the timing circuit, so as to transmit the first power supply signal to the timing circuit when the shutdown button is turned on. The timing circuit comprises a second resistor, a first transistor, a first capacitor, a second transistor and a third transistor, one end of the second resistor is connected to the fixed end of the shutdown button, and the other end is connected to the emitter of the first transistor, the base of the first transistor is connected to the fixed end of the shutdown button, the collector is connected in series with the first capacitor and then grounded, the base of the second transistor is connected to the collector of the first transistor, the collector is connected to the second power supply through the third resistor, the emitter is grounded, the base of the third transistor is connected to the collector of the second transistor, the emitter is connected to the second power supply, and the collector is connected to the power-off circuit; The power-off circuit includes a relay and a contactor, the coil of the relay is connected to the collector of the third transistor, the auxiliary contact is connected between the auxiliary contact of the contactor and the coil, the auxiliary contact of the contactor is connected to the third power supply, and the coil is grounded.

2. The circuit according to claim 1, characterized in that The timing circuit also includes a first diode, a photocoupler, a fourth resistor and a fifth resistor. The first diode and the input side of the photocoupler are connected in series between the fixed end of the shutdown button and the base of the first transistor, the fifth resistor is connected in series between the input side of the photocoupler and the ground, and the output side of the fourth resistor and the photocoupler are connected in series between the fourth power supply and the ground. When the photocoupler is turned on, its output side outputs a turn-on signal.

3. The circuit according to claim 2, characterized in that It also includes a detection chip, which is used to receive the conduction signal of the photoelectric coupler and realize the software timed shutdown function according to the timing duration of the conduction signal; The timing duration for implementing the software timed shutdown function is less than the charging duration of the first capacitor.

4. The circuit according to claim 1, characterized in that It also includes a voltage stabilizing circuit, which includes a sixth resistor and a voltage stabilizing diode connected in series between the fifth power supply and the ground, and a connection node between the sixth resistor and the voltage stabilizing diode is connected to the emitter of the second transistor.

5. The circuit according to claim 1 or 4, characterized in that: The timing circuit also includes a second capacitor connected in series between the emitter of the second transistor and the ground.

6. The circuit according to claim 1, characterized in that It also includes a power-on button, which is connected to both ends of the auxiliary contacts of the contactor.

7. The circuit according to claim 1, characterized in that The timing circuit also includes a second diode which is reversely connected in series with the fixed end of the shutdown button and the input end of the first capacitor.

8. The circuit according to claim 1, characterized in that The timing circuit also includes a third diode which is reversely connected in series between the collector of the third transistor and the ground.

9. The circuit according to claim 1, characterized in that The first transistor and the third transistor are PNP transistors, and the second transistor is an NPN transistor.

10. An ATE test system, characterized in that: It comprises a power supply cabinet, a test head and a timed shutdown circuit as claimed in any one of claims 1 to 9; The timed shutdown circuit is connected between the power cabinet and the test head, and is used to implement power switch control from the power cabinet to the test head.

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