SAR ADC sampling circuit, ADC circuit and device

Abstract

The invention discloses an SAR ADC sampling circuit, and the circuit comprises a front-end driving module which is used for carrying out the buffering amplification of an input signal, and outputting an amplified signal; the sampling capacitor array is used for carrying out signal sampling and quantitative conversion; and the control module is used for controlling the amplification signal output by the input driving module to pre-charge the sampling capacitor of the sampling capacitor array after the sampling period starts, and controlling the sampling capacitor array to sample the input signal after a set time is delayed. By utilizing the scheme of the invention, the sampling capacitor array can adopt a larger unit capacitor, and the sampling precision is ensured.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a SAR ADC sampling circuit, an ADC circuit and a device. Background Art

[0002] SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a common analog-to-digital converter. Its working principle is to achieve the conversion of analog signals to digital signals through successive approximation. The accuracy of SAR ADC can range from 8 bits to 16 bits, and the throughput rate can range from extremely slow on-demand conversion requests to more than 1 million conversions per second. Due to its speed and performance flexibility, SAR ADC is widely used in chips such as MCU.

[0003] SAR ADC generally uses a pure capacitor structure capacitor array (C-DAC) to achieve signal sampling and conversion. The number of unit capacitors in the capacitor array is related to the accuracy and is: , N is the number of bits of the SAR ADC. For high-precision SAR ADCs (bit number N>12), the size of the traditional capacitor array increases exponentially with the increase in the number of bits ( ) grows, and with the increase of the number of bits N, the requirement for unit capacitance mismatch becomes more stringent, and a larger unit capacitance is needed to reduce the mismatch in order to meet the requirement of ADC output linearity.

[0004] During the sampling phase, the SAR ADC requires the front-end driver circuit to charge and discharge the sampling capacitor and stabilize the voltage on the sampling capacitor within the ADC accuracy requirements within a specified time. Obviously, the larger the unit capacitance in the capacitor array, the higher the requirements for the front-end driver. To address this problem, the following two methods are usually used: (1) Segmented capacitor structure, that is, the entire capacitor array is divided into high-order segments and low-order segments to reduce the number of capacitors in the high-order segment. However, no matter how the segmentation is performed, once the segmentation structure is determined, the capacitor size is also determined. In some applications, it cannot be guaranteed that the input signal provided by the user to all channels can meet the driving requirements. (2) Adding a front-end driver circuit, that is, the input signal is first buffered and amplified by the front-end driver circuit, and then sampled by the ADC sampling capacitor. This method will introduce errors in the front-end driver circuit and affect the accuracy of the ADC. Moreover, the range of the input signal will be limited by the internal buffer of the front-end driver circuit. Summary of the invention

[0005] The embodiments of the present invention provide a SAR ADC sampling circuit, an ADC circuit and a device to reduce the driving requirements of the ADC for the input signal, so that the ADC can adapt to a wider input signal range and ensure the sampling accuracy.

[0006] In one aspect, the present invention provides a SAR ADC sampling circuit, the circuit comprising: The front-end driving module is used to buffer and amplify the input signal and output the amplified signal; Sampling capacitor array, used for signal sampling and quantization conversion; The control module is used to control the amplified signal output by the input driving module to pre-charge the sampling capacitor of the sampling capacitor array after the sampling period starts, and control the sampling capacitor array to sample the input signal after a delay setting time.

[0007] Optionally, the control module includes: a control unit, a first switch, and a second switch; the first switch is respectively connected to the output end of the input driver module and the input end of the sampling capacitor array; the second switch is respectively connected to the input end of the input driver module and the input end of the sampling capacitor array; The control unit is used to control the first switch to be closed and the second switch to be opened after the sampling period starts; and to control the first switch to be opened and the second switch to be closed after a certain delay.

[0008] Optionally, the first switch and the second switch are any one of the following: a MOS tube and a triode.

[0009] Optionally, the control unit comprises: A first control signal generating unit, used to generate a first control signal according to an external reset signal, so as to control the first switch to be closed after sampling starts and to be opened after a certain delay; an inverter, configured to invert the first control signal; The second control signal generating unit is used to generate a second control signal according to the sampling signal to control the second switch to be closed and open after the sampling period ends.

[0010] Optionally, the first control signal generating unit includes a first D flip-flop, the clock signal of the first D flip-flop is the ADC clock signal, and the control signal of the first D flip-flop is the external reset signal; the second control signal generating unit includes a second D flip-flop, the clock signal of the second D flip-flop is the output signal of the inverter, and the control signal of the second D flip-flop is the sampling signal.

[0011] Optionally, the front-end driving module includes: a unity gain amplifier.

[0012] Optionally, the sampling capacitor array includes any one of the following: a capacitor array with a pure capacitor structure, and a capacitor structure array with a segmented structure.

[0013] Optionally, the sampling mode of the sampling capacitor array includes any one of the following: upper plate sampling and lower plate sampling.

[0014] On the other hand, an embodiment of the present invention further provides an ADC circuit, wherein the ADC circuit includes the SAR ADC sampling circuit.

[0015] On the other hand, an embodiment of the present invention further provides an ADC device, the device comprising: a multiplexer, and the ADC circuit; The multiplexer is connected to a plurality of external inputs and is used to select one of the external inputs as an input signal of the ADC circuit; The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

[0016] The SAR ADC sampling circuit provided by the embodiment of the present invention first uses the front-end driving module to buffer and amplify the input signal after the sampling period starts, samples the output amplified signal, and then samples the input signal. The driving capability of the input signal is improved by the front-end driving module, and the driving requirements of the ADC for the input signal are reduced, so that the ADC can adapt to a wider range of input signals. Moreover, since the front-end driving module only plays an auxiliary role and the sampling signal is ultimately driven by an external circuit, the error of the front-end driving module itself will not affect the accuracy of the sampling result.

[0017] By using the SAR ADC sampling circuit provided by the embodiment of the present invention, the design index of the sampling capacitor array inside the ADC can be relaxed, and the sampling capacitor array can use a larger unit capacitor to meet the linearity requirements of the ADC and ensure sampling accuracy.

[0018] Compared with the existing segmented C-DAC, the SAR ADC sampling circuit provided by the embodiment of the present invention can allow the ADC to select a larger unit capacitor and input capacitor during design, thereby reducing the mismatch of the capacitor array.

[0019] Compared with the existing circuit adopting the front-end driving mode, the front-end driving module in the SAR ADC sampling circuit provided by the embodiment of the present invention only plays an auxiliary role, and the error caused by it will not affect the sampling accuracy of the ADC; moreover, it can also reduce the performance requirements of the front driving module in the design.

[0020] In addition, by using the SAR ADC sampling circuit provided by the embodiment of the present invention, the ADC can be matched with a front-end multiplexer, so that the input signal can have a wider range of applications. Moreover, the multiplexer can increase the number of channels arbitrarily, and only one front-end driver module is used, which effectively saves the ADC chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 It is a schematic diagram of the segmented capacitor structure in the existing SAR ADC; Figure 2 It is a structural schematic diagram of a sampling capacitor array and a front-end driving circuit in an existing SAR ADC with an additional front-end driving circuit; Figure 3 is a schematic diagram of the structure of a SAR ADC sampling circuit provided by an embodiment of the present invention; Figure 4 Schematic diagram of the control principle of the control module on the sampling signal in an embodiment of the present invention; Figure 5 It is a specific structural schematic diagram of a SAR ADC sampling circuit and a control module provided in an embodiment of the present invention; Figure 6 yes Figure 5 A schematic diagram of the timing relationship of each signal in the embodiment shown; Figure 7 This is a schematic diagram of two commonly used sampling methods for ADC; Figure 8 It is a structural schematic diagram of a SAR ADC sampling circuit provided by an embodiment of the present invention, in which a sampling capacitor array adopts a segmented structure and a lower plate sampling method; Fig. 9 yes Figure 8 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown; Fig.10 It is a structural schematic diagram of a SAR ADC sampling circuit provided by an embodiment of the present invention, in which a sampling capacitor array adopts a segmented structure and a lower plate sampling method; Fig.11 yes Fig.10 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown; Fig.12It is a structural schematic diagram of a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention adopting a non-segmented structure and an upper plate sampling method; Fig.13 yes Fig.12 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown. DETAILED DESCRIPTION

[0023] The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

[0024] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0025] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0026] High-precision SAR ADC requires increasing the unit capacitance in the sampling capacitor array, and the increase in unit capacitance places higher requirements on the front-end driver. The following first briefly introduces the segmented capacitor structure method and the method of increasing the front-end driver circuit used in the prior art to solve this problem.

[0027] Reference Figure 1 As shown in FIG. 1 , it is a schematic diagram of a segmented capacitor structure in an existing SAR ADC.

[0028] The segmented capacitor structure divides the entire capacitor array into a high-order segment (M high-order capacitors) and a low-order segment (L low-order capacitors), where M+L=N, and N is the total number of bits of the ADC. The segmented capacitor structure uses bridge capacitors to divide the number of capacitors in the high-order segment into equal proportions (i.e. ) is reduced, thus reducing the size of the input capacitor times.

[0029] Taking 8 bits as an example, the input capacitance of the traditional structure is 256C, while Figure 1The segmented capacitor structure shown in the figure divides the capacitor array into 4-4 segments through the bridge capacitor Ca, that is, the high segment is 4 bits and the low segment is 4 bits. The sampling capacitor can be reduced to 16C (C is the unit capacitance).

[0030] Figure 1 Where Vin is the sampling voltage and Vrefp is the reference voltage.

[0031] In this segmented capacitor structure, the reduction ratio of the capacitor will be affected by the parasitic capacitance and produce deviations, thus causing the nonlinearity of the ADC. Therefore, L should not be too large, otherwise it will affect the linearity of the ADC output; while too small L will cause too much capacitance in the high-order segment, resulting in a still large input capacitance.

[0032] In addition, in some applications, the input of the SAR ADC passes through a multiplexer to allow multiple channels to call the ADC, and the above-mentioned segmented capacitor structure sometimes finds it difficult to meet the driving requirements of all channels, that is, the driving capabilities of multiple channels are different. The external input circuits of some channels can drive the capacitors inside the ADC to work normally, while the external input circuits of some channels with weak driving capabilities may not be able to drive the capacitors inside the ADC to work normally.

[0033] Reference Figure 2 , which is a schematic structural diagram of a sampling capacitor array and a front-end driving circuit in an existing SAR ADC with an additional front-end driving circuit.

[0034] The input signal Vin first passes through the front-end drive circuit 21, and the output of the front-end drive circuit 21 is then sampled by the sampling capacitor. The front-end drive circuit 21 is generally connected to a unit gain amplifier with an amplifier, and the output will have a gain error. For example, if the amplifier has a gain factor of 40dB, then the output will have a gain error of 1%, that is, if the input is 1V, the output is 0.99V, and if the gain factor is 80dB, there will be a gain error of 0.01%, that is, if the input is 1V, the output is 0.9999V. In any case, the output will have a gain error. Secondly, even if it is a rail-to-rail (i.e. full swing) amplifier, since the PMOS tube and NMOS tube in the buffer will consume a source-drain voltage Vds respectively, Vds is generally around 100mV to 200mV. For example, if the input is 0mV, the output will be around Vds; if the input is Vdd, the output will be around Vdd-Vds.

[0035] Therefore, this method of adding a front-end driver circuit will cause the error of the front-end driver circuit 21 to be sampled by the ADC, directly affecting the accuracy of the ADC. At the same time, the input buffer in the front-end driver circuit 21 will limit the input range of the ADC, because the output of the front-end driver circuit 21 cannot reach the actual input range of the input signal 0~Vdd.

[0036] To this end, an embodiment of the present invention provides a SAR ADC sampling circuit, which first uses a front-end driver module to buffer and amplify the input signal after the sampling period starts, samples the output amplified signal, and then samples the input signal. The front-end driver module improves the driving capability of the input signal and reduces the driving requirements of the ADC for the input signal, so that the ADC can adapt to a wider range of input signals. Moreover, since the front-end driver module only plays an auxiliary role and the sampling signal is ultimately driven by an external circuit, the error of the front-end driver module itself will not affect the accuracy of the sampling result.

[0037] like Figure 3 , which is a schematic diagram of the structure of a SAR ADC sampling circuit provided by an embodiment of the present invention.

[0038] The SAR ADC sampling circuit 300 includes: a front-end driving module 301, a sampling capacitor array 302, and a control module 303. Wherein: The front-end driving module 301 is used to buffer and amplify the input signal and output the amplified signal; The sampling capacitor array 302 is used for signal sampling and quantization conversion; The control module 303 is used to control the amplified signal output by the input driving module to pre-charge the sampling capacitor of the sampling capacitor array after the sampling period starts, and control the sampling capacitor array to sample the input signal after a delay of a set time.

[0039] The front-end driving module 301 may be implemented by using a unity gain amplifier.

[0040] The sampling capacitor array 302 may be a capacitor array with a pure capacitor structure (C-DAC) or a capacitor array with a segmented structure.

[0041] In a non-limiting embodiment, the control module 303 can implement the above functions through corresponding switches.

[0042] like Figure 4 FIG. 1 is a schematic diagram of the control principle of the control module on the sampling signal in an embodiment of the present invention.

[0043] In the SAR ADC sampling circuit provided in the embodiment of the present invention, sampling is divided into two stages: In the first stage, the first switch K1 is closed, and the input signal Vin passes through the front-end driving module 301 , and the signal with error (ie, the output signal of the front-end driving module 301 ) is quickly sampled onto the input capacitor.

[0044] In the second stage, the front-end driving module 301 is turned off, the second switch K2 is closed, and the accurate input signal Vin is directly sampled to the input capacitor through external driving. Then, the ADC is waited to enter the conversion stage.

[0045] It can be seen that in the solution of the present invention, the front-end driver module 301 only plays an auxiliary role, so that the voltage on the input capacitor is quickly increased to be close to the actual input signal Vin, and the final decision of the sampling voltage is the externally driven input signal Vin. Therefore, no matter how large the error of the front-end driver module 301 is, it will not affect the sampling signal of the ADC.

[0046] In some embodiments, Figure 3 The control module 303 in the embodiment may include: a control unit, a first switch, and a second switch. Figure 4 The first switch K1 is connected to the output end of the input driver module 301 and the input end of the sampling capacitor array 302 respectively; the second switch K2 is connected to the input end of the input driver module 301 and the input end of the sampling capacitor array 302 respectively.

[0047] The control unit is used to control the first switch K1 to close and the second switch K2 to open after the sampling period starts; after a certain delay, the first switch K1 is controlled to open and the second switch K2 is controlled to close. It should be noted that in order to further reduce power consumption, when the first switch K1 is opened, the front-end driver module 301 can also be turned off at the same time, or only the front-end driver module 301 can be turned off to stop output, which is not limited in this embodiment of the present invention.

[0048] The closing or opening of the first switch K1 and the second switch K2 can be controlled by the corresponding control unit ( Figure 4 (not shown) generates a first control signal to control the second control signal.

[0049] In one non-limiting embodiment, the control unit may include: A first control signal generating unit, used to generate a first control signal according to an external reset signal, so as to control the first switch to be closed after sampling starts and to be opened after a certain delay; an inverter, configured to invert the first control signal; The second control signal generating unit is used to generate a second control signal according to the sampling signal to control the second switch to be closed and open after the sampling period ends.

[0050] In a specific implementation, the first switch K1 and the second switch K2 can be implemented by any of the following devices: MOS tube, triode, etc.

[0051] Take NMOS tube as an example, Figure 5, which is a specific structural diagram of a SAR ADC sampling circuit and a control module provided in an embodiment of the present invention.

[0052] In this example, the control module 303 includes a first NMOS transistor N1 , a second NMOS transistor N2 , and a control unit composed of a first D flip-flop 331 , a second D flip-flop 332 , and an inverter 333 .

[0053] Figure 5 In the figure, CLK is the clock of ADC; SMP is the sampling signal, which is input to the reset terminal of the second D flip-flop, and the sampling time is Ts; RST is the reset signal of the first D flip-flop 331.

[0054] Figure 5 The timing relationship of each signal in Figure 6 shown.

[0055] Also refer to Figure 5 and Figure 6 , after power-on, RST and SMP are high level, entering the first sampling cycle. Since RST is high level, the first control signal S1 output from the Q end of the first D flip-flop 331 is pulled up to Vdd (Vdd is the working voltage of the D flip-flop) at the rising edge of the clock signal CLK, and the first control signal S1 controls the first NMOS tube N1 to turn on; while the first control signal S1 remains high level, the second control signal S2 output from the Q end of the second D flip-flop is low level, and the second control signal S2 controls the second NMOS tube N2 to turn off. The duration of the RST high level is T1, during which the amplified signal with error output by the front-end driver module 301 is used to quickly charge the sampling capacitor array 302, and the charging duration is T1.

[0056] Then, RST becomes a low level, and accordingly, the first control signal S1 is reset to 0. The falling edge of the first control signal S1 triggers the second control signal output by the second D flip-flop 332 to be connected to Vdd for a duration of T2. During this period, the first control signal S1 controls the first NMOS transistor N1 to be turned off, and the second control signal S2 controls the second NMOS transistor N2 to be turned on. The sampling capacitor array 302 is charged by the input signal Vin to achieve sampling of the input signal Vin. When the continuous charging duration reaches T2, the sampling ends, and the sampling signal SMP is set to 0, ending this round of sampling. The total sampling duration Ts=T1+T2.

[0057] It should be noted that, in a specific implementation, the conduction time of the switches P1 and P2 can be flexibly adjusted according to the bandwidth of the sampling buffer.

[0058] Above Figure 5In the illustrated embodiment, the first switch tube and the second switch tube are described by taking PMOS tube as an example. In specific implementation, other switch devices may also be used to implement the above functions. The principles are similar and will not be described in detail here.

[0059] By using the SAR ADC sampling circuit provided by the embodiment of the present invention, the driving requirements of the ADC for the input signal can be reduced, so that the ADC can adapt to a wider range of input signals. Moreover, since the front-end driving module only plays an auxiliary role and the sampling signal is ultimately driven by the external circuit, the error of the front-end driving module itself will not affect the accuracy of the sampling result.

[0060] In the SAR ADC sampling circuit provided by the embodiment of the present invention, Figure 3 The sampling capacitor array 302 in the embodiment can be a capacitor array of a pure capacitor structure or a segmented capacitor array; the sampling method can be upper plate sampling or lower plate sampling.

[0061] SAR ADC sampling can be divided into two schemes: upper plate sampling and lower plate sampling. Figure 7 As shown in the figure, (a) is the upper plate sampling, and (b) is the lower plate sampling.

[0062] For upper plate sampling, if the switch SW connected to the input signal source Vin is disconnected, the sampling capacitor C completes the sampling. The lower plate sampling structure consists of two switches SWb and SWt. When sampling is completed, the switch SWb is disconnected first, and then the switch SWt connected to the input signal source Vin is disconnected.

[0063] The following examples illustrate different structures and sampling methods of the sampling capacitor array in the SAR ADC sampling circuit provided in the embodiments of the present invention.

[0064] Example 1: Reference Figure 8 and Fig. 9 , Figure 8 1 is a schematic diagram of a structure in which a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention adopts a segmented structure and a lower plate sampling method. Fig. 9 yes Figure 8 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown.

[0065] In the figure, VCM is the input common mode voltage of SAR ADC, and Vrefp is the reference voltage of SAR ADC. During sampling, the upper plate switch is controlled by the sampling signal SMP, the upper plate of the high segment is connected to VCM, the lower plate is connected to the input signal Vin, and the lower plates of all capacitors in the low segment are grounded; after the sampling is completed, the upper plate switch of the high segment is disconnected and floated, the lower plate switch is also disconnected, and the lower plate of the capacitor in the low segment is still grounded. At this time, the input signal is sampled and stored in the sampling capacitor array. The total amount of stored charge Q can be calculated by the following formula: ; in, Indicates the total capacitance of the high-order segment.

[0066] Example 2: Reference Fig.10 and Fig.11 , Fig.10 1 is a schematic diagram of a structure in which a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention adopts a traditional non-segmented structure and a lower plate sampling method. Fig.11 yes Fig.10 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown.

[0067] In the figure, VCM is the input common mode voltage of the SAR ADC, and Vrefp is the reference voltage of the SAR ADC.

[0068] During sampling, the upper plate switch is turned on by the sampling signal SMP, the upper plates of each capacitor in the capacitor array are connected to VCM, and the lower plates are connected to the input signal Vin; after sampling, the upper plate switch is turned off, and the lower plate switch is also turned off. At this time, the input signal is stored in the capacitor array. The total amount of stored charge Q can be calculated by the following formula: ; in, Represents the total capacitance of the capacitor array.

[0069] Example 3: Reference Fig.12 and Fig.13 , Fig.12 1 is a schematic diagram of a structure in which a sampling capacitor array in a SAR ADC sampling circuit provided by an embodiment of the present invention adopts a non-segmented structure and an upper plate sampling method. Fig.13 yes Fig.12 The schematic diagram of the working state of the SAR ADC sampling circuit during sampling is shown.

[0070] In the figure, VCM is the input common mode voltage of SAR ADC, and Vrefp is the reference voltage of SAR ADC. During sampling, the first control signal S1 controls the upper plate of the capacitor in the capacitor array to be connected to the amplified signal of the input signal Vin, and then the second control signal S2 controls the upper plate to be connected to the input signal Vin, and the lower plate is connected to Vcm; after the sampling is completed, the upper plate switch is disconnected, and the lower plate switch is also disconnected. At this time, the input signal is stored in the capacitor array. The total amount of stored charge Q can be calculated by the following formula: ; in, Represents the total capacitance of the capacitor array.

[0071] Correspondingly, an embodiment of the present invention further provides an ADC circuit, which includes the above-mentioned SAR ADC sampling circuit.

[0072] Accordingly, an embodiment of the present invention further provides an ADC device, which includes a multiplexer and the above-mentioned ADC circuit. The multiplexer is connected to a plurality of external inputs and is used to select one of the external inputs as an input signal of the ADC circuit; The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

[0073] The ADC device provided in the embodiment of the present invention can adapt to input signals of various ranges. In some applications where ADC conversion of signals of various ranges is required, the ADC chip area can be greatly saved, and the integrated and miniaturized design of the product can be better utilized.

[0074] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0075] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A SAR ADC sampling circuit, characterized in that: The circuit comprises: The front-end driving module is used to buffer and amplify the input signal and output the amplified signal; Sampling capacitor array, used for signal sampling and quantization conversion; The control module is used to control the amplified signal output by the input driving module to pre-charge the sampling capacitor of the sampling capacitor array after the sampling period starts, and control the sampling capacitor array to sample the input signal after a delay setting time.

2. The SAR ADC sampling circuit according to claim 1, characterized in that: The control module includes: a control unit, a first switch, and a second switch; the first switch is respectively connected to the output end of the input driver module and the input end of the sampling capacitor array; the second switch is respectively connected to the input end of the input driver module and the input end of the sampling capacitor array; The control unit is used to control the first switch to be closed and the second switch to be opened after the sampling period starts; and to control the first switch to be opened and the second switch to be closed after a certain delay.

3. The SAR ADC sampling circuit according to claim 2, characterized in that: The first switch and the second switch are any one of the following: a MOS tube and a triode.

4. The SAR ADC sampling circuit according to claim 2, characterized in that: The control unit comprises: A first control signal generating unit, used to generate a first control signal according to an external reset signal, so as to control the first switch to be closed after sampling starts and to be opened after a certain delay; an inverter, configured to invert the first control signal; The second control signal generating unit is used to generate a second control signal according to the sampling signal to control the second switch to be closed and open after the sampling period ends.

5. The SAR ADC sampling circuit according to claim 4, characterized in that: The first control signal generating unit comprises a first D flip-flop, the clock signal of the first D flip-flop is the ADC clock signal, and the control signal of the first D flip-flop is the external reset signal; The second control signal generating unit includes a second D flip-flop, a clock signal of the second D flip-flop is the output signal of the inverter, and a control signal of the second D flip-flop is the sampling signal.

6. The SAR ADC sampling circuit according to claim 1, characterized in that: The front-end driving module includes: a unity gain amplifier.

7. The SAR ADC sampling circuit according to any one of claims 1 to 6, characterized in that: The sampling capacitor array includes any one of the following: a capacitor array with a pure capacitor structure, and a capacitor structure array with a segmented structure.

8. The SAR ADC sampling circuit according to any one of claims 1 to 6, characterized in that: The sampling mode of the sampling capacitor array includes any one of the following: upper plate sampling and lower plate sampling.

9. An ADC circuit, characterized in that: The ADC circuit comprises the SARADC sampling circuit according to any one of claims 1 to 8.

10. An ADC device, characterized in that: The device comprises: a multiplexer, and the ADC circuit as claimed in claim 9; The multiplexer is connected to a plurality of external inputs and is used to select one of the external inputs as an input signal of the ADC circuit; The ADC circuit is used to sample and convert the input signal and output the converted digital signal.

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