Circuit board and manufacturing method thereof

Abstract

The circuit board comprises a circuit structure and a capacitor element. The circuit structure includes a plurality of circuit layers and a plurality of insulating layers. The circuit layers and the insulating layers are stacked in a staggered manner along a first direction. The capacitor element is disposed in the circuit structure and passes through the circuit layer and the insulating layer. The capacitor element includes a first electrode, a second electrode and a dielectric material. The first electrode extends along a first direction and passes through the circuit layers and the insulating layer. The first electrode is connected with at least one circuit layer. The second electrodes are arranged along the first direction and are separated from each other, where each second electrode is separated from the first electrode. Each second electrode overlaps the first electrode along a second direction, wherein the second direction is perpendicular to the first direction. Each of the second electrodes is connected with at least one of the circuit layers. The dielectric material is disposed between the first electrode and the second electrode. The capacitor element does not occupy too much size or area of a circuit board so as to meet the miniaturization development trend of the existing electronic device.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board including a capacitor element and a manufacturing method thereof. Background Art

[0002] At present, the embedded capacitor element in the circuit board is usually composed of two metal layers and a dielectric layer sandwiched between the two metal layers, wherein the two metal layers are electrodes and are arranged in parallel with the circuit layer of the circuit board, and the distance between the two metal layers is equal to the distance between two adjacent circuit layers. Therefore, the distance between the two metal layers is difficult to change. The capacitance value of the embedded capacitor element is proportional to the overlapping area between the two metal layers (i.e., electrodes), and the parallel arrangement of the metal layer and the circuit layer requires the circuit board to have sufficient size, i.e., a certain length and width, to accommodate the embedded capacitor element. Summary of the invention

[0003] At least one embodiment of the present invention provides a circuit board including a capacitor element and a plurality of circuit layers, wherein electrodes of the capacitor element extend along a stacking direction of the circuit layers.

[0004] Another embodiment of the present invention provides a method for manufacturing the above-mentioned circuit board.

[0005] The circuit board provided by at least one embodiment of the present invention includes a circuit structure and a capacitor element. The circuit structure includes a plurality of circuit layers and a plurality of insulating layers, wherein the circuit layers and the insulating layers are stacked along a first direction. The capacitor element is arranged in the circuit structure and passes through the circuit layers and the insulating layers. The capacitor element includes a first electrode, a second electrode and a dielectric material. The first electrode extends along a first direction and passes through the circuit layers and the insulating layers, wherein the first electrode connects at least one of the circuit layers. The second electrodes are arranged along a first direction and separated from each other, wherein each of the second electrodes is separated from the first electrode. Each of the second electrodes overlaps with the first electrode along a second direction, wherein the second direction is perpendicular to the first direction. Each of the second electrodes connects at least one of the circuit layers. The dielectric material is arranged between the first electrode and the second electrode.

[0006] In at least one embodiment of the present invention, the dielectric material includes a plurality of filling materials. The filling materials are arranged along a first direction, wherein each of the filling materials is sandwiched between the first electrode and one of the second electrodes. The filling materials overlap the second electrodes respectively in a second direction, wherein at least two of the filling materials have different dielectric constants.

[0007] In at least one embodiment of the present invention, the distances between the second electrodes and the first electrodes in the second direction are equal to each other.

[0008] In at least one embodiment of the present invention, the dielectric material has at least one through hole, and the through hole extends along the first direction.

[0009] In at least one embodiment of the present invention, the dielectric material has at least one blind hole, and the blind hole extends along the first direction, wherein the depth of the blind hole is less than the thickness of the circuit structure.

[0010] At least one embodiment of the present invention also provides a method for manufacturing a circuit board, which includes the following steps. A circuit substrate is provided, which includes two core circuit layers and a core insulating layer arranged between the two core circuit layers. Afterwards, two initial grooves parallel to each other are formed on the core insulating layer, wherein the two initial grooves are respectively adjacent to the sides of the core circuit layer. Afterwards, a first initial electrode and a second initial electrode are respectively formed in the two initial grooves. Afterwards, a plurality of build-up circuit layers and a plurality of build-up insulating layers are formed on opposite sides of the core insulating layer, wherein the build-up insulating layers cover the first initial electrode and the second initial electrode. Afterwards, a portion of the build-up insulating layers is removed to form two first grooves and two second grooves on these build-up insulating layers, wherein the two first grooves are respectively located on opposite sides of the first initial electrode and expose the first initial electrode, and the two second grooves are respectively located on opposite sides of the second initial electrode. The depth of the second groove is less than the depth of the first groove. Then, a metal material is deposited in the first trench and the second trench to form a first electrode in the first trench and a plurality of second electrodes in the plurality of second trenches, wherein each of the second electrodes is connected to at least one of the build-up circuit layers.

[0011] In at least one embodiment of the present invention, the method further includes forming at least one through hole on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the through hole extends between the build-up insulating layer and the initial insulating layer.

[0012] In at least one embodiment of the present invention, the method further includes forming at least one blind hole on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the blind hole at least extends to the build-up insulating layer.

[0013] In at least one embodiment of the present invention, the method further includes removing a portion of the build-up insulating layer and a portion of the core insulating layer between the first electrode and the second electrode to form a groove, wherein the groove exposes the first electrode, the second electrode and the second initial electrode, and then filling the groove with a dielectric material.

[0014] In at least one embodiment of the present invention, the step of filling the dielectric material in the trench includes sequentially filling a plurality of filling materials in the trench, wherein one of the filling materials is sandwiched between the first electrode and the second initial electrode, and each of the other filling materials is sandwiched between the first electrode and one of the second electrodes.

[0015] In at least one embodiment of the present invention, a sidewall of each of the initial trenches is flush with a side edge of at least one of the core circuit layers.

[0016] Based on the above, the electrodes (i.e., the first and second electrodes) of the above capacitor elements extend along the stacking direction of the circuit layer (i.e., the first direction). Therefore, compared with the existing embedded capacitor elements, the capacitor element of the present invention will not occupy too much size or area of ​​the circuit board to meet the development trend of current electronic devices (such as mobile devices) towards miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a schematic top view of a circuit board according to at least one embodiment of the present invention.

[0018] Figure 1B yes Figure 1A Schematic diagram of the cross section along line 1B-1B.

[0019] Figures 2A to 2G Is manufacturing Figure 1A Schematic diagram of the process cross section of the circuit board in.

[0020] Figure 3A FIG. 4 is a schematic top view of a circuit board according to another embodiment of the present invention.

[0021] Figure 3B yes Figure 3A A schematic cross-sectional view taken along line 3B-3B. DETAILED DESCRIPTION

[0022] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations thereof caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, while the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0023] Secondly, the words "about", "approximately" or "substantially" that appear in the content of this case not only cover the numerical values ​​and numerical ranges that are clearly recorded, but also cover the allowable deviation range that can be understood by those skilled in the art of the invention, wherein this deviation range can be determined by the error generated during measurement, and this error is caused by, for example, the limitations of the measurement system or process conditions. In addition, "about" can mean within one or more standard deviations of the above numerical values, such as ±30%, ±20%, ±10% or ±5%. The words "about", "approximately" or "substantially" that appear in this text can select an acceptable deviation range or standard deviation based on the optical properties, etching properties, mechanical properties or other properties, and not just one standard deviation can be applied to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0024] Figure 1A is a schematic top view of a circuit board according to at least one embodiment of the present invention, and Figure 1B yes Figure 1A Schematic diagram of the cross section along line 1B-1B. Figure 1A and Figure 1B The circuit board 100 includes a circuit structure 110, wherein the circuit structure 110 includes a plurality of circuit layers 111a and 111b and a plurality of insulating layers 112a and 112b. The circuit layers 111a and 111b and the insulating layers 112a and 112b are stacked along a first direction D1, that is, the first direction D1 is the stacking direction of the circuit layers 111a, 111b and the insulating layers 112a, 112b. Figure 1B In the embodiment, the first direction D1 is a vertical direction.

[0025] The circuit layers 111a and 111b and the insulating layers 112a and 112b may be stacked alternately so that each of the insulating layers 112a and 112b is located between two adjacent circuit layers 111a and 111b. The circuit structure 110 may be formed by building up the opposite sides of a core substrate, wherein the core circuit layer and the core insulating layer of the core substrate are the circuit layer 111a and the insulating layer 112a, respectively.

[0026] In addition, the circuit structure 110 may further include at least one conductive connection portion 113, wherein the conductive connection portion 113 connects at least two of the circuit layers 111a and 111b. Figure 1B For example, the circuit board 100 includes two conductive connecting portions 113, and each conductive connecting portion 113 connects the adjacent circuit layers 111a and 111b, so that the circuit layers 111a and 111b can be electrically connected to each other. In addition, the conductive connecting portion 113 can be a conductive blind hole, a conductive through hole or a conductive buried hole, wherein Figure 1BThe conductive blind via is used as an example for illustration, and the conductive connecting portion 113 is not limited to be a conductive blind via.

[0027] The circuit board 100 further includes at least one capacitor element 120, wherein the capacitor element 120 is disposed in the circuit structure 110 and passes through the circuit layers 111a and 111b and the insulating layers 112a and 112b. The capacitor element 120 includes a first electrode 121 and at least two second electrodes 122, wherein the first electrode 121 extends along a first direction D1 and passes through the circuit layers 111a and 111b and the insulating layers 112a and 112b, and the second electrodes 122 are separated from each other and arranged along the first direction D1.

[0028] In addition, from Figure 1B Therefore, the first electrode 121 and the second electrode 122 of the capacitor element 120 extend along the stacking direction of the circuit layers 111a and 111b, and the first electrode 121 and the second electrodes 122 are not arranged parallel to the circuit layers 111a and 111b.

[0029] The first electrode 121 is connected to at least one of the wiring layers 111a and 111b, and each of the second electrodes 122 is connected to at least one of the wiring layers 111a and 111b. Figure 1B For example, the capacitor element 120 includes a first electrode 121 and three second electrodes 122 , wherein the first electrode 121 passes through the wiring layers 111a and 111b and connects all the wiring layers 111a and 111b , and each of the second electrodes 122 connects two of the wiring layers 111a and 111b .

[0030] It should be noted that in other embodiments, the capacitor element 120 may include two or more than three second electrodes 122, wherein the first electrode 121 may be connected to one, two or more than three of the wiring layers 111a and 111b, and each second electrode 122 may be connected to one or more than three of the wiring layers 111a and 111b. Figure 1B The capacitor element 120 shown is only for illustration, and the number of the second electrodes 122 included in the capacitor element 120 and the number of the first electrodes 121 and the second electrodes 122 connected to the wiring layers 111 a and 111 b are not limited.

[0031] Each second electrode 122 is separated from the first electrode 121, and each second electrode 122 overlaps with the first electrode 121 along a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1. Figure 1B For example, the second direction D2 is a horizontal direction. Figure 1BFrom the perspective of FIG. 1 , the first electrode 121 and the second electrode 122 do not overlap or stack in the first direction D1. The first electrode 121 and the second electrode 122 do not overlap with any circuit layers 111a and 111b in the first direction D1. Figure 1B shown.

[0032] The distances W12 between the second electrodes 122 and the first electrodes 121 in the second direction D2 are equal to each other. In other words, the second electrodes 122 are coplanar with each other, that is, the side surfaces of the second electrodes 122 are aligned with each other and are located in the same plane, and each second electrode 122 is parallel to the first electrode 121. It should be noted that the second electrodes 122 are substantially coplanar with each other, and each second electrode 122 is substantially parallel to the first electrode 121. In detail, within the allowable error range, the second electrodes 122 may not be coplanar, and each second electrode 122 may not be parallel to the first electrode 121.

[0033] The capacitor element 120 further includes a dielectric material 123, wherein the dielectric material 123 is disposed between the first electrode 121 and the second electrode 122. The dielectric material 123 may include a plurality of filling materials F1, F2, and F3. The filling materials F1, F2, and F3 are arranged along a first direction D1, and each of the filling materials F1, F2, and F3 is sandwiched between the first electrode 121 and one of the second electrodes 122, wherein the filling materials F1, F2, and F3 overlap with the second electrodes 122 in a second direction D2, such as Figure 1B shown.

[0034] In the present embodiment, at least two of the filling materials F1, F2 and F3 may be different from each other, so that the dielectric constants of at least two of the filling materials F1, F2 and F3 are different from each other. For example, the filling material F1 may be polyimide (PI), the filling material F2 may be epoxy, such as FR4 or barium titanate filled epoxy, and the filling material F3 may be ceramic, so that the dielectric material 123 may have a plurality of different dielectric constants, so that the capacitor element 120 has a plurality of capacitance values.

[0035] It can be seen from this that the capacitor element 120 is more flexible in circuit design, so that the capacitor element 120 can be applied to more types of circuits. Figure 1BFor example, when the dielectric constants of the filling materials F1, F2 and F3 are different from each other, the three second electrodes 122 can be electrically connected to three switch elements (not shown). By turning on and off the three switch elements, the capacitor element 120 can provide eight capacitance values ​​(including zero). In this way, the capacitor element 120 can be widely used in a variety of circuits and electronic components. For example, the capacitor element 120 that can provide a variety of capacitance values ​​(e.g., eight) is suitable for use in an oscillation frequency modulation circuit, thereby facilitating the matching of the antenna.

[0036] In addition to the filling materials F1, F2, and F3, the sizes (e.g., areas) of the first electrode 121 and each of the second electrodes 122 and the distance W12 between the second electrode 122 and the first electrode 121 in the second direction D2 can determine the capacitance of the capacitor 120. Compared to the conventional embedded capacitor, the distance W12 between the second electrode 122 and the first electrode 121 is easier to change, so that the capacitor 120 can generate a predetermined capacitance value through the distance W12 and the sizes of the first electrode 121 and the second electrode 122.

[0037] It is worth mentioning that, in other embodiments, the dielectric material 123 may include only a single filling material. Figure 1B Two of the filling materials F1, F2 and F3 in the embodiment may be omitted, and the remaining one completely fills the space between the first electrode 121 and the second electrodes 122. Therefore, the dielectric material 123 may have only one dielectric constant. In addition, the dielectric material 123 in the present embodiment may be solid, but in other embodiments, the dielectric material 123 may also be a gas, such as air. Alternatively, at least one of the filling materials F1, F2 and F3 may be a gas (such as air).

[0038] Figures 2A to 2G Is manufacturing Figure 1A It should be noted that the circuit structure 110 other than the capacitor element 120 can be manufactured using the current circuit board process. Figures 2A to 2G The manufacturing process of the capacitor element 120 is mainly described, and part of the circuit structure 110 other than the capacitor element 120 is omitted. Figure 2A First, a circuit substrate 10 is provided, which includes a core circuit layer and a core insulating layer, wherein the core insulating layer is arranged between the two core circuit layers.

[0039] The circuit substrate 10 is a core substrate, wherein each core circuit layer is a circuit layer 111a, and the core insulating layer is an insulating layer 112a, so the components included in the circuit substrate 10 are the same as some components of the circuit board 100. In addition, the constituent material of the circuit layer 111a can be metal, such as copper, and the constituent material of the insulating layer 112a can be a polymer material, such as epoxy resin.

[0040] See also Figure 2B After that, two initial trenches R20 are formed in parallel on the insulating layer 112a (i.e., the core insulating layer), wherein the initial trenches R20 can be formed by routing, milling, or laser ablation. These initial trenches R20 are adjacent to the side edges of the circuit layer 111a, respectively, wherein each sidewall S12 of the initial trench R20 can be aligned with the side edge S11 of at least one layer of the circuit layer 111a. Figure 2B For example, the sidewall S12 of each initial trench R20 may be flush with the side edge S11 of the two wiring layers 111 a.

[0041] See also Figure 2C After the initial grooves R20 are formed, a first initial electrode 121i and a second initial electrode 122i are formed in the two initial grooves R20, respectively. The first initial electrode 121i and the second initial electrode 122i can be formed by electroless plating and electrolytic plating. Before the electroless plating and electrolytic plating, two mask layers 29 can be respectively covered on opposite sides of the insulating layer 112a, wherein the mask layer 29 can be a photoresist layer after development, such as a dry film, and the mask layer 29 does not cover any initial grooves R20 to expose the initial grooves R20. In this way, these mask layers 29 can limit the first initial electrode 121i and the second initial electrode 122i to be formed only in the initial grooves R20.

[0042] In this embodiment, the first initial electrode 121i and the second initial electrode 122i may be connected to the circuit layer 111a, so that the first initial electrode 121i and the second initial electrode 122i can be electrically connected to the circuit layer 111a. However, in other embodiments, at least one of the first initial electrode 121i and the second initial electrode 122i may be separated from any layer of the circuit layer 111a. For example, at least one of the first initial electrode 121i and the second initial electrode 122i is not connected to any circuit layer 111a. Therefore, the first initial electrode 121i and the second initial electrode 122i are not limited to being connected to the circuit layer 111a.

[0043] See also Figure 2D, then, a plurality of build-up wiring layers and a plurality of build-up insulation layers are formed on opposite sides of the insulation layer 112a, wherein the build-up wiring layer is the wiring layer 111b, and the build-up insulation layer is the insulation layer 112b. These build-up wiring layers (i.e., the wiring layer 111b) and these build-up insulation layers (i.e., the insulation layer 112b) can be formed by a build-up method, and the insulation layer 112b will cover the first initial electrode 121i and the second initial electrode 122i, such as Figure 2D shown.

[0044] See also Figure 2D and Figure 2E After that, a portion of the insulating layer 112b is removed to form two first trenches R21 and two second trenches R22 on the insulating layer 112b, wherein the two first trenches R21 are respectively located at two opposite sides of the first initial electrode 121i and expose the first initial electrode 121i. The two second trenches R22 are respectively located at two opposite sides of the second initial electrode 122i. Figure 2E From the perspective of FIG. 1 , the depth of the second trenches R22 is less than that of the first trenches R21 , and thus the second trenches R22 do not expose the second initial electrodes 122 i. In addition, the formation method of the first trenches R21 and the second trenches R22 may be the same as the formation method of the initial trenches R20 .

[0045] See also Figure 2E and Figure 2F After that, metal material is deposited in the first trench R21 and the second trench R22 to form a first electrode 121 in the first trench R21 and a plurality of second electrodes 122 in the second trenches R22. The method of depositing the metal material may include electroless plating and electrolytic plating. Before performing electroless plating and electrolytic plating, two mask layers may be used, such as Figure 2C The mask layers 29 shown cover the outermost insulating layer 112b and expose the first trenches R21 and the second trenches R22. Thus, the mask layers can limit the first electrode 121 and the second electrode 122 to be formed only in the first trench R21 and the second trench R22.

[0046] Since the first trenches R21 expose the first initial electrodes 121i, the first electrode 121 includes the first initial electrodes 121i. The second trenches R22 do not expose the second initial electrodes 122i, so that the second initial electrodes 122i are covered by the insulating layers 112a and 112b. Therefore, the second electrodes 122 are separated from the second initial electrodes 122i.

[0047] It is worth mentioning that the second initial electrode 122i is one of the second electrodes 122. Figure 1B and Figure 2F In the figure, the second electrode 122 located in the middle is Figure 2E The second initial electrode 122i in Figure 2F In the following drawings and descriptions, the second initial electrodes 122i will be changed to second electrodes 122. In addition, except for the middle second electrode 122 (ie, the original second initial electrode 122i), each second electrode 122 is connected to at least one circuit layer 111b. Figure 2F For example, each second electrode 122 is connected to two of the circuit layers 111 b.

[0048] See also Figure 2F and Figure 2G , then, remove the portion of the insulating layer 112a and 112b between the first electrode 121 and the second electrode 122 (including the original second initial electrode 122i) to form a groove (not shown), wherein the groove exposes the first electrode 121 and all the second electrodes 122. Then, fill the groove with a dielectric material 123, wherein the dielectric material 123 can directly contact the first electrode 121 and all the second electrodes 122. At this point, the circuit board 100 is basically manufactured.

[0049] The dielectric material 123 may include filling materials F1, F2 and F3, and the step of filling the dielectric material 123 in the trench may include sequentially filling the filling materials F1, F2 and F3 in the trench, wherein the filling materials F1, F2 and F3 are respectively sandwiched between the first electrode 121 and the second electrodes 122. Figure 2G For example, the filling material F2 is sandwiched between the first electrode 121 and the middle second electrode 122 (i.e., the second initial electrode 122i), and the other filling materials F1 and F3 are each sandwiched between the first electrode 121 and one of the second electrodes 122. For example, the filling material F1 is sandwiched between the first electrode 121 and the lower second electrode 122, and the filling material F2 is sandwiched between the first electrode 121 and the upper second electrode 122.

[0050] See also Figure 2F In particular, in other embodiments, the portions of the insulating layers 112a and 112b between the first electrode 121 and the second electrodes 122 may not be removed, so that the portions of the insulating layers 112a and 112b sandwiched between the first electrode 121 and all the second electrodes 122 are used as dielectric materials, thereby forming a capacitor element including the portions of the insulating layers 112a and 112b, such as Figure 2F Therefore, the portions of the insulating layers 112a and 112b can be used as dielectric materials of the capacitor element, which are not limited to include the filling materials F1, F2 and F3.

[0051] Figure 3A is a schematic top view of a circuit board according to another embodiment of the present invention, and Figure 3B yes Figure 3A Schematic diagram of the cross section along line 3B-3B. Figure 3A and Figure 3B The circuit board 300 of this embodiment is similar to the circuit board 100 of the aforementioned embodiment. For example, the circuit board 300 includes a capacitor element 330, a plurality of circuit layers 111a, 111b, and a plurality of insulating layers 112a, 112b, wherein the capacitor element 330 includes a first electrode 121 and a plurality of second electrodes 122. The following mainly describes the differences between the circuit boards 300 and 100, and the common features of the two are basically not repeated.

[0052] The capacitor element 330 is different from the capacitor element 120, wherein the dielectric material 323 included in the capacitor element 330 is different from the aforementioned dielectric material 123. Specifically, the dielectric material 323 has at least one through hole T3 and at least one blind hole V3, wherein the through hole T3 and the blind hole V3 can be formed after the first electrode 121 and the second electrodes 122 are formed (please refer to Figure 2F In addition, in the present embodiment, the dielectric material 323 may have a plurality of through holes T3 and a plurality of blind holes V3, but the present invention does not limit the number of through holes T3 and blind holes V3 of the dielectric material 323, wherein the dielectric material 323 may also have only one of the through holes T3 and the blind holes V3.

[0053] That is, after the first electrode 121 and the second electrodes 122 are formed, at least one through hole T3 and at least one blind hole V3 may be formed on a portion of the insulating layer 112b between the first electrode 121 and the second electrodes 122, wherein the through hole T3 extends along the first direction D1 in the insulating layers 112a and 112b, and the blind hole V3 extends along the first direction D1 at least in the insulating layer 112b. Figure 3B For example, the blind hole V3 extends to the insulating layer 112a and some insulating layers 112b. Figure 3B From the above, it can be seen that the depth of the blind hole V3 is obviously smaller than the thickness of the circuit structure (not shown) of the capacitor element 330 and also smaller than the depth of the through hole T3.

[0054] In addition, the capacitor element 330 may further include a plurality of filling materials 321 and 322, wherein the filling materials 321 and 322 are respectively filled in the through hole T3 and the blind hole V3, and the filling materials 321 and 322 may be the same as the filling materials F1, F2 and F3 in the aforementioned embodiment (please refer to Figure 1B ). For example, the filling materials 321 and 322 may be the same as the filling materials F1 and F2, respectively. In addition, at least one of the filling materials 321 and 322 may be a gas, such as air.

[0055] In summary, in the circuit board disclosed in at least one embodiment of the present invention, the electrodes of the capacitor element (i.e., the first and second electrodes) extend along the stacking direction of the circuit layer (i.e., the first direction). Therefore, compared with the existing embedded capacitor element, the electrodes of the capacitor element in at least one embodiment of the present invention will not be arranged in parallel with the circuit layer, that is, the capacitor element will not occupy too much size or area of ​​the circuit board, so that the circuit board of at least one embodiment of the present invention can meet the development trend of current electronic devices (such as mobile devices) towards miniaturization.

[0056] Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person skilled in the art in the art to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0057]

Explanation of symbols

[0058] 10: Circuit board

[0059] 29: Mask layer

[0060] 100, 300: Circuit board

[0061] 110: Line structure

[0062] 111a, 111b: Circuit layer

[0063] 112a, 112b: Insulation layer

[0064] 113: Conductive connection part

[0065] 120, 330: Capacitor elements

[0066] 121: First electrode

[0067] 121i: First initial electrode

[0068] 122: Second electrode

[0069] 122i: Second initial electrode

[0070] 123, 323: Dielectric materials

[0071] 321, 322, F1, F2, F3: Filling material

[0072] D1: First direction

[0073] D2: Second direction

[0074] R20: Initial groove

[0075] R21: First groove

[0076] R22: Second groove

[0077] S11: Side

[0078] S12: Sidewall

[0079] T3: Through hole

[0080] V3: Blind Via

[0081] W12: Distance.

Claims

1. A circuit board, characterized in that: include: A circuit structure, comprising a plurality of circuit layers and a plurality of insulating layers, wherein the circuit layers and the insulating layers are alternately stacked along a first direction; A capacitor element is disposed in the circuit structure and passes through the plurality of circuit layers and the plurality of insulating layers, wherein the capacitor element comprises: A first electrode extending along the first direction and passing through the plurality of circuit layers and the plurality of insulating layers, wherein the first electrode is connected to at least one of the circuit layers; a plurality of second electrodes arranged along the first direction and separated from each other, wherein each of the second electrodes is separated from the first electrode and each of the second electrodes overlaps with the first electrode along a second direction, wherein the second direction is perpendicular to the first direction, and each of the second electrodes is connected to at least one of the circuit layers; and The dielectric material is disposed between the first electrode and the second electrode.

2. The circuit board according to claim 1, characterized in that: The dielectric material comprises: A plurality of filling materials are arranged along the first direction, wherein each of the filling materials is sandwiched between the first electrode and one of the second electrodes, and the plurality of filling materials overlap with the plurality of second electrodes respectively in the second direction, wherein at least two of the filling materials have different dielectric constants from each other.

3. The circuit board according to claim 1, characterized in that: The plurality of second electrodes are equidistant from the first electrode in the second direction.

4. The circuit board according to claim 1, characterized in that: The dielectric material has at least one through hole, and the through hole extends along the first direction.

5. The circuit board according to claim 1, characterized in that: The dielectric material has at least one blind hole, and the blind hole extends along the first direction, wherein a depth of the blind hole is less than a thickness of the circuit structure.

6. A method for manufacturing a circuit board, characterized in that: include: Providing a circuit substrate, which includes two core circuit layers and a core insulation layer arranged between the two core circuit layers; Forming two initial grooves parallel to each other on the core insulating layer, wherein the two initial grooves are respectively adjacent to the side edges of the core wiring layer; forming a first initial electrode and a second initial electrode in the two initial grooves respectively; forming a plurality of build-up circuit layers and a plurality of build-up insulation layers on opposite sides of the core insulation layer, wherein the build-up insulation layers cover the first initial electrode and the second initial electrode; removing a portion of the build-up insulating layer to form two first trenches and two second trenches on the plurality of build-up insulating layers, wherein the two first trenches are respectively located at two opposite sides of the first initial electrode and expose the first initial electrode, and the two second trenches are respectively located at two opposite sides of the second initial electrode, wherein the depth of the second trenches is less than the depth of the first trenches; as well as A metal material is deposited in the first trench and the second trench to form a first electrode in the first trench, and a plurality of second electrodes are formed in the plurality of second trenches, wherein each of the second electrodes is connected to at least one of the build-up circuit layers.

7. The method for manufacturing a circuit board according to claim 6, characterized in that: Also includes: At least one through hole is formed on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the through hole extends between the build-up insulating layer and the initial insulating layer.

8. The method for manufacturing a circuit board according to claim 6, characterized in that: Also includes: At least one blind hole is formed on a portion of the build-up insulating layer between the first electrode and the second electrode, wherein the blind hole at least extends to the build-up insulating layer.

9. The method for manufacturing a circuit board according to claim 6, characterized in that: Also includes: removing a portion of the build-up insulating layer and a portion of the core insulating layer between the first electrode and the second electrode to form a groove, wherein the groove exposes the first electrode, the second electrode, and the second initial electrode; as well as Filling the trench with dielectric material.

10. The method for manufacturing a circuit board according to claim 9, characterized in that: The step of filling the dielectric material in the groove comprises: A plurality of filling materials are sequentially filled into the grooves, wherein one of the filling materials is sandwiched between the first electrode and the second initial electrode, and each of the other filling materials is sandwiched between the first electrode and one of the second electrodes.

11. The method for manufacturing a circuit board according to claim 6, characterized in that: The sidewall of each of the initial grooves is flush with the side edge of at least one of the core circuit layers.

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