Semiconductor device and electronic system including the same

Abstract

A semiconductor device includes: a circuit region including a peripheral circuit on a substrate; and a cell region adjacent to the circuit region. The cell region includes a cell array region and a connection region. The cell region further includes: a gate stack including interlayer insulating layers and gate electrodes alternately stacked on the substrate; a channel in the cell array region, the channel extending through the gate stack; a main support in the connection region, the main support extending through the gate stack; and a contact electrode in the connection region, the contact electrode being connected to the gate electrode through the gate stack. The main support includes: a first portion extending in a first direction; and a second portion extending from the first portion in a second direction crossing the first direction. At least a portion of the contact electrode is surrounded by the first portion and the second portion of the main support.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0079751 filed on June 21, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background Art

[0004] Semiconductor is a material belonging to the middle area between conductor and insulator, and refers to a material that conducts electricity under predetermined conditions. Various semiconductor devices can be manufactured by using such semiconductor materials, and for example, memory devices and the like can be manufactured. Memory devices can be classified into volatile memory devices and non-volatile memory devices. In the case of non-volatile memory devices, the content is not deleted even if the power is cut off, and can be used in various electronic devices such as mobile phones, digital cameras, and PCs.

[0005] According to the recent trend of increasing storage capacity, it is expected to improve the integration of non-volatile memory devices. The integration of memory devices arranged two-dimensionally on a plane may be limited. Therefore, vertical non-volatile memory devices arranged three-dimensionally have been proposed. Summary of the invention

[0006] Example embodiments attempt to provide a semiconductor device capable of improving reliability and productivity and an electronic system including the semiconductor device.

[0007] An example embodiment of the present disclosure provides a semiconductor device, comprising: a circuit region, configured to include a peripheral circuit structure on a substrate; and a cell region, adjacent to the circuit region and configured to include a cell array region and a connection region, wherein the cell region includes: a gate stack structure, configured to include an interlayer insulating layer and a gate electrode alternately stacked on a substrate; a channel structure, in the cell array region, configured to extend through the gate stack structure; a main support structure, in the connection region, configured to extend through the gate stack structure; and a contact electrode, in the connection region, connected to the gate electrode through the gate stack structure, and the main support structure includes: a first portion, configured to extend along a first direction; and a second portion, configured to extend from the first portion in a second direction intersecting the first direction, wherein at least a portion of the contact electrode is surrounded by the first portion and the second portion of the main support structure.

[0008] An example embodiment of the present disclosure provides a semiconductor device, including: a circuit region, configured to include a peripheral circuit structure on a substrate; and a cell region, adjacent to the circuit region and configured to include a cell array region and a connection region, and the cell region may include: a gate stack structure, configured to include a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure, in the cell array region, and configured to extend through the gate stack structure; a support structure, in the connection region to extend through the gate stack structure; and a contact electrode, in the connection region, the contact electrode is connected to the gate electrode through the gate stack structure, wherein each of the gate electrodes may include a pad electrode in the connection region, the contact electrode may be electrically connected to the pad electrode of one of the gate electrodes and insulated from the remaining gate electrodes, an insulating pattern is provided between the contact electrode and the remaining gate electrodes, and the contact electrode may be at least partially surrounded by the support structure in a plan view, and may include: a first contact portion, surrounded by the gate stack structure in a cross-sectional view and connected to the peripheral circuit structure; and a second contact portion, on the first contact portion and on the gate stack structure, and connected to the upper surface of the pad electrode.

[0009] An example embodiment of the present disclosure provides an electronic system, including: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, the semiconductor device may include: a circuit region configured to include a peripheral circuit structure on the substrate; and a cell region adjacent to the circuit region and configured to include a cell array region and a connection region, the cell region may include: a gate stack structure configured to include a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure in the cell array region and configured to extend through the gate stack structure; a support structure in the connection region and configured to extend through the gate stack structure ; and a contact electrode, which is connected to the gate electrode through the gate stack structure in the connection region, wherein each of the gate electrodes may include a pad electrode in the connection region configured to be connected to the contact electrode, the contact electrode may be electrically connected to the pad electrode of one of the gate electrodes and insulated from the remaining gate electrodes, an insulating pattern is arranged between the contact electrode and the remaining gate electrodes, and the contact electrode may be at least partially surrounded by the support structure in a plan view, and may include: a first contact portion, which is surrounded by the gate stack structure in a cross-sectional view and is connected to the peripheral circuit structure; and a second contact portion, which is on the first contact portion and on the gate stack structure and is connected to the upper surface of the pad electrode.

[0010] According to example embodiments, in an etching process step for forming a plurality of contact electrodes, since etching is performed in the same etching environment (eg, type or thickness of layers in regions where contact electrodes are formed), reliability and productivity of semiconductor devices may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A partial top plan view illustrating a semiconductor device according to example embodiments is shown.

[0012] Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA' and line BB'.

[0013] Figure 3 Shows Figure 2 A local enlarged view of region R2.

[0014] Figure 4 Shows Figure 1 A local enlarged view of area R1.

[0015] FIG. 5A to FIG. 5E According to some example embodiments, Figure 1 A cross-sectional view taken along line CC'.

[0016] Figures 6 to 8 A partial top plan view illustrating a semiconductor device according to some example embodiments is illustrated.

[0017] Fig. 9 , Fig.11 , FIG. 14A to FIG. 14D , Fig.16 , FIG. 19A to FIG. 19D , Fig.21 and Fig.23 A top plan view for describing a method of manufacturing a semiconductor device according to example embodiments is shown.

[0018] Fig.10 , Fig.12 , Fig.17 , Fig. 22 and Fig.24 A cross-sectional view corresponding to a top plan view for describing a method of manufacturing a semiconductor device according to example embodiments is shown.

[0019] Fig.13 and Fig.18 A partial perspective view for describing a method of manufacturing a semiconductor device according to example embodiments is shown.

[0020] Fig.15 Shows Fig.14D A local enlarged view of area R3.

[0021] Fig. 20 Shows Fig.16 A local enlarged view of area R4.

[0022] Fig.25 An electronic system including a semiconductor device according to example embodiments is schematically illustrated.

[0023] Fig.26 A schematic perspective view illustrating an electronic system including a semiconductor device according to example embodiments is shown.

[0024] Fig. 27 and Fig.28 Schematic cross-sectional views illustrating semiconductor packages according to example embodiments are respectively shown. DETAILED DESCRIPTION

[0025] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings showing example embodiments of the present disclosure. As those skilled in the art will appreciate, the described example embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0026] In order to clearly describe the present disclosure, parts irrelevant to the description are omitted, and the same reference numerals refer to the same or similar constituent elements throughout the specification.

[0027] In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0028] It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intermediate elements. In contrast, when an element is referred to as being "directly above" another element, there are no intermediate elements. In addition, in this specification, the word "on" or "above" means being above or below an object part, but does not necessarily mean being on the upper side of the object part based on the direction of gravity.

[0029] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0030] Furthermore, throughout this specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross section taken by vertically cutting the object portion is viewed from the side.

[0031] In the following, reference will be made to Figure 1 and Figure 5E A semiconductor device according to example embodiments is described.

[0032] Figure 1 A partial top plan view illustrating a semiconductor device according to example embodiments is shown.

[0033] Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA' and line BB'. Figure 3 Shows Figure 2 A local enlarged view of region R2. Figure 4 Shows Figure 1 A local enlarged view of region R1. FIG. 5A to FIG. 5E According to some example embodiments, Figure 1 A cross-sectional view taken along line CC'.

[0034] For the sake of simplicity and clarity of understanding, Figure 1 In FIG. 1 , some components are omitted, and the channel structure CH, the contact electrode 184, the main support structure 164 and the sub-support structure 162 are mainly shown. Figure 1 In order to clearly understand the arrangement and shape of components in the plan view, illustration of some insulating layers is omitted.

[0035] refer to Figures 1 to 5E , a semiconductor device 10 according to an example embodiment includes: a cell region 100 including a memory cell structure; and a circuit region 200 including a peripheral circuit structure for controlling the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may be respectively Fig.25 The electronic system 1000 shown in FIG. 1 includes a first structure 1100F and a second structure 1100S of the semiconductor device 1100. Alternatively, the circuit region 200 and the unit region 100 may include Fig. 27 The semiconductor chip 2200 is shown including a first structure 3100 and a second structure 3200 .

[0036] Herein, the circuit region 200 may include a peripheral circuit structure located on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH located on a cell array region 102 of a second substrate 110 as a memory cell structure. A first wiring portion 230 electrically connected to the peripheral circuit structure may be located in the circuit region 200, and a second wiring portion 180 electrically connected to the memory cell structure may be located in the cell region 100.

[0037] In example embodiments, the cell region 100 may be located on the circuit region 200. Therefore, since it is not necessary to ensure an area corresponding to the circuit region 200 separately from the cell region 100, the area of ​​the semiconductor device 10 may be reduced. However, the present disclosure is not limited thereto, and the circuit region 200 may be located beside the cell region 100. In addition, the arrangement relationship between the cell region 100 and the circuit region 200 may be variously changed.

[0038] The circuit region 200 may include a first substrate 210 , and a circuit element 220 and a first wiring portion 230 located on the first substrate 210 .

[0039] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate having a semiconductor layer formed on a base substrate. For example, the first substrate 210 may include, for example, silicon, epitaxial silicon, germanium, silicon-germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0040] The circuit element 220 formed on the first substrate 210 may include various circuit elements that control the operation of the memory cell structure provided in the cell region 100. For example, the circuit element 220 may configure a decoder circuit 1110 (see Fig.25 ), page buffer 1120 (see Fig.25 ) and logic circuit 1130 (see Fig.25 ) and other peripheral circuit structures.

[0041] The circuit element 220 may include, for example, a transistor, but the present disclosure is not limited thereto. For example, the peripheral circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, and inductors.

[0042] The first wiring portion 230 located on the first substrate 210 may be electrically connected to the circuit element 220. As an example, the first wiring portion 230 may include a plurality of wiring layers 236 that are separated by a circuit insulation layer 232 disposed therebetween and connected to form a desired path through a contact via 234. The wiring layer 236 or the contact via 234 may include various conductive materials, and the circuit insulation layer 232 may include various insulating materials.

[0043] The cell region 100 may include a cell array region 102 and a connection region 104. The gate stack structure 120 and the channel structure CH may be located on the second substrate 110 in the cell array region 102. In the connection region 104, a structure for connecting the gate stack structure 120 and / or the channel structure CH formed in the cell array region 102 to the circuit region 200 or an external circuit may be provided.

[0044] The second substrate 110 may include a semiconductor material. For example, the second substrate 110 may include polysilicon doped with impurities. The second substrate 110 may be used as a common source line. The second substrate 110 may be used as a source region for supplying current to a memory cell located on the second substrate 110. The second substrate 110 may be formed in a plate shape. That is, the second substrate 110 may be formed as a plate-shaped common source line.

[0045] In example embodiments, the second substrate 110 may include a semiconductor layer including a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, or may be a substrate provided with a semiconductor layer on a base substrate.

[0046] For example, the second substrate 110 may be formed of silicon, germanium, silicon-germanium, silicon on insulator, or germanium on insulator. Herein, the semiconductor layer included in the second substrate 110 may be doped with P-type or N-type impurities, and for example, may be doped with n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0047] The substrate insulating portion 110i may be provided in a region of the second substrate 110 through which the contact electrode 186 extends. However, the material of the second substrate 110, the conductivity type of impurities doped in the semiconductor layer, and the material of the semiconductor layer are not limited thereto and may be variously changed.

[0048] At least a portion of the circuit insulating layer 232 may be located between the second substrate 110 and the first wiring portion 230. The portion of the circuit insulating layer 232 disposed between the second substrate 110 and the first wiring portion 230 may be formed of a single layer or a plurality of layers. For example, a layer containing silicon nitride and a layer containing silicon oxide may be located between the second substrate 110 and the first wiring portion 230. Herein, the layer containing silicon oxide may be located on the layer containing silicon nitride.

[0049] In the cell array region 102, the gate stack structure 120 includes a cell insulation layer 132 and a gate electrode 130 alternately stacked on a first surface (e.g., a front surface or an upper surface) of a second substrate 110, and a channel structure CH may be provided extending through the gate stack structure 120 in a direction intersecting the second substrate 110.

[0050] The horizontal conductive layers 112 and 114 may be disposed between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 may be used to electrically connect the channel structure CH and the second substrate 110. For example, the horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 disposed on a first surface of the second substrate 110, and may further include a second horizontal conductive layer 114 disposed on the first horizontal conductive layer 112. That is, the first horizontal conductive layer 112 may be disposed between the second substrate 110 and the second horizontal conductive layer 114.

[0051] The first horizontal conductive layer 112 may not be provided, and the horizontal insulating layer 116 may be provided between the second substrate 110 and the gate stack structure 120 in a portion of the connection region 104. In the manufacturing process, a portion of the horizontal insulating layer 116 may be replaced with the first horizontal conductive layer 112, and another portion of the horizontal insulating layer 116 located in the connection region 104 may remain in the connection region 104.

[0052] The first horizontal conductive layer 112 may function as a portion of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 and the second substrate 110 may function as a common source line.

[0053] like Figure 3 As shown in the enlarged view of FIG. 1 , the channel structure CH may extend to the second substrate 110 through the horizontal conductive layers 112 and 114, and the gate dielectric layer 150 may be removed from the portion where the first horizontal conductive layer 112 is located, so that the first horizontal conductive layer 112 may be directly connected to the channel layer 140 around the channel layer 140. Therefore, the first horizontal conductive layer 112 may electrically connect the second substrate 110 and the channel layer 140 to each other.

[0054] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material. For example, the first horizontal conductive layer 112 may be polysilicon doped with impurities, and the second horizontal conductive layer 114 may be polysilicon doped with impurities or a layer including impurities diffused from the first horizontal conductive layer 112. The present disclosure is not limited thereto, and the second horizontal conductive layer 114 may include an insulating material. In addition, in some example embodiments, the second horizontal conductive layer 114 may be omitted.

[0055] The gate stack structure 120 in which the cell insulating layers 132 and the gate electrodes 130 are alternately stacked may be located on the second substrate 110. That is, the gate stack structure 120 may be located on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 disposed on the second substrate 110.

[0056] exist Figure 2Although the gate stack structure 120 is shown as including one gate stack structure, the present disclosure is not limited thereto, and the gate stack structure 120 may be formed to include one gate stack structure, or may be formed to include three or more gate stack structures.

[0057] For example, in some example embodiments, the gate stack structure 120 may include a plurality of gate stack structures sequentially stacked on the second substrate 110. Therefore, since the number of stacked gate electrodes 130 may be increased, the number of memory cells may be increased with a stable structure. That is, when the gate stack structure 120 is formed to include a plurality of gate stack structures, its structure may be simplified while increasing data storage capacity.

[0058] In the gate stack structure 120 , the gate electrode 130 may include a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U sequentially located on the second substrate 110 .

[0059] The lower gate electrode 130L may function as a gate electrode of a ground selection transistor, the memory cell gate electrode 130M may constitute a memory cell, and the upper gate electrode 130U may function as a gate electrode of a string selection transistor.

[0060] The number of memory cell gate electrodes 130M may be determined according to the data storage capacity of the semiconductor device 10. According to some example embodiments, one or two or more lower gate electrodes 130L and one or two or more upper gate electrodes 130U may be provided and may have substantially the same or different structures as the memory cell gate electrodes 130M.

[0061] In addition, a portion of the gate electrode 130 (eg, the memory cell gate electrode 130M adjacent to the lower gate electrode 130L and the upper gate electrode 130U) may be a dummy gate electrode.

[0062] The unit insulating layer 132 may include: an interlayer insulating layer 132L, located below the gate electrode 130 in the gate stack structure 120 or between two adjacent gate electrodes 130; an intermediate insulating layer 132M, used to flatten the steps of the gate stack structure 120 with a step shape in the dummy regions DMR1 and DMR2 and the steps between the gate stack structures 120 located in different regions; and an upper insulating layer 132U, located at the upper portion of the gate stack structure 120.

[0063] The upper insulating layer 132U may form part or all of the cell region insulating layer located at the entire upper portion of the cell region 100. In some example embodiments, the thicknesses of the cell insulating layers 132 may not all be the same. For example, the thickness of the middle insulating layer 132M is greater than the thickness of the interlayer insulating layer 132L and the thickness of the upper insulating layer 132U, and the thickness of the upper insulating layer 132U may be greater than the thickness of the interlayer insulating layer 132L. However, the configuration, shape, and structure of the cell insulating layer 132 are not limited thereto, and various changes may be made.

[0064] The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may include a metal material such as tungsten (W), copper (Cu), or aluminum (Al).

[0065] In some example embodiments, the gate electrode 130 may include polysilicon, metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. Although not shown, an insulating film made of an insulating material may be disposed outside the gate electrode 130, or a portion of the gate dielectric layer 150 may be disposed.

[0066] The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

[0067] In example embodiments, a channel structure CH extending in a direction crossing the second substrate 110 (eg, a Z direction perpendicular to the second substrate 110 ) may be formed by the gate stack structure 120 .

[0068] Specifically, the channel structure CH may include a channel layer 140 , and a gate dielectric layer 150 disposed on the channel layer 140 between the gate electrode 130 and the channel layer 140 .

[0069] The channel structure CH may further include a core insulating layer 142 disposed inside the channel layer 140 , and a channel pad 144 located on the channel layer 140 and / or the gate dielectric layer 150 .

[0070] Each channel structure CH forms a memory cell string, and a plurality of channel structures CH may be spaced apart from each other while forming rows and columns in a plan view. For example, the channel structures CH may be arranged in various forms in a plan view, such as a lattice form or a zigzag form.

[0071] The channel structures CH may each have a columnar shape in a cross-sectional view. For example, when the channel structure CH is viewed in a cross-sectional view, the channel structure CH may have an inclined side surface so that the width of the channel structure CH becomes narrower as it approaches the second substrate 110 according to the aspect ratio. The cross-sectional shape of the channel structure CH is not limited thereto, and the arrangement, structure, and shape of the channel structure CH may be variously changed.

[0072] The core insulating layer 142 may be provided in the central portion of the channel structure CH, and the channel layer 140 may be formed while surrounding the sidewall of the core insulating layer 142. For example, the core insulating layer 142 may have a columnar shape such as a cylindrical shape or a polygonal columnar shape, and the channel layer 140 may have a planar shape such as a cylindrical ring shape. However, the present disclosure is not limited thereto, and the core insulating layer 142 may not be provided, and the channel layer 140 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape).

[0073] The channel layer 140 may include a semiconductor material, such as polysilicon. The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the materials of the channel layer 140 and the core insulating layer 142 are not limited thereto, and various changes may be made.

[0074] The gate dielectric layer 150 between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156 sequentially stacked on the channel layer 140 .

[0075] Herein, the tunneling layer 152 is a layer that tunnels charges according to a voltage applied to the gate electrode 130, and may include an insulating material that enables charges to tunnel. The tunneling layer 152 may include a material such as silicon oxide or silicon nitride. For example, the tunneling layer 152 may be formed by stacking a layer including silicon oxide and a layer including silicon nitride.

[0076] The charge storage layer 154 disposed between the tunneling layer 152 and the blocking layer 156 may be used as a data storage area. For example, the charge storage layer 154 may include silicon nitride capable of trapping charges. If the charge storage layer 154 is made of silicon nitride, the charge storage layer 154 may have a relatively excellent retention force compared to the case where it is made of polysilicon, and may be advantageous for integration. However, the material of the charge storage layer 154 is not limited thereto, and various changes may be made.

[0077] The blocking layer 156 may be disposed between the charge storage layer 154 and the gate electrode 130. The blocking layer 156 may include an insulating material capable of preventing charges from undesirably flowing into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material, or a combination thereof.

[0078] In this article, the high dielectric constant material refers to a dielectric material with a dielectric constant higher than that of silicon oxide. For example, the high dielectric constant material may include aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide TiO 2 , Yttrium oxide Y 2 O 3 、ZrO 2 、ZrO2 silicon x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ), praseodymium oxide (Pr 2 O 3 ) or a combination thereof.

[0079] The channel pad 144 may be disposed on the channel layer 140 and / or the gate dielectric layer 150. The channel pad 144 may be disposed to cover the upper surface of the core insulating layer 142 and be electrically connected to the channel layer 140. Although the channel pad 144 is shown as covering the upper surface of the gate dielectric layer 150, the present disclosure is not limited thereto. For example, the channel pad 144 may not cover the upper surface of the gate dielectric layer 150. That is, the side surface of the channel pad 144 may be surrounded by the gate dielectric layer 150.

[0080] A side surface of the channel pad 144 may contact the tunnel layer 152. The channel pad 144 may include a conductive material such as polysilicon doped with impurities. However, the material of the channel pad 144 is not limited thereto and may be variously changed.

[0081] although Figure 2Although not shown in the figure, if the gate stack structure 120 includes a plurality of stacked gate stack structures, the channel structure CH may include a plurality of channel structures extending through each gate stack structure. For example, if the plurality of gate stack structures 120 include a first gate stack structure and a second gate stack structure, the plurality of channel structures CH may include a first channel structure extending through the first gate stack structure and a second channel structure extending through the second gate stack structure.

[0082] The first channel structure and the second channel structure may have a form of being connected to each other. Each of the first channel structure and the second channel structure may have an inclined side surface so that its width becomes narrower as it approaches the second substrate 110 according to the aspect ratio in the cross-sectional view. Therefore, if the gate stack structure 120 is formed to include a plurality of stacked gate stack structures, a curved portion may be provided due to the difference in width at the portion where the first channel structure and the second channel structure are connected. However, the shapes of the first channel structure and the second channel structure are not limited thereto, and various changes may be made. For example, the first channel structure and the second channel structure may have an inclined side surface that is continuously connected without being bent.

[0083] In example embodiments, the semiconductor device 10 may include a separation structure WLC. The separation structure WLC may extend in the second direction Y in a plan view and may be spaced apart from each other in a first direction X intersecting the second direction Y. That is, the separation structure WLC may extend in the second direction Y in a plan view and may be spaced apart from each other in the first direction X to be located at edges of the cell array region 102 and the connection region 104.

[0084] The gate stack structure 120 divided by the separation structure WLC may constitute one memory cell block. However, the scope of the memory cell block is not limited thereto and may be variously changed.

[0085] The separation structure WLC may have a linear shape extending in the second direction Y in a plan view. The side surface of the separation structure WLC may have a concave-convex shape including a convex portion and a concave portion in a plan view. However, the arrangement and shape of the separation structure WLC are not limited thereto, and various changes may be made. For example, the separation structure WLC may have a linear side surface including a straight line, and may be located not only at the edge of the extension region 146 but also in other regions. For example, although Figure 1Although not shown in the figure, the separation structure WLC extends in the first direction X, it may also be located at the first edge of the cell array region 102 in the second direction Y and the second edge of the connection region 104 in the second direction Y, respectively, and may be connected to the separation structure WLC extending in the second direction Y. That is, the separation structure WLC may extend in the first direction X and the second direction Y, may be located at the edges of the cell array region 102 and the connection region 104, and may surround the elements located in the cell array region 102 and the connection region 104. However, the arrangement and shape of the separation structure WLC are not limited thereto, and various changes may be made.

[0086] In the cross-sectional view, the separation structure 146 may extend to the second substrate 110 through the gate electrode 130 and the cell insulating layer 132. As an example, the separation structure WLC may have an inclined side surface whose width decreases toward the second substrate 110 due to a high aspect ratio when viewed in the cross-sectional view. However, the cross-sectional shape of the separation structure WLC is not limited thereto, and the side surface of the separation structure WLC may be perpendicular to the second substrate 110.

[0087] In addition, although Figure 2 Although not shown, if the gate stack structure 120 includes a plurality of stacked gate stack structures, in the cross-sectional view, the separation structure WLC may have a continuously inclined side surface in the first gate stack structure and the second gate stack structure, and may not include a bent portion. In addition, in some example embodiments, in the cross-sectional view, the separation structure WLC may include a bent portion at a boundary between the first gate stack structure and the second gate stack structure.

[0088] The separation structure WLC may be filled with various insulating materials. For example, the separation structure WLC may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. However, the materials included in the structure WLC are not limited thereto, and various changes may be made.

[0089] although Figure 2 Although not shown in the figure, the semiconductor device 10 according to the example embodiment may further include an upper separation pattern (not shown) located between the channel structures CH. That is, the upper separation pattern may be positioned by extending through one or more gate electrodes 130 including the upper gate electrode 130U located between the separation structures WLC. The upper separation pattern may separate, for example, three gate electrodes 130 from each other in the crossing direction (X-axis direction). However, the number of gate electrodes 130 separated by the upper separation pattern is not limited thereto, and various changes may be made.

[0090] The upper separation pattern may have a form filled with an insulating material and may be referred to as an insulating pattern herein. For example, the upper separation pattern (e.g., insulating pattern) may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the present disclosure is not limited thereto, and various modifications may be made to the structure, shape, and material of the upper separation pattern.

[0091] The connection region 104 and the second wiring portion 180 may be provided to connect the gate stack structure 120 and the channel structure CH provided in the cell array region 102 to the circuit region 200 or an external circuit.

[0092] Herein, the second wiring portion 180 may include all members that electrically connect the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring portion 180 may include a bit line 182, a contact electrode 186, and a contact via 180a connected to each of them.

[0093] The bit line 182 may be located on the cell insulating layer 132 of the gate stack structure 120 formed in the cell array region 102. The bit line 182 may extend in a crossing direction (X-axis direction in the drawing) that crosses one direction in which the gate electrode 130 extends. The bit line 182 may be electrically connected to the channel structure CH, such as the channel pad 144, through the contact via 180a.

[0094] The connection region 104 may be located around the cell array region 102. Members for connecting with the gate electrode 130, the horizontal conductive layers 112 and 114, and / or the second substrate 110 and the circuit region 200 may be located in the connection region 104. In addition, the connection region 104 may include a portion where an input / output pad and an input / output connection wiring are formed.

[0095] The connection region 104 may include a pad contact region PCA located at the center of the connection region 104, and dummy regions DMR1 and DMR2 located at opposite sides of the pad contact region PCA. That is, the first dummy region DMR1 may be located between the pad contact region PCA and the separation structure WLC located at a first edge of the connection region 104, and the second dummy region DMR2 may be located between the pad contact region PCA and the separation structure WLC located at a second edge of the connection region 104.

[0096] The gate stack structures 120 located in the first and second dummy regions DMR1 and DMR2 may be disconnected by the main support structure 164 located in the pad contact area PCA.

[0097] A main support structure 164 extending from the pad contact area PCA in the first direction X and the second direction Y in a plan view, and a plurality of pad areas PA at least partially surrounded by the main support structure 164 may be located in the pad contact area PCA. In addition, a contact electrode 186 connected to a pad electrode PD connected to the gate electrode 130 extending from the dummy regions DMR1 and DMR2 toward the pad contact area PCA may be located in each of the pad areas PA. A detailed description of the pad electrode PD and the contact electrode 186 will be described later.

[0098] A plurality of sub-support structures 162 may be located in the dummy regions DMR1 and DMR2 .

[0099] Specifically, the main support structure 164 may include a first portion 164a extending in the second direction Y in the pad contact area PCA, and a second portion 164b extending from the first portion 164a toward a first direction X intersecting the second direction Y. That is, the second portion 164b of the main support structure 164 may extend from the first portion 164a toward a first side and a second side of the first direction X in a plan view.

[0100] In an example embodiment, similar to the above-described separation structure WLC, the main support structure 164 may have a linear shape in a plan view. That is, at least one of the first portion 164a or the second portion 164b of the main support structure 164 may have a linear shape. In other words, in a plan view, the first portion 164a and the second portion 164b of the main support structure 164 may be integrally formed, and the first portion 164a and the second portion 164b may have a shape that is integrally connected without being disconnected.

[0101] The side surface of the main support structure 164 may have a concavo-convex shape including a convex portion and a concave portion in a plan view. Specifically, the side surface of the first portion 164a of the main support structure 164 may have a concavo-convex shape in a plan view. The side surface of the second portion 164b of the main support structure 164 may have a concavo-convex shape in a plan view.

[0102] In addition, the end of the second part 164b of the main support structure 164 may have a straight line shape in a plan view, and the end is located at the first side and the second side of the main support structure 164 in the first direction X and is aligned on a boundary substantially the same as the boundary of the side surface of the contact electrode 186. However, the shape of the side surface of the main support structure 164 in a plan view is not limited thereto, and various changes may be made. For example, the side surface of the main support structure 164 may have various shapes in a plan view, such as a flat straight line or a curve. For example, the end of the second part 164b of the main support structure 164 may have a concave-convex shape similar to the side surface of the first part 164a in a plan view, and the end is located at the first side and the second side of the main support structure 164 in the first direction X and is aligned on a boundary substantially the same as the boundary of the side surface of the contact electrode 186.

[0103] The semiconductor device 10 according to the example embodiment may include a plurality of sub-support structures 162 located in the dummy regions DMR1 and DMR2. Unlike the above-described separation structure WLC and the main support structure 164, the sub-support structures 162 may be arranged in an island shape in a plan view. That is, the sub-support structures 162 may be arranged to be spaced apart in the first direction X and spaced side by side along the second direction Y. In other words, since the sub-support structures 162 are spaced apart from each other, they may have an island shape in a plan view. Although the shape of the sub-support structures 162 is shown to have Figure 1 The sub-support structure 162 may be a circular shape in the plan view, but the present disclosure is not limited thereto, and the shape of the sub-support structure 162 in the plan view may be variously changed. For example, in the plan view, the shape of the sub-support structure 162 may have a polygonal shape.

[0104] exist Figure 1 , although the sub-support structures 162 located in the dummy regions DMR1 and DMR2 are spaced apart in the first direction X and arranged along the second direction Y to form two rows, the number and arrangement of the sub-support structures 162 are not limited thereto, and various changes may be made. For example, the sub-support structures 162 located in the dummy regions DMR1 and DMR2 may be omitted. As another example, in addition to the dummy regions DMR1 and DMR2, the sub-support structure 162 may also be located in the pad contact area PCA. That is, the sub-support structure 162 may be located between the contact electrode 186 and the main support structure 164 in the pad contact area PCA.

[0105] In this case, in the pad contact area PCA, the sub support structure 162 may be located at opposite sides of the first contact portion 186a of the contact electrode 186. In the pad contact area PCA, the sub support structure 162 and the first contact portion 186a of the contact electrode 186 may be aligned along the second direction Y.

[0106] The sub-support structure 162 and the main support structure 164 may be used to reduce stress applied to the gate stack structure 120 during a process step of etching the gate stack structure 120 , and maintain its shape against external force applied to the gate stack structure 120 .

[0107] Each of the pad areas PA located in the pad contact area PCA may be surrounded in a plan view by the second portion 164b of the main support structure 164 spaced apart from the first portion 164a of the main support structure 164 in the second direction Y. That is, in a plan view, the pad areas PA may be spaced apart in the second direction Y with the second portion 164b of the main support structure 164 disposed therebetween, and the pad areas PA may be positioned to face each other in the first direction X with the first portion 164a of the main support structure 164 disposed therebetween.

[0108] For example, the pad area PA may include: a first pad area PA1, a third pad area PA3, a fifth pad area PA5, a seventh pad area PA7, and a ninth pad area PA9, which are located at a first side of the main support structure 164 in the first direction X and are sequentially arranged in a direction from far to near relative to the cell array area 102; and a second pad area PA2, a fourth pad area PA4, a sixth pad area PA6, an eighth pad area PA8, and a tenth pad area PA10, which are located at a second side of the main support structure 164 in the first direction X and are sequentially arranged in a direction from far to near relative to the cell array area 102. That is, each of the first pad area PA1 and the second pad area PA2, the third pad area PA3 and the fourth pad area PA4, the fifth pad area PA5 and the sixth pad area PA6, the seventh pad area PA7 and the eighth pad area PA8, the ninth pad area PA9, and the tenth pad area PA10 may face each other in the first direction X, with the first portion 164a of the main support structure 164 interposed therebetween.

[0109] exist Figure 1 In the figure, for convenience, only 10 pad regions are shown, but this is only an example, and the number of pad regions may vary according to the number of layers of the gate electrode 130 included in the gate stack structure 120 .

[0110] In each of the pad areas PA, a pad electrode PD connected to the gate electrode 130 from the dummy areas DMR1 and DMR2 toward the pad area PA may be arranged. That is, the gate electrode 130 extending from the cell array area 102 to the connection area 104 may extend from the dummy areas DMR1 and DMR2 toward the pad area PA, and the gate electrode 130 located in the pad area PA may be the pad electrode PD connected to the contact electrode 186. In other words, the pad electrode PD may be a portion of the gate electrode 130 located in the pad area PA.

[0111] The contact electrode 186 connected to the pad electrode PD may be located in each of the pad areas PA. The pad electrode PD and the contact electrode 186 located in each of the pad areas PA may be surrounded by at least the main support structure 164 in a plan view. That is, three of the four edges of the contact electrode 186 may be surrounded by the second portion 164b and the first portion 164a of the main support structure 164 in a plan view. However, in a plan view, the arrangement relationship between the contact electrode 186 and the main support structure 164 is not limited thereto, and various changes may be made.

[0112] like Figure 5A As shown, the contact electrode 186 according to an example embodiment may include: a first contact portion 186a extending through the gate stack structure 120 located in the pad contact area PCA; and a second contact portion 186b located on the first contact portion 186a and connected to the upper surface of the pad electrode PD.

[0113] The contact electrodes 186 have a plate shape in a plan view and may be arranged in an island shape by being spaced apart in the first direction X and the second direction Y with the main support structure 164 disposed therebetween. Side surfaces of the contact electrodes 186 may directly contact side surfaces of the main support structure 164 .

[0114] In some example embodiments, another insulating layer may also be located between the contact electrode 186 and the main support structure 164. For example, the sacrificial insulating layer 130P is removed before forming the contact electrode 186 (see Fig. 22 ) and the interlayer insulating layer 132L, when a portion of the sacrificial insulating layer 130P and a portion of the interlayer insulating layer 132L are retained, the sacrificial insulating layer 130P and the interlayer insulating layer 132L can be set between the contact electrode 186 and the main support structure 164.

[0115] In the process step of forming the contact electrode hole 186H according to some example embodiments, when a portion of the insulating pattern 186i is etched together, the shape of the contact electrode 186H may change. Therefore, the shape of the contact electrode 186 located within the contact electrode hole 186H may vary.

[0116] For example, Figure 5B As shown, according to some example embodiments, the contact electrode 186_1 may include: a first contact portion 186a_1, extending through the gate stack structure 120 located in the pad contact area PCA; a second contact portion 186b_1, located on the first contact portion 186a_1 and connected to the side surface of the pad electrode PD; and a third contact portion 186c_1, located on the second contact portion 186b_1 and connected to the upper surface of the pad electrode PD.

[0117] In addition, the widths of the first contact portion 186a_1, the second contact portion 186b_1, and the third contact portion 186c_1 in the first direction X may be different. That is, the width of the first contact portion 186a_1 in the first direction X may be the smallest, and the width of the third contact portion 186c_1 in the first direction X may be the largest.

[0118] In some example embodiments, contact electrodes 186_2 , 186_3 , and 186_4 may surround a filling insulation layer 186L on the contact electrode holes 186H in the pad areas PA3 and PA4 .

[0119] For example, Figure 5C As shown, the contact electrode 186_2 may include: a first contact portion 186a_2 extending through the gate stack structure 120 located in the pad areas PA3 and PA4; and a second contact portion 186b_2 surrounding the filling insulation layer 186L located on the first contact portion 186a_2.

[0120] That is, the second contact portion 186b_2 is located on the first contact portion 186a_2 and may be connected to the upper surface of the pad electrode PD. The second contact portion 186b_2 may surround the lower surface and the side surface of the filling insulation layer 186L.

[0121] The second contact portion 186b_2 may be conformally arranged along the side surface of the intermediate insulating layer 132M, the side surface of the first portion 164a of the main support structure 164, the upper surface of the pad electrode PD, and the upper surface of the insulating pattern 186i. Therefore, the width of the second contact portion 186b_2 along the first direction X may be smaller than the width of the first contact portion 186a_2 along the first direction X.

[0122] An upper surface of the filling insulation layer 186L may be located at substantially the same height as an upper surface of the middle insulation layer 132M and an upper surface of the second contact portion 186b_2. In addition, an upper surface of the filling insulation layer 186L may directly contact the upper insulation layer 132U.

[0123] In some example embodiments, Figure 5D As shown, the filling insulating layer 186L having a lower surface and a side surface surrounded by the contact electrode 1863 may include an air gap, and the contact electrode 186_3 includes a first contact portion 186a_3 and a second contact portion 186b_3 located on the first contact portion 186a_3.

[0124] The air gap may be located approximately at the center of the filling insulating layer 186L, and the air gap may be surrounded by the filling insulating layer 186L. The air gap may be formed in a process step of forming the filling insulating layer 186L. Figure 5D , it has been shown that the air gap is located approximately at the center of the filling insulation layer 186L and has an elliptical shape, but the position and shape of the air gap are not limited thereto and may be variously changed.

[0125] The filling insulating layer 186L may include an insulating material. For example, the filling insulating layer 1186L may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the material included in the filling insulating layer 186L is not limited thereto, and various changes may be made.

[0126] As another example, Figure 5E As shown, the contact electrode 186_4 may include: a first contact portion 186a_4 extending through the gate stack structure 120 located in the pad areas PA3 and PA4; and a second contact portion 186b_4 surrounding the filling insulation layer 186L located on the first contact portion 186a_4.

[0127] and Figure 5C Unlike the example embodiment shown, in the present example embodiment, the second contact portion 186b_4 may cover the upper surface of the filling insulation layer 186L and the lower surface and side surface of the filling insulation layer 186L. That is, the filling insulation layer 186L may be buried in the second contact portion 186b_4. Therefore, the upper surface of the filling insulation layer 186L may directly contact the second contact portion 186b_4.

[0128] In addition, the upper surface of the filling insulation layer 186L may be located at a height lower than that of the upper surface of the middle insulation layer 132M and the upper surface of the second contact portion 186b_4.

[0129] The gate electrode 130 may extend from the cell array region 102 to the dummy regions DMR1 and DMR2 of the connection region 104 along the second direction Y. The extension length of the gate electrode 130 in the dummy regions DMR1 and DMR2 of the connection region 104 along the second direction Y may sequentially decrease as the distance from the second substrate 110 increases. That is, the gate electrode 130 in the dummy regions DMR1 and DMR2 of the connection region 104 may have a step shape in a cross-sectional view.

[0130] The gate electrode 130 may extend from the dummy regions DMR1 and DMR2 to the pad region PA. Similar to the gate electrode 130 located in the dummy regions DMR1 and DMR2, the gate electrode 130 located in the pad contact region PCA may have a step shape in a cross-sectional view. However, unlike the gate electrode 130 located in the pad contact region PCA, the gate electrodes 130 located in the dummy regions DMR1 and DMR2 may be disconnected by the main support structure 164 located at each end of the gate electrode 130.

[0131] Therefore, since the gate electrode 130 located in the dummy regions DMR1 and DMR2 and the pad area PA has a step shape in a cross-sectional view, each of the upper surfaces of the pad electrodes PD connected to the gate electrode 130 extending from the dummy regions DMR1 and DMR2 to the pad area PA can contact the contact electrode 186 at different heights.

[0132] The gate electrodes 130 located in the dummy regions DMR1 and DMR2 may be connected to the pad electrode PD located in the pad area PA of the pad contact area PCA. Herein, the gate electrodes 130 connected to the pad electrode PD may be located at substantially the same height and may be integrally formed.

[0133] For example, Figure 1 and Figure 2 As shown, the pad electrodes PD respectively located in the second pad area PA2 , the fourth pad area PA4 , the sixth pad area PA6 , the eighth pad area PA8 , and the tenth pad area PA10 may be located at higher heights as they approach the cell array area 102 .

[0134] Therefore, the pad electrode PD located in the second pad area PA2 may be located at the lowest height, and the pad electrode PD located in the tenth pad area PA10 may be located at the highest height.

[0135] although Figure 2 Although not shown, the pad electrodes PD respectively located in the first pad area PA1, the third pad area PA3, the fifth pad area PA5, the seventh pad area PA7 and the ninth pad area PA9 may be located at a higher height in a direction closer to the cell array area 102.

[0136] The gate electrode 130 located in the first dummy region DMR1 and having a step shape in a cross-sectional view may have a different height from the gate electrode 130 located in the second dummy region DMR2 and having a step shape in a cross-sectional view.

[0137] Therefore, the pad electrodes PD located in the pad area PA may be located at different heights. That is, the pad electrodes PD located in the pad area PA, which are spaced apart from each other and between which the first portion 164a of the main support structure 164 is disposed, may be located at different heights. In other words, the pad electrode PD connected to the gate electrode 130 extending from the second dummy region DMR2 may be located at a height higher than that of the pad electrode PD connected to the gate electrode 130 extending from the first dummy region DMR1.

[0138] For example, Figure 5A As shown, the pad electrode PD located in the third pad area PA3 (which are spaced apart from each other in the first direction X and between which the first portion 164a of the main support structure 164 is disposed) may be located at a height lower than that of the pad electrode PD located in the fourth pad area PA4. Figure 5A Not shown, the pad electrodes PD respectively located in the first pad area PA1, the fifth pad area PA5, the seventh pad area PA7 and the ninth pad area PA9 may be located at a height lower than that of the pad electrodes PD respectively located in the second pad area PA2, the sixth pad area PA6, the eighth pad area PA8 and the tenth pad area PA10.

[0139] The shapes of the gate electrodes 130 located in the above-mentioned dummy regions DMR1 and DMR2 and the pad contact region PCA, and the shapes for positioning the pad electrode PD at different heights in each pad region PA are examples, but are not limited thereto, and various changes may be made. For example, some of the gate electrodes 130 located in the pad contact region PCA and the dummy regions DMR1 and DMR2 have a step shape that descends as the distance from the cell array region 102 increases, and if the remaining gate electrodes 130 have a step shape that rises as the distance from the cell array region 102 increases, the height at which the pad electrode PD is located may be variously changed.

[0140] As another example, although in Figure 2 , the gate stack structure 120 is shown as including one gate stack structure 120, but if the gate stack structure 120 is formed to include one or more gate stack structures 120, or is formed to include one or more gate stack structures 120 and some of the gate electrodes 130 located in the pad contact area PCA and the dummy areas DMR1 and DMR2 have a step shape that descends as it moves away from the cell array area 102, and the remaining gate electrodes 130 have a step shape that rises as the distance from the cell array area 102 increases, the height at which the pad electrode PD is located may be variously changed.

[0141] refer to Figure 2 and Figure 5A The contact electrode 186 may be connected to the pad electrode PD connected to the gate electrode 130 , and may extend through the gate stack structure 120 and to a pad portion located in the circuit region 200 to be electrically connected to the circuit region 200 .

[0142] The contact electrode 186 may include a first contact portion 186a extending through the gate stack structure 120 and a second contact portion 186b located on the first contact portion 186a and connected to the upper surface of the pad electrode PD. The second contact portion 186b of the contact electrode 186 may be formed in a region where a stack structure described later is removed.

[0143] The first contact portion 186a of the contact electrode 186 may extend through the gate stack structure 120 and be connected to a pad portion located in the circuit region 200. The second contact portion 186b of the contact electrode 186 is electrically connected to an upper surface of the pad electrode PD located in each pad region PA, and the second contact portion 186b of the contact electrode 186 may be electrically connected to the pad portion of the circuit region 200 through the first contact portion 186a.

[0144] The second contact portion 186b of the contact electrode 186 may be electrically connected to the pad electrode PD connected to the gate electrode 130 located on the uppermost portion of each layer among the gate electrodes 130 having a step shape in the cross-sectional view in the dummy regions DMR1 and DMR2. The first contact portion 186a of the contact electrode 186 may be insulated from the gate electrode 130 located below the pad electrode PD with an insulating pattern 186i disposed therebetween.

[0145] That is, the side surface of the first contact portion 186a of the contact electrode 186 may directly contact the insulating pattern 186i, and the side surface of the second contact portion 186b may directly contact the main support structure 164 and the intermediate insulating layer 132M. However, the present disclosure is not limited thereto, and other layers may also be located between the first contact portion 186a of the contact electrode 186 and the insulating pattern 186i, and between the second contact portion 186b of the contact electrode 186 and the main support structure 164 and the intermediate insulating layer 132M.

[0146] In example embodiments, the insulating pattern 186i may include the same material as that of the above-described unit insulating layer 132. However, the material included in the insulating pattern 186i is not limited thereto and may be variously changed.

[0147] The width of the first contact portion 186a of the contact electrode 186 may be smaller than the width of the second contact portion 186b. The first contact portion 186a and the second contact portion 186b of the contact electrode 186 may be surrounded by the main support structure 164 in a plan view, and the second contact portion 186b of the contact electrode 186 may completely cover the first contact portion 186a in a plan view.

[0148] Each first contact portion 186a of the contact electrode 186 may have an inclined side surface such that its width becomes narrower according to an aspect ratio in a cross-sectional view as it approaches the second substrate 110. In addition, the length of the first contact portion 186a of each of the contact electrodes 186 along the third direction Z may decrease as the distance from the cell array region 102 increases.

[0149] Each second contact portion 186b of the contact electrode 186 may have an inclined side surface such that its width becomes wider according to an aspect ratio in a cross-sectional view as it is closer to the second substrate 110. In addition, the length of the second contact portion 186b of each of the contact electrodes 186 along the third direction Z may increase as the distance from the cell array region 102 increases.

[0150] For example, the length of the first contact portion 186a of the contact electrode 186 located in the second pad area PA2 along the third direction Z may be the shortest, while the length of the first contact portion 186a of the contact electrode 186 located in the tenth pad area PA10 along the third direction Z may be the longest. In addition, the length of the second contact portion 186b of the contact electrode 186 located in the second pad area PA2 along the third direction Z may be the longest, while the length of the second contact portion 186b of the contact electrode 186 located in the pad area PA10 along the third direction Z may be the shortest.

[0151] In addition, since the pad electrodes PD respectively located in the pad areas PA (spaced apart from each other in the first direction X, with the first portion 164a of the main support structure 164 interposed therebetween) are located at different heights, the lengths of the first contact portion 186a and the second contact portion 186b of the contact electrode 186 respectively located in the pad areas PA (spaced apart from each other and facing each other in the first direction X, with the first portion 164a of the main support structure 164 interposed therebetween) may be different.

[0152] For example, Figure 5AAs shown, the length of the first contact portion 186a of the contact electrode 186 located in the fourth pad area PA4 along the third direction Z may be longer than the length of the first contact portion 186a of the contact electrode 186 located in the third pad area PA3 along the third direction Z, and the length of the second contact portion 186b of the contact electrode 186 located in the fourth pad area PA4 along the third direction Z may be shorter than the length of the second contact portion 186b of the contact electrode 186 located in the third pad area PA3 along the third direction Z.

[0153] Therefore, the difference between the length of the first contact portion 186a of each of the plurality of contact electrodes 186 along the third direction Z and the length of the second contact portion 186b along the third direction Z is due to the difference in the height at which the pad electrode PD electrically connected to each contact electrode 186 is located. However, the shape and structure of the contact electrode 186 are not limited thereto, and the shape and structure of each of the contact electrodes 186 may be variously changed according to the connection form between the contact electrode 186 and the pad electrode PD. In addition, the cross-sectional shape of the contact electrode 186 is not limited thereto, and the side surface of the contact electrode 186 may be perpendicular to the second substrate 110.

[0154] The contact electrode 186 may include a conductive material. For example, the contact electrode 186 may include tungsten (W), copper (Cu), aluminum (Al), etc., and may also include a diffusion barrier layer. However, the material included in the contact electrode 186 is not limited thereto, and various changes may be made. In addition, the first contact portion 186a and the second contact portion 186b of the contact electrode 186 may include different materials.

[0155] The first portion 164a and the second portion 164b of the main support structure 164 may extend through the gate stack structure 120 and the horizontal insulating layer 116, and the lower region of the main support structure 164 may be located at a height between the upper surface and the lower surface of the second substrate 110. However, the present disclosure is not limited thereto, and in some example embodiments, the lower region of the main support structure 164 may also extend in the third direction Z to extend through the second substrate 110.

[0156] The main support structure 164 may have an inclined side surface such that its width becomes narrower as it approaches the second substrate 110 according to the aspect ratio in the cross-sectional view. In addition, the cross-sectional shape of the main support structure 164 is not limited thereto, and the side surface of the main support structure 164 may be perpendicular to the second substrate 110.

[0157] The sub-support structure 162 may extend through the gate stack structure 120 and may be located in the dummy regions DMR1 and DMR2. The sub-support structure 162 may have an inclined side surface so that its width becomes narrower as it approaches the second substrate 110 according to the aspect ratio in the cross-sectional view. However, the cross-sectional shape of the sub-support structure 162 is not limited thereto, and the side surface of the sub-support structure 162 may be perpendicular to the second substrate 110.

[0158] Since the gate stack structure 120 of the dummy regions DMR1 and DMR2 where the sub-support structure 162 is located and the pad contact region PCA where the contact electrode 186 is located has a step shape in the cross-sectional view, the thickness of the gate stack structure 120 where the first contact portion 186a of the contact electrode 186 in the pad contact region PCA and the dummy regions DMR1 and DMR2 where the sub-support structure 162 is located may be thinner than the stacking thickness of the gate stack structure 120 where the separation structure WLC is located. In addition, the thickness of the gate stack structure 120 where the sub-support structure 162 is located may be substantially the same as the thickness of the gate stack structure 120 where the first contact portion 186a of the contact electrode 186 is located.

[0159] Therefore, the upper surface of the sub-support structure 162 and the upper surface of the first contact portion 186a of the contact electrode 186 can be located at substantially the same height, and the upper surface of the sub-support structure 162 and the upper surface of the first contact portion 186a of the contact electrode 186 can be located at a height lower than the height of the upper surface of the separation structure WLC and the upper surface of the main support structure 164.

[0160] As described above, the step shape of the gate stack structure 120 located in the first dummy region DMR1 and the second dummy region DMR2 has a height difference, so the upper surface of the sub-support structure 162 located in the first dummy region DMR1 and the upper surface of the sub-support structure 162 located in the second dummy region DMR2 can be located at different heights. In addition, the upper surface of the sub-support structure 162 located in the second dummy region DMR1 can be located at substantially the same height as the upper surface of the first contact portion 186a of the contact electrode 186 located in the pad region PA adjacent to the second dummy region DMR2, so the upper surface of the sub-support structure 162 located in the second dummy region DMR2 can be located at a different height from the upper surface of the first contact portion 186a of the contact electrode 186 located in the pad region PA adjacent to the first dummy region DMR1.

[0161] For example, Figure 5AAs shown, the upper surface of the sub-support structure 162 located in the second dummy region DMR2 and the upper surface of the first contact portion 186a of the contact electrode 186 located in the fourth pad region PA4 can be located at a height higher than the upper surface of the sub-support structure 162 located in the first dummy region DMR1 and the upper surface of the first contact portion 186a of the contact electrode 186 located in the third pad region PA3.

[0162] As another example, Figure 5B As shown, the upper surface of the sub-support structure 162 located in the second dummy region DMR2 can be located at a height higher than the height of the upper surface of the first contact portion 186a_1 of the contact electrode 186_1 located in the fourth pad region PA4, and can be located at substantially the same height as the upper surface of the second contact portion 186b_1 of the contact electrode 186_1 located in the fourth pad region PA4.

[0163] like Figure 4 and Figure 5A As shown, the separation structure WLC located in the connection region 104 may be surrounded by the gate stack structure 120 in a plan view. For example, the upper surface of the separation structure WLC located in the connection region 104 may be surrounded by the gate electrode 130 in a plan view, and the separation structure WLC may be spaced apart from the intermediate insulating layer 132M located in the dummy regions DMR1 and DMR2 to be described later, with the gate electrode 130 disposed therebetween. In addition, in a cross-sectional view, the side surface of the separation structure WLC located in the connection region 104 may be surrounded by the gate stack structure 120.

[0164] The upper surface of the separation structure WLC and the upper surface of the main support structure 164 may be located at substantially the same height. In addition, the upper surface of the second contact portion 186b of the contact electrode 186 located in the pad area PA may be located at substantially the same height as the upper surface of the separation structure WLC and the upper surface of the main support structure 164, and the lower surface of the second contact portion 186b of the contact electrode 186 may be located at substantially the same height as the upper surface of the sub-support structure 162 located in the dummy regions DMR1 and DMR2 adjacent to each other.

[0165] For example, Figure 5AAs shown, the lower surface of the second contact portion 186b of the contact electrode 186 located in the fourth pad region PA4 may be located at substantially the same height as the upper surface of the sub-support structure 162 located in the second dummy region DMR2, and the lower surface of the second contact portion 186b of the contact electrode 186 located in the third pad region PA3 may be located at substantially the same height as the upper surface of the sub-support structure 162 located in the first dummy region DMR1. However, the arrangement relationship between the sub-support structure 162, the main support structure 164, the contact electrode 186, and the separation structure WLC is not limited thereto, and various changes may be made.

[0166] like Figure 2 and Figure 5A As shown, the width of the first portion 164 a of the main support structure 164 in the first direction X may be greater than the width of the separation structure WLC in the first direction X.

[0167] The width of the second portion 164 b of the main support structure 164 along the first direction X may be greater than or less than the width of the first contact portion 186 a of the contact electrode 186 along the first direction X.

[0168] In addition, the width of the main support structure 164 along the first direction X may be greater than the width of the separation structure WLC along the first direction X. In addition, the width of the main support structure 164 along the first direction X and the second direction Y may be greater than the width of the sub-support structure 162 along the first direction X and the second direction Y.

[0169] The width of the separation structure WLC along the first direction X may be greater than the width of the sub-support structure 162 along the first direction X. In addition, the width of the separation structure WLC along the first direction X may be greater than the width of the first contact portion 186 a of the contact electrode 186 along the first direction X.

[0170] The width of the sub-support structure 162 along the first direction X may be substantially the same as the width of the first contact portion 186a of the contact electrode 186 along the first direction X. However, the width relationship between the sub-support structure 162, the main support structure 164, the contact electrode 186, and the separation structure WLC is not limited thereto, and various changes may be made. For example, the width of the first portion 164a of the main support structure 164 along the first direction X and the width of the second portion 164b along the second direction Y may be substantially the same as the width of the sub-support structure 162.

[0171] The intermediate insulating layer 132M may be disposed on the sub-support structure 162 and the gate stack structure 120 in the dummy regions DMR1 and DMR2. The intermediate insulating layer 132M is formed for the purpose of flattening the step due to the step shape of the gate stack structure 120 located in the dummy regions DMR1 and DMR2. Therefore, the upper surface of the intermediate insulating layer 132M may be located at substantially the same height as the upper surface of the separation structure WLC, the upper surface of the second contact portion 186b of the contact electrode 186, and the upper surface of the main support structure 164.

[0172] like Figure 5A As shown, the upper insulating layer 132U may cover the separation structure WLC, the middle insulating layer 132M, the upper surface of the second contact portion 186 b of the contact electrode 186 , the upper surface of the main support structure 164 , and the gate stack structure 120 .

[0173] The sub-support structure 162 and the main support structure 164 may have a form filled with an insulating material. For example, the upper separation pattern may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the present disclosure is not limited thereto, and the structure, shape, and material of the sub-support structure 162 and the main support structure 164 may be variously changed.

[0174] According to the semiconductor device 10 of the example embodiment, if an etching process is performed in the process step of forming a plurality of contact electrodes 186 in the pad contact area PCA, each region of the stacked structure for forming contact electrodes 186 may include substantially the same layer and may have the same stack thickness.

[0175] Therefore, when the etching process is performed in substantially the same environment, each region of the stacked structure where the contact electrode 186 is formed can prevent the occurrence of defects due to differences in etching conditions, which may occur in some regions of the stacked structure depending on the process conditions (for example, the type of stacked layer or the thickness of the stacked layer).

[0176] Therefore, the reliability of the semiconductor device and the productivity of the semiconductor device may be improved by improving the electrical characteristics of the contact electrode 186 connected to each pad electrode PD provided in the pad area PA.

[0177] In the following, reference will be made to Figures 6 to 9 Other example embodiments of the semiconductor device are described. In the following example embodiments, the same reference numerals refer to the same components as those of the previously described example embodiments, and repeated descriptions will be omitted or simplified, and the description will focus on the differences.

[0178] Figures 6 to 8 A partial top plan view illustrating a semiconductor device according to some example embodiments is illustrated.

[0179] and Figure 1 The semiconductor device 10 according to the exemplary embodiment shown is different from Figure 6 The semiconductor device 10_1 of the illustrated example embodiment is different in that the sub-support structure 162 located in the dummy regions DMR1 and DMR2 is omitted.

[0180] In this example embodiment, Figure 1 Unlike the illustrated example embodiment, the main support structure 164_1 may be located in the pad contact area PCA and the dummy regions DMR1 and DMR2 of the connection region 104 .

[0181] Specifically, refer to Figure 6 The main support structure 164_1 includes a first portion 164a_1 extending in the second direction Y and a second portion 164b_1 extending from the first portion 164a_1 in the first direction X, and Figure 1 Compared to the illustrated example embodiment, the second portion 164 b_1 may further extend from the pad contact area PCA in the first direction X to be further located in the dummy regions DMR1 and DMR2 .

[0182] In addition, in this exemplary embodiment, Figure 1 Compared to the illustrated example embodiment, since the ends of the second portion 164 b_1 of the main support structure 164_1 extend toward the first and second sides in the first direction X, the area of ​​the contact electrode 186 surrounded by the main support structure 164_1 may be wider in a plan view.

[0183] Therefore, with Figure 1 Compared to the example embodiment shown, the dummy regions DMR1 and DMR2 may have a smaller width in the first direction X, and the width of the pad contact area PCA may be larger along the first direction X. In other words, the width of the pad contact area PCA along the first direction X may be greater than the width of the dummy regions DMR1 and DMR2 along the first direction X.

[0184] In this example embodiment, Figure 1 Unlike the example embodiment shown, even if the sub-support structure 162 is not located in the dummy regions DMR1 and DMR2, the second portion 164b_1 of the main support structure 164_1 extending from the pad contact area PCA to the dummy regions DMR1 and DMR2 can maintain its shape to resist external forces applied to the gate stack while reducing stress that may be applied to the gate stack structure 120 during the process step of etching the gate stack structure 120.

[0185] In addition, the width of the gate stack structure 120 located in the dummy regions DMR1 and DMR2 and having a step shape along the first direction X is less than Figure 1 The width of the gate stack structure 120 of the example embodiment shown, therefore, even if the sub-support structure 162 is not located in the dummy regions DMR1 and DMR2, the original shape can be maintained during the process step of forming a step shape in the gate stack structure 120 located in the dummy regions DMR1 and DMR2 without being deformed due to stress or external force applied to the gate stack structure 120 located in the dummy regions DMR1 and DMR2.

[0186] Therefore, in the case of the semiconductor device 10_1 according to the present exemplary embodiment, the order of the process steps of forming a step shape in the gate stack structure 120 located in the dummy regions DMR1 and DMR2 and the process steps of forming the contact electrode 186 in the pad contact area PCA is not limited. That is, no matter which process is performed first among the process steps of forming a step shape in the gate stack structure 120 located in the dummy regions DMR1 and DMR2 and the process steps of forming the contact electrode 186 in the pad contact area PCA, the corresponding fixing step can be performed while maintaining the original shape of the gate stack structure 120, so that the process order can be diversified.

[0187] and Figure 2 The semiconductor device 10 according to the exemplary embodiment shown is different from Figure 7 The semiconductor device 10_1 of the illustrated example embodiment may include a plurality of cell array regions 102 , and the connection region 104 may further include a cell contact region CCA.

[0188] According to the semiconductor device 10_2 of the present example embodiment, the cell array regions 102 may be spaced apart from each other in the second direction Y with the connection region 104 disposed therebetween. That is, the connection region 104 may be located between the cell array regions 102. However, the arrangement relationship between the cell array region 102 and the connection region 104 is not limited thereto, and various changes may be made.

[0189] According to Figure 1 Unlike the semiconductor device 10 of the illustrated example embodiment, the semiconductor device 10_2 according to the present example embodiment is different in that the connection region 104 further includes a cell contact region CCA connecting the cell array region 102 , and the dummy region DMR is only provided at a first side of the connection region 104 .

[0190] Specifically, Figure 7As shown, the pad contact area PCA is located at the center of the connection area 104, the cell contact area CCA is located at a first side of the pad contact area PCA in the first direction X, and the dummy region DMR may be located at a second side of the pad contact area PCA in the first direction X.

[0191] and Figure 1 Unlike the exemplary embodiment shown, the second portion 164b_2 of the main support structure 164_2 according to the present exemplary embodiment may extend to the first side of the first direction X. That is, Figure 1 Unlike the illustrated example embodiment in which the second portion 164b of the main support structure 164 extends to the first side and the second side in the first direction X, in the present example embodiment, the second portion 164b_2 of the main support structure 164_2 may extend along the first side of the first direction X. That is, the second portion 164b_2 of the main support structure 164_2 may extend toward the dummy region DMR.

[0192] and Figure 1 , Figure 2 and Figure 5A Similar to the illustrated example embodiment, a plurality of gate electrodes (not shown) may extend from the dummy region DMR to each of the pad region PA_2. The gate electrode located in the pad contact region PCA and the gate electrode located in the dummy region DMR may have a step shape in a cross-sectional view.

[0193] However, with Figure 1 , Figure 2 and Figure 5A Unlike the example embodiment shown in FIG. 1 having a step shape that descends as the distance from the cell array region 102 increases in the cross-sectional view, in the present example embodiment, the gate electrode located in the dummy region DMR has a step shape that descends as the distance from the cell array region 102 located at the first side of the connection region 104 in the second direction Y increases in the cross-sectional view, and the connection region 104 may have a step shape that descends downward as the distance from the second side of the cell array region 102 located in the second direction Y increases. That is, the gate electrode located in the dummy region DMR may have a shape in which the step shape that descends as the distance from the cell array region 102 located at the first side of the connection region 104 increases and the step shape that descends as the distance from the cell array region 102 located at the second side of the connection region 104 increase are opposite to each other in the cross-sectional view.

[0194] A plurality of pad areas PA_2 may be located in the pad contact area PCA. Figure 1 Unlike the illustrated example embodiment, in the present example embodiment, the pad area PA_2 may be located only at the first side in the first direction X of the main support structure 164_2 .

[0195] In addition, Figure 1 The example embodiments shown are different (in Figure 1 In the illustrated example embodiment, the pad areas PA are spaced apart from each other in the first direction X, with the pad contact area PCA disposed therebetween, and are sequentially arranged from a position away from the cell array area 102, i.e., arranged in one direction along the second direction Y). In the present example embodiment, some of the pad areas PA_2 may be sequentially arranged in a direction away from the cell array area 102 located at a first side of the connection area 104 to closer to the cell array area 102 along the second direction Y, and the remaining pad areas PA_2 may be sequentially arranged in a direction starting from a far side of the cell array area 102 located at a second side of the connection area 104 in the second direction Y to closer to the cell array area 102. That is, the pad areas PA_2 are arranged along substantially the same row, and may be sequentially arranged toward different directions.

[0196] Therefore, since the plurality of gate electrodes located in the dummy region DMR and the pad region PA_2 have a stepped shape facing each other in a cross-sectional view, the upper surface of the pad electrode (not shown) connected to the gate electrode extending from the dummy region DMR to the pad region PA_2 may be exposed. That is, the pad electrode connected to the contact electrode 186_2 in each of the pad regions PA_2 may be located at different heights.

[0197] For example, the first to fifth pad regions PA1_2 , PA3_2 , and PA5_2 may be sequentially arranged along a first direction of the second direction Y, and the second to fourth pad regions PA2_2 and PA4_2 may be sequentially arranged along a second direction of the second direction Y.

[0198] That is, the gate electrodes respectively extending from the dummy region DMR to the first, third, and fifth pad regions PA1_2 , PA3_2 , and PA5_2 may have a stepped shape rising as they get closer to the cell array region 102 located at the second side of the connection region 104 .

[0199] The gate electrodes respectively extending from the dummy region DMR to the second and fourth pad regions PA2_2 and PA4_2 may have a stepped shape rising as they get closer to the cell array region 102 disposed at the first side of the connection region 104 .

[0200] In addition, the pad electrode extending from the dummy region DMR to the pad region PA_2 (the pad electrode is configured to be connected to the contact electrode 186_2 in each of the first pad region PA1_2, the second pad region PA2_2, the third pad region PA3_2, the fourth pad region PA4_2, and the fifth pad region PA5_2) may be located at different heights. That is, the height of the pad electrode located in the second pad region PA2_2 may be higher than the height of the pad electrode located in the first pad region PA1_2, the height of the pad electrode located in the third pad region PA3_2 may be higher than the height of the pad electrode located in the second pad region PA2_2, the height of the pad electrode located in the fourth pad region PA4_2 may be higher than the height of the pad electrode located in the third pad region PA3_2, and the height of the pad electrode located in the fifth pad region PA5_2 may be higher than the height of the pad electrode located in the fourth pad region PA4_2.

[0201] In each of the first pad region PA1_2, the third pad region PA3_2, and the fifth pad region PA5_2, the gate electrode electrically connected to the pad electrode through the contact electrode 186_2 may be connected to the cell array region 102 located at the second side of the connection region 104, and in each of the second pad region PA2_2 and the fourth pad region PA4_2, the gate electrode electrically connected to the pad electrode through the contact electrode 186_2 may be connected to the cell array region 102 located at the first side of the connection region 104. However, the number and arrangement of the pad regions PA_2 and the shape of the gate electrode located in the dummy region DMR are not limited thereto, and various changes may be made as long as the pad electrode is sequentially exposed in each of the above-mentioned pad regions PA_2 and has a shape or contour connected to each of the contact electrodes 186.

[0202] In the present exemplary embodiment, the sub-support structure 162_2 for maintaining its original shape without being deformed due to stress or external force applied to the gate stack structure 120 may be arranged in the cell contact region CCA and the dummy region DMR. The sub-support structures 162_2 are spaced apart from each other in the first direction X and the second direction Y, and may be arranged in an island shape in a plan view. However, the position, shape, and arrangement of the sub-support structure 162_2 are not limited thereto, and various changes may be made. For example, as shown in reference Figure 6 As described above, the sub-support structure 162_2 located in the dummy region DMR can be omitted. Figure 6 Similar to the illustrated example embodiment, the sub-support structure 162_2 located in the dummy region DMR is omitted, and the second portion 164b_2 of the main support structure 164_2 may be further extended along the first direction X to be located in the dummy region DMR.

[0203] Figure 8 A partial cross-sectional view schematically illustrating a semiconductor device according to another example embodiment is shown.

[0204] Figure 8 The semiconductor device according to the example embodiment shown may have a chip-to-chip (C2C) structure bonded by a wafer bonding method. That is, after manufacturing a lower chip including a circuit region 200a located on a first substrate 210 and manufacturing an upper chip including a cell region 100a located on a second substrate 110a, a semiconductor device 10_3 may be manufactured by bonding them together.

[0205] The circuit region 200 a may have a first bonding structure 238 on a surface facing the cell region 100 a on the first substrate 210 , the circuit element 220 , and the first wiring portion 230 .

[0206] The cell region 100 a may include a second bonding structure 194 on a surface facing the circuit region 200 a on the second substrate 110 , the gate stack structure 120 , the channel structure CH, and the second wiring portion 180 .

[0207] The second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor substrate having a semiconductor layer formed thereon on a base substrate. For example, the second substrate 110a may be formed of single crystal or polycrystalline silicon, germanium, silicon-germanium, silicon on insulator, or germanium on insulator.

[0208] In the gate stack structure 120 , the gate electrode 130 may include a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U sequentially located on the second substrate 110 a from the second substrate 110 a toward the circuit region 200 a .

[0209] That is, Figure 8 As shown, the gate stack structure 120 can be sequentially stacked on the lower portion of the second substrate 110a in the figure, so Figure 2 The gate stack structure 120 shown may be arranged in a vertically inverted manner.

[0210] Therefore, the channel pad 144 and the second wiring portion 180 located on the gate stack structure 120 can be arranged adjacent to the circuit region 200a. In addition, the second bonding structure 194 electrically connected to the second wiring portion 180 can be provided on the surface facing the circuit region 200a. The area other than the second bonding structure 194 can be covered by the insulating layer 196. Therefore, in the cell region 100a, the second wiring portion 180 and the second bonding structure 194 can be arranged to face the circuit region 200a.

[0211] For example, the second bonding structure 194 of the cell region 100a and the first bonding structure 238 of the circuit region 200a may be made of aluminum, copper, tungsten, or alloys thereof. For example, since the first bonding structure 238 and the second bonding structure 194 include copper, the cell region 100a and the circuit region 200a may be bonded by copper-to-copper bonding (direct contact and bonding).

[0212] exist Figure 8 The above reference can be used as is. Figures 2 to 5A The gate stack structure 120 and the channel structure CH are described in detail. Figure 8 The gate stack structure 120 is shown to be formed as a single gate stack structure, but may include a plurality of gate stack structures.

[0213] exist Figure 8 , the channel structure CH and the horizontal conductive layers 112 and 114 and / or the second substrate 110a are shown. Figure 1 However, the present disclosure is not limited thereto, and the electrical connection structure between the channel structure CH and the horizontal conductive layers 112 and 114 and / or the second substrate 110a may be variously modified.

[0214] The semiconductor device 10_3 according to the present example embodiment may include an input / output pad (not shown) and an input / output connection wiring (not shown) electrically connected thereto. The input / output connection wiring may be electrically connected to a portion of the second bonding structure 194. The input / output pad may be located, for example, on an insulating layer 198b covering the outer surface of the second substrate 110a. According to some example embodiments, a separate input / output pad electrically connected to the circuit region 200a may be provided.

[0215] For example, the circuit region 200a and the unit region 100a may be Fig.25 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 are shown as corresponding parts. Alternatively, the circuit region 200a and the unit region 100a may include Fig.28 The semiconductor chip 2200 a is shown including the first structure 4400 and the second structure 4200 .

[0216] In the following, reference will be made to Figures 9 to 25 A method of manufacturing a semiconductor device according to example embodiments is described.

[0217] Figures 9 to 25 Process cross-sectional views, top plan views, and perspective views sequentially illustrating a method of fabricating a semiconductor device according to example embodiments are illustrated.

[0218] Fig. 9 , Fig.11 , FIG. 14A to FIG. 14D , Fig.16 , FIG. 19A to FIG. 19D , Fig.21 and Fig.23 A top plan view for describing a method of manufacturing a semiconductor device according to example embodiments is shown. Fig.15 Shows Fig.14D A local enlarged view of area R3. Fig. 20 Shows Fig.16 A local enlarged view of area R4.

[0219] Fig.13 and Fig.18 A partial perspective view for describing a method of manufacturing a semiconductor device according to example embodiments is shown.

[0220] Fig.10 , Fig.12 , Fig.17 , Fig. 22 and Fig.24 A cross-sectional view corresponding to a top plan view for describing a method of manufacturing a semiconductor device according to example embodiments is shown.

[0221] For convenience, Figures 9 to 24 The connection region 104 and the cell region 100 located in the connection region 104 are partially shown, and illustration of the cell array region 102 and the cell region 100 located in the cell array region 102 is omitted. Hereinafter, a method of manufacturing the cell region 100 located in the connection region 104 of a semiconductor device according to example embodiments will be mainly described.

[0222] First, refer to Fig. 9 and Fig.10 , a stacked structure 120P may be formed by alternately stacking interlayer insulating layers 132L and sacrificial insulating layers 130P on a first surface (eg, a front surface or an upper surface) of a second substrate (not shown) located in a connection region 104 of the semiconductor device 10 according to example embodiments.

[0223] The sacrificial insulating layer 130P may include a material different from that of the interlayer insulating layer 132L. For example, the interlayer insulating layer 132L may include silicon oxide, silicon nitride, silicon nitride, and a low dielectric constant material, and the sacrificial insulating layer 130P includes at least one of silicon, silicon oxide, silicon carbide, or silicon nitride, but may be made of a material different from that of the interlayer insulating layer 132L.

[0224] For example, the interlayer insulating layer 132L may include silicon oxide, and the sacrificial insulating layer 130P may include silicon nitride. In a subsequent process, the sacrificial insulating layer 130P may be replaced with the gate electrode 130 (see Figure 2 That is, the sacrificial insulating layer 130P may be formed to be parallel to the gate electrode 130 to be formed (see Figure 2 ) part.

[0225] The stack structure 120P located in the connection region 104 of the semiconductor device 10 according to example embodiments may include a pad contact area PCA located approximately at the center, and dummy regions DMR1 and DMR2 located at first and second sides in the first direction X of the pad contact area PCA.

[0226] Then, if Fig. 9 and Fig.10 As shown, the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H, and the contact electrode hole 186H may be formed together in the stack structure 120P.

[0227] The stacked structure 120P may extend through the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H, and the contact electrode hole 186H. For example, the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H, and the contact electrode hole 186H may have an inclined side surface, each of which has a width that decreases from the upper surface to the lower surface of the stacked structure 120P in a cross-sectional view due to its high aspect ratio. However, the cross-sectional shapes of the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H, and the contact electrode hole 186H are not limited thereto, and their side surfaces may be perpendicular to the second substrate (not shown).

[0228] In a plan view, the separation structure holes WLCH may be formed at the edge of the stack structure 120P located in the connection region 104. The separation structure holes WLCH are spaced apart in the second direction Y and may have a line shape in a plan view.

[0229] In a plan view, the sub-support structure holes 162H may be formed in the dummy regions DMR1 and DMR2 of the connection region 104. The sub-support structure holes 162H may be spaced apart from the dummy regions DMR1 and DMR2 in the first direction X and the second direction Y, and may be arranged side by side in an island shape along the second direction Y in a plan view.

[0230] In a plan view, the main support structure holes 164H may be formed in the pad contact area PCA of the connection area 104. The number of the main support structure holes 164H may be greater than the number of the separation structure holes WLCH and the number of the sub-support structure holes 162H. The main support structure holes 164H may be arranged in the pad contact area PCA along the first direction X and the second direction Y, and may have a line shape in a plan view.

[0231] In a plan view, the contact electrode hole 186H may be formed in the pad contact area PCA of the connection area 104. In a plan view, at least a portion of the contact electrode hole 186H may be surrounded by the main support structure hole 164H. The contact electrode hole 186H may be arranged parallel to the separation structure hole WLCH, the sub-support structure hole 162H, and the main support structure hole 164H along the first direction X in a plan view.

[0232] exist Fig. 9 In the figure, the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H and the contact electrode hole 186H have a circular shape in the plan view, and the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H and the contact electrode hole 186H are all shown to have substantially the same diameter, but the present disclosure is not limited thereto, and in the plan view, the shapes and diameters of the separation structure hole WLCH, the sub-support structure hole 162H, the main support structure hole 164H and the contact electrode hole 186H may be variously changed.

[0233] In addition, the number, arrangement, and positional relationship of each of the separation structure holes WLCH, the sub-support structure holes 162H, the main support structure holes 164H, and the contact electrode holes 186H are not limited thereto, and various changes may be made.

[0234] Then, refer to Figures 11 to 15 , first, a process of enlarging the separation structure hole WLCH and the main support structure hole 164H may be performed.

[0235] Therefore, the separation structure holes WLCH arranged side by side in the second direction Y may be integrally connected to each other. That is, the separation structure hole WLCH may have a line shape extending in the second direction Y in a plan view.

[0236] In addition, the main support structure holes 164H spaced apart in the first direction X and the second direction Y may be integrally connected to each other. That is, similar to the separation structure hole WLCH, the main support structure hole 164H may have a line shape extending in the first direction X and the second direction Y.

[0237] Then, the sacrificial layers 166P and 168P may be filled in the separation structure hole WLCH and the contact electrode hole 186H, respectively, and the sub-support structure 162 and the main support structure 164 may be formed by filling the sub-support structure hole 162H and the main support structure hole 164H with an insulating material.

[0238] The sacrificial layers 166P and 168P respectively filled in the separation structure hole WLCH and the contact electrode hole 186H may include a material different from the insulating material filled in each of the sub-support structure hole 162H and the main support structure hole 164H. For example, the sacrificial layers 166P and 168P respectively filled in the separation structure hole WLCH and the contact electrode hole 186H may be made of polysilicon. However, the sacrificial layers 166P and 168P respectively filled in the separation structure hole WLCH and the contact electrode hole 186H are not limited thereto, and various changes may be made.

[0239] The sacrificial layers 166P and 168P respectively filled in the separation structure hole WLCH and the contact electrode hole 186H may include, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the insulating material filled in each of the sub-support structure hole 162H and the main support structure hole 164H is not limited thereto, and various changes may be made.

[0240] When the insulating material is filled in the main support structure hole 164H, the main support structure 164 may include: a first portion 164a extending in the second direction Y in the pad contact area PCA; and a second portion 164b extending from the first portion 164a toward a first direction X intersecting the second direction Y. That is, the second portion 164b of the main support structure 164 may extend from the first portion 164a toward a first side and a second side of the first direction X in a plan view.

[0241] In addition, when the insulating material is filled in the sub-support structure hole 162H, the sub-support structure 162 may be formed.

[0242] Subsequently, after forming a mask layer on the pad contact area PCA of the stacked structure 120P and the separation structure hole WLCH located at the edge of the stacked structure 120P, a mask pattern ML may be formed by patterning the mask layer. According to an example embodiment, the mask pattern ML located on the pad contact area PCA may expose a portion of the second portion 164b of the main support structure 164 in a plan view. That is, the mask pattern ML may expose the end portions of the second portion 164b of the main support structure 164 located at the first side and the second side in the first direction X. This is to ensure a margin for misalignment by exposing a portion of the second portion 164b of the main support structure 164 in a plan view to prevent defects due to misalignment that may occur in a patterning process using the mask pattern ML.

[0243] Then, if Fig.12 and Fig.13 As shown, the stack structure 120P located in the dummy regions DMR1 and DMR2 may be patterned to have a step shape using the mask pattern ML.

[0244] Will refer to it later Fig.13 as well as FIG. 14A to FIG. 14D A detailed description of the stepped shape of the stack structure 120P located in the dummy regions DMR1 and DMR2 is described.

[0245] In the step of patterning the stack structure 120P located in the dummy regions DMR1 and DMR2 to have a step shape, since each of the sub-support structure 162 exposed by the mask pattern ML and the main support structure 164 partially exposed by the mask pattern ML includes a material different from that of the stack structure 120P exposed by the mask pattern ML,

[0246] Therefore, differences in etching extent may occur during the patterning step.

[0247] For example, in the step of partially patterning the main support structure 164 and the stacked structure 120P exposed by the mask pattern ML so that the stacked structure 120P located in the dummy regions DMR1 and DMR2 has a step shape, the insulating material filling the sub-support structure holes 162H and the main support structure holes 164H can be etched more toward the third direction Z which is the thickness direction compared to the stacked structure 120P.

[0248] Therefore, each of the upper surfaces of the sub-support structure 162 and the main support structure 164 located on each layer of the stepped stacking structure 120P and extending through the stepped stacking structure 120P can be located at a height lower than the height of the upper surface of the sacrificial insulating layer 130P located on each layer of the stepped stacking structure 120P.

[0249] Therefore, the manufacturing method of the semiconductor device 10 according to the example embodiment may include the following process steps: additionally filling the sub-support structure hole 162H and the main support structure hole 164H with insulating material, so that each of the upper surfaces of the sub-support structure hole 162H and the main support structure hole 164H can be located at substantially the same height as the upper surface of the sacrificial insulating layer 130P located on each layer of the stepped stacking structure 120P.

[0250] In addition, in some example embodiments, since the insulating material filling the sub-support structure holes 162H and the main support structure holes 164H to be described later is etched more in the third direction Z which is the thickness direction compared to the stacked structure 120P, in the step of forming the intermediate insulating layer 132M to be described later, the empty space formed in the upper area of ​​each of the sub-support structure holes 162H and the main support structure holes 164H can be filled with the intermediate insulating layer 132M.

[0251] The mask pattern ML may not pattern the stack structure 120P located in the pad contact area PCA and the stack structure 120P surrounding the separation structure WLC. Therefore, the thickness of the stack structure 120P located in the pad contact area PCA and the stack structure 120P surrounding the separation structure WLC may be thicker than the thickness of the gate stack structure 120 located in the dummy regions DMR1 and DMR2.

[0252] That is, upper surfaces of the stack structure 120P located in the pad contact area PCA and the stack structure 120P surrounding the separation structure WLC may be located in the dummy regions DMR1 and DMR2 and may be located at a height higher than that of the upper surface of the stepped stack structure 120P.

[0253] In the stack structure 120P located in the pad contact area (PCA), a plurality of pad areas PA may be formed by process steps to be described later, wherein the pad electrodes PD (see Figure 2 ) is connected to the gate electrode 130 extending from the dummy regions DMR1 and DMR2 to the pad contact area PCA (see Figure 2 ). In a plan view, the stack structure 120P formed with the pad area PA may be surrounded by the main support structure 164.

[0254] For example, the pad area PA may include: a first pad area PA1, a third pad area PA3, a fifth pad area PA5, a seventh pad area PA7 and a ninth pad area PA9, which are located at a first side of the main support structure 164 in the first direction X and are arranged sequentially in a direction from far to near relative to the unit array area 102; and a second pad area PA2, a fourth pad area PA4, a sixth pad area PA6, an eighth pad area PA8 and a tenth pad area PA10, which are located at a second side of the main support structure 164 in the first direction X and are arranged sequentially in a direction from far to near relative to the unit array area 102.

[0255] That is, each of the first pad area PA1 and the second pad area PA2, the third pad area PA3 and the fourth pad area PA4, the fifth pad area PA5 and the sixth pad area PA6, the seventh pad area PA7 and the eighth pad area PA8, the ninth pad area PA9 and the tenth pad area PA10 can face each other in the first direction X, and the first part 164a of the main support structure 164 is interposed therebetween.

[0256] Then, refer to Figures 13 to 14D , a step shape formed in the stack structure 120P located in the dummy regions DMR1 and DMR2 will be described.

[0257] Fig.13 A partial perspective view showing a partial region of a stack structure 120P located in a connection region 104 is illustrated to describe a method of manufacturing a semiconductor device according to example embodiments. FIG. 14A to FIG. 14D Shown are shown separately Fig.13 A partial top plan view of some of the layers of the stacked structure 120P is shown.

[0258] like Figures 13 to 14D As shown, as described above, the stacked structure 120P located in the dummy regions DMR1 and DMR2 of the connection region 104 can be formed by using the mask pattern ML (see Fig.11 ) is patterned to have a step shape.

[0259] Specifically, refer to Figures 13 to 14D The stack structure 120P located at the connection region 104 may include a first sacrificial insulating layer 130P1 , a second sacrificial insulating layer 130P2 , a third sacrificial insulating layer 130P3 , and a fourth sacrificial insulating layer 130P4 that are sequentially stacked.

[0260] When the stack structure 120P is patterned to form a step shape in the stack structure 120P located in the dummy regions DMR1 and DMR2, as shown in FIG. FIG. 14A to FIG. 14D As shown, the first sacrificial insulating layer 130P1 , the second sacrificial insulating layer 130P2 , the third sacrificial insulating layer 130P3 , and the fourth sacrificial insulating layer 130P4 included in the stack structure 120P may be patterned to have different areas and planar shapes in a plan view.

[0261] For example, the first sacrificial insulating layer 130P1 may be located in both the dummy regions DMR1 and DMR2 and the pad contact area PCA.

[0262] The second sacrificial insulating layer 130P2 may be located in the dummy regions DMR1 and DMR2 and the pad contact area PCA, and may have an area smaller than that of the first sacrificial insulating layer 130P1 in the first dummy region DMR1. That is, the length of the second sacrificial insulating layer 130P2 in the first dummy region DMR1 along the second direction Y may be shorter than the length of the first sacrificial insulating layer 130P1 in the first dummy region DMR1 along the second direction Y.

[0263] The third sacrificial insulating layer 130P3 may be located in the dummy regions DMR1 and DMR2 and the pad contact area PCA, and may have an area smaller than that of the second sacrificial insulating layer 130P2 in the second dummy region DMR2. That is, the third sacrificial insulating layer 130P3 may have substantially the same area as the second sacrificial insulating layer 130P2 in the first dummy region DMR1, and the length of the third sacrificial insulating layer 130P3 in the second dummy region DMR2 along the second direction Y may be shorter than the length of the second sacrificial insulating layer 130P2 in the second dummy region DMR2 along the second direction Y.

[0264] The fourth sacrificial insulating layer 130P4 may be located in the dummy region DMR2 and the pad contact area PCA, and may have an area smaller than that of the first sacrificial insulating layer 130P3. That is, the fourth sacrificial insulating layer 130P4 may not be located in the first dummy region DMR1, and may have substantially the same area as the third sacrificial insulating layer 130P3 in the second dummy region DMR2.

[0265] Each of the first, second, third, and fourth sacrificial insulating layers 130P1, 130P2, 130P3, and 130P4 may extend from the dummy regions DMR1 and DMR2 to the pad contact area PCA and may be connected to the pad areas PA1, PA2, PA3, and PA4 located at different layers.

[0266] Therefore, when the first sacrificial insulating layer 130P1, the second sacrificial insulating layer 130P2, the third sacrificial insulating layer 130P3 and the fourth sacrificial insulating layer 130P4 having different areas are sequentially stacked by patterning the stack structure 120P, the stack structure 120P located in the dummy regions DMR1 and DMR2 has a step shape, and the stepped upper surfaces of the stack structure 120P located in the first dummy region DMR1 and the second dummy region DMR2 can be located at different heights.

[0267] The sacrificial insulating layer 130P extending from the first dummy region DMR1 to the second dummy region DMR2 may be disconnected by the main support structure 164 located in the pad contact area PCA.

[0268] Apart from Fig.12 and Fig.13 In addition, refer to Fig.15 In the process step of patterning the stacked structure 120P located in the dummy regions DMR1 and DMR2 to form a step shape, the sacrificial layer 166P filling the separation structure hole WLCH may be surrounded by the stacked structure 120P. In addition, the side surface of the sacrificial layer 166P filling the separation structure hole WLCH may be surrounded by the stacked structure 120P in a cross-sectional view and may directly contact the stacked structure 120P.

[0269] Fig.18 A partial perspective view showing a partial region of the gate stack structure 120 located in the connection region 104 is illustrated to describe a method of manufacturing a semiconductor device according to example embodiments. FIG. 19A to FIG. 19D Shown are shown separately Fig.18 A partial top plan view of some layers of the gate stack structure 120 is shown.

[0270] Then, refer to Figures 16 to 20 After forming the intermediate insulating layer 132M in the dummy regions DMR1 and DMR2, a process step of replacing the sacrificial insulating layer 130P of the stacked structure 120P with the gate electrode 130 may be performed.

[0271] Thus, a gate stack structure 120 in which the gate electrode 130 and the interlayer insulating layer 132L are cross-stacked may be formed. In addition, a portion of the side surface of the sacrificial layer 168P filling the contact electrode hole 186H may be surrounded by the gate stack structure 120, and the remaining portion of the side surface may be surrounded by the stack structure 120P. That is, a portion of the sacrificial insulating layer 130P of the stack structure 120P may not be replaced by the gate electrode 130. This is because: FIG. 14A to FIG. 14D As shown, the stack structure 120P surrounding the separation structure hole WLCH is spaced apart from the stack structure 120P located in the pad contact area PCA.

[0272] Specifically, the intermediate insulating layer 132M may be formed in the dummy regions DMR1 and DMR2 to planarize the stepped steps in the dummy regions DMR1 and DMR2. The intermediate insulating layer 132M may include the same material as that of the above-described cell insulating layer 132.

[0273] Subsequently, after removing the sacrificial layer 166P filled in the separation structure hole WLCH, the sacrificial insulating layer 130P located on the stacked structure 120P may be removed through the separation structure hole WLCH, and the gate electrode 130 may be formed in the space where the sacrificial insulating layer 130P is removed. That is, after removing the sacrificial insulating layer 130P using an etching process, a metal material such as tungsten (W), copper (Cu), or aluminum (Al) may be deposited to form the gate electrode 130.

[0274] Further references FIG. 19A to FIG. 19D as well as FIG. 14A to FIG. 14D , a portion of the first sacrificial insulating layer 130P1 , the second sacrificial insulating layer 130P2 , the third sacrificial insulating layer 130P3 , and the fourth sacrificial insulating layer 130P4 may be replaced with the first gate electrode 130_1 , the second gate electrode 130_2 , the third gate electrode 130_3 , and the fourth gate electrode 130_4 .

[0275] Specifically, the first sacrificial insulating layer 130P1 may be replaced with the first gate electrode 130_1 in the dummy regions DMR1 and DMR2 and the pad contact area PCA. Thus, the first gate electrode 130_1 extending from the first dummy region DMR1 and located in the first pad area PA1 becomes the pad electrode PD.

[0276] The second sacrificial insulating layer 130P2 may be replaced with the second gate electrode 130_2 except for a portion of the second sacrificial insulating layer 130P2 overlapping the dummy regions DMR1 and DMR2 and the first pad region PA1 in the pad contact region PCA. Therefore, the second gate electrode 130_2 extending from the second dummy region DMR2 and located in the second pad region PA2 becomes the pad electrode PD.

[0277] The third sacrificial insulating layer 130P3 may be replaced with the third gate electrode 130_3 except for a portion of the third sacrificial insulating layer 130P3 overlapping the dummy regions DMR1 and DMR22 and the first and second pad regions PA1 and PA in the pad contact region PCA. Therefore, the third gate electrode 130_3 extending from the first dummy region DMR1 and located in the third pad region PA3 becomes the pad electrode PD.

[0278] Except for the portion of the fourth sacrificial insulating layer 130P4 overlapping with the first pad area PA1, the second pad area PA2, and the third pad area PA3 in the second dummy area DMR2 and the pad contact area PCA, the fourth sacrificial insulating layer 130P4 may be replaced with the fourth gate electrode 130_4. Therefore, the fourth gate electrode 130_4 extending from the second dummy area DMR2 and located in the fourth pad area PA4 becomes the pad electrode PD.

[0279] In addition, the sacrificial insulating layers 130P1 , 130P2 , 130P3 , and 130P4 surrounding the separation structure hole WLCH may be replaced with the first, second, third, and fourth gate electrodes 130_1 , 130_2 , 130_3 , and 130_4 .

[0280] The reason why a portion of the second sacrificial insulating layer 130P2, the third sacrificial insulating layer 130P3 and the fourth sacrificial insulating layer 130P4 located in the pad contact area PCA is retained without being replaced by the gate electrode 130 is that each of the second sacrificial insulating layer 130P2, the third sacrificial insulating layer 130P3 and the fourth sacrificial insulating layer 130P4 located in the pad contact area PCA and each of the second sacrificial insulating layer 130P2, the third sacrificial insulating layer 130P3 and the fourth sacrificial insulating layer 130P4 surrounding the separation structure WLC are disconnected by the main support structure 164 and the space.

[0281] As described above, when the first gate electrode 130_1, the second gate electrode 130_2, the third gate electrode 130_3 and the fourth gate electrode 130_4 having different areas and shapes are sequentially stacked in a plan view, the gate electrode 130 located in the dummy regions DMR1 and DMR2 has a step shape and extends from the dummy regions DMR1 and DMR2 to the pad area PA, so that the pad electrode PD connected to the gate electrode 130 can be located at different heights.

[0282] In addition, as described above, the stacked structure 120P located on the pad electrode PD may have different heights because some of the sacrificial insulating layer 130P located in the pad contact area PCA remains without being replaced by the gate electrode 130. Therefore, the stacked structure 120P remaining on the pad electrode PD in the pad contact area PCA may be etched in a process step to be described later.

[0283] Subsequently, in addition to Fig.15 In addition, refer to Fig.17 , Fig.18 and Fig. 20 , the separation structure WLC can be formed by filling the separation structure hole WLCH with various insulating materials. For example, the separation structure WLC may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the material included in the structure WLC is not limited thereto, and various changes may be made.

[0284] Since the sacrificial insulating layer 130P is replaced by the gate electrode 130, the separation structure WLC may be surrounded by the gate stack structure 120 in the plan view and the cross-sectional view. The separation structure WLC may be spaced apart from the intermediate insulating layer 132M, with the gate stack structure 120 disposed therebetween. In addition, the upper surface of the separation structure WLC may be located at substantially the same height as the upper surface of the gate electrode 130. However, the present disclosure is not limited thereto, and the arrangement relationship between the separation structure WLC and the gate stack structure 120 may be variously changed.

[0285] Then, refer to Fig.21 and Fig. 22 After removing the sacrificial layer 168P filled in the contact electrode hole 186H, a process of etching a portion of the gate electrode 130 located below the stacked structure 120P may be performed. In the process of etching the portion of the gate electrode 130, since the etching process is performed using an etching material having a high etching selectivity with respect to the gate electrode 130, the interlayer insulating layer 132L may remain without being etched.

[0286] Thus, a portion of the gate electrode 130 is etched toward the first and second sides in the first direction X, and an empty space may be formed in a region where a portion of the gate electrode 130 is etched.

[0287] Subsequently, an insulating pattern 186i may be formed in the empty space formed by etching a portion of the gate electrode 130. The process of forming the insulating pattern 186i may include a process step of wet-etching the insulating pattern material layer located in a region other than the insulating pattern material layer filling the empty space formed by partially etching the gate electrode 130 after filling the contact electrode hole 186H with the insulating pattern material layer. However, the method for forming the insulating pattern 186i is not limited thereto, and various changes may be made.

[0288] Then, refer to Fig.23 and Fig.24 , after selectively etching the sacrificial insulating layer 130P included in the stack structure 120P remaining on the pad electrode PD, the interlayer insulating layer 132L of the stack structure 120P remaining on the pad electrode PD may be removed.

[0289] In the process step of removing the interlayer insulating layer 132L of the stack structure 120P remaining on the pad electrode PD, a portion of the insulating pattern 186i may be etched together so that the length of the insulating pattern 186i in the first direction X may be reduced.

[0290] Therefore, a portion of the contact electrode hole 186H may extend through a portion of the gate stack structure 120, and the remaining portion may be located on the pad electrode PD, and the upper surface of the pad electrode PD may be exposed. However, a portion of the sacrificial insulating layer 130P and a portion of the interlayer insulating layer 132L may be retained in the process steps according to some example embodiments. That is, a portion of the sacrificial insulating layer 130P and a portion of the interlayer insulating layer 132L may be retained, and the upper surface of the pad electrode PD may be exposed.

[0291] In addition, the width of the contact electrode hole 186H of the gate stack structure 120 may be smaller than the width of the contact electrode hole 186H located on the pad electrode PD. That is, the contact electrode hole 186H may include portions having different widths.

[0292] Subsequently, a conductive material may be filled in the contact electrode hole 186H to form a contact electrode 186 connected to the upper surface of the pad electrode PD. The contact electrode 186 may include a conductive material. For example, the contact electrode 186 may include tungsten (W), copper (Cu), or aluminum (Al). However, the material included in the contact electrode 186 is not limited thereto, and various changes may be made.

[0293] As described above, since the contact electrode hole 186H includes portions having different widths, the contact electrode 186 may include portions having different widths in a cross-sectional view in a process step of forming the contact electrode 186 in the contact electrode hole 186H.

[0294] That is, the contact electrode 186 may include: a first contact portion 186a extending through the gate stack structure 120; and a second contact portion 186b located on the first contact portion 186a and connected to the upper surface of the pad electrode PD. The width of the first contact portion 186a of the contact electrode 186 may be smaller than the width of the second contact portion 186b.

[0295] The second contact portion 186 b of the contact electrode 186 may completely cover the first contact portion 186 a in a plan view and may directly contact the side surface of the main support structure 164 , and at least a portion of the side surface of the second contact portion 186 b may be surrounded by the main support structure 164 .

[0296] The first contact portion 186a of the contact electrode 186 may be insulated from the gate electrode 130 located under the pad electrode PD by the insulating pattern 186i. In addition, as described above, since the pad electrodes PD located in the pad area PA are located at different heights, each of the pad electrodes PD located in the pad area PA may be connected to the contact electrode 186 at a different height. Since the pad electrodes PD are located at different heights, the lengths of the second contact portions 186b of the contact electrode 186 connected to the respective pad electrodes PD may be different along the third direction Z.

[0297] According to the manufacturing method of the semiconductor device 10 of the example embodiment, if an etching process is performed on the stack structure 120P located in the pad contact area PCA to form the contact electrode hole 186H, each area of ​​the stack structure 120P where the contact electrode hole 186H is formed can be formed to include substantially the same layers and can have the same stack thickness.

[0298] Therefore, when the etching process for forming the contact electrode hole 186H is performed in substantially the same environment, each region of the stacked structure 120P where the contact electrode hole 186H is formed can reduce the occurrence of defects due to differences in process conditions, which may occur in some regions of the stacked structure 120P depending on the process conditions (for example, the type of stacked layer or the thickness of the stacked layer).

[0299] Therefore, the reliability of the semiconductor device can be improved, and the productivity of the semiconductor device can be improved.

[0300] Next, we will refer to Fig.25 An electronic system including a semiconductor device according to example embodiments is described.

[0301] Fig.25 An electronic system including a semiconductor device according to example embodiments is schematically illustrated.

[0302] like Fig.25 As shown, an electronic system 1000 according to an example embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0303] The semiconductor device 1100 may be a nonvolatile memory device, and may be, for example, a reference Figures 1 to 8The NAND flash memory device described herein. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be arranged adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0304] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT located between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to another example embodiment, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously changed.

[0305] In some example embodiments, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first lower gate line LL1 and the second lower gate line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0306] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection wiring 1125 extending in the first structure 1100F to the second structure 1100S.

[0307] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one memory cell transistor selected from the memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0308] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to another example embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the semiconductor devices 1100.

[0309] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be sent through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0310] Fig.26 A schematic perspective view illustrating an electronic system including a semiconductor device according to example embodiments is shown.

[0311] like Fig.26 As shown, the electronic system 2000 according to the example embodiment includes a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 located on the main substrate 2001.

[0312] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host according to any of the following interfaces: for example, a universal serial bus (USB), a peripheral component interconnect express (PCI express), a serial advanced technology attachment (SATA), M-Phy for universal flash memory (UFS), etc.

[0313] In some example embodiments, the electronic system 2000 may operate using power supplied from an external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes power provided from the external host to the controller 2002 and the semiconductor package 2003.

[0314] The controller 2002 may record data in the semiconductor package 2003 or may read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0315] The DRAM 2004 may be a buffer memory for buffering a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may also be used as a buffer memory, and may also provide a space for temporarily storing data under the control operation of the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0316] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may be semiconductor packages each including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chips 2200 on the package substrate 2100 and the connection structure 2400.

[0317] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.25 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chip 2200 may include a reference Figures 1 to 8 A semiconductor device is described.

[0318] In some example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the on-package pad 2130. Therefore, the semiconductor chips 2200 may be electrically connected to each other by using a bonding wire method, and may be electrically connected to the on-package pad 2130 of the package substrate 2100 in each of the first semiconductor package 2003a and the second semiconductor package 2003b. According to example embodiments, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) in each of the first semiconductor package 2003a and the second semiconductor package 2003b instead of the bonding wire connection structure 2400.

[0319] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring located on the interposer substrate.

[0320] Fig. 27 and Fig.28 Schematic cross-sectional views illustrating semiconductor packages according to example embodiments are respectively shown. Fig. 27 and Fig.28 They are shown respectively Fig.26 An example embodiment of a semiconductor package 2003 and conceptually illustrates Fig.26 An area of ​​the semiconductor package 2003 taken along line II'.

[0321] refer to Fig. 27 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a package upper pad 2130 located on the upper surface of the package substrate body 2120, a lower pad 2125 located on the surface of the package substrate body 2120, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. Fig.23As shown, the lower pad 2125 may be connected to the wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 through the conductive connector 2800 .

[0322] The semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include: a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation structure 3230 passing through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL (see FIG. 1 ) connected to the gate stack structure 3210. Fig.25 ) is electrically connected to the gate connection wiring.

[0323] In the semiconductor chip 2200 or the semiconductor device according to the example embodiment, when the etching process is performed in substantially the same environment, each region of the stacked structure where the contact electrode 186 is formed can prevent the occurrence of defects due to differences in etching conditions, which may occur in some regions of the stacked structure depending on process conditions (e.g., the type of the stacked layer or the thickness of the stacked layer). Therefore, the reliability of the semiconductor device and the productivity of the semiconductor device can be improved by improving the electrical characteristics of the contact electrode 186 connected to each pad electrode PD provided in the pad area PA.

[0324] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may extend through the gate stack structure 3210 and may also be located outside the gate stack structure 3210. Each semiconductor chip 2200 may also include: an input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100; and an input / output pad 2210 electrically connected to the input / output connection wiring 3265 extending into the second structure 3200.

[0325] In an example embodiment, a plurality of semiconductor chips 2200 in a semiconductor package 2003 may be electrically connected to each other through a connection structure 2400 in the form of a bonding wire. As another example, a plurality of semiconductor chips 2200 or portions constituting the semiconductor chip 2200 may be electrically connected through a connection structure including a through silicon via (TSV).

[0326] refer to Fig.28In the semiconductor package 2003A, each semiconductor chip 2200 may include a semiconductor substrate 4010 , a first structure 4100 on the semiconductor substrate 4010 , and a second structure 4200 bonded to the first structure 4100 by wafer bonding on the first structure 4100 .

[0327] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 extending through the gate stack structure 4210, and a word line WL (see FIG. 4 ) connected to each of the channel structure 4220 and the gate stack structure 4210. Fig.25 , the same below) is electrically connected to the second bonding structure 4250. For example, the second bonding structure 4250 may be electrically connected to the channel structure 4220 and the word line WL through the bit line 4240 electrically connected to the channel structure 4220 and the gate connection wiring electrically connected to the word line WL, respectively.

[0328] The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be bonded while in contact with each other. Bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be formed of, for example, copper (Cu).

[0329] In the semiconductor chip 2200 or the semiconductor device according to the example embodiment, when the etching process is performed in substantially the same environment, each region of the stacked structure where the contact electrode 186 is formed can prevent the occurrence of defects due to differences in etching conditions, which may occur in some regions of the stacked structure depending on process conditions (e.g., the type of the stacked layer or the thickness of the stacked layer). Therefore, the reliability of the semiconductor device and the productivity of the semiconductor device can be improved by improving the electrical characteristics of the contact electrode 186 connected to each pad electrode PD provided in the pad area PA.

[0330] Each of the semiconductor chips 2200 may further include an input / output pad 2210 and an input / output connection wiring 4265 located below the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0331] In an example embodiment, a plurality of semiconductor chips 2200 in a semiconductor package 2003 may be electrically connected to each other through a connection structure 2400 in the form of a bonding wire. As another example, a plurality of semiconductor chips 2200 or portions constituting the semiconductor chip 2200 may be electrically connected through a connection structure including a through silicon via (TSV).

[0332] Throughout the specification and claims, when a component is “connected” to another component, it includes not only the case where the components are “directly connected” but also the case where the components are “indirectly connected” via another component therebetween.

[0333] Any functional blocks shown in the figures and described above may be implemented in a processing circuit (e.g., hardware including logic circuits, a hardware / software combination such as a processor that executes software, or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0334] When any of the terms "about" or "substantially" is used in conjunction with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operating tolerances (e.g., ±10%) around the numerical value. In addition, when the words "generally" or "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified by the term "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape. In addition, it should be understood that when elements, functions, shapes, etc. are referred to as the same, they may be substantially the same or similar even if the terms substantially and similar are not used.

[0335] While the present disclosure has been described in connection with what are presently considered to be practical example embodiments, it should be understood that the present disclosure is not limited to the disclosed example embodiments, but on the contrary is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a circuit region configured to include a peripheral circuit structure on the substrate; as well as a cell region adjacent to the circuit region and configured to include a cell array region and a connection region, Wherein, the unit area includes: A gate stack structure configured to include interlayer insulating layers and gate electrodes alternately stacked on the substrate; a channel structure in the cell array region and configured to extend through the gate stack structure; a main support structure in the connection region and configured to extend through the gate stack structure; and a contact electrode in the connection region and connected to the gate electrode through the gate stack structure, and The main supporting structure comprises: A first portion configured to extend along a first direction; and a second portion configured to extend from the first portion in a second direction intersecting the first direction, Wherein, at least a portion of the contact electrode is surrounded by the first portion and the second portion of the main support structure.

2. The semiconductor device according to claim 1, wherein The gate stack structure includes a plurality of gate electrodes separated by the interlayer insulating layer, The gate electrode extends from the cell array region to the connection region, The gate electrodes each include a pad electrode in the connection region configured to be connected to the contact electrode, and The contact electrode is electrically connected to a pad electrode of one of the gate electrodes and is insulated from the remaining gate electrodes, with an insulation pattern interposed between the contact electrode and the remaining gate electrodes.

3. The semiconductor device according to claim 2, further comprising: a separation structure configured to extend from the cell array region to the connection region and to extend through the gate stack structure, Wherein, the connection area includes: a pad contact region, comprising a main support structure, the pad electrode and the contact electrode; and The dummy region is between the pad contact region and the separation structure.

4. The semiconductor device according to claim 3, further comprising: an intermediate insulating layer, configured to cover the gate stack structure in the dummy region, Wherein, the gate stack structure is between the separation structure and the intermediate insulating layer.

5. The semiconductor device according to claim 3, further comprising: a sub-support structure in the dummy region and configured to extend through the gate stack structure, Wherein, the height of the upper surface of the main support structure is higher than the height of the upper surface of the sub-support structure.

6. The semiconductor device according to claim 3, wherein: A plurality of sub-support structures arranged to be spaced apart from each other and having an island shape in a plan view are in the dummy area, and The main supporting structure has a linear shape in plan view.

7. The semiconductor device according to claim 3, wherein: The upper surface of the separation structure is at the same height as the upper surface of the main support structure, An upper surface of the separation structure and an upper surface of the main support structure are at a height higher than an upper surface of the gate stack structure located in the dummy region, and In a cross-sectional view, the gate stack structure in the dummy region has a step shape.

8. The semiconductor device according to claim 2, wherein: The contact electrode comprises: a first contact portion surrounded by the gate stack structure and connected to the peripheral circuit structure; and a second contact portion on the first contact portion and the gate stack structure and connected to an upper surface of the pad electrode, wherein the first contact portion of the contact electrode, the second contact portion of the contact electrode, and the pad electrode are surrounded by the main support structure in a plan view, and An upper surface of the first contact portion of the contact electrode is completely covered by the second contact portion of the contact electrode.

9. The semiconductor device according to claim 1, wherein: The main support structure includes a plurality of second portions spaced apart along the first direction in a plan view, The contact electrode is between the second portions of the main support structure in plan view, and The contact electrode directly contacts the first portion and the second portion of the main support structure.

10. The semiconductor device according to claim 1, wherein At least one of the first portion or the second portion of the main supporting structure has a linear shape in a plan view.

11. The semiconductor device according to claim 10, wherein: The edge of the main supporting structure has a concave-convex shape in a plan view.

12. A semiconductor device comprising: a circuit region configured to include a peripheral circuit structure on the substrate; as well as a cell region adjacent to the circuit region and configured to include a cell array region and a connection region, Wherein, the unit area includes: A gate stack structure configured to include a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure, wherein in the cell array region, the channel structure is configured to extend through the gate stack structure; a support structure extending through the gate stack structure in the connection region; and a contact electrode, wherein in the connection region, the contact electrode is connected to the gate electrode through the gate stack structure, wherein each of the gate electrodes comprises a pad electrode in the connection region, The contact electrode is electrically connected to a pad electrode of one of the gate electrodes and is insulated from the remaining gate electrodes, an insulating pattern is provided between the contact electrode and the remaining gate electrodes, and The contact electrode is at least partially surrounded by the support structure in a plan view, and The contact electrode comprises: a first contact portion, surrounded by the gate stack structure in a cross-sectional view, and connected to the peripheral circuit structure; and A second contact portion is on the first contact portion and on the gate stack structure, and is connected to an upper surface of the pad electrode.

13. The semiconductor device according to claim 12, wherein: A width of the first contact portion is smaller than a width of the second contact portion.

14. The semiconductor device according to claim 13, wherein: The first contact portion is surrounded by the interlayer insulating layer and the insulating pattern, and The second contact portion is surrounded by the support structure.

15. The semiconductor device according to claim 14, wherein: The first contact portion directly contacts the interlayer insulating layer and the insulating pattern, and The second contact portion directly contacts the support structure.

16. The semiconductor device according to claim 12, wherein: The contact electrode includes a plurality of contact electrodes spaced apart from each other, the support structure is disposed between the plurality of contact electrodes, and The second contact portions of the respective contact electrodes of the plurality of contact electrodes have different vertical lengths.

17. The semiconductor device according to claim 16, wherein: A vertical length of the second contact portion of at least some of the respective contact electrodes increases as a distance from the cell array region increases.

18. The semiconductor device according to claim 12, wherein: An upper surface of the contact electrode is located at the same height as an upper surface of the support structure.

19. The semiconductor device according to claim 12, wherein: In a cross-sectional view, the width of the support structure and the width of the first contact portion narrow toward the substrate, and A width of the second contact portion increases toward the substrate.

20. An electronic system comprising: Main substrate; a semiconductor device on the main substrate; as well as a controller connected to the semiconductor device on the main substrate, Wherein, the semiconductor device comprises: a circuit region configured to include a peripheral circuit structure on a substrate; and a cell region adjacent to the circuit region and configured to include a cell array region and a connection region, Wherein, the unit area includes: A gate stack structure configured to include a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure in the cell array region and configured to extend through the gate stack structure; a support structure in the connection region and configured to extend through the gate stack structure; and a contact electrode in the connection region and connected to the gate electrode through the gate stack structure, wherein each of the gate electrodes includes a pad electrode in the connection region configured to be connected to the contact electrode, and The contact electrode is electrically connected to a pad electrode of one of the gate electrodes and is insulated from the remaining gate electrodes, an insulating pattern is provided between the contact electrode and the remaining gate electrodes, and The gate electrode is at least partially surrounded by the support structure in a plan view, and comprises: a first contact portion, surrounded by the gate stack structure in a cross-sectional view and connected to the peripheral circuit structure; and A second contact portion is on the first contact portion and on the gate stack structure, and is connected to an upper surface of the pad electrode.

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