Resistive random access memory and manufacturing method thereof
By adopting a double-layer gap wall structure in resistive random access memory, the problem of oxygen atoms passing through the dielectric layer is solved, the read-write resistance and durability of the memory are improved, and stable storage in high temperature environments is achieved.
Patent Information
- Application Number
- CN202310742341.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-21
- Publication Date
- 2024-12-24
AI Technical Summary
In the high temperature environment, oxygen atoms pass through the dielectric layer and enter the resistance conversion layer, resulting in a decrease in resistance value, affecting the memory's readability and write tolerance and durability.
A double-layer gap wall structure is adopted, wherein the thickness of the first gap wall is greater than the second gap wall, the first gap wall contacts the resistance conversion layer and the third side wall of the upper electrode, and the second gap wall contacts the first gap wall and the upper electrode The third side wall formed by the structure can effectively block oxygen atoms and increase the reliability of the memory.
Effectively blocking oxygen atoms, improving the read-write resistance and durability of resistive random access memory in high temperature environments, and avoiding the problem of a decrease in resistance.
Smart Images
Figure CN119183346A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a resistance random access memory with a double-layer spacer and a manufacturing method thereof, in particular to a resistance random access memory using a double-layer spacer to block oxygen atoms and a manufacturing method thereof. Background Art
[0002] Resistive Random Access Memory (RRAM) is a type of non-volatile memory that offers the following advantages: small memory cell size, ultra-high-speed operation, low-power operation, high endurance, and CMOS compatibility.
[0003] The main operating principle of RRAM is to use the resistance of metal oxide to change with the applied bias voltage to generate different resistance values to store data. How to distinguish the internally stored value is determined by the resistance value of the RRAM.
[0004] As the amount of electronic data grows, the demand for memory with high capacity, high read / write times and faster read / write speed has also increased significantly. In order to achieve high-performance operation, the retention and endurance of RRAM must be increased. Summary of the invention
[0005] In view of this, the present invention provides a resistance random access memory with double-layer spacers to increase the reliability of the resistance random access memory.
[0006] According to a preferred embodiment of the present invention, a resistive random access memory comprises a lower electrode, a resistive conversion layer, an upper electrode and an upper cover layer stacked from bottom to top, wherein the upper cover layer comprises an upper surface and two fourth side walls, wherein the edge of the upper surface connects the fourth side walls, a first spacer contacts a first side wall of the lower electrode and a second side wall of the resistive conversion layer, and a second spacer contacts the first spacer and contacts a third side wall of the upper electrode, wherein the thickness of the first spacer is greater than the thickness of the second spacer, and the first spacer and the second spacer do not cover the upper surface.
[0007] According to a preferred embodiment of the present invention, a method for manufacturing a resistive random access memory includes forming a lower electrode, a resistance conversion layer, an upper electrode and an upper cover layer stacked in sequence from bottom to top, wherein the upper cover layer includes an upper surface and two fourth side walls, wherein the edge of the upper surface connects each fourth side wall to form a first spacer contacting a first side wall of the lower electrode and a second side wall of the resistance conversion layer, and then forming a second spacer contacting the first spacer and a third side wall of the upper electrode, wherein the thickness of the first spacer is greater than the thickness of the second spacer, and wherein the first spacer and the second spacer do not cover the upper surface.
[0008] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figures 1 to 6 A schematic diagram of a method for manufacturing a resistance random access memory according to a preferred embodiment of the present invention;
[0010] Figure 7 A schematic diagram of a resistance random access memory string according to a preferred embodiment of the present invention;
[0011] Figure 8 The diagram is a schematic diagram of a method for manufacturing a metal conductive line on a resistance random access memory according to a preferred embodiment of the present invention.
[0012] Main component symbols
[0013] 10: Base
[0014] 12: Conductive thread
[0015] 14: Lower electrode
[0016] 14a: first side wall
[0017] 16: Resistance conversion layer
[0018] 16a: Second side wall
[0019] 18: Upper electrode
[0020] 18a: Third side wall
[0021] 20: Upper cover
[0022] 20a: Upper surface
[0023] 20b: Fourth side wall
[0024] 22: First spacer
[0025] 22a: first spacer material layer
[0026] 24: Second spacer
[0027] 24a: second spacer material layer
[0028] 26: Dielectric layer
[0029] 28: Dielectric layer
[0030] 30: Groove
[0031] 32:Metal wire
[0032] B: Turning point
[0033] L: Logic element area
[0034] M: Memory area
[0035] S: Slope
[0036] 100: Resistive Random Access Memory
[0037] 100a: Resistive Random Access Memory
[0038] 100b: Resistive Random Access Memory
[0039] 200: Resistive Random Access Memory String DETAILED DESCRIPTION
[0040] Figures 1 to 6 A method for manufacturing a resistance random access memory is shown in a preferred embodiment of the present invention.
[0041] like Figure 1 As shown, a substrate 10 is first provided, the substrate includes a memory area M and a logic element area L, a conductive line 12 is buried in the substrate 10 in the memory area M, and then a lower electrode material layer, a resistance conversion material layer, an upper electrode material layer and an upper cover material layer are sequentially formed to cover the memory area M and the logic element area L from bottom to top, and then the lower electrode material layer, the resistance conversion material layer, the upper electrode material and the upper cover material layer are patterned to form a lower electrode 14, a resistance conversion layer 16, an upper electrode 18 and an upper cover layer 20 in the memory area M, which are sequentially stacked from bottom to top and the lower electrode material layer, the resistance conversion material layer, the upper electrode material and the upper cover material layer in the logic element area L are completely removed, wherein the upper cover layer 20 includes an upper surface 20a and two fourth side walls 20b, wherein the edge of the upper surface 20a is connected to the two fourth side walls 20b, and the lower electrode 14 contacts the conductive line 12. The conductive line 12 may include conductive materials such as copper, aluminum or tungsten.
[0042] like Figure 2 and Figure 3 As shown, a first spacer material layer 22a is formed to conform to cover the lower electrode 14, the resistance conversion layer 16, the upper electrode 18, the upper cover layer 20, the substrate 10 of the memory area M and the substrate 10 of the logic element area L, and then the first spacer material layer 22a is etched to remove the first spacer material layer 22a located on the upper surface 20a of the upper cover layer 20, the fourth sidewall 20b and part of the third sidewall 18a of the upper electrode 18 to form a first spacer 22. When forming the first spacer 22, the first spacer material layer 22a on the logic element area M is also removed, wherein the first spacer 22 is preferably silicon nitride. The first spacer 22 preferably contacts part of the third sidewall 18a of the upper electrode 18, the entire first sidewall 14a of the lower electrode 14 and the entire second sidewall 16a of the resistance conversion layer 16. And the first spacer 22 does not contact the fourth sidewall 20b and the upper surface 20a of the upper cover layer 20.
[0043] like Figure 4 As shown, a second spacer material layer 24a is formed to conformally cover the first spacer 22, contact the upper electrode 18, the upper cover layer 20, and the substrate 10 of the memory area M and the substrate 10 of the logic element area L, and the second spacer material layer 24a contacts the first spacer 22. As shown in FIG. 5, a dielectric layer 26 is formed to cover the second spacer material layer 24a, the substrate 10 of the memory area M, and the substrate 10 of the logic element area L, wherein the dielectric layer 26 contacts the second spacer material layer 24a, and the dielectric layer 26 preferably comprises silicon oxide. Figure 6 As shown, the dielectric layer 26 and the second spacer material layer 24a are etched back to completely remove the second spacer material layer 24a and the dielectric layer 26 located on the upper surface 20a and completely remove the second spacer material layer 24a and the dielectric layer 26 in the logic element area L. After removing the second spacer material layer 24a located on the upper surface 20a, the second spacer material layer 24a is cut off to become a second spacer 24 located on both sides of the lower electrode 14, the resistance conversion layer 16, the upper electrode 18, and the upper cover layer 20, wherein the second spacer 24 is preferably silicon nitride, and the second spacer 24 needs to cover the third side wall 18a not covered by the first spacer 22 to protect the upper electrode 18 from being damaged in the subsequent manufacturing process. In addition, the second spacer 24 on the first spacer 22 extends to the substrate 10 in the contact memory area M.
[0044] At this point, the RRAM 100 of the present invention has been completed. When etching back the dielectric layer 26 and the second spacer material layer 24a, no mask is used, and the dielectric layer 26 and the second spacer material layer 24a in the logic element region L and the memory region M are removed by utilizing the different etching rates (loading effect) caused by the different densities of the components in the logic element region L and the memory region M, and the second spacer material layer 24a in the memory region M is cut off.
[0045] Figure 7 A resistance random access memory string is shown according to another preferred embodiment of the present invention.
[0046] Please also see Figure 6 and Figure 7 ,exist Figure 6 The RRAM 100 shown in the example is located in the middle of the RRAM string 200. Specifically, there is a RRAM 100a and a RRAM 100b on the left and right sides of the RRAM 100, respectively. The RRAM string 200 is located in the memory area M. The RRAM 100, the RRAM 100a and the RRAM 100b have the same structure. The second spacer 24 on one side of the RRAM 100a extends to the substrate 10 and the second spacer on one side of the RRAM 100 also extends to the substrate 10. The second spacer 24 on the RRAM 100a and the second spacer 24 on the RRAM 100 are connected on the substrate 10. Furthermore, in the resistance random access memory string 200, the resistance random access memory 100a and the resistance random access memory 100b are each the resistance random access memories at the end of the resistance random access memory string 200. Figure 6 After the step of etching back the dielectric layer 26 and the second spacer material layer 24a is completed, because they are located at the very end, due to the load effect, the dielectric layer 26 on one side of the RRAM 100a and the RRAM 100b will have a slope S, and the very end of the slope S touches the second spacer 24 located on the surface of the substrate 10. However, because the RRAM 100 is in the middle of the RRAM string 200, the surfaces of the dielectric layer 26 on both sides of the RRAM 100 are roughly flat.
[0047] According to a preferred embodiment of the present invention, Figure 6A resistive random access memory 100 includes a lower electrode 14, a resistance conversion layer 16, an upper electrode 18 and an upper cover layer 20 stacked from bottom to top, wherein the upper cover layer 20 includes an upper surface 20a and two fourth sidewalls 20b, a first spacer 22 contacts a first sidewall 14a of the lower electrode 14 and a second sidewall 16a of the resistance conversion layer 16, a second spacer 24 contacts the first spacer 22 and contacts a third sidewall 18a of the upper electrode 18, and the third sidewall 18a and the fourth sidewall 20a The first spacer 22 is cut flush, wherein the thickness of the first spacer 22 is greater than the thickness of the second spacer 24. According to a preferred embodiment of the present invention, the thickness of the first spacer 22 is between 250 angstroms and 500 angstroms, the thickness of the second spacer 24 is between 100 angstroms and 150 angstroms, and the thickness of the first spacer 22 plus the second spacer 24 is between 350 angstroms and 650 angstroms. It is worth noting that the first spacer 22 and the second spacer 24 do not cover the upper surface 20a and the first spacer 22 does not contact the fourth side wall 20b.
[0048] In addition, the first spacer 22 preferably extends from the second sidewall 16a to the third sidewall 18a of the contact portion, that is, the first spacer 22 at least completely covers the second sidewall 16a of the resistance switching layer 16, and the second spacer 24 extends from the first spacer 22 to the surface of the substrate 10. A dielectric layer 26 covers the second spacer 24 and the memory area M, wherein the upper surface 20a is exposed by the dielectric layer 26, but there is no dielectric layer 26, the second spacer 24, the first spacer 22, the lower electrode 14, the resistance switching layer 16, the upper electrode 18 and the upper cover layer 20 in the logic element area L.
[0049] The cross section of the first spacer 22 includes a sail-shaped profile, so the second spacer 24 contacting the third sidewall 18a and the second spacer 24 contacting the top of the first spacer 22 together form a turning point (bend) B, and the turning point B is concave toward the direction of the upper electrode 18.
[0050] The substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-coated insulating substrate. The resistance conversion layer 16 includes tantalum oxide, nickel oxide, hafnium oxide, titanium oxide or other transition metal oxides. The upper electrode 18 and the lower electrode 14 can each include a conductive material such as tantalum, titanium, iridium, titanium nitride, tantalum nitride, etc. The upper cover layer 20 is preferably silicon oxide.
[0051] The first spacer 22 and the second spacer 24 are preferably made of silicon nitride, and the dielectric layer 26 is made of silicon oxide. Since the ambient temperature of the RRAM 100 of the present invention during operation is greater than 120°C, if only the second spacer 24 is used without the first spacer 22, at temperatures above 120°C, oxygen atoms will still pass through the second spacer 24 from the dielectric layer 26 into the resistance conversion layer 16, causing the resistance of the RRAM 100 in the low resistance state to decrease. Therefore, the present invention specifically adds a first spacer 22 with a larger thickness, which is used together with the second spacer 24 to block oxygen atoms.
[0052] In addition, although the RRAM 100 uses only a single layer of the second spacer 24, increasing the thickness of the second spacer 24 can also achieve the effect of blocking oxygen atoms. Figure 6 Problems will occur in the back etching step. Specifically, because the current back etching is only applicable to removing thin material layers, such as silicon nitride layers less than 200 angstroms, if the second spacer 24 is thickened to more than 200 angstroms in order to block oxygen atoms, during the back etching, there will be multiple second spacer material layers 24a remaining in the logic element area L.
[0053] In addition, Figure 8 As shown, after the resistance random access memory 100 is completed, the manufacturing process of the metal wire can be continued, for example, a dielectric layer 28 is first formed to cover the dielectric layer 26, and the dielectric layer 28 is preferably silicon oxide, and then the dielectric layer 28 and the upper cover layer 20 are etched to form a trench 30 in the dielectric layer 28 and the upper cover layer 20, and finally metal is filled in the trench 30 to form a metal wire 32. Figure 6 The second spacer material layer 24a on the upper surface 20a of the upper cover layer 20 has been removed in the back etching, so when forming the groove 30, only the dielectric layer 28 and the upper cover layer 20 need to be etched. If the second spacer material layer 24a on the upper surface 20a of the upper cover layer 20 is not removed, one more layer of the second spacer material layer 24a must be etched when forming the groove 30. However, the second spacer material layer 24a is silicon nitride. Since the etching conditions when forming the groove 30 are more suitable for etching silicon oxide, the second spacer material layer 24a will be incompletely etched. The present invention removes the second spacer material layer 24a on the upper surface 20a in advance, so that the problem of incomplete formation of the groove 30 can be avoided.
[0054] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A resistance random access memory, comprising: The lower electrode, the resistance conversion layer, the upper electrode and the upper cover layer are stacked from bottom to top, wherein the upper cover layer comprises an upper surface and two fourth side walls, wherein the edge of the upper surface is connected to each of the fourth side walls; A first spacer contacting a first side wall of the lower electrode and a second side wall of the resistance switching layer; as well as A second spacer wall contacts the first spacer wall and contacts the third side wall of the upper electrode, wherein the thickness of the first spacer wall is greater than the thickness of the second spacer wall; The first spacer and the second spacer do not cover the upper surface. 2 . The resistance random access memory as claimed in claim 1 , wherein the first spacer contacts the third sidewall of the upper electrode. 3 . The resistance random access memory as claimed in claim 1 , wherein the entire second spacer has the same thickness. 4 . The resistance random access memory as claimed in claim 1 , wherein the second spacer contacting the third sidewall and the second spacer contacting the top of the first spacer together form a turning point, and the turning point is concave toward the upper electrode.
5. The resistance random access memory according to claim 1, further comprising: A substrate comprising a memory area and a logic element area, wherein the second spacer on the first spacer extends to a surface of the substrate; A conductive line is embedded in the memory area and contacts the lower electrode; as well as A dielectric layer covers the second spacer and the memory area, wherein the upper surface is exposed by the dielectric layer. 6 . The resistance random access memory as claimed in claim 5 , wherein the dielectric layer and the second spacer are not present in the logic element region. 7 . The resistance random access memory as claimed in claim 1 , wherein the thickness of the first spacer is between 250 angstroms and 500 angstroms, and the thickness of the second spacer is between 100 angstroms and 150 angstroms.
8. The resistance random access memory as claimed in claim 1, wherein a cross section of the first spacer comprises a sail-shaped profile. 9 . The resistance random access memory as claimed in claim 1 , wherein the resistance switching layer comprises tantalum oxide, titanium oxide or hafnium oxide.
10. A method for manufacturing a resistance random access memory, comprising: Forming a lower electrode, a resistance conversion layer, an upper electrode and an upper cover layer stacked in order from bottom to top, wherein the upper cover layer comprises an upper surface and two fourth side walls, wherein an edge of the upper surface is connected to each of the fourth side walls; Form a first spacer to contact the first side wall of the lower electrode and the second side wall of the resistance switching layer; as well as Forming a second spacer that contacts the first spacer and the third sidewall of the upper electrode, wherein the thickness of the first spacer is greater than the thickness of the second spacer; The first spacer and the second spacer do not cover the upper surface.
11. The method for manufacturing a resistance random access memory according to claim 10, further comprising: Providing a substrate, the substrate comprising a memory area and a logic element area, the lower electrode, the resistance conversion layer, the upper electrode and the upper cover layer are stacked on the substrate in the memory area; After forming the upper cover layer, forming a first spacer material layer to cover the lower electrode, the resistance conversion layer, the upper electrode, the upper cover layer and the substrate; Etching the first spacer material layer to remove the first spacer material layer located on the upper surface to form the first spacer; After forming the first spacer, forming a second spacer material layer to cover the first spacer, contact the upper electrode, the upper cover layer and the substrate; forming a dielectric layer to cover the second spacer material layer; as well as The dielectric layer and the second spacer material layer are etched to remove the second spacer material layer and the dielectric layer located on the upper surface, thereby forming the second spacer.
12. The method for manufacturing a resistance random access memory according to claim 11, further comprising: When the second spacer material layer is formed to cover the first spacer, the second spacer material layer covers the logic element region; When the dielectric layer is formed to cover the second spacer material layer, the dielectric layer covers the logic element region; and When etching the dielectric layer and the second spacer material layer, the second spacer material layer and the dielectric layer located in the logic element region are completely removed. 13 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein the first spacer contacts a portion of the third sidewall of the upper electrode. 14 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein the entire second spacer has the same thickness. 15 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein the second spacer contacting the third sidewall and the second spacer contacting the top of the first spacer together form a turning point, and the turning point is concave toward the upper electrode. 16 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein a thickness of the first spacer is between 250 angstroms and 500 angstroms, and a thickness of the second spacer is between 100 angstroms and 150 angstroms. 17 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein a cross section of the first spacer comprises a sail-shaped profile. 18 . The method for manufacturing a resistance random access memory as claimed in claim 10 , wherein the resistance switching layer comprises tantalum oxide, titanium oxide or hafnium oxide.