Three-dimensional memory devices including etch stop metal plates for backside via structures and methods of forming same

Abstract

A semiconductor structure includes: an alternating stack of insulating layers and conductive layers on a front side of at least one layer of semiconductor material; a memory opening extending vertically through the alternating stack; a memory opening fill structure; and a dielectric material portion, the dielectric material portion contacting sidewalls of the alternately stacked insulating layers. In one embodiment, a connection via structure may extend vertically through the dielectric material portion, and a metal plate may contact the connection via structure. Alternatively or additionally, an integrated via and pad structure may be provided, the integrated via and pad structure comprising: a conductive via portion extending vertically through the dielectric material portion; and a conductive pad portion on an end portion of the conductive via portion.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Patent Application No. 17 / 857,335 filed on July 5, 2022 and U.S. Non-Provisional Patent Application No. 17 / 857,375 filed on July 5, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional memory device including an etch stop metal plate providing electrical connection to a backside via structure and a method of forming the same. Background Art

[0004] Support circuits for performing write, read, and erase operations of memory cells in the vertical NAND strings may be provided by complementary metal oxide semiconductor (CMOS) devices formed on the same substrate as the three-dimensional memory device. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: an alternating stack of insulating layers and conductive layers; a memory opening, which extends vertically through the alternating stack; a memory opening filling structure, which is located in the memory opening and includes a corresponding vertical semiconductor channel and a corresponding vertical memory element stack; a dielectric material portion; a contact through-hole structure, which extends vertically through the dielectric material portion and contacts a corresponding one of the conductive layers; and an integrated through-hole and pad structure, which contacts the front side of the conductive pad portion; and a back side contact pad structure, which contacts the flat back side surface of the integrated through-hole and pad structure.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided. The method includes: forming an alternating stack of insulating layers and spacer material layers above at least one semiconductor material layer located above a first substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by the conductive layer; forming a dielectric material portion; forming a contact via cavity through the dielectric material portion on a corresponding one of the conductive layers; forming a connecting via cavity through the dielectric material portion into the at least one semiconductor material layer; forming a pad cavity by recessing a portion of the at least one semiconductor material layer around a bottom area of ​​the connecting via cavity, wherein a continuous void including the connecting via cavity and the pad cavity is formed; and forming a contact via structure in the contact via cavity and forming an integrated via and pad structure in the continuous void.

[0007] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: an alternating stack of insulating layers and conductive layers, the alternating stack being located on the front side of at least one semiconductor material layer; a memory opening, the memory opening extending vertically through the alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening and including a corresponding vertical semiconductor channel and a corresponding vertical memory element stack, wherein the at least one semiconductor material layer is in contact with the vertical semiconductor channel; a dielectric material portion; a connecting via structure, the connecting via structure extending vertically through the dielectric material portion; a metal plate, the metal plate in contact with a proximal end surface of the connecting via structure; and a back side contact pad structure, the back side contact pad structure in contact with the metal plate and separated from the connecting via structure by the metal plate.

[0008] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of insulating layers and spacer material layers above at least one semiconductor material layer located above a first substrate, wherein the spacer material layer is formed as a conductive layer or is subsequently replaced by the conductive layer; forming a metal plate above the at least one semiconductor material layer; forming a dielectric material portion; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each of the memory opening filling structures includes a corresponding vertical semiconductor channel and a corresponding vertical memory element stack; forming a connecting through-hole structure passing through the dielectric material portion directly on the top surface of the metal plate; removing a portion of the at least one semiconductor material layer that has an area overlap with the metal plate; and forming a back contact pad structure directly on the back surface of the metal plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming a buffer dielectric layer, a source level material layer, and alternating stacks of insulating layers and sacrificial material layers over a carrier substrate according to the first embodiment of the present disclosure.

[0010] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped surface according to the first embodiment of the present disclosure.

[0011] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming a patterned plate, a stepped dielectric material portion, and a drain select level isolation structure according to the first embodiment of the present disclosure.

[0012] Figure 4 is a schematic vertical cross-sectional view of a first exemplary structure after forming a storage opening and a support opening according to the first embodiment of the present disclosure.

[0013] Figure 5 is a schematic vertical cross-sectional view of a first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0014] Fig. 6A is a schematic vertical cross-sectional view of a first exemplary structure after forming a contact level dielectric layer, a trench through the stack, and a connection region trench according to the first embodiment of the present disclosure.

[0015] Figure 6B for Fig. 6A A partial perspective top view of an exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 6A A schematic vertical cross-sectional view of a plane.

[0016] Figure 7 is a schematic vertical cross-sectional view of a first exemplary structure after forming sacrificial etch stop spacers according to the first embodiment of the present disclosure.

[0017] Figure 8 is a schematic vertical cross-sectional view of a first exemplary structure after forming a source cavity according to the first embodiment of the present disclosure.

[0018] Fig. 9 is a schematic vertical cross-sectional view of a first exemplary structure after forming a source contact layer according to the first embodiment of the present disclosure.

[0019] Fig.10 is a schematic vertical cross-sectional view of the first exemplary structure after removing the sacrificial etch stop spacers and forming a backside recess according to the first embodiment of the present disclosure.

[0020] Fig.11 is a schematic vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to the first embodiment of the present disclosure.

[0021] Fig.12 is a schematic vertical cross-sectional view of a first exemplary structure after applying and patterning a patterned film according to a first embodiment of the present disclosure.

[0022] Fig.13 is a schematic vertical cross-sectional view of a first exemplary structure after forming a trench-fill dielectric structure according to the first embodiment of the present disclosure.

[0023] Fig.14 is a schematic vertical cross-sectional view of a first exemplary structure after removing a patterned film according to the first embodiment of the present disclosure.

[0024] Fig.15is a schematic vertical cross-sectional view of the first exemplary structure after forming insulating trench spacers and a through-stack contact via structure in the remaining volume of the through-stack trench according to the first embodiment of the present disclosure.

[0025] Fig.16A is a schematic vertical cross-sectional view of the first exemplary structure after forming an additional contact via structure, a connecting via structure, and a bit line level metal line according to the first embodiment of the present disclosure.

[0026] Fig. 16B for Fig.16A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig.16A A schematic vertical cross-sectional view of a plane.

[0027] Fig.17 is a schematic vertical cross-sectional view of a first exemplary structure of forming a memory die after forming an additional metal interconnect structure according to the first embodiment of the present disclosure.

[0028] Fig.18 is a schematic vertical cross-sectional view of a first exemplary structure after bonding a logic die to a memory die according to the first embodiment of the present disclosure.

[0029] Fig.19 for Fig.18 Schematic vertical cross-sectional view of a region of a first exemplary structure.

[0030] Fig. 20 is a schematic vertical cross-sectional view of a first exemplary structure after removal of a carrier substrate according to the first embodiment of the present disclosure.

[0031] Fig.21 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside dielectric liner and a patterned photoresist layer according to the first embodiment of the present disclosure.

[0032] Fig. 22 is a schematic vertical cross-sectional view of the first exemplary structure after removing unmasked portions of the backside dielectric liner, the buffer dielectric layer, and the source level material layer according to the first embodiment of the present disclosure.

[0033] Fig.23 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside dielectric layer according to the first embodiment of the present disclosure.

[0034] Fig.24 is a schematic vertical cross-sectional view of a first exemplary structure after forming a first backside contact via cavity according to the first embodiment of the present disclosure.

[0035] Fig.25 is a schematic vertical cross-sectional view of the first exemplary structure after forming a second backside contact via cavity according to the first embodiment of the present disclosure.

[0036] Fig.26 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside contact pad structure according to the first embodiment of the present disclosure.

[0037] Fig.27A is a schematic vertical cross-sectional view of a first exemplary structure after forming a passivation dielectric layer and a via cavity according to the first embodiment of the present disclosure.

[0038] Fig.27B is a schematic vertical cross-sectional view of a first alternative configuration of the first exemplary structure after forming a passivation dielectric layer and a via cavity according to the first embodiment of the present disclosure.

[0039] Fig.27C is a schematic vertical cross-sectional view of a second alternative configuration of the first exemplary structure after forming a passivation dielectric layer and a via cavity according to the first embodiment of the present disclosure.

[0040] Fig.28A and Fig.28B is a schematic vertical cross-sectional view of an alternative configuration of a second exemplary structure after forming a recessed region in a buffer dielectric layer according to a second embodiment of the present disclosure.

[0041] Fig.29 is a schematic vertical cross-sectional view of a second exemplary structure after a source level material layer is formed in accordance with a second embodiment of the present disclosure.

[0042] Fig.30 is a schematic vertical cross-sectional view of a second exemplary structure after forming a plate stack including respective metal plates according to a second embodiment of the present disclosure.

[0043] Fig.31A and Fig.31B is a schematic vertical cross-sectional view of an alternative configuration of a second exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to the second embodiment of the present disclosure.

[0044] Fig.32 is a schematic vertical cross-sectional view of a second exemplary structure after forming a stepped surface, a stepped dielectric material portion, and a drain select level isolation structure according to the second embodiment of the present disclosure.

[0045] Fig.33 is a schematic vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a supporting pillar structure according to the second embodiment of the present disclosure.

[0046] Fig.34A is a schematic vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer and a trench through the stack according to the second embodiment of the present disclosure.

[0047] Fig.34B for Fig.34A A partial perspective top view of an exemplary structure of FIG. The hinged vertical plane A-A' is Fig.34A A schematic vertical cross-sectional view of a plane.

[0048] Fig.35 is a schematic vertical cross-sectional view of a second exemplary structure after forming a source contact layer and replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure.

[0049] Fig.36 is a schematic vertical cross-sectional view of a second exemplary structure after forming a trench filling dielectric structure, an insulating trench spacer, and a contact via structure through the stack according to the second embodiment of the present disclosure.

[0050] Fig.37 is a schematic vertical cross-sectional view of a second exemplary structure after forming an additional contact via structure, a connecting via structure, and a bit line level metal line according to the second embodiment of the present disclosure.

[0051] Fig.38 is a schematic vertical cross-sectional view of a region of a second exemplary structure after bonding a logic die to a memory die according to a second embodiment of the present disclosure.

[0052] Fig.39 is a schematic vertical cross-sectional view of a second exemplary structure after removal of a carrier substrate according to a second embodiment of the present disclosure.

[0053] Fig.40 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside dielectric liner and a patterned photoresist layer according to a second embodiment of the present disclosure.

[0054] Fig.41 is a schematic vertical cross-sectional view of a second exemplary structure after removing unmasked portions of a backside dielectric liner, a buffer dielectric layer, and a source level material layer according to a second embodiment of the present disclosure.

[0055] Fig.42 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside dielectric layer according to the second embodiment of the present disclosure.

[0056] Fig.43is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside contact via cavity according to the second embodiment of the present disclosure.

[0057] Fig.44 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside contact pad structure according to the second embodiment of the present disclosure.

[0058] Fig.45 is a schematic vertical cross-sectional view of a second exemplary structure after forming a passivation dielectric layer and a via cavity according to a second embodiment of the present disclosure.

[0059] Fig.46A is a schematic vertical cross-sectional view of a third exemplary structure after forming a recessed region through a buffer dielectric layer according to a third embodiment of the present disclosure.

[0060] Fig.46B is a schematic vertical cross-sectional view of an alternative configuration of the third exemplary structure after forming a recessed region through a buffer dielectric layer according to the third embodiment of the present disclosure.

[0061] Fig.47A is a schematic vertical cross-sectional view of a third exemplary structure after forming a source level material layer and a plate stack including corresponding metal plates according to a third embodiment of the present disclosure.

[0062] Fig.47B is a schematic vertical cross-sectional view of an alternative configuration of a third exemplary structure after forming a source level material layer and a plate stack including corresponding metal plates according to a third embodiment of the present disclosure.

[0063] Fig.48 is a schematic vertical cross-sectional view of a third exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers, a stepped surface, a stepped dielectric material portion, and a drain select level isolation structure according to the third embodiment of the present disclosure.

[0064] Fig.49 is a schematic vertical cross-sectional view of a third exemplary structure after forming a conductive layer, a trench filling structure through the stack, an additional contact via structure, a connecting via structure, and a bit line level metal line according to the third embodiment of the present disclosure.

[0065] Fig.50 is a schematic vertical cross-sectional view of a third exemplary structure after bonding a logic die to a memory die and after removing a carrier substrate according to a third embodiment of the present disclosure.

[0066] Fig.51is a schematic vertical cross-sectional view of a third exemplary structure after removing a backside dielectric liner and patterning the backside dielectric liner and a source level material layer according to a third embodiment of the present disclosure.

[0067] Fig.52 is a schematic vertical cross-sectional view of a third exemplary structure after forming and patterning a backside dielectric layer according to a third embodiment of the present disclosure.

[0068] Fig.53 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a buffer dielectric layer, a source level material layer, and a plate stack including corresponding metal plates according to a fourth embodiment of the present disclosure.

[0069] Fig.54 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to a fourth embodiment of the present disclosure.

[0070] Fig.55 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a stepped surface, a stepped dielectric material portion, and a drain select level isolation structure according to a fourth embodiment of the present disclosure.

[0071] Fig.56 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a memory opening filling structure and a supporting pillar structure according to a fourth embodiment of the present disclosure.

[0072] Fig.57A is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a contact-level dielectric layer and a trench through the stack according to a fourth embodiment of the present disclosure.

[0073] Fig.57B for Fig.57A A partial perspective top view of an exemplary structure of FIG. The hinged vertical plane A-A' is Fig.57A A schematic vertical cross-sectional view of a plane.

[0074] Fig.58 is a schematic vertical cross-sectional view of the third exemplary structure after forming a conductive layer, a trench filling structure through the stack, an additional contact via structure, a connecting via structure, and a bit line level metal line according to the fourth embodiment of the present disclosure.

[0075] Fig.59 is a schematic vertical cross-sectional view of a region of a fourth exemplary structure after bonding a logic die to a memory die according to a fourth embodiment of the present disclosure.

[0076] Fig.60is a schematic vertical cross-sectional view of a fourth exemplary structure after removal of a carrier substrate according to a fourth embodiment of the present disclosure.

[0077] Fig.61 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a backside dielectric liner and patterning the backside dielectric liner, the buffer dielectric layer, and the source level material layer according to the fourth embodiment of the present disclosure.

[0078] Fig.62 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a backside dielectric layer and a backside contact via cavity according to a fourth embodiment of the present disclosure.

[0079] Fig.63 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a backside contact pad structure according to a fourth embodiment of the present disclosure.

[0080] Fig.64 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a passivation dielectric layer and a via cavity according to a fourth embodiment of the present disclosure.

[0081] Fig.65 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a buffer dielectric layer, a source level material layer, and alternating stacks of insulating layers and sacrificial material layers over a carrier substrate according to a fifth embodiment of the present disclosure.

[0082] Fig.66 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a stepped surface, a stepped dielectric material portion, and a drain select level isolation structure according to a fifth embodiment of the present disclosure.

[0083] Fig.67 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a memory opening filling structure and a supporting pillar structure according to a fifth embodiment of the present disclosure.

[0084] Fig.68 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a contact-level dielectric layer and a trench through the stack according to a fifth embodiment of the present disclosure.

[0085] Fig.69 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a source contact layer and replacing the sacrificial material layer with a conductive layer according to the fifth embodiment of the present disclosure.

[0086] Fig.70 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a trench filling structure through the stack according to a fifth embodiment of the present disclosure.

[0087] Fig.71 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a layer-contact via cavity and a connecting via cavity according to a fifth embodiment of the present disclosure.

[0088] Fig.72A is a schematic vertical cross-sectional view of a bottom region of a layer-contact via cavity after removal of a metal oxide surface layer according to a fifth embodiment of the present disclosure.

[0089] Fig.72B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity during an isotropic etching process for laterally expanding the bottom region of the connecting via cavity according to a fifth embodiment of the present disclosure.

[0090] Fig.73A is a schematic vertical cross-sectional view of a bottom region of a layer contact via cavity after an isotropic etching process according to a fifth embodiment of the present disclosure.

[0091] Fig.73B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity after an isotropic etching process according to a fifth embodiment of the present disclosure.

[0092] Fig.74A is a schematic vertical cross-sectional view of a bottom region of a layer-contact via cavity after forming a metal portion according to a fifth embodiment of the present disclosure.

[0093] Fig.74B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity after forming a metal portion according to a fifth embodiment of the present disclosure.

[0094] Fig.75 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a layer contact via structure and a connection via structure according to a fifth embodiment of the present disclosure.

[0095] Fig.76 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming an additional connecting via structure and a bit line level metal line according to the fifth embodiment of the present disclosure.

[0096] Fig.77 is a schematic vertical cross-sectional view of a fifth exemplary structure after bonding a logic die to a memory die according to a fifth embodiment of the present disclosure.

[0097] Fig.78 is a schematic vertical cross-sectional view of a fifth exemplary structure after removal of a carrier substrate according to a fifth embodiment of the present disclosure.

[0098] Fig.79is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a backside dielectric liner according to a fifth embodiment of the present disclosure.

[0099] Fig.80 is a schematic vertical cross-sectional view of the fifth exemplary structure after removing unmasked portions of the backside dielectric liner, the buffer dielectric layer, and the source level material layer according to the fifth embodiment of the present disclosure.

[0100] Fig.81 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a backside dielectric layer according to a fifth embodiment of the present disclosure.

[0101] Fig.82 is a schematic vertical cross-sectional view of a fifth exemplary structure after forming a backside contact pad structure according to a fifth embodiment of the present disclosure.

[0102] Fig.83 is a vertical cross-sectional view of a sixth exemplary structure after forming a layer-contact via cavity and a connecting via cavity according to a sixth embodiment of the present disclosure.

[0103] Fig.84A is a schematic vertical cross-sectional view of a bottom region of a layer-contact via cavity after removal of a metal oxide surface layer according to a sixth embodiment of the present disclosure.

[0104] Fig.84B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity during an isotropic etching process for laterally expanding the bottom region of the connecting via cavity according to a sixth embodiment of the present disclosure.

[0105] Fig.85A is a schematic vertical cross-sectional view of a bottom region of a layer contact via cavity after an isotropic etching process according to a sixth embodiment of the present disclosure.

[0106] Fig.85B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity after an isotropic etching process according to a sixth embodiment of the present disclosure.

[0107] Fig.86A is a schematic vertical cross-sectional view of a bottom region of a layer-contact via cavity after forming a first base metal portion according to a sixth embodiment of the present disclosure.

[0108] Fig.86B is a schematic vertical cross-sectional view of a bottom region of a connecting via cavity after forming a second base metal portion according to a sixth embodiment of the present disclosure.

[0109] Fig.87is a vertical cross-sectional view of a sixth exemplary structure after forming a layer contact via structure and a connection via structure according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0110] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device and a method of forming the same, the three-dimensional memory device including an etch stop metal plate that provides electrical connections to a backside via structure, and various aspects of the three-dimensional memory device and method of forming the same are described below. Embodiments of the present disclosure can be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as a three-dimensional memory array device including multiple NAND memory strings. Embodiments of the present disclosure can be used to form a bonded assembly of multiple semiconductor dies including a memory die.

[0111] The accompanying drawings are not drawn to scale. Multiple instances of an element may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components. As used herein, if there is a conductive path between a first electronic component and a second electronic component, the first electronic component is electrically connected to the second electronic component.

[0112] As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm in the absence of an electrical dopant, and is capable of producing a doped material having an electrical conductivity in the range of 1.0S / cm to 1.0x105S / cm when an electrical dopant is appropriately doped. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0x105S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity less than 1.0x10-6S / cm. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0x105S / cm) when it is formed into a crystalline material or converted into a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. "Doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0x10-6S / cm to 1.0x105S / cm. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Therefore, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0113] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0114] Typically, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. Each plane includes multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming.

[0115] refer to Figure 1 , shows a first exemplary structure according to the first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which is also referred to as a first substrate. The carrier substrate 9 may include a semiconductor material, an insulating material and / or a conductive material. In an illustrative example, the carrier substrate 9 may be a commercially available semiconductor wafer, such as a single crystal silicon wafer.

[0116] A buffer dielectric layer 111 may be deposited on the front side of the carrier substrate 9. The buffer dielectric layer 111 includes a dielectric material different from the material of the carrier substrate 9. For example, the buffer dielectric layer 111 may include silicon oxide. The thickness of the buffer dielectric layer 111 may be in the range of 50 nm to 1,000 nm, such as 100 nm to 500 nm, although lesser and greater thicknesses may also be employed.

[0117] The process source level material layer (112, 103, 104, 105, 116) may be deposited above the buffer dielectric layer 111. The process source level material layer (112, 103, 104, 105, 116) may include from bottom to top: a first source level semiconductor layer 112, the first source level semiconductor layer including a doped semiconductor material; a lower sacrificial dielectric liner 103; a source level sacrificial layer 104, the source level sacrificial layer including a source level sacrificial material; an upper sacrificial dielectric liner 105; and a second source level semiconductor layer 116, the second source level semiconductor layer including a doped semiconductor material. The doped semiconductor material of the second source level semiconductor layer 116 may be the same as or different from the doped semiconductor material of the first source level semiconductor layer 112. In one embodiment, the vertical semiconductor channel to be formed subsequently may have a first conductivity type of doping, and the first source level semiconductor layer 112 and the second source level semiconductor layer 116 may have a second conductivity type of doping opposite to the first conductivity type. Each of the first source level semiconductor layer 112 and the second source level semiconductor layer 116 may include an undoped polysilicon layer or an amorphous silicon layer having a thickness in the range of 100 nm to 1,000 nm, but smaller and larger thicknesses may also be employed.

[0118] The source level sacrificial material of the source level sacrificial layer 104 includes a material that is selectively removable relative to the doped semiconductor material of the first source level semiconductor layer 112 and the second source level semiconductor layer 116. The source level sacrificial material of the source level sacrificial layer 104 may include silicon nitride, silicon germanium alloy, undoped amorphous silicon, undoped polysilicon, organosilicate glass, or any other material that may subsequently be selectively removed relative to the material of the first source level semiconductor layer 112 and the second source level semiconductor layer 116. The source level sacrificial layer 104 may be patterned such that a portion of the source level sacrificial layer 104 located in the connecting via region 200 is removed, while the source level sacrificial material layer 104 is present in the memory array region 100 and in the staircase region 300. The connection via region 200 is a region where a connection via structure will be formed later, the memory array region 100 is a region where a three-dimensional memory array will be formed later, and the staircase region 300 is a region where a stepped surface of a conductive layer and a layer contact via structure will be formed later. Therefore, the source level sacrificial layer 104 is located between the lower sacrificial dielectric liner 103 and the upper sacrificial dielectric liner 105 in the memory array region 100 and in the staircase region 300. The lower sacrificial dielectric liner 103 contacts the upper sacrificial dielectric liner 105 in the connection via region 300, and the source level sacrificial layer 104 does not exist in the connection via region 200. The thickness of the source level sacrificial layer 104 can be in the range of 10nm to 100nm, such as 20nm to 50nm, but smaller and larger thicknesses can also be used. The lower dielectric liner 103 and the upper dielectric liner 105 include a sacrificial dielectric material such as silicon oxide and may have a thickness in a range of 3 nm to 60 nm, such as 15 nm to 30 nm, although lesser or greater thicknesses may also be employed.

[0119] A stack of alternating multiple first material layers (which may be insulating layers 32) and second material layers (which may be sacrificial material layers 42) is formed over the top surface of the source level material layer (112, 103, 104, 105, 116) during the process. As used herein, "material layer" refers to a layer including a material throughout its entirety. As used herein, alternating multiple first elements and second elements refer to a structure in which instances of the first element and instances of the second element are alternating. Each instance of a first element that is not an end element of an alternating multiple element is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating multiple element is adjacent to two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating multiple first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating multiple elements.

[0120] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating multiple insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42.

[0121] The alternating plurality of stacks are referred to herein as alternating stacks (32, 42). In one embodiment, the alternating stacks (32, 42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Therefore, each insulating layer 32 may be an insulating material layer. Insulating materials that can be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0122] The second material of sacrificial material layer 42 is a sacrificial material that is selectively removable with respect to the first material of insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0123] The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may be used, for example, as a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride.

[0124] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0125] The topmost layer of the alternating stack (32, 42) can be an insulating layer 32, which is referred to as the topmost insulating layer 32T below. The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the paired insulating layer 32 and the sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0126] Although in the previous embodiments, the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, in other embodiments, the sacrificial material layer is formed as a conductive layer. In such embodiments, the step of replacing the spacer material layer with a conductive layer can be omitted. In general, an alternating stack (32, 42) of insulating layers 32 and spacer material layers can be formed over at least one semiconductor material layer (112, 104, 116). The spacer material layer is formed as a conductive layer, or is subsequently replaced by the conductive layer.

[0127] refer to Figure 2 , a stepped surface is formed by patterning alternate stacking (32, 42). The area including the stepped surface is referred to as a step area in this article. As used herein, "stepped surface" refers to a group of surfaces including at least two horizontal surfaces and at least two vertical surfaces, so that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity 69 is formed in the volume, and the portion of the alternate stacking (32, 42) is removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0128] The stepped cavity 69 may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the bottom surface of the buffer dielectric layer 111. In one embodiment, the stepped cavity 69 may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more levels and a second type of etching process that laterally expands the area to be vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including an alternating plurality is defined as the relative position of a pair of first material layers and a second material layer within the structure.

[0129] Each sacrificial material layer 42 except the topmost sacrificial material layer 42 in the alternating stack (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from a bottommost layer in the alternating stack (32, 42) to a topmost layer in the alternating stack (32, 42).

[0130] In one embodiment, all layers in the alternating stack (32, 42) except the bottommost insulating layer 32, the bottommost sacrificial material layer 42, and the insulating layer 32 directly overlying the bottommost sacrificial material layer 42 may be patterned to provide a stepped surface. In this case, each layer in the alternating stack (32, 42) except the bottommost insulating layer 32, the bottommost sacrificial material layer 42, and the insulating layer 32 directly overlying the bottommost sacrificial material layer 42 may have a corresponding physically exposed sidewall exposed to the stepped cavity 69. In one embodiment, each physically exposed sidewall of the sacrificial material layer 42 may vertically coincide with a physically exposed sidewall of a corresponding overlying or underlying insulating material layer 32. In forming the stepped surface, the lateral extent of the sacrificial material layer 42 decreases as the vertical distance from the source level material layer (112, 103, 104, 105, 116) in the process decreases.

[0131] refer to Figure 3 , a photoresist layer (not shown) may be applied over the patterned alternating stack (32, 42), and the photoresist layer may be patterned to form a moat-shaped opening that laterally surrounds the corresponding remaining patterned portion of the photoresist layer. The pattern of the moat-shaped opening in the photoresist layer may be formed in an area where no more than one sacrificial material layer 42 is present. In other words, the pattern of the moat-shaped opening in the photoresist layer may be formed in an area where the bottom two sacrificial material layers 42 are present and no other sacrificial material layers 42 are present. An etching process may be performed to transfer the pattern of the moat-shaped opening in the photoresist layer through the underlying insulating layer 32 and the bottommost sacrificial material layer 42. Portions of the bottommost sacrificial material layer 42 are isolated from the rest of the bottommost sacrificial material layer 42 by cutting through the insulating layer 32 (which is the second insulating layer from the bottom 32) and the corresponding moat trench of the bottommost sacrificial material layer 42.

[0132] Each patterned portion of the bottommost sacrificial material layer 42 constitutes a sacrificial material plate 142. Each patterned portion of the insulating layer 32 constitutes an insulating plate 132. Each insulating plate 132 may have the same area as the underlying sacrificial material plate 142. Each sidewall of the sacrificial material plate 142 may vertically coincide with the sidewall of the corresponding overlying insulating plate 132. As used herein, if the second surface overlies the first surface or underlies the first surface and if there is a vertical plane including the first surface and the second surface, the first surface vertically coincides with the second surface. In one embodiment, each insulating plate 132 may contact the front horizontal surface of the corresponding sacrificial material plate 142. The sidewalls of each sacrificial material plate 142 may vertically coincide with the sidewalls of the corresponding insulating plate 132.

[0133] A stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed therein by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element exists. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the stepped dielectric material portion 65 has a lateral extent that increases gradually as the vertical distance from the carrier substrate 9 increases.

[0134] The stepped dielectric material portion 65 contacts the sidewalls of the insulating layer 32 of the alternating stack (32, 42). In one embodiment, the stepped dielectric material portion 65 contacts the stepped surface of the alternating stack (32, 42) and has a variable lateral extent that increases with increasing vertical distance from a horizontal plane including an interface between the alternating stack (32, 42) and the source level material layer (112, 103, 104, 105, 116) in the process.

[0135] Optionally, a drain select level isolation structure 72 may be formed through the topmost insulating layer 32T and a subset of the sacrificial material layer 42 at the drain select level. The drain select level isolation structure 72 may be formed, for example, by forming a drain select level isolation trench and filling the drain select level isolation trench with a dielectric material such as silicon oxide. Excess portions of the dielectric material may be removed from above the top surface of the topmost insulating layer 32T. Alternatively, the drain select level isolation structure 72 may be formed in a subsequent step of the process.

[0136] refer to Figure 4A photoresist material stack (not shown) including at least a photoresist layer may be formed over the topmost insulating layer 32T and the stepped dielectric material portion 65, and the photoresist material stack may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over a memory array region where each layer of the alternating stack (32, 42) exists and a second set of openings formed over a staircase region including a stepped surface of the alternating stack (32, 42). The pattern in the photoresist material stack may be transferred through the topmost insulating layer 32T or the stepped dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etch using the patterned photoresist material stack as an etch mask. Portions of the alternating stack (32, 42) below the openings in the patterned photoresist material stack are etched to form memory openings 49 and support openings 19. As used herein, "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, "support opening" refers to a structure in which a support structure (such as a support post structure) is subsequently formed to mechanically support other elements. Memory opening 49 is formed through the entirety of the topmost insulating layer 32T and the alternating stacks (32, 42) in the memory array region. Support opening 19 is formed through the stepped dielectric material portion 65 and the portion of the alternating stacks (32, 42) underlying the stepped surface in the staircase region.

[0137] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0138] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) onto the upper portion of the first source level semiconductor layer 112. The surface of the first source level semiconductor layer 112 may be physically exposed at the bottom of each memory opening 49 and the bottom of each support opening 19.

[0139] refer to Figure 5 , a sequence of processing steps may be performed to form a memory opening fill structure 58 in each memory opening 49 and to form a support post structure 20 in each support opening 19 .

[0140] In an illustrative example, a layer stack including a blocking dielectric layer 52, a memory material layer 54, and a dielectric material liner 56 may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0141] Subsequently, a memory material layer 54 may be formed. In general, the memory material layer may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store a data bit in the form of the presence or absence of charge, ferroelectric polarization direction, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (which may be silicon nitride, for example). Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0142] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and anisotropic etching process may be used to form the memory material layer 54 into a plurality of vertically spaced discrete memory material portions. Thus, in the above-described embodiments, the memory material layer 54 is a single continuous layer, but embodiments are expressly contemplated herein in which the memory material layer 54 is replaced by a plurality of vertically spaced discrete memory material portions (which may be charge trapping material portions or floating gates). The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed.

[0143] The dielectric material liner 56 is an optional material layer that may or may not be used. In the case where the memory material layer 54 includes a charge storage layer, the dielectric material liner 56 may include a tunneling dielectric layer, which includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The dielectric material liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, their alloys and / or their combinations. In one embodiment, the dielectric material liner 56 may include a stack of a silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the dielectric material liner 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of dielectric material liner 56 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0144] The semiconductor channel material layer may be conformally deposited in the memory opening 49 and in the support opening 19. The semiconductor channel material layer may include an undoped semiconductor material or a doped semiconductor material. The semiconductor channel material layer includes at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer may have uniform doping. In one embodiment, the semiconductor channel material layer includes amorphous silicon or polycrystalline silicon and includes a dopant of a first conductivity type, the atomic concentration of which is in the range of 1.0×1012 / cm3 to 1.0×1018 / cm3, such as 1.0×1014 / cm3 to 1.0×1017 / cm3. The thickness of the semiconductor channel material layer may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. A cavity may exist in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56).

[0145] In the case where the memory opening 49 and the support opening 19 are not completely filled with the semiconductor channel material layer, a dielectric core layer may be deposited in the unfilled volume of the memory opening 49 and / or the support opening 19. The dielectric core layer includes a dielectric material, such as silicon oxide or an organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self-planarization deposition process, such as spin coating. The horizontal portion of the dielectric core layer overlying the topmost surface of the vertical alternating sequence (32, 42) may be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0146] Doped semiconductor material having a second conductivity type doping may be deposited in a cavity overlying dielectric core 62. The second conductivity type is opposite to the conductivity type. For example, if the conductivity type is p-type, the second conductivity type is n-type, and vice versa. Portions of the deposited doped semiconductor material, semiconductor channel material layer, dielectric material liner 56, memory material layer 54, and blocking dielectric layer 52 overlying a horizontal plane (which includes the top surface of the topmost insulating layer 32T) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0147] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, although smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0148] Each remaining portion of the semiconductor channel material layer constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The dielectric material liner 56 is surrounded by the memory material layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, memory material layers 54, and dielectric material liner 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0149] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the dielectric material liner 56, a plurality of memory elements including a portion of the memory material layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. Generally speaking, the memory opening filling structure 58 is formed within the memory opening 49. Each of the memory opening filling structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0150] Each support opening 19 may be filled with a corresponding set of material portions having the same material composition as the corresponding components in the memory opening filling structure 58. Each set of material portions filling the support opening 19 is referred to herein as a support pillar structure 20. Generally speaking, the support pillar structure 20 is formed in the staircase area. Each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical memory element stack, which includes a portion of the corresponding memory material layer 54 located at the level of the sacrificial material layer 42. In the process, at least one semiconductor material layer (such as the first source level semiconductor layer 112 and / or the second source level semiconductor layer 116) within the source level material layer (112, 103, 104, 105, 116) contacts each memory opening filling structure in the memory opening filling structure 58.

[0151] refer to Fig. 6A and Figure 6B, a contact level dielectric layer 80 may be formed over the alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42, and over the memory opening fill structure 58 and the support pillar structure 20. The contact level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact level dielectric layer 80 may include silicon oxide formed by decomposing tetraethyl orthosilicate (TEOS). The contact level dielectric layer 80 may have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses may also be used.

[0152] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and photolithographically patterned to form first openings in the regions between the clusters of the memory opening fill structures 58 and second openings in the connection via region 200. Anisotropic etching may be used to transfer the pattern in the photoresist layer through the contact level dielectric layer 80, the alternating stacks (32, 42) and / or the stepped dielectric material portions 65 to form through-stack trenches 79 in the memory array region 100 and in the staircase region 300, and connection region trenches 77 in the connection region 200. Each of the through-stack trenches 79 vertically extends from the top surface of the contact level dielectric layer 80 to at least the top surface of the source level sacrificial layer 104. Each connection region trench 77 vertically extends from the top surface of the contact level dielectric layer 80 to at least the top surface of the upper sacrificial dielectric liner 105. The trench 79 penetrating the stack and the connection region trench 77 may be formed simultaneously.

[0153] According to an aspect of the present disclosure, each of the sacrificial material plates 142 may be partially etched during the formation of the connection region trenches 77, so that each remaining portion of the sacrificial material plates 142 has at least one sidewall physically exposed to a corresponding one of the connection region trenches 77. In one embodiment, during the formation of the connection region trenches 77, one or more sacrificial material plates 142 may be cut into a corresponding plurality of sacrificial material plates 142. In one embodiment, the memory opening filling structure 58 may be formed in the memory array region 100, the support pillar structure 20 and the stepped surface of the alternating stacks (32, 42) may be formed in the staircase region 300, and the sacrificial material plates 142 may be formed in the connection via region 200. The trenches 79 that penetrate the stacks may extend laterally and continuously throughout the memory array region 100 and the staircase region 300, and may optionally extend into the connection via region 200. The connection region trenches 77 may be formed in the connection via region 200.

[0154] In one embodiment, the trenches 79 that penetrate the stack may extend laterally along a first horizontal direction hd1, and may be spaced laterally from each other along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 may be arranged in rows extending along the first horizontal direction hd1. The drain selection level isolation structure 72 may extend laterally along the first horizontal direction hd1. Each trench 79 that penetrates the stack may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. Multiple rows of memory opening filling structures 58 may be located between an adjacent pair of trenches 79 that penetrate the stack and the drain selection level isolation structure 72, or between an adjacent pair of drain selection level isolation structures 72 (if present at this point in the process). In one embodiment, the trench 79 through the stack may include a source contact opening, wherein a source contact via structure may be subsequently formed.The photoresist layer may be removed, for example, by ashing.

[0155] refer to Figure 7 , a sacrificial etch stop material may be conformally deposited in the trenches 79 through the stack and the connection region trenches 77 and over the contact level dielectric layer 80, and the sacrificial etch stop material may be anisotropically etched to form sacrificial etch stop spacers 75 at peripheral portions of each of the trenches 79 through the stack and the connection region trenches 77. The sacrificial etch stop material is different from the material of the source level sacrificial layer 104. In an illustrative example, if the source level sacrificial layer 104 includes silicon nitride, the sacrificial etch stop material may include silicon oxide. The thickness of the sacrificial etch stop spacers 75 as measured between the inner sidewall and the outer sidewall of the respective sacrificial etch stop spacers 75 may be in the range of 10 nm to 100 nm, but smaller and larger thicknesses may also be employed.

[0156] refer to Figure 8, a selective isotropic etching process may be performed to etch the material of the source level sacrificial layer 104 selectively relative to the material of the lower sacrificial dielectric liner 103 and the upper sacrificial dielectric liner 105 and selectively relative to the material of the sacrificial etch stop spacer 75. For example, if the source level sacrificial layer 104 comprises silicon nitride, a wet etching process using hot phosphoric acid may be performed to selectively etch the source level sacrificial layer 104 relative to the sacrificial dielectric liner (103, 105), the sacrificial etch stop spacer 75, and the contact level dielectric layer 80. If the source level sacrificial layer 104 comprises undoped amorphous silicon, a wet etching process using tetramethylammonium hydroxide may be performed to selectively etch the source level sacrificial layer 104 relative to the sacrificial dielectric liner (103, 105), the sacrificial etch stop spacer 75, and the contact level dielectric layer 80. A source cavity 109 is formed in the volume from which the material of the source level sacrificial layer 104 is removed. During the etching of the source level sacrificial layer 104 , the sacrificial dielectric liner ( 103 , 105 ) may be incidentally etched in the source cavity 109 .

[0157] Subsequently, an isotropic etching process sequence may be performed to remove physically exposed portions of the memory film 50 in the memory opening filling structure 58 and in the support pillar structure 20. For example, the isotropic etching process sequence may sequentially etch portions of the blocking dielectric layer 52, the memory material layer 54, and the dielectric material liner 56. A cylindrical outer surface portion of each vertical semiconductor channel 60 may be physically exposed to the source cavity 109.

[0158] refer to Fig. 9 , a source contact layer 114 may be formed in the source cavity 109 by depositing a heavily doped semiconductor material (such as polysilicon or amorphous silicon) having a dopant of the second conductivity type in the source cavity 109. In one embodiment, the source contact layer 114 may be formed by a selective doped semiconductor deposition process, wherein a semiconductor precursor gas (such as silane, disilane, or dichlorosilane) and a dopant gas (such as phosphine, arsine, or antimonide) flow simultaneously or alternately with an etchant gas (such as hydrogen chloride gas) into the process chamber. In this case, a growth rate of the doped semiconductor material from the semiconductor surface is greater than an etching rate during the selective doped semiconductor deposition process, and a growth rate of the doped semiconductor material from the dielectric surface (such as the surface of the sacrificial etch stop spacer 75 and the contact level dielectric layer 80) is less than an etching rate during the selective doped semiconductor deposition process. Therefore, the doped semiconductor material grows only from the semiconductor surfaces of the first source level semiconductor and the second source level semiconductor layers ( 112 , 116 ) to fill the source cavity 109 , thereby forming a source contact layer 114 in the memory array region 100 and in the staircase region 300 .

[0159] Alternatively, the source contact layer 114 may be formed by a non-selective doped semiconductor deposition process. In this case, a doped semiconductor material (such as polysilicon or amorphous silicon) may be deposited on all physically exposed surfaces of the first exemplary structure. The duration of the non-selective doped semiconductor deposition process may be selected so that the entire volume of the source cavity 109 is filled with the doped semiconductor material. An etch-back process may be performed to remove portions of the doped semiconductor material present in the trenches 79 that penetrate the stack, in the connection region trenches 77, or above the contact level dielectric layer 80. The etch-back process may include an isotropic etching process or an anisotropic etching process. The remaining portion of the doped semiconductor material that fills the source cavity 109 constitutes the source contact layer 114.

[0160] The combination of the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 constitutes a source-level material layer (112, 114, 116) (e.g., a horizontal source region and / or a source contact line). In general, the source-level material layer (112, 114, 116) includes at least one doped semiconductor material layer. In one embodiment, each of the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 may be a doped semiconductor layer having a second conductivity type that is opposite to the first conductivity type of the vertical semiconductor channel 60. Therefore, a pn junction may be formed between the source contact layer 114 and the vertical semiconductor channel 60. The dopant concentrations in the first source-level semiconductor layer 112, the source contact layer 114, and the second source-level semiconductor layer 116 may be different from each other. In one embodiment, each of the vertical semiconductor channels 60 includes a respective cylindrical surface in contact with a respective surface segment of the source contact layer 114 .

[0161] refer to Fig.10 , an etchant that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 may be introduced into the through-stack trench 79 and the connection region trench 77, for example, using an etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 may be selectively removed relative to the first material of the insulating layer 32, the material of the stepped dielectric material portion 65, the semiconductor material of the source level material layer (112, 114, 116), and the material of the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0162] The etching process that selectively removes the second material relative to the first material and the outermost layer of the memory film 50 may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process that introduces an etchant in a vapor phase into the trench 79 that penetrates the stack and the connection area trench 77. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process that immerses the exemplary structure in a wet etching tank including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. When the backside recess 43 exists in the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support. In general, the backside recess 43 can be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32 and the memory opening filling structure 58.

[0163] Each back side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side recess 43 may be greater than the height of the back side recess 43. A plurality of back side recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory opening filling structure 58 is formed is referred to herein as the front side opening or the front side cavity, in contrast to the back side recess 43. In one embodiment, the memory array area includes an array of three-dimensional NAND strings. In this case, each back side recess 43 may define a space for receiving a corresponding word line of the three-dimensional NAND string array. Each back side recess in the plurality of back side recesses 43 may extend substantially parallel to the topmost surface of the source level material layer (112, 114, 116). The back side recess 43 may be vertically defined by the top surface of the lower insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each back-side recess 43 may have a uniform height throughout.

[0164] According to an aspect of the present disclosure, each of the sacrificial material plates 142 may be etched by an isotropic etchant of an etching process. A plate cavity 143 is formed in the volume from which the sacrificial material plate 142 is removed. Each of the plate cavities 143 abuts a corresponding one of the connection area grooves 77. Each of the plate cavities 143 may underlie a corresponding one of the insulation plates 132.

[0165] refer to Fig.11A backside blocking dielectric layer (not shown) may optionally be formed by conformal deposition on the physically exposed surfaces of the memory opening filling structure 58, the support pillar structure 20, the insulating layer 32, the contact level dielectric layer 80, and the source level material layer (112, 114, 116). The backside blocking dielectric layer (if present) includes a dielectric material used as a control gate dielectric for a control gate to be subsequently formed in the backside recess 43. In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer is present.

[0166] At least one conductive material may be deposited in the plurality of backside recesses, on the sidewalls of the trenches 79 that penetrate the stack, on the sidewalls of the connection region trenches 77, and over the contact layer dielectric layer 80. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0167] In one embodiment, at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filling material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess may be a combination of a titanium nitride layer and a tungsten filling material.

[0168] A conductive layer 46 may be formed in the backside recess 43 by depositing at least one conductive material. A metal plate 146 may be formed in the plate cavity 143 by depositing at least one conductive material. A plurality of conductive layers 46 may be formed in a plurality of backside recesses 43, and a continuous metal material layer (not shown) may be formed on the sidewalls of each through-stacked trench 79 and each connection region trench 77 and above the contact layer dielectric layer 80. Each of the conductive layers may include a corresponding conductive metal nitride liner and a corresponding conductive filling material. Therefore, the second sacrificial material layer 42 may be replaced with a conductive layer 46. Specifically, each sacrificial material layer 42 may be replaced with an optional portion of a backside blocking dielectric layer and a conductive layer 46. The backside cavity exists in a portion of each through-stacked trench 79 that is not filled with a continuous metal material layer, and in a portion of each connection region trench 77 that is not filled with a continuous metal material layer.

[0169] Residual conductive material may be removed from inside the through-stack trenches 79 and the connection region trenches 77. Specifically, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each through-stack trench 79, from the sidewalls of each connection region trench 77, and from above the contact level dielectric layer 80, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive layer 46. Each remaining portion of the deposited metal material in the plate cavity 143 constitutes a metal plate 146. The sidewalls of the conductive material layer 46 may be physically exposed to the corresponding through-stack trenches 79.

[0170] Each conductive layer 46 may be a conductive sheet including openings therein. A subset of the openings through each conductive layer 46 may be filled with a memory opening fill structure 58. A second subset of the openings through each conductive layer 46 may be filled with a support pillar structure 20. A subset of conductive layers 46 may include word lines for memory elements.

[0171] In a first embodiment, the spacer material layer is formed as a sacrificial material layer 42 and is subsequently replaced by a conductive layer 46. The metal plate 146 is formed by patterning the bottommost spacer material layer (i.e., the bottommost sacrificial material layer 42) into a sacrificial material plate 142 and then replacing the sacrificial material plate 142 with a portion of the metal material constituting the metal plate 146. The bottommost sacrificial material layer 42 is the sacrificial material layer closest to the source level material layer (112, 114, 116). The sacrificial material plate 142 may be replaced by the metal plate 146 by forming a trench 79 through the alternating stack (32, 46) and through the sacrificial material plate 142; forming a plate cavity 143 by removing the sacrificial material plate 142; and depositing the metal plate in the plate cavity 143 by providing a metal-containing precursor gas through the trench 79 through the stack into the plate cavity 143. Generally, a metal plate 146 is formed over the source level material layer (112, 114, 116) including at least one semiconductor material layer. The metal plate 146 may extend along a horizontal direction with a uniform vertical thickness.

[0172] Metal plate 146 may comprise the same material and have the same vertical thickness as bottommost conductive layer 46. Bottommost conductive layer 46 is the conductive layer 46 that is closest to the source level material layers (112, 114, 116).

[0173] The lateral extent of the conductive layer 46 decreases with decreasing vertical distance from the at least one semiconductor material layer (112, 114, 116). The dielectric material portion 65 contacts the stepped surface of the alternating stack (32, 46) and has a variable lateral extent that increases stepwise with increasing vertical distance from a horizontal plane including an interface between the alternating stack (32, 46) and the at least one semiconductor material layer (112, 114, 116).

[0174] refer to Fig.12 , an optional patterned film 73 may be applied over the contact level dielectric layer 80 by an anisotropic deposition method. The patterned film 73 may include a carbon-based material such as amorphous carbon or diamond-like carbon, and may be deposited by a plasma enhanced chemical vapor deposition process. A cavity may be formed in the lower portion of each through-stacked trench 79 in a volume not filled with the patterned film 73. The patterned film 73 may then be photolithographically patterned to remove the portion of the patterned film 73 located in the connection via region 200. The connection region trench 77 is physically exposed. Therefore, the patterned film 73 covers the through-stacked trench 79, but does not cover the connection region trench 77.

[0175] refer to Fig.13, a dielectric fill material such as silicon oxide may be deposited in the connection region trench 77 and over the patterned film 73. A recess etching process may be performed to remove the portion of the dielectric fill material deposited over the contact level dielectric layer 80. The remaining portion of the dielectric fill material filling the connection region trench 77 constitutes a trench dielectric fill structure 76. Generally speaking, the duration of the deposition process for depositing the dielectric fill material is selected so that the connection region trench 77 is completely filled with the dielectric fill material. The duration of the recess etching process may be selected so that the dielectric fill material is completely removed from over the top surface of the patterned film 73. In one embodiment, each dielectric trench fill structure 76 may be embedded in the dielectric material portion 65 and may be laterally spaced apart from each of the conductive layers 46.

[0176] refer to Fig.14 , the patterned film 75 may be removed, for example, by ashing.

[0177] refer to Fig.15 A conformal insulating material layer (such as a silicon oxide layer) may be deposited in the peripheral portions of the through-stack trenches 79 and over the contact level dielectric material layer 80. The thickness of the conformal insulating material layer may be in the range of 10 nm to 200 nm, although lesser and greater thicknesses may also be employed. An anisotropic etching process may be performed to remove the horizontal portions of the conformal insulating material layer. Each remaining vertical portion of the conformal insulating material layer remaining in a corresponding one of the through-stack trenches 79 constitutes an insulating trench spacer 74.

[0178] At least one conductive material may be deposited in the remaining unfilled volume of the through-stack trench 79, and excess portions of the at least one conductive filling material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the at least one conductive material constitutes a through-stack contact via structure 78. Each through-stack contact via structure 78 contacts at least one semiconductor material layer (112, 114, 116), namely, a source-level material layer (112, 114, 116). Each through-stack contact via structure 78 is laterally surrounded by an insulating trench spacer 74. Each adjoining combination of a through-stack contact via structure 78 and an insulating trench spacer 74 constitutes a through-stack trench filling structure (74, 78).

[0179] In an alternative embodiment, all trenches 79 that penetrate the stack may be filled with a corresponding dielectric trench filling structure. In this alternative embodiment, the Fig.12 , Fig.14 and Fig.15 Steps shown.

[0180] refer to Fig.16A and Fig. 16B, various via cavities may be formed through the contact level dielectric layer 80 and the stepped dielectric material portion 65. The via cavities may include a drain contact via cavity extending downward to the corresponding drain region 63 in the memory opening filling structure 58, a layer contact via cavity extending downward to the corresponding conductive layer 46 at or below the stepped surface of the alternating stack (32, 46) below the stepped dielectric material portion 65, and a connection via cavity extending downward to the top surface of the corresponding metal plate 146.

[0181] At least one conductive material may be deposited in each of the via cavities, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the contact-level dielectric layer 80. Each remaining portion of the at least one conductive material constitutes a via structure (88, 86, 84). The via structures (88, 86, 84) include drain contact via structures 88 formed in the drain contact via cavities and contacting a top surface of a corresponding one of the drain regions 63. Thus, the drain contact via structures 88 extend vertically through the contact-level dielectric layer 80 and contact an end surface of a corresponding one of the memory opening filling structures 58. The via structures (88, 86, 84) also include a layer contact via structure (e.g., word line and select gate contact) 86 formed in the layer contact via cavities and contacting a top surface of a corresponding one of the conductive layers 46. The via structures (88, 86, 84) further include a connection via structure (e.g., a word line terminal contact) 84 formed in the connection via cavity and contacting the top surface of a corresponding one of the metal plates 146. Each connection via structure 84 may be formed directly on the top surface of the corresponding metal plate 146 through the dielectric material portion 65. The connection via structure 84 is also referred to as a connection via structure passing through the memory level. The distal end surface of the drain contact via structure 88, the distal end surface of the layer contact via structure 86, and the distal end surface of the connection via structure 84 may be located in the same horizontal plane (such as a horizontal plane including the top surface of the contact level dielectric layer 80).

[0182] Generally, at least one connecting via structure 84 extends vertically through the dielectric material portion 65. The metal plate 146 may contact the proximal end surface of the corresponding connecting via structure 84. As used herein, the proximal end of the connecting via structure 84 refers to the end of the connecting via structure 84 that is close to the horizontal plane including the interface between the alternating stack (32, 46) and the source level material layer (112, 114, 116). In one embodiment, the insulating plate 132 may contact the front horizontal surface (i.e., the top surface) of each metal plate 146. The sidewalls of each metal plate 146 vertically coincide with the sidewalls of the corresponding overlying insulating plate 132. In one embodiment, the connecting via structure 84 extends vertically through the insulating plate 132 and contacts the top surface of the underlying metal plate 146.

[0183] A via-level dielectric layer 190 is formed over the contact-level dielectric layer 80. Various contact via structures (198, 196, 194) may be formed through the via-level dielectric layer 190. For example, a bit line connection via structure 198 may be formed on the drain contact via structure 88, a word line connection via structure 196 may be formed on the layer contact via structure 86, and a peripheral extension via structure 194 may be formed on the connection via structure 84.

[0184] A first line-level dielectric layer 90 is deposited over the via-level dielectric layer 190. Various metal line structures (98, 96, 94) are formed in the first line-level dielectric layer 90. The metal line structures (98, 96, 94) are referred to herein as first line-level metal interconnect structures. The various metal line structures (98, 96, 94) include bit lines 98 electrically connected to a corresponding plurality of drain contact via structures 88 (e.g., through bit line connection via structures 198), sub-line connection metal interconnect lines 96 electrically connected to a corresponding one of the layer contact via structures 86 (e.g., through sub-line connection via structures 196), and peripheral metal interconnect lines 94 electrically connected to a corresponding one of the connection via structures 94 (e.g., through peripheral extension via structures 194).

[0185] The bit lines 98 are electrically connected to upper ends of a corresponding subset of vertical semiconductor channels 60 in the memory opening filling structures 58 in the memory array area 100. In one embodiment, the memory opening filling structures 58 are arranged in rows extending along a first horizontal direction hd1, and the bit lines 98 extend laterally along a second horizontal direction hd2.

[0186] refer to Fig.17, providing a memory die 900 by performing additional processing steps. Specifically, an additional metal interconnect structure 168 embedded in the additional interconnect level dielectric layer 160 is formed. In an exemplary example, the additional interconnect level dielectric layer 160 may include a via level dielectric layer 110, a second line level dielectric layer 120, a second via level dielectric layer 130, and a bonding level dielectric layer 140. The metal interconnect structure 168 may include: a first metal via structure 108, the first metal via structure included in the first via level dielectric layer 110; a second metal line structure 118, the second metal line structure included in the second line level dielectric layer 120; a second metal via structure 128, the second metal via structure included in the second via level dielectric layer 130; and a memory side bonding pad 178 (such as a metal pad structure), the memory side bonding pad included in the bonding level dielectric layer 140. Generally, a first bond pad, such as memory-side bond pad 178, may be formed on the first metal interconnect structure.

[0187] Although in the previous embodiments, the additional interconnect level dielectric layer 160 includes the first via level dielectric layer 110, the second line level dielectric layer 120, the second via level dielectric layer 130 and the bonding level dielectric layer 140, embodiments in which the additional interconnect level dielectric layer 160 includes a different number and / or different combination of dielectric material layers are expressly contemplated herein. The memory die 900 includes a three-dimensional array of memory elements. An electrical connection path can be provided between each memory side bonding pad 178 and a corresponding set of metal interconnect structures {(194, 94, 108, 118, 128), (196, 96, 108, 118, 128) or (198, 98, 108, 118, 128)}. The memory die 900 includes a memory device 920 that may include a three-dimensional memory array including vertical NAND strings and memory-side metal interconnect structures (86, 88, 194, 94, 196, 96, 198, 98, 168). Generally, a memory-side dielectric material layer 160 embedding the memory-side metal interconnect structures (86, 88, 194, 94, 196, 96, 198, 98, 168) and memory-side bonding pads 178 may be formed over the alternating stacks (32, 46) to provide the memory die 900.

[0188] refer to Fig.18 and Fig.19, a logic die 700 may be provided, the logic die including a logic side substrate 709, a peripheral circuit 720 located on the logic side substrate 709 and including a logic side semiconductor device (such as a field effect transistor) and a logic side metal interconnect structure, and a logic side bonding pad 778. The peripheral circuit 720 may be configured to control the operation of the memory device 920 within the memory die 900. Specifically, the peripheral circuit 720 may be configured to drive various electrical components within the memory device 920, including (but not limited to) the conductive layer 46 (e.g., word lines and select gate electrodes) and the bit line 98.

[0189] Logic die 700 may be attached to memory die 900, for example, by bonding logic side bond pads 778 to memory side bond pads 178. The bonding between memory die 900 and logic die 700 may be performed using a wafer-to-wafer bonding process, wherein a two-dimensional array of memory die 900 is bonded to a two-dimensional array of logic die 700 by a die-to-bonding process or by a die-to-die bonding process.

[0190] Generally speaking, a component including at least one semiconductor material layer (112, 114, 116), an alternating stack (32, 46), a first dielectric material layer and a first bonding pad (such as a memory side bonding pad 178) can be bonded to a second bonding pad (such as a logic side bonding pad 778) located on a semiconductor die, which includes a second substrate, a semiconductor device, and a second metal interconnect structure embedded in the second dielectric material layer.

[0191] refer to Fig. 20 , the carrier substrate 9 can be removed and the backside flat surface of the buffer dielectric layer 111 can be physically exposed. For example, the carrier substrate 9 can be thinned by grinding, polishing, an isotropic etching process, and / or an anisotropic etching process. Other substrate removal processes can also be used.

[0192] refer to Fig.21 , a backside dielectric liner (602, 604) may be optionally formed on the backside planar surface of the buffer dielectric layer 111. The backside dielectric liner (602, 604) may include a layer stack of a first backside dielectric liner 602 and a second backside dielectric liner 604. For example, the first backside dielectric liner 602 may be a silicon nitride or silicon carbonitride liner having a thickness in the range of 10 nm to 200 nm, and the second backside dielectric liner 604 may be a silicon oxide liner having a thickness in the range of 10 nm to 200 nm.

[0193] A photoresist layer 607 may then be applied over the backside dielectric liner ( 602 , 604 ) and may be photolithographically patterned such that the patterned photoresist layer covers a continuous area including all memory opening fill structures 58 , and does not cover an area of ​​the metal plate 146 .

[0194] refer to Fig. 22 , an etching process sequence may be performed to remove portions of the backside dielectric liner (602, 604), the buffer dielectric layer 111, and the source level material layer (112, 103, 105, 116) that are not masked by the patterned photoresist layer 607. The etching process sequence may include at least one anisotropic etching process and / or at least one isotropic etching process. For example, the etching process sequence may include a first etching process to etch the material of the second backside dielectric liner 604, a second etching process to etch the material of the first backside dielectric liner 602, a third etching process to etch the dielectric material of the buffer dielectric layer 111 and the dielectric trench filling structure 76, and a fourth etching process to selectively etch the semiconductor material of the source level material layer (112, 103, 105, 116) relative to the insulating layer 32 and the dielectric trench filling structure 76. In one embodiment, the fourth etching process may be performed for a duration such that the recessed surface of the dielectric trench fill structure 76 is formed at or near a horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 103, 105, 116).

[0195] Portions of the source level material layer (112, 103, 105, 116) having an area overlap with the metal plate 146 are removed. Generally, the unmasked portions of the backside dielectric liner (602, 604), the buffer dielectric layer 111, and the source level material layer (112, 103, 105, 116) can be removed. Subsequently, the patterned photoresist layer 607 can be removed, for example, by ashing.

[0196] refer to Fig.23 , a backside dielectric material layer 620 may be deposited over the backside of the metal plate 146. The backside dielectric material layer 620 includes a dielectric material such as silicon oxide and may be deposited by a conformal or non-conformal deposition method. The vertical thickness of the planar portion of the backside dielectric material layer 620 may be in a range of 100 nm to 1,000 nm, such as 200 nm to 600 nm, although smaller and larger vertical thicknesses may also be employed.

[0197] refer to Fig.24, a first photoresist layer 611 may be applied over the backside dielectric material layer 620 and the first photoresist layer may be photolithographically patterned to form at least one opening overlying a corresponding subset of the metal plate 146. An anisotropic etching process may be performed to remove portions of the backside dielectric material layer 620 that are not masked by the first photoresist layer 611. The anisotropic etching process may also etch segments of the stepped dielectric material portion 65 and the dielectric trench filling structure 76 that are not masked by the first photoresist layer 611 or the metal plate 146. The sidewalls of the metal plate 146 may be physically exposed by the anisotropic etching process. The metal plate 146 acts as an etch stop layer during the etching process. A first backside contact via cavity 613 may be formed in each volume, from which the material of the backside dielectric material layer 620, the nearest insulating layer 32, and the segments of the stepped dielectric material portion 65 and the dielectric filling structure 76 are removed. The first photoresist layer 611 may then be removed, for example, by ashing.

[0198] refer to Fig.25 , a second photoresist layer 615 may be applied over the backside dielectric material layer 620, and the second photoresist layer may be photolithographically patterned to form at least one opening overlying the source level material layers (112, 114, 116) in the memory array region 100 (these source level material layers include at least one semiconductor material layer). An anisotropic etching process may be performed to remove portions of the backside dielectric material layer 620, the backside dielectric liner (602, 604), and the buffer dielectric layer 111 that are not masked by the second photoresist layer 615. The anisotropic etching process may be selective to the semiconductor material of the source level material layer (112, 114, 116). The backside surface of the source level material layer (112, 114, 116), such as the backside surface of the first source level semiconductor layer 112, may be physically exposed by the anisotropic etching process. A second backside contact via cavity 617 may be formed in each volume from which the material of the backside dielectric material layer 620, backside dielectric liner (602, 604) and buffer dielectric layer 111 are removed. The second photoresist layer 615 may then be removed, for example, by ashing.

[0199] refer to Fig.26, at least one metal material may be deposited in the opening in the backside dielectric material layer 620 and over the physically exposed backside surface of the backside dielectric material layer 620. The at least one metal material may include a metal liner layer and a metal layer. The metal liner layer may include a metal barrier material such as Ti, Ta, TiN, TaN, WN, MoN, or a combination thereof. The thickness of the metal liner layer may be in the range of 10nm to 100nm, but smaller and larger thicknesses may also be used. The metal layer includes a metal such as W, Mo, Ti, Ta, Ru, Co, Cu, Al, or any other suitable metal that can provide high conductivity. The thickness of the metal layer may be in the range of 100nm to 1,000nm, but smaller and larger thicknesses may also be used. The metal liner layer and the metal layer may be patterned to form a contact pad structure (628A, 628B). The patterning of the metal layer and the metal liner layer may employ a patterned photoresist layer and at least one etching process. Alternatively, the metal layer may be formed by electroplating while the metal pad layer is covered by a patterned photoresist layer. In this case, the portion of the metal pad layer not covered by the electroplated metal portion may be removed by an etching process. In general, any known process for forming the contact pad structure (628A, 628B) may be employed.

[0200] The contact pad structures (628A, 628B) may include at least one source contact pad structure 628A formed directly on a backside surface of at least one semiconductor material layer, such as a source level material layer (112, 114, 116). In addition, the contact pad structures (628A, 628B) may include at least one backside contact pad structure 628B formed directly on a backside surface of a corresponding subset of the metal plates 146. Each backside contact pad structure 628B may be in contact with at least one metal plate 146, may be spaced apart from at least one connecting via structure 84 by at least one metal plate 146, and may be electrically connected to at least one connecting via structure 84 by at least one metal plate 146.

[0201] Each source contact pad structure 628A contacts the backside surface of at least one semiconductor material layer (112, 114, 116) and includes the same set of materials as the backside contact pad structure 628B. In one embodiment, each source contact pad structure 628A may include a first metal liner 622A including the material of the metal liner layer and a first profile metal plate 624A including the material of the metal layer. Each backside contact pad structure 628B may include a second metal liner 622B including the material of the metal liner layer and a second profile metal plate 624B including the material of the metal layer.

[0202] In one embodiment, the second metal liner 622B contacts at least one sidewall of at least one metal plate 146, and optionally contacts at least one sidewall of at least one insulating plate 132. The second metal liner 622B may contact at least one horizontal surface segment of the stepped dielectric material portion 65 that is farther from the horizontal plane including the interface between the alternating stacks (32, 46) and the at least one semiconductor material layer (112, 114, 116) than the insulating plate 132. In one embodiment, the second metal liner 622B may contact a recessed end surface of the dielectric trench filling structure 76 that is farther from the horizontal plane including the interface between the alternating stacks (32, 46) and the at least one semiconductor material layer (112, 114, 116) than the insulating plate 132.

[0203] refer to Fig.27A , at least one backside dielectric capping layer (632, 634) may be deposited over the source contact pad structure 628A and the backside contact pad structure 628B. The at least one backside dielectric capping layer (632, 634) may include a first backside dielectric capping layer 632 and a second backside dielectric capping layer 634. In one embodiment, the first backside dielectric capping layer 632 may include a silicon oxide layer, and the second backside dielectric capping layer 634 may include a silicon nitride layer.

[0204] A passivation dielectric layer 636 may be formed over at least one backside dielectric cap layer (632, 634). The passivation dielectric layer 636 includes a passivation dielectric material such as polyimide. The passivation dielectric layer 636 may be patterned to form a via cavity (639A, 639B) therethrough. An etching process may be performed to form an opening through at least one backside dielectric cap layer (632, 634) over a respective one of the source contact pad structure 628A and the backside contact pad structure 628B below the via cavity (639A, 639B) in the passivation dielectric layer 636. The via cavity (639A, 639B) may extend vertically through the passivation dielectric layer 636 and the at least one backside dielectric cap layer (632, 634). The backside surface of one of the source contact pad structure 628A and the backside contact pad structure 628B is located at the bottom region of each via cavity (639A, 639B). The via cavity (639A, 639B) is also referred to as a backside via cavity, which can accommodate an external contact.

[0205] Fig.27B and Fig.27CAn alternative configuration of the first exemplary structure is shown, in which a via cavity 639B overlying the backside contact pad structure 628B is formed on a non-recessed portion of the backside contact pad structure 628B that is vertically offset from the recessed portion of the backside contact pad structure 628B that directly contacts the metal pad 146. The physically exposed area of ​​the backside contact pad structure 628B underlying the via cavity 639B may or may not have an area overlap with the metal pad 146. In addition, the physically exposed area of ​​the backside contact pad structure 628B underlying the via cavity 639B may or may not have an area overlap with the connected via structure 84. In addition, the area of ​​the via cavity 639B may or may not have an area overlap with the contact area between the backside contact pad structure 628B and the metal pad 146. The backside contact pad structure 628B may or may not have a vertical protrusion that contacts the sidewall of the metal plate 146. The backside contact pad structure 628B may contact a single metal pad 146, or may contact multiple metal pads 146. Generally, at least one backside dielectric cap layer (632, 634) includes an opening therethrough. Each opening may have an end periphery located on the backside surface of a respective one of the source contact pad structure 628A and the backside contact pad structure 628B.

[0206] refer to Fig.28A , showing a second exemplary structure according to the second embodiment of the present disclosure. The second exemplary structure includes a carrier substrate 9 and a buffer dielectric layer 111 formed on the carrier substrate 9. The carrier substrate 9 may be Figure 1 The first exemplary structure shown is the same. A buffer dielectric layer 111 may be deposited on the front side of the carrier substrate 9. The buffer dielectric layer 111 includes a dielectric material different from the material of the carrier substrate 9. For example, the buffer dielectric layer 111 may include silicon oxide. The thickness of the buffer dielectric layer 111 may be in the range of 50nm to 1,000nm, such as 100nm to 500nm, but smaller and larger thicknesses may also be used.

[0207] A photoresist layer 203 may be formed on the front surface of the buffer dielectric layer 111, and the photoresist layer may be photolithographically patterned to form an opening in a region where a connecting via structure will be subsequently formed. An etching process may be performed to vertically etch portions of the buffer dielectric layer 111 that are not masked by the photoresist layer 203. At least one recess 205 is formed in an upper region of the buffer dielectric layer 111. The photoresist layer 203 may then be removed, for example, by ashing.

[0208] refer to Fig.28B In an alternative configuration, the opening in the photoresist layer 203 may be formed only in the contact pad region where the metal plate will be formed later. In this configuration, each recess 205 is formed only in the region where the metal plate will be formed later in the region of the connecting via region 200.

[0209] refer to Fig.29 , the source level material layer (112, 103, 104, 105, 116) can be formed in the memory array area 100 and above the buffer dielectric layer 111 in the staircase area 300. As described above, the source level material layer (112, 103, 105, 116) can be formed in the process above the buffer dielectric layer 111 in the connecting via area 200. Each component in the source level material layer (112, 103, 104, 105, 116) can have the same Figure 1 The same material composition and the same thickness range as in the first exemplary structure shown. The topography of the recessed front surface of the buffer dielectric layer 111 is replicated on the top surface of the process source level material layer (112, 103, 105, 116) in the connecting via region 200, so that a recessed portion 205 is formed in the top surface of the second source level semiconductor layer 116 in the connecting via region 200.

[0210] refer to Fig.30 , a first insulating material layer, a metal material layer, and a second insulating material layer may be deposited above the source level material layer (112, 103, 104, 105, 116) during the process. Each of the first insulating material layer and the second insulating material layer includes an insulating material such as silicon oxide, silicon nitride, or a dielectric metal oxide. The metal material layer includes any metal material, such as W, Ti, Ta, Ru, Co, Mo, Cu, Ni, Pt, Pd, TiN, TaN, WN, MoN, their alloys, or stacks thereof. The first insulating material layer and the second insulating material layer may have respective thicknesses in the range of 5nm to 100nm, but smaller and larger thicknesses may also be used. The thickness of the metal material layer may be in the range of 10nm to 200nm, but smaller and larger thicknesses may also be used.

[0211] A photoresist layer 227 may be applied over the second insulating material layer, and the photoresist layer may be photolithographically patterned to cover discrete areas within a region (hereinafter referred to as a connecting via region 200) where a connecting via structure will subsequently be formed. An anisotropic etching process may be performed to transfer the pattern of the photoresist layer through the layer stack of the second insulating material layer, the metal material layer, and the first insulating material layer in the recess 205. Portions of the second insulating material layer, the metal material layer, and the first insulating material layer that are not masked by the photoresist layer 227 may be removed by the anisotropic etching process. Each patterned portion of the second insulating material layer and the first insulating material layer constitutes an insulating plate 232. Each patterned portion of the metal material layer constitutes a metal plate 246 located in the recess 205.

[0212] At least one plate stack including a first insulating plate 232, a metal plate 246, and a second insulating plate 232 may be formed above at least one semiconductor material layer (112, 114, 116) within a recessed region 205 in which a top surface of at least one semiconductor material layer (112, 114, 116) is vertically recessed. One, a plurality of, or each of the sidewalls of the metal plate 246 may vertically coincide with a corresponding sidewall of the overlying second insulating plate 232 and with a corresponding sidewall of the underlying first insulating plate 232. Subsequently, the photoresist layer 227 may be removed, for example, by ashing.

[0213] refer to Fig.31A , an alternating stack (32, 42) of insulating layers 32 and spacer material layers (such as sacrificial material layers 42) may be formed over at least one semiconductor material layer (112, 114, 116) and at least one plate stack (232, 246). Figure 1 The processing steps are described to form an alternating stack of insulating layers 32 and spacer material layers, such as sacrificial material layers 42 .

[0214] refer to Fig.31B , in such Fig.28B In the case where each recess 205 is formed in the region where the metal plate 246 is formed, the portion of the alternating stack (32, 42) located outside the region of the metal plate 246 can be flat. In other words, the topographical changes in the surface of the layers within the alternating stack (32, 42) can be minimized by forming the recess 205 only below the metal plate 246 and completely in the region of the connecting via area 200.

[0215] refer to Fig.32 ,refer to Figure 2 The described processing steps may be performed with any necessary modifications to form a stepped surface on the alternating stack (32, 42). In this case, patterning of the sacrificial material plates 142 and the insulating plates 132 may be omitted.

[0216] Then, you can execute the reference Figure 3 The processing steps are described to form the stepped dielectric material portion 65 and (optionally) the drain select level isolation structure 72. Alternatively, the drain select level isolation structure 72 may be formed in a later process step.

[0217] refer to Fig.33 , executable reference Figure 4 and Figure 5 The processing steps are described to form memory opening 49 and support opening 19 , as well as to form memory opening filling structure 58 in memory opening 49 and support opening 20 in support opening 19 , respectively.

[0218] refer to Fig.34A and Fig.34B , executable reference Fig. 6A and Figure 6B The processing steps are described to form the contact level dielectric layer 80 and the through-stack trench 79. The through-stack trench 79 may or may not cut through any of the metal plates 246. In one embodiment, the metal plates 246 are not physically exposed to the through-stack trench 79.

[0219] refer to Fig.35 , executable reference Figures 7 to 9 The processing steps described are to replace the source level sacrificial layer 104 with the source contact layer 114 in the memory array area 100 and the staircase area 300. Subsequently, the reference Fig.10 and Fig.11 The processing steps are described to replace sacrificial material layer 42 with conductive layer 46 .

[0220] In one embodiment, the metal plate 246 in the second exemplary structure extends along the second horizontal direction hd2 and has a uniform vertical thickness. The metal plate 246 and the alternating stack (32, 46) may be located on opposite sides of a horizontal plane including an interface between the at least one semiconductor material layer (112, 116) and the alternating stack (32, 46). In one embodiment, the metal plate 246 may include a different material or have a different thickness than the conductive layer 46 closest to the horizontal plane including the interface between the at least one semiconductor material layer (112, 116) and the alternating stack (32, 46).

[0221] refer to Fig.36 , executable reference Fig.12 , Fig.13 , Fig.14 and Fig.15 Processing steps are described to form optional through-stack trench fill structures (74, 78) within each through-stack trench 79.

[0222] refer to Fig.37 , executable reference Fig.16A and 16BThe processing steps described are used to form various via structures (88, 86, 84). The via structures (88, 86, 84) include drain contact via structures 88 formed in the drain contact via cavities and contacting the top surface of a corresponding one of the drain regions 63. The via structures (88, 86, 84) also include layer contact via structures 86 formed in the layer contact via cavities and contacting the top surface of a corresponding one of the conductive layers 46. The via structures (88, 86, 84) also include connection via structures 84 formed in the connection via cavities and contacting the top surface of a corresponding one of the metal plates 246. Each connection via structure 84 may be formed directly on the top surface of the corresponding metal plate 246 through the dielectric material portion 65. The connection via structures 84 are also referred to as connection via structures that pass through the memory level. Distal end surfaces of the drain contact via structure 88 , the layer contact via structure 86 , and the connection via structure 84 may lie within the same horizontal plane, such as a horizontal plane including a top surface of the contact level dielectric layer 80 .

[0223] In a second embodiment, at least one connecting via structure 84 extends vertically through the dielectric material portion 65. The metal plate 246 contacts the proximal end surface of the corresponding connecting via structure 84. In one embodiment, the insulating plate 232 may contact the front horizontal surface (i.e., the top surface) of each metal plate 246, and another insulating plate may contact the back surface (i.e., the bottom surface) of each metal plate 246. The sidewalls of each metal plate 246 vertically coincide with the sidewalls of the corresponding overlying insulating plate 232 and with the sidewalls of the corresponding underlying insulating plate 232. In one embodiment, the connecting via structure 84 extends vertically through the insulating plate 232 and contacts the top surface of the underlying metal plate 246.

[0224] Subsequently, a connecting via structure (198, 196, 194) embedded in the via level dielectric layer 190 may be formed. In addition, a metal line structure (98, 96, 94) embedded in the first line level dielectric layer 90 may be formed. In general, reference may be performed. Fig.16A and Fig. 16B Processing steps are described to form a metal interconnect structure embedded in a dielectric material layer.

[0225] refer to Fig.38 , executable reference Fig.17 , Fig.18 and Fig.19 Processing steps are described to provide the memory die 900 and the logic die 700 , and to bond the memory die 900 and the logic die 700 .

[0226] refer to Fig.39 , executable reference Fig. 20 Processing steps are described to remove the carrier substrate 9 from the bonded assembly of the memory die 900 and the logic die 700 .

[0227] refer to Fig.40 , executable reference Fig.21 Processing steps are described to form backside dielectric liners (602, 604) and patterned photoresist layer 607.

[0228] refer to Fig.41 , executable reference Fig. 22 Processing steps are described to remove unmasked portions of the backside dielectric liner (602, 604), buffer dielectric layer 111, and source level material layer (112, 116) (ie, at least one semiconductor material layer). The patterned photoresist layer 607 may then be removed, for example, by ashing.

[0229] refer to Fig.42 , executable reference Fig.23 Processing steps are described to form a backside dielectric material layer 620 .

[0230] refer to Fig.43 ,refer to Fig.24 The described processing steps may be performed with any necessary modifications to form the first backside contact via cavity 613. In this case, the etching process to form the first backside contact via cavity 613 may etch through the proximal insulating plate 232 within each plate stack (232, 246, 232), and the proximal horizontal surface of each metal plate 246 may be physically exposed to the corresponding first backside contact via cavity 613.

[0231] Then, you can execute the reference Fig.25 The processing steps are described to form the second backside contact via cavity 617 .

[0232] refer to Fig.44 , executable reference Fig.26 The processing steps are described to form contact pad structures (628A, 628B). The contact pad structures (628A, 628B) may include at least one source contact pad structure 628A and at least one backside contact pad structure 628B formed directly on the backside surface of a corresponding subset of the metal plates 246. Each backside contact pad structure 628B may be in contact with at least one metal plate 246, may be spaced apart from at least one connecting via structure 84 by at least one metal plate 246, and may be electrically connected to at least one connecting via structure 84 by at least one metal plate 246.

[0233] refer to Fig.45 , executable reference Fig.27AThe processing steps described are to form at least one backside dielectric cap layer (632, 634) and a passivation dielectric layer 636, and to form a via cavity (639A, 639B). Generally, at least one backside dielectric cap layer (632, 634) includes an opening therethrough. Each opening may have an end periphery located on a backside surface of a respective one of the source contact pad structure 628A and the backside contact pad structure 628B.

[0234] refer to Fig.46A and Fig.46B , showing a third exemplary structure according to the third embodiment of the present disclosure. The third exemplary structure includes a carrier substrate 9 and a buffer dielectric layer 111 formed on the carrier substrate 9. The carrier substrate 9 may be Figure 1 The first exemplary structure shown is the same. A buffer dielectric layer 111 may be deposited on the front side of the carrier substrate 9. The buffer dielectric layer 111 includes a dielectric material different from the material of the carrier substrate 9. For example, the buffer dielectric layer 111 may include silicon oxide. The thickness of the buffer dielectric layer 111 may be in the range of 5nm to 1,000nm, such as 20nm to 500nm, but smaller and larger thicknesses may also be used.

[0235] A photoresist layer 203 may be formed on the front surface of the buffer dielectric layer 111, and the photoresist layer may be photolithographically patterned to form an opening in a region where a connecting via structure will be subsequently formed. Generally speaking, the region of the opening in the photoresist layer 203 may be completely within the region of the connecting via region 200. An etching process may be performed to etch through the portion of the buffer dielectric layer 111 that is not masked by the photoresist layer 203. A recessed region 205 is formed in which the horizontal surface of the carrier substrate 9 is physically exposed. The physically exposed horizontal surface of the carrier substrate 9 may also be vertically recessed relative to a horizontal plane including an interface between the carrier substrate 9 and the buffer dielectric layer 111. The lateral offset between the periphery of the recessed region 205 and the periphery of the region where the metal plate will be subsequently formed may vary. Fig.46A An example is shown where the lateral offset distance is relatively large, and Fig.46B An example is shown where the lateral offset distance is relatively small. In general, the lateral offset between the periphery of the recessed area 205 and the periphery of the area where the metal plate will be subsequently formed can be less than the total thickness of the alternating stack (32, 42) to be subsequently formed, and can be about the thickness of a single insulating layer 32 or less, such as Fig.46B The photoresist layer 203 may then be removed, for example, by ashing.

[0236] refer to Fig.47A and Fig.47B, the processing steps described with reference to FIG. 28 may be performed to form the source level material layers (112, 103, 104, 105, 116) in the process. As discussed above, the source level sacrificial layer 104 may be present in the memory array region 100 and in the staircase region 300, and may not be present in the connecting via region 200. Subsequently, the processing steps described with reference to FIG. 28 may be performed to form the source level material layers (112, 103, 104, 105, 116) in the process. As discussed above, the source level sacrificial layer 104 may be present in the memory array region 100 and in the staircase region 300, and may not be present in the connecting via region 200. Fig.30 The processing steps are described to form at least one plate stack including a first insulating plate 232, a metal plate 246, and a second insulating plate 232 above at least one semiconductor material layer (112, 116) in a region where the top surface of the at least one semiconductor material layer (112, 116) is vertically recessed. One, a plurality of, or each of the sidewalls of the metal plate 246 may vertically coincide with a corresponding sidewall of the overlying second insulating plate 232 and with a corresponding sidewall of the underlying first insulating plate 232. The lateral offset between the sidewall of each metal plate 246 and the adjacent physically exposed sidewall of the second source level semiconductor layer 116 may vary. Fig.47A An example is shown where the lateral offset distance is relatively large (ie, the sidewall is outside the region shown), and Fig.47B An example of a relatively small lateral offset distance is shown. In general, the lateral offset between the sidewall of each metal plate 246 and the adjacent physically exposed sidewall of the second source-level semiconductor layer 116 can be less than the total thickness of the alternating stack (32, 42) to be formed later, and can be about the thickness of a single insulating layer 32 or less, such as Fig.47B shown.

[0237] refer to Fig.48 , you can refer to Figure 31, Fig.32 and Fig.33 The processing steps are described to form the alternating stacks (32, 42), the stepped dielectric material portion 65, the drain select level isolation structure 72, the memory opening fill structure 58 and the support pillar structure.

[0238] refer to Fig.49 , executable reference Fig.34A and Fig.34B as well as Figure 35 to Figure 37 Processing steps are described to form a contact level dielectric layer 80 and through-stack trenches 79, replace the source level sacrificial layer 104 with a source contact layer 114, replace the sacrificial material layer 42 with a conductive layer 46, form through-stack trench fill structures (74, 78) within each through-stack trench 79, form various through-stack structures (88, 86, 84), form connecting through-stack structures (198, 196, 194) embedded in the through-stack dielectric layer 190, and form metal line structures (98, 96, 94) embedded in the first line level dielectric layer 90.

[0239] refer to Fig.50 , executable Fig.38 and Fig.39 The processing steps are as follows to provide the memory die 900 and the logic die 700 , to bond the memory die 900 and the logic die 700 , and to remove the carrier substrate 9 from the bonded assembly of the memory die 900 and the logic die 700 .

[0240] refer to Fig.51 , executable Fig.40 The backside dielectric liner (602, 604) is formed by processing steps. The backside dielectric liner (602, 604) and the source level material layer (112, 103, 105, 116) are patterned to expose the insulating plate 232 in the connecting via region 200.

[0241] refer to Fig.52 , a backside dielectric material layer 620 is formed over the physically exposed insulating plate 232 over the backside dielectric liner (602, 604). Then, the backside dielectric material layer 620 and the exposed insulating plate 232 are patterned to form a first backside via cavity 613. At least one metal plate 246 is exposed in the first backside via cavity 613. The second backside via cavity 617 can be formed simultaneously with the first backside via cavity 613 or during a subsequent step.

[0242] Thereafter, a contact pad structure (628A, 628B), at least one backside dielectric cap layer (632, 634) and a passivation dielectric layer 636 and a via cavity (639A, 639B) are formed as described above with respect to the second embodiment. As in the previously described exemplary structure, the backside contact pad structure 628B may contact the backside horizontal surface of at least one metal plate 246, and may contact at least one sidewall (such as multiple sidewalls) of at least one metal plate 246, and may contact at least one sidewall of the insulating plate 232.

[0243] refer to Fig.53 , the recess 205 that enters or passes through the buffer dielectric layer 111 may be omitted. Fig.30 47 or a fourth exemplary structure according to a fourth embodiment of the present disclosure is derived from the third exemplary structure shown in FIG. 47. In this case, at least one plate stack including the first insulating plate 232, the metal plate 246, and the second insulating plate 232 may be formed above a horizontal plane including the topmost surface of at least one semiconductor material layer (112, 116) within the region 200 where the connecting via structure will be subsequently formed. One sidewall, multiple sidewalls, or each sidewall of the sidewalls of the metal plate 246 may be vertically coincident with the corresponding sidewall of the overlying second insulating plate 232 and with the corresponding sidewall of the underlying first insulating plate 232.

[0244] refer to Fig.54, the processing steps described with reference to FIG. 31 may be performed to form an alternating stack of insulating layers 32 and sacrificial material layers 46 .

[0245] refer to Fig.55 ,refer to Figure 2 The described processing steps may be performed with any necessary modifications to form a stepped surface on the alternating stack (32, 42). In this case, patterning of the sacrificial material plates 142 and the insulating plates 132 may be omitted.

[0246] Then, you can execute the reference Figure 3 Processing steps are described to form the stepped dielectric material portion 65 and (optionally) the drain select level isolation structure 72 .

[0247] refer to Fig.56 , executable reference Figure 4 and Figure 5 The processing steps are described to form memory opening 49 and support opening 19 , as well as to form memory opening filling structure 58 in memory opening 49 and support opening 20 in support opening 19 , respectively.

[0248] refer to Fig.57A and Fig.57B , executable reference Fig. 6A and Figure 6B The processing steps are described to form the contact level dielectric layer 80 and the through-stack trench 79. The through-stack trench 79 may or may not cut through any of the metal plates 246. In one embodiment, the metal plates 246 are not physically exposed to the through-stack trench 79.

[0249] refer to Fig.58 , executable reference Figures 7 to 9 The processing steps described are to replace the source level sacrificial layer 104 with the source contact layer 114 in the memory array area 100 and the staircase area 300. Subsequently, the reference Fig.10 and Fig.11 The processing steps are described to replace sacrificial material layer 42 with conductive layer 46 .

[0250] In one embodiment, the metal plate 246 in the fourth exemplary structure extends along the second horizontal direction hd2 and has a uniform vertical thickness. The metal plate 246 and the alternating stack (32, 46) may be located on the same side of a horizontal plane including an interface between the at least one semiconductor material layer (112, 116) and the alternating stack (32, 46). In one embodiment, the metal plate 246 may include a different material or have a different thickness than the thickness of the conductive layer 46 closest to the horizontal plane including the interface between the at least one semiconductor material layer (112, 116) and the alternating stack (32, 46).

[0251] Then, you can execute the reference Fig.12 , Fig.13 , Fig.14 and Fig.15 The processing steps described above are performed to form a through-stack trench fill structure (74, 78) within each through-stack trench 79. Fig.16A and 16B Processing steps are described to form various via structures (88, 86, 84).

[0252] Subsequently, a connecting via structure (198, 196, 194) embedded in the via level dielectric layer 190 may be formed. In addition, a metal line structure (98, 96, 94) embedded in the first line level dielectric layer 90 may be formed. In general, reference may be performed. Fig.16A and Fig. 16B Processing steps are described to form a metal interconnect structure embedded in a dielectric material layer.

[0253] refer to Fig.59 , executable reference Fig.17 , Fig.18 and Fig.19 Processing steps are described to provide the memory die 900 and the logic die 700 , and to bond the memory die 900 and the logic die 700 .

[0254] refer to Fig.60 , executable reference Fig. 20 The processing steps are described to remove the carrier substrate 9 from the bonded assembly of the memory die 900 and the logic die 700 .

[0255] refer to Fig.61 , executable reference Fig.21 The processing steps described above are used to form the backside dielectric liner (602, 604) and the patterned photoresist layer. Subsequently, the process described in reference Fig. 22 Processing steps are described to remove unmasked portions of the backside dielectric liner (602, 604), buffer dielectric layer 222, and source level material layer (112, 103, 105, 116). The patterned photoresist layer may then be removed, for example, by ashing.

[0256] refer to Fig.62 , executable reference Fig.23 The processing steps described above are used to form the backside dielectric material layer 620. Fig.24The described processing steps may be performed with any necessary modifications to form the first backside contact via cavity 613. In this case, the etching process to form the first backside contact via cavity 613 may etch through the proximal insulating plate 232, the metal plate 246, and the proximal insulating plate 232 within each plate stack (232, 246) of the distal insulating plate 232, and the proximal horizontal surface of each metal plate 246 may be physically exposed to the corresponding first backside contact via cavity 613. Subsequently, the reference may be performed Fig.25 The processing steps are described to form the second backside contact via cavity 617 .

[0257] refer to Fig.63 , executable reference Fig.26 The processing steps are described to form contact pad structures (628A, 628B). The contact pad structures (628A, 628B) may include at least one source contact pad structure 628A and at least one backside contact pad structure 628B formed directly on the backside surface of a corresponding subset of the metal plates 246. Each backside contact pad structure 628B may be in contact with at least one metal plate 246, may be spaced apart from at least one connecting via structure 84 by at least one metal plate 246, and may be electrically connected to at least one connecting via structure 84 by at least one metal plate 246.

[0258] refer to Fig.64 , executable reference Fig.27A The processing steps described are to form at least one backside dielectric cap layer (632, 634) and a passivation dielectric layer 636, and to form a via cavity (639A, 639B). Generally, at least one backside dielectric cap layer (632, 634) includes an opening therethrough. Each opening may have an end periphery located on a backside surface of a respective one of the source contact pad structure 628A and the backside contact pad structure 628B.

[0259] Common Reference Figures 1 to 64According to various embodiments related to the first exemplary structure to the fourth exemplary structure, a semiconductor structure is provided, the semiconductor structure comprising: an alternating stack (32, 46) of insulating layers 32 and conductive layers 46, the alternating stack being located on the front side of at least one semiconductor material layer (112, 114, 116); a memory opening 49, the memory opening vertically extending through the alternating stack (32, 46); a memory opening filling structure 58, the memory opening filling structure being located in the memory opening 49 and comprising a corresponding vertical semiconductor channel 60 and a corresponding A vertical memory element stack should be provided, wherein at least one semiconductor material layer (112, 114, 116) is in contact with the vertical semiconductor channel 60; a dielectric material portion 65; a connecting via structure 84, which extends vertically through the dielectric material portion 65; a metal plate (146, 246) which is in contact with the proximal end surface of the connecting via structure 84; and a back side contact pad structure 628B, which is in contact with the metal plate (146, 246) and is separated from the connecting via structure 84 by the metal plate (146, 246).

[0260] In one embodiment, the connecting via structure 84 has a variable horizontal cross-sectional area that increases with increasing vertical distance from a horizontal plane including the horizontal interface between the backside contact pad structure 628B and the metal plate (146, 246).

[0261] In one embodiment, the metal plate (146, 246) extends in a horizontal direction and has a uniform vertical thickness.

[0262] In one embodiment, the lateral extent of the conductive layer 46 decreases as the vertical distance from at least one semiconductor material layer (112, 114, 116) decreases; and the dielectric material portion 65 contacts the stepped surface of the alternating stack (32, 46) and has a variable lateral extent that increases as the vertical distance from a horizontal plane including an interface between the alternating stack (32, 46) and at least one semiconductor material layer (112, 114, 116).

[0263] In one embodiment, the semiconductor structure includes a contact level dielectric layer 80 located on the front side of the alternating stack (32, 46); and a drain contact via structure 88 extends vertically through the contact level dielectric layer 80 and contacts the end surface of a corresponding one of the memory opening filling structures 58, wherein the distal end surface of the drain contact via structure 88 and the distal end surface of the connecting via structure 84 are located in the same horizontal plane.

[0264] In one embodiment, the semiconductor structure includes an insulating plate (132, 232) that contacts a front horizontal surface of a metal plate (146, 246), wherein sidewalls of the metal plate (146, 246) vertically coincide with corresponding sidewalls of the insulating plate (132, 232), and a connecting via structure 84 vertically extends through the insulating plate (132, 232).

[0265] In one embodiment, the semiconductor structure includes: a back side dielectric material layer 620, which is located on the back side of at least one semiconductor material layer (112, 114, 116) and laterally surrounds and contacts a back side contact pad structure 628B; and at least one back side dielectric cap layer (632, 634), which is located on the back side of the back side dielectric material layer 620 and includes an opening therethrough, wherein an end periphery of the opening is located on the back side surface of the back side contact pad structure 628B.

[0266] In one embodiment, at least one semiconductor material layer ( 112 , 114 , 116 ) includes a source contact layer 114 including a doped semiconductor material; and each of the vertical semiconductor channels 60 includes a respective cylindrical surface in contact with a respective surface segment of the source contact layer 114 .

[0267] In one embodiment, the semiconductor structure includes a source contact pad structure 628A that contacts a backside surface of at least one semiconductor material layer (112, 114, 116) and includes the same set of materials as the backside contact pad structure 628B.

[0268] In one embodiment, the metal plate (146, 246) comprises the same material and has the same vertical thickness as the conductive layer 46 closest to the horizontal plane of the conductive layer 46 including the interface between the at least one semiconductor material layer (112, 114, 116) and the alternating stack (32, 46).

[0269] In one embodiment, the semiconductor structure includes a dielectric trench fill structure 76 contacting a sidewall of the dielectric material portion 65 and laterally spaced apart from the conductive layer 46 by the stepped dielectric material portion 65 .

[0270] In one embodiment, the semiconductor structure includes a through-stack contact via structure 78 that is laterally surrounded by insulating trench spacers 74 and contacts at least one semiconductor material layer ( 112 , 114 , 116 ).

[0271] In one embodiment, the metal plate (146, 246) and the at least one semiconductor material layer (112, 114, 116) are located on the same side of a horizontal plane including an interface between the at least one semiconductor material layer (112, 114, 116) and the alternating stack (32, 46).

[0272] In one embodiment, the metal plate (146, 246) and the alternating stack (32, 46) are located on the same side of a horizontal plane including an interface between at least one semiconductor material layer (112, 114, 116) and the alternating stack (32, 46); and the metal plate (146, 246) includes a different material than the conductive layer 46 closest to the horizontal plane including the interface between at least one semiconductor material layer (112, 114, 116) and the alternating stack (32, 46) or has a different thickness than the thickness of the conductive layer.

[0273] In one embodiment, a first metal interconnect structure is embedded in a first dielectric material layer above the alternating stack and the metal plate, a first bonding pad electrically contacts the first metal interconnect structure, and the semiconductor die includes a semiconductor device, a second metal interconnect structure embedded in a second dielectric material layer, and a second bonding pad bonded to the first bonding pad.

[0274] refer to Fig.65 , showing that the fifth embodiment according to the present disclosure can be Figure 1 The fifth exemplary structure is the same as the first exemplary structure shown.

[0275] refer to Fig.66 ,refer to Figure 2 The described processing steps may be performed in any necessary manner to form a stepped surface on the alternating stacks (32, 42) in the staircase region. In this case, the formation of the sacrificial material plate 142 and the insulating plate 132 may be omitted. Subsequently, the reference Figure 3 The processing steps are described to form the stepped dielectric material portion 65 and the drain select level isolation structure 72 .

[0276] refer to Fig.67 , executable reference Figure 4 The processing steps described above are used to form the storage opening 49 and the support opening 19. Subsequently, the reference Figure 5 The processing steps are described to form memory opening filling structure 58 and support pillar structure 20 .

[0277] refer to Fig.68 , executable reference Fig. 6A and Figure 6BThe processing steps are described to form the contact-level dielectric layer 80 and the through-stack trenches 79. The surface of the source-level sacrificial layer 104 may be physically exposed at the bottom of each through-stack trench 79.

[0278] refer to Fig.69 , executable reference Figures 7 to 9 The processing steps described in the embodiment of the present invention are to replace the source level sacrificial layer 104 with the source contact layer 114. Subsequently, the reference Fig.10 and Fig.11 The processing steps are described to replace sacrificial material layer 42 with conductive layer 46 .

[0279] In one embodiment, a backside blocking dielectric layer 44 may be deposited within each backside recess 43 prior to forming the conductive layer 46. In this case, the backside blocking dielectric layer 44 may be deposited directly on the cylindrical surface segments of the memory opening filling structure 58, the cylindrical surface segments of the support pillar structure 20, and the horizontal surface of the insulating layer 32. As discussed above, the backside blocking dielectric layer 44 includes a dielectric material used as a control gate dielectric for a control gate / word line that includes the conductive layer 46. In one embodiment, the backside blocking dielectric layer 44 may include and / or may be substantially composed of a dielectric metal oxide such as aluminum oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 1 nm to 12 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0280] Conductive layer 46 may be formed by depositing a metal barrier liner 46A and a metal filler material layer 46B within each of backside recesses 43. Metal barrier liner 46A includes a metal barrier material, such as a conductive metal nitride. For example, metal barrier liner 46A may include and / or may consist essentially of Ti, Ta, TiN, TaN, WN, or MoN. Metal barrier liner 46A may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The thickness of metal barrier liner 46A may be in the range of 1 nm to 6 nm, although lesser and greater thicknesses may also be employed.

[0281] Metal fill material layer 46B includes and / or consists essentially of a metal such as W, Ti, Ta, Co, Ru, Mo, Cu, etc. Metal fill material layer 46B may be formed by a conformal deposition process such as a chemical vapor deposition process. As discussed above, excess portions of at least one conductive material deposited to form conductive layer 46 may be removed from within trenches 79 through the stack and from above contact level dielectric layer 80 by an etch back process. Each conductive layer 46 includes a respective metal barrier liner 46A and a respective metal fill material layer 46B.

[0282] refer to Fig.70 , executable reference Figures 12 to 15Processing steps are described to form through-stack trench fill structures (74, 78) in through-stack trench 79.

[0283] refer to Fig.71 , a first photoresist layer (not shown) may be applied over the contact level dielectric layer 80, and the first photoresist layer may be photolithographically patterned to form openings over the stepped surface of the alternating stack (32, 46) in the staircase region. A first anisotropic etching process may be performed to etch through the contact level dielectric layer 80 and the portion of the stepped dielectric material portion 65 underlying the opening in the first photoresist layer. The chemistry of the first anisotropic etching process may be selected so that the first anisotropic etching process selectively etches the material of the contact level dielectric layer 80, the stepped dielectric material portion 65, and the backside blocking dielectric layer 44 relative to the metal material of the metal barrier liner 46A and the metal fill material layer 46B. In other words, the conductive layer 46 serves as an etch stop layer for the first anisotropic etching process. A layer contact via cavity 85 is formed under the opening in the first photoresist layer. Each layer contact via cavity 85 extends vertically from the top surface of the contact-level dielectric layer 80 into the corresponding conductive layer 46 .

[0284] In one embodiment, one, more than one, or each of the layer contact via cavities 85 may extend into the respective conductive layer 46 such that the recessed top surface of the respective conductive layer 46 is recessed relative to the topmost surface of the respective conductive layer 46. The vertical recessed distance of the recessed top surface may be in the range of 0.1% to 90% of the thickness of the respective conductive layer 46. In some embodiments, a metal oxide surface layer 46O may be formed on the recessed surface of the conductive layer 46 below the layer contact via cavity 85. The metal oxide surface layer 46O may include an oxide of the metal within the metal fill material layer 46B. For example, if the metal fill material layer 46B includes tungsten, the metal oxide surface layer 46O may include tungsten oxide. The first photoresist layer may be removed, for example, by ashing.

[0285] The connecting via cavity 83 may be formed through the stepped dielectric material portion 65, the bottommost insulating layer 32, and at least some of the source level material layers (112, 114, 116). The connecting via cavity 83 may be formed simultaneously with the layer contact via cavity 85 using a first anisotropic etching process and a patterned first photoresist layer as a mask.

[0286] Alternatively, a second photoresist layer (not shown) may be applied over the contact-level dielectric layer 80, and the second photoresist layer may be photolithographically patterned to form openings over areas where the conductive layer 46 and the trench fill structures (74, 78) that penetrate the stack are not present. A second anisotropic etching process may be performed to etch through the contact-level dielectric layer 80, the stepped dielectric material portion 65, the bottommost insulating layer 32, and the portions of the source-level material layer (112, 114, 116) that are not masked by the second photoresist layer. A connecting via cavity 83 may be formed below the opening in the second photoresist layer. In one embodiment, the connecting via cavity 83 may extend vertically through the second source-level semiconductor layer 116 and the source contact layer 114 and into an upper portion of the first source-level semiconductor layer 112. The second photoresist layer may be removed, for example, by ashing.

[0287] Generally, a contact via cavity, such as layer contact via cavity 85, may be formed through dielectric material portion 65 on a respective one of conductive layers 46. A connection via cavity 83 may be formed through contact level dielectric layer 80 and dielectric material portion 65 into at least one semiconductor material layer (112, 114, 116).

[0288] refer to Fig.72A and Fig.72B , a surface cleaning process such as a wet cleaning process may be performed to remove the metal oxide surface layer 46O and recess the semiconductor material of the source level material layer (112, 114, 116) without etching the metal material of the conductive layer 46 or the dielectric material of the insulating layer 32. For example, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) may be performed to selectively remove the metal oxide surface layer 46O (e.g., tungsten oxide layer) and selectively etch a proximal portion of the material of the source level material layer (112, 114, 116) at the bottom of each of the connecting via cavities 83. The isotropic etching process extends the bottom portion of each of the connecting via cavities 83 to below a horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layer (112, 114, 116).

[0289] refer to Fig.73A and Fig.73B, the isotropic etching process may be continued until adjacent pairs of connecting via cavities 83 are merged as the bottom portions of the connecting via cavities 83 expand below the horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 114, 116). Each merged portion of the connecting via cavities 83 located below the horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 114, 116) may have the general shape of a pad and is referred to herein as a pad cavity 83P. Thus, multiple connecting via cavities 83 may be interconnected to each other through a common pad cavity 83P.

[0290] Generally, the pad cavity 83P may be formed by recessing a portion of at least one semiconductor material layer (112, 114, 116) around a bottom region of two or more connecting via cavities 83. A continuous void is formed including the two or more connecting via cavities 83 and the pad cavity 83P. In one embodiment, a top portion of the pad cavity 83P may be vertically defined by a first horizontal plane located at an interface between the alternating stack (32, 46) and the at least one semiconductor material layer (112, 114, 116).

[0291] refer to Fig.74A and Fig.74B , a selective metal deposition process may be performed to grow metal portions from physically exposed metal surfaces or physically exposed semiconductor surfaces while inhibiting the growth of any metal from physically exposed dielectric surfaces. Such a selective metal deposition process may include a CVD or ALD process using a metal precursor gas that nucleates and forms metal deposits on metal surfaces and semiconductor surfaces without growing metal on dielectric surfaces. Such metal precursor gases include, but are not limited to, tungsten hexafluoride in a selective CVD process, or alternating ruthenium oxide deposition and hydrogen reduction steps in a selective ALD process. Other metal precursor gases may be used as long as the growth of metal on dielectric surfaces (such as the surface of insulating layer 32) can be inhibited.

[0292] The metal portion may be formed at the base region of each layer contact via cavity 85 and at the peripheral region of each pad cavity 83P. Each metal portion formed at the base region of the layer contact via cavity 85 is referred to herein as a first base metal portion 86A. Each metal portion formed at the peripheral region of each pad cavity 83P is referred to herein as a second base metal portion 82A. During the selective metal deposition process, each first base metal portion 86A grows from the physically exposed surface of the corresponding conductive layer 46 at the base region of the corresponding layer contact via cavity 85. During the selective metal deposition process, each second base metal portion 82A grows from the physically exposed surface of the source level material layer (112, 114, 116) at the peripheral region of the corresponding pad cavity 83P. In one embodiment, the entirety of each base metal portion 82A may be formed within the volume of the corresponding pad cavity 83P.

[0293] In some embodiments where the second base metal portion 82A includes and / or consists essentially of a metal that forms a metal-semiconductor alloy, such as a metal silicide, a surface metal-semiconductor compound layer (e.g., a metal silicide layer) 82S can be formed between the at least one semiconductor material layer (112, 114, 116) and each of the second base metal portions 82A by reacting a surface portion of the at least one semiconductor material layer (112, 114, 116) with a surface portion of the second base metal portion 82A during or after the selective metal deposition process. The thickness of the surface metal-semiconductor compound layer 82S can be in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, but lesser or greater thicknesses can also be used. In an illustrative example, both the first base metal portion 86A and the second base metal portion 82A include tungsten, and the surface metal-semiconductor compound layer 82S includes tungsten silicide.

[0294] Generally, the base metal material may be selectively deposited on the physically exposed surface of the conductive layer 46 and the physically exposed surface of at least one semiconductor material of the source level material layer (112, 114, 116). A first base metal portion 86A is formed on each physically exposed surface of each conductive layer 46, and a second base metal portion 82A is formed on each physically exposed surface of at least one semiconductor material of the source level material layer (112, 114, 116). A surface metal silicide 82S may be formed between the source level material layer (112, 114, 116) and the second base metal portion 82A.

[0295] refer to Fig.75, a drain contact via cavity may be formed above the drain region 63 in the memory opening filling structure 58. For example, a photoresist layer (not shown) may be applied above the contact level dielectric layer 80, and the photoresist layer may be photolithographically patterned to form an opening above the memory opening filling structure 58. Each opening in the photoresist layer may have an area overlap within the top surface of the drain region 63 in the corresponding underlying memory opening filling structure 58. The layer contact via cavity 85 and the connection via cavity 83 may be covered with a photoresist layer. An anisotropic etching process may be performed to etch through the portion of the contact level dielectric layer 80 that is not masked by the first photoresist layer. A drain contact via cavity may be formed below the opening in the first photoresist layer. The top surface of the drain region 63 may be physically exposed at the bottom of each drain contact via cavity. The photoresist layer may be removed, for example, by ashing.

[0296] The metal barrier material may be non-selectively deposited on physically exposed surfaces of the first base metal portion 86A, the second base metal portion 82A, and the drain region 63, and all other physically exposed surfaces of the drain contact via cavity, the layer contact via cavity 85, and the connection via cavity 83. A first metal barrier liner 86B may be formed on each first base metal portion 86A, a second metal barrier liner 82B may be formed on each second base metal portion 82A, and a third metal barrier liner (not explicitly shown) may be formed on each drain region 63. The metal barrier material may be deposited by a conformal deposition process such as chemical vapor deposition or a non-conformal deposition process such as physical vapor deposition. The metal barrier material may include a metal such as Ti or Ta and / or a conductive metal nitride material such as TiN, TaN, WN, or MoN. The thickness of the metal barrier material may be in the range of 3 nm to 30 nm, such as 6 nm to 15 nm, but smaller and larger thicknesses may also be used.

[0297] The metal filling material may be deposited in the remaining volume of the drain cavity, the layer contact via cavity 85, and the connecting via cavity 83. The metal filling material may include a metal such as W, Ti, Ta, Ru, Co, Mo, Cu, or a combination thereof. The metal filling material may be deposited by a conformal deposition method such as chemical vapor deposition. Excess portions of the metal filling material and the metal barrier material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process. For example, a chemical mechanical polishing (CMP) process may be used to implement the planarization process. Each remaining portion of the metal filling material filling the corresponding layer contact via cavity 85 constitutes a first metal filling material portion 86C. Each remaining portion of the metal filling material filling the corresponding connecting via cavity 83 constitutes a second metal filling material portion 82C. Each remaining portion of the metal filling material portion filling the corresponding drain cavity constitutes a third metal filling material portion (not explicitly shown).

[0298] Each contiguous combination of the first base metal portion 86A, the first metal barrier liner 86B, and the first metal fill material portion 86C constitutes a layer contact via structure (e.g., a word line contact via structure) 86. Each contiguous combination of the second base metal portion 82A, the optional surface metal-semiconductor alloy layer 82S, the second metal barrier liner 82B, and the second metal fill material portion 82C constitutes an integrated via and pad structure 82. The integrated via and pad structure 82 is formed in a continuous void including a pad cavity 83P and at least one connecting via cavity 83. Each continuous combination of a third metal barrier liner and a third metal fill material portion formed in a corresponding drain contact via cavity constitutes a drain contact via structure 88.

[0299] Generally, layer contact via structures 86 are contact via structures that contact a corresponding one of conductive layers 46. Thus, layer contact via structures 86 extend vertically through dielectric material portions 65 and contact a corresponding one of conductive layers 46. Each integrated via and pad structure 82 includes at least one conductive via portion 82V that extends vertically through dielectric material portion 65 and contacts a front side of conductive pad portion 82P. Backside contact pad structures 628B contact a planar backside surface of integrated via and pad structures 82 (i.e., a planar backside surface of pad portion 82P).

[0300] In one embodiment, each of the layer contact via structures 86 includes: a first base metal portion 86A, which contacts a corresponding one of the conductive layers 46; a first metal liner 86B, which contacts the first base metal portion 86A; and a first metal filling material portion 86C, which is laterally surrounded by the first metal liner 86B and vertically spaced apart from the first base metal portion 86A by a horizontally extending portion of the first metal liner 86B.

[0301] In one embodiment, each integrated through-hole and pad structure 82 includes: a second base metal portion 82A, which is completely located within the conductive pad portion 82P; a second metal liner 82B, which contacts the second base metal portion 82A; and a second metal fill material portion 82C, which is laterally surrounded by the second metal liner 82B.

[0302] In one embodiment, the first base metal portion 86A and the second base metal portion 82A have a first material composition (such as a material composition of a first metal (e.g., tungsten)); the first metal liner 86B and the second metal liner 82B have a second material composition (such as a material composition of a conductive metal nitride material) and the same thickness; and the first metal fill material portion and the second metal fill material portion 82C have a third metal composition (such as a material composition of a second metal (such as tungsten), which may be the same as or different from the material composition of the first metal).

[0303] In one embodiment, one, more than one, or each of the integrated via and pad structures 82 may include a corresponding additional conductive via portion 82V physically connected to the conductive pad portion 82P; and the second metal liner 82B and the second metal fill material portion 82C extend continuously from the conductive via portion 82V, through a portion of the conductive pad portion 82P and into the corresponding additional conductive via portion 82V.

[0304] In one embodiment, the end periphery of the conductive through-hole portion 82V is adjacent to the horizontal top surface of the conductive pad portion 82P; the conductive pad portion 82P includes a segment of the second metal liner 82B and a segment of the second metal filling material portion 82C; the first region of the horizontal top surface of the conductive pad portion 82P includes the surface of the second metal liner 82B; and the second region of the horizontal top surface of the conductive pad portion 82P includes the surface of the second base metal portion 82A.

[0305] In one embodiment, each of the conductive layers 46 includes a metal barrier liner 46A and a metal filler material layer 46B; and the metal barrier liner 46A and the metal filler material layer 46B are in direct contact with a corresponding one of the first base metal portions 86A. In one embodiment, each of the conductive layers 46 is vertically spaced apart from an adjacent one of the insulating layers 32 by a backside blocking dielectric layer 44 comprising a dielectric material; and each of the first base metal portions 86A is in direct contact with a corresponding surface segment of the backside blocking dielectric layer 44. In one embodiment, each of the first base metal portions 86A is in direct contact with a corresponding one of the insulating layers 32 at a corresponding cylindrical contact area.

[0306] In one embodiment, the vertical extent of the second metal liner 82B is greater than the vertical extent of the conductive via portion 82V and less than the sum of the vertical extent of the conductive pad portion 82P and the vertical extent of the conductive via portion 82V.

[0307] In one embodiment, at least one semiconductor material layer (112, 114, 116) may contact the alternating stack (32, 46) at an interface located in a first horizontal plane. In one embodiment, the conductive pad portion 82P includes a horizontal surface located in the first horizontal plane; and the conductive via portion 82V abuts the conductive pad portion 82P at a periphery located in the first horizontal plane.

[0308] In one embodiment, the distal end surface of the layer contact via structure 86 and the distal end surface of the conductive via portion 82V are located in a second horizontal plane (such as a horizontal plane including the top surface of the contact level dielectric layer 80), which is farther from the first horizontal plane than the farthest surface of the alternating stack (32, 46) is from the first horizontal plane.

[0309] In one embodiment, the integrated via and pad structure 82 includes a surface metal-semiconductor compound layer 82S that includes a compound of a metal within the second base metal portion 82A and a semiconductor material within the at least one semiconductor material layer (112, 114, 116).

[0310] In one embodiment, each conductive via portion 82V may have a variable horizontal cross-sectional area that increases with increasing vertical distance from the conductive pad portion 82P.

[0311] refer to Fig.76 , executable reference Fig.16A and Fig. 16B A subset of the processing steps are described to form connecting via structures ( 198 , 196 , 194 ) embedded in the via-level dielectric layer 190 , and to form metal line structures ( 98 , 96 , 94 ) embedded in the first line-level dielectric layer 90 .

[0312] refer to Fig.77 , executable reference Fig.17 , Fig.18 and Fig.19 Processing steps are described to provide the memory die 900 and the logic die 700 , and to bond the memory die 900 and the logic die 700 .

[0313] refer to Fig.78 , executable reference Fig. 20 Processing steps are described to remove the carrier substrate 9 from the bonded assembly of the memory die 900 and the logic die 700 .

[0314] refer to Fig.79 , executable reference Fig.21 Processing steps are described to form a backside dielectric liner (602, 604).

[0315] refer to Fig.80 , a patterned photoresist layer 607 is formed over the backside dielectric liner (602, 604). The backside dielectric liner (602, 604), the buffer dielectric layer 111, and the source level material layer (112, 114, 116) are patterned to remove the unmasked portions of the backside dielectric liner (602, 604), the buffer dielectric layer 111, and the source level material layer (112, 114, 116), so that the bottom surface of the integrated via and pad structure 82 is physically exposed.

[0316] refer to Fig.81 , a backside dielectric material layer 620 is formed over the integrated via and pad structure 82 and over the backside dielectric liner (602, 604). The backside dielectric material layer 620 is then patterned to form a first backside via cavity 613 that extends through a portion of the backside dielectric material layer 620 overlying the integrated via and pad structure 82. At least a bottom surface (e.g., a bottom surface and (optionally) at least one sidewall of the pad portion 82P) of the integrated via and pad structure 82 is physically exposed to the first backside via cavity 613. The second backside via cavity 617 may be formed simultaneously with the first backside via cavity 613 or during a subsequent step.

[0317] refer to Fig.82 , forming contact pad structures (628A, 628B) as described above with respect to the first embodiment or the second embodiment. As in the previously described exemplary structures, the backside contact pad structure 628B may contact the backside horizontal surface of the integrated via and pad structure 82 (i.e., the bottom of the pad portion 82P), and may contact at least one sidewall (such as multiple sidewalls) of the integrated via and pad structure 82 (i.e., the sidewall of the pad portion 82P). Then, at least one backside dielectric cap layer (632, 634), a passivation dielectric layer 636, and a via cavity (639A, 639B) are formed as described above with respect to the first embodiment or the second embodiment.

[0318] refer to Fig.83 , in the corresponding Fig.71The sixth exemplary structure according to the sixth embodiment of the present disclosure is shown at the processing step of the processing step. The sixth exemplary structure can be derived from the fifth exemplary structure by modifying the pattern of the trench 79 that penetrates the stack so that the portion of the source level sacrificial layer 104 located in the connecting via region is not replaced by the source contact layer 114. In this case, the layout of the trench 79 that penetrates the stack can be modified so that the trench 79 that penetrates the stack is laterally spaced from the connecting via region by a lateral spacing that is greater than the lateral etching distance of the isotropic etching process for etching the material of the source level sacrificial layer 104. The lateral extent of the source cavity 109 does not extend into the connecting via region. Therefore, the lateral extent of the source contact layer 114 does not extend into the connecting via region, where the source level sacrificial layer 104 still exists.

[0319] During the anisotropic etching process of etching the connecting via cavity 83, the etching chemistry of the terminal step of the anisotropic etching process can be selected so that the anisotropic etching process sequentially etches through the second source level semiconductor layer 116 and the source level sacrificial layer 104, and etches the upper portion of the first source level semiconductor layer 112.

[0320] refer to Fig.84A and Fig.84B , executable reference Fig.72A and Fig.72B The processing steps are described to recess the semiconductor material of the first source level semiconductor layer 112 and the second source level semiconductor layer 116 without etching the metal material of the conductive layer 46, the dielectric material of the insulating layer 32, or the material of the source level sacrificial layer 104. In one embodiment, the source level sacrificial layer 104 comprises silicon nitride, and a wet etching process using TMY can be performed to selectively etch the proximal portion of the material of the first source level semiconductor layer 112 and the second source level semiconductor layer 116 at the bottom of each of the connecting via cavities 83. The isotropic etching process extends the bottom portion of each of the connecting via cavities 83 to below the horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 114, 116).

[0321] refer to Fig.85A and Fig.85B, the isotropic etching process may continue until adjacent pairs of connecting via cavities 83 merge as bottom portions of the connecting via cavities 83 expand below a horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 114, 116). Each merged portion of the connecting via cavities 83 located below a horizontal plane including the interface between the alternating stacks (32, 46) and the source level material layers (112, 114, 116) may have the general shape of a pad and is referred to herein as a pad cavity 83P. Thus, a plurality of connecting via cavities 83 may be interconnected to one another via a common pad cavity 83P. In the sixth exemplary structure, a portion of the source level sacrificial layer 104, which may be a portion of a dielectric material layer such as a silicon nitride layer, may protrude from a sidewall of the pad cavity 83P and may include a plurality of holes therethrough corresponding to the plurality of holes at Fig.86A and Fig.86B The etched volume of the source level sacrificial layer 104 during the formation of the discrete connection via cavity 83 before the processing step of FIG.

[0322] Generally, the pad cavity 83P may be formed by recessing a portion of at least one semiconductor material layer (112, 116) around a bottom region of two or more connecting via cavities 83. A continuous void is formed including the two or more connecting via cavities 83 and the pad cavity 83P. In one embodiment, a top portion of the pad cavity 83P may be vertically defined by a first horizontal plane located at an interface between the alternating stack (32, 46) and the at least one semiconductor material layer (112, 114, 116).

[0323] refer to Fig.86A and 86B , executable Fig.74A and Fig.74B The processing steps are as follows to form a first base metal portion 86A, a second base metal portion 82A and (optionally) a surface metal-semiconductor compound layer 82S.

[0324] refer to Fig.87 , executable Fig.75 The processing steps are performed to form the layer contact via structure 86, the connecting via structure 84 and the drain contact via structure 88. Subsequently, Figures 76 to 82 The processing steps of the source contact layer 114 can be modified to provide various additional features. In this case, the anisotropic etching process that etches the unshielded portion of the source contact layer 114 can be modified to additionally etch the unshielded portion of the source level sacrificial layer 104. The non-semiconductor material portion 104' can be embedded in the conductive via portion 82P of the integrated via and pad structure 82. In one embodiment, the non-semiconductor material portion 104' can include a plurality of openings therethrough. In one embodiment, the non-semiconductor material portion 104' can be a dielectric material portion, such as a perforated silicon nitride plate.

[0325] Various embodiments of the present disclosure may be employed to provide reliable electrical contact between the backside contact pad structure 628B and at least one connecting via structure (84, 82V) through a flat metal pad (146, 246) or a conductive pad portion 82P. The flat metal pad (146, 246) or the flat conductive pad portion 82P acts as an etch stop during etching of the cavity 613 and provides a more reliable contact with the backside contact pad structure 628B than an exposed vertical protruding tip of the at least one connecting via structure (84, 82V). In addition, electrical contact with the conductive layer 46 or the backside contact pad structure 628B may be enhanced by a base metal portion (82A, 86A) that may be selectively deposited on metal surfaces and semiconductor surfaces.

[0326] Although specific preferred embodiments are mentioned above, it will be understood that the claims are not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the claims may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack being located on a front side of at least one layer of semiconductor material; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening and comprising a respective vertical semiconductor channel and a respective vertical memory element stack, wherein the at least one semiconductor material layer is in contact with the vertical semiconductor channel; Dielectric material section; a connecting via structure extending vertically through the dielectric material portion; a metal plate, the metal plate being in contact with a proximal end surface of the connecting through-hole structure; and A backside contact pad structure is in contact with the metal plate and is spaced apart from the connecting via structure by the metal plate.

2. The semiconductor structure of claim 1 , wherein the connecting via structure has a variable horizontal cross-sectional area that increases with increasing vertical distance from a horizontal plane including a horizontal interface between the backside contact pad structure and the metal plate. 3 . The semiconductor structure of claim 1 , wherein the metal plate extends along a horizontal direction and has a uniform vertical thickness.

4. The semiconductor structure of claim 1, wherein: The lateral extent of the conductive layer decreases with decreasing vertical distance from the at least one layer of semiconductor material; and The dielectric material portion contacts the stepped surface of the alternating stack and has a variable lateral extent that increases with increasing vertical distance from a horizontal plane including an interface between the alternating stack and the at least one semiconductor material layer.

5. The semiconductor structure according to claim 1, further comprising: a contact level dielectric layer on a front side of the alternating stack; and a drain contact via structure extending vertically through the contact level dielectric layer and contacting an end surface of a corresponding one of the memory opening filling structures, The distal end surface of the drain contact via structure and the distal end surface of the connection via structure are located in the same horizontal plane.

6. The semiconductor structure according to claim 1, further comprising an insulating plate, the insulating plate being in contact with the front horizontal surface of the metal plate, wherein the sidewalls of the metal plate vertically coincide with the corresponding sidewalls of the insulating plate, and the connecting via structure vertically extends through the insulating plate.

7. The semiconductor structure according to claim 1, further comprising: a backside dielectric material layer, the backside dielectric material layer being located over the backside of the at least one semiconductor material layer and laterally surrounding and contacting the backside contact pad structure; and At least one backside dielectric cap layer is located on the backside of the backside dielectric material layer and includes an opening therethrough, wherein an end periphery of the opening is located on the backside surface of the backside contact pad structure.

8. The semiconductor structure of claim 1, wherein: The at least one semiconductor material layer includes a source contact layer comprising a doped semiconductor material; and Each of the vertical semiconductor channels includes a respective cylindrical surface in contact with a respective surface segment of the source contact layer. 9 . The semiconductor structure of claim 1 , further comprising a source contact pad structure contacting a backside surface of the at least one semiconductor material layer and comprising a same set of materials as the backside contact pad structure.

10. The semiconductor structure of claim 1, wherein the metal plate comprises the same material composition and has the same vertical thickness as a conductive layer of the conductive layers closest to a horizontal plane including an interface between the at least one semiconductor material layer and the alternating stack.

11. The semiconductor structure according to claim 1, further comprising: a dielectric trench fill structure contacting a sidewall of the dielectric material portion; and A contact via structure penetrates the stack and is laterally surrounded by insulating trench spacers and contacts the at least one semiconductor material layer.

12. The semiconductor structure of claim 1, wherein the metal plate and the at least one semiconductor material layer are located on the same side of a horizontal plane including an interface between the at least one semiconductor material layer and the alternating stack.

13. The semiconductor structure of claim 1, wherein: The metal plate and the alternating stack are located on the same side of a horizontal plane including an interface between the at least one semiconductor material layer and the alternating stack; and The metal plate comprises a different material than or has a different thickness than that of the conductive layer closest to the horizontal plane comprising the interface between the at least one semiconductor material layer and the alternating stack.

14. The semiconductor structure according to claim 1, further comprising: a first metal interconnect structure embedded in a first dielectric material layer over the alternating stack and the metal plate; a first bonding pad, the first bonding pad electrically contacting the first metal interconnect structure; and A semiconductor die includes a semiconductor device, a second metal interconnect structure embedded in a second dielectric material layer, and a second bonding pad bonded to the first bonding pad.

15. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and spacer material layers over at least one semiconductor material layer over the first substrate, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by the conductive layers; forming a metal plate over the at least one semiconductor material layer; forming a dielectric material portion; forming a memory opening through the alternating stack; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures includes a respective vertical semiconductor channel and a respective vertical memory element stack; forming a connecting via structure directly on the top surface of the metal plate through the dielectric material portion; removing a portion of the at least one semiconductor material layer having an area overlapping with the metal plate; as well as A backside contact pad structure is formed directly on the exposed backside surface of the metal plate.

16. The method of claim 15, wherein: The spacer material layer is formed as a sacrificial material layer, which is subsequently replaced by the conductive layer; and The metal plate is formed by patterning a spacer material layer of the spacer material layers that is closest to the at least one semiconductor material layer into a sacrificial material plate and then partially replacing the sacrificial material plate with a metal material.

17. The method according to claim 16, further comprising: forming a connection region trench through the dielectric material portion and through the sacrificial material plate; forming a plate cavity by removing the sacrificial material plate; as well as The metal material portion is deposited in the plate cavity by providing a metal-containing precursor gas into the plate cavity through the connection region grooves.

18. The method according to claim 15, further comprising: forming a plate stack including an insulating plate and the metal plate over the at least one semiconductor material layer; forming said alternating stack above said plate stack; as well as Portions of the alternating stack are removed from over the plate stack by patterning the alternating stack, wherein the dielectric material portion is formed over the plate stack after patterning the alternating stack.

19. The method according to claim 18, further comprising: forming a buffer dielectric layer having a uniform thickness over a substrate, wherein the at least one semiconductor material layer is formed over the buffer dielectric layer; as well as A recess is formed in an upper portion of the buffer dielectric layer, wherein the plate stack is formed within the recess.

20. The method according to claim 15, further comprising: forming a first metal interconnect structure embedded in a first dielectric material layer over the alternating stacks and the connecting via structure; forming a first bonding pad on the first metal interconnect structure; bonding an assembly including the at least one semiconductor material layer, the alternating stack, the first dielectric material layer, and the first bonding pad to a second bonding pad located on a semiconductor die, the semiconductor die including a second substrate, a semiconductor device, a second metal interconnect structure embedded in the second dielectric material layer; removing the first substrate; depositing a backside dielectric material layer over a backside of the at least one semiconductor material layer; as well as An opening is formed through the backside dielectric material layer using the metal plate as an etch stop to expose the backside surface of the metal plate.

21. A semiconductor structure, comprising: Alternating stacking of insulating and conducting layers; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening and comprising a corresponding vertical semiconductor channel and a corresponding vertical memory element stack; Dielectric material section; a contact via structure extending vertically through the dielectric material portion and contacting a corresponding one of the conductive layers; an integrated via and pad structure including a conductive via portion extending vertically through the dielectric material portion and contacting a front side of a conductive pad portion; and A backside contact pad structure contacts the planar backside surface of the integrated via and pad structure.

22. The semiconductor structure of claim 21 , wherein each of the contact via structures comprises: a first base metal portion in contact with the corresponding one of the conductive layers; a first metal pad, the first metal pad being in contact with the first base metal portion; and a first metallic fill material portion, the first metallic fill material portion being laterally surrounded by the first metallic liner and vertically spaced apart from the first base metal portion by a horizontally extending portion of the first metallic liner.

23. The semiconductor structure of claim 22, wherein the integrated via and pad structure comprises: a second base metal portion, the second base metal portion being completely located within the conductive pad portion; a second metal pad contacting the second base metal portion; and a second metallic fill material portion, the second metallic fill material portion being laterally surrounded by the second metallic liner.

24. The semiconductor structure of claim 23, wherein: The first base metal portion and the second base metal portion have a first material composition; The first metal liner and the second metal liner have a second material composition and a same thickness; and The first metallic fill material portion and the second metallic fill material portion have a third metallic composition.

25. The semiconductor structure of claim 23, wherein: The integrated via and pad structure includes an additional conductive via portion physically connected to the conductive pad portion; and The second metal liner and the second metal fill material portion extend continuously from the conductive via portion, through a portion of the conductive pad portion and into the additional conductive via portion.

26. The semiconductor structure of claim 23, wherein: The end periphery of the conductive via portion abuts against the horizontal top surface of the conductive pad portion; The conductive pad portion includes a segment of the second metal liner and a segment of the second metal fill material portion; A first region of the horizontal top surface of the conductive pad portion includes a surface of the second metal pad; and A second region of the horizontal top surface of the conductive pad portion includes a surface of the second base metal portion.

27. The semiconductor structure of claim 22, wherein: Each of the conductive layers includes a metal barrier liner and a metal filling material layer; and The metal barrier liner and the metal filler material layer are in direct contact with a corresponding one of the first base metal portions.

28. The semiconductor structure of claim 27, wherein: Each of the conductive layers is vertically spaced apart from an adjacent one of the insulating layers by a backside blocking dielectric layer comprising a dielectric material; and Each of the first base metal portions is in direct contact with a corresponding surface segment of the backside blocking dielectric layer.

29. The semiconductor structure of Claim 27, wherein each of said first base metal portions is in direct contact with a respective one of said insulating layers at a respective cylindrical contact region.

30. The semiconductor structure of claim 23, wherein a vertical extent of the second metal liner is greater than a vertical extent of the conductive via portion and is less than a sum of a vertical extent of the conductive pad portion and a vertical extent of the conductive via portion.

31. The semiconductor structure of claim 21, further comprising at least one source-level semiconductor material layer contacting the alternating stack at an interface within a first horizontal plane and contacting an end portion of the vertical semiconductor channel.

32. The semiconductor structure of claim 31 , wherein: The conductive pad portion includes a horizontal surface located within the first horizontal plane; and The conductive via portion adjoins the conductive pad portion at a periphery that lies within the first horizontal plane.

33. The semiconductor structure of claim 31 , wherein: The distal end surfaces of the contact via structures and the distal end surfaces of the conductive via portions are located in a second horizontal plane that is farther from the first horizontal plane than the distal-most surfaces of the alternating stacks are from the first horizontal plane; and The integrated via and pad structure includes a surface metal-semiconductor compound layer including a compound of a metal within the second base metal portion and a semiconductor material within the at least one semiconductor material layer.

34. The semiconductor structure of claim 21, the method further comprising: a first metal interconnect structure embedded in a first dielectric material layer over the alternating stack and the integrated via and pad structure; a first bonding pad, the first bonding pad electrically contacting the first metal interconnect structure; and A semiconductor die includes a semiconductor device, a second metal interconnect structure embedded in a second dielectric material layer, and a second bonding pad bonded to the first bonding pad.

35. The semiconductor structure of Claim 21, wherein the conductive via portion has a variable horizontal cross-sectional area that increases with increasing vertical distance from the conductive pad portion.

36. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and spacer material layers over at least one semiconductor material layer over the first substrate, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by the conductive layers; forming a dielectric material portion; forming a contact via cavity through the dielectric material portion on a corresponding one of the conductive layers; forming a connecting via cavity through the dielectric material portion into the at least one semiconductor material layer; forming a pad cavity by recessing a portion of the at least one semiconductor material layer around a bottom region of the connecting via cavity, wherein a continuous void including the connecting via cavity and the pad cavity is formed; as well as A contact via structure is formed in the contact via cavity and an integrated via and pad structure is formed in the continuous void.

37. The method of claim 36, further comprising: selectively depositing a base metal material on physically exposed surfaces of the conductive layer and on physically exposed surfaces of at least one semiconductor material, wherein a first base metal portion is formed on each physically exposed surface of the conductive layer and a second base metal portion is formed on the physically exposed surfaces of the at least one semiconductor material; as well as A metal barrier material is non-selectively deposited wherein a first metal barrier liner is formed on each first base metal portion and a second metal barrier liner is formed on the second base metal portion.

38. The method of claim 37, further comprising: forming a surface metal-semiconductor compound layer by reacting a surface portion of the at least one semiconductor material layer with a surface portion of the second base metal portion; forming a contact level dielectric layer over the alternating stack and the dielectric material portion, wherein the contact via cavity and the connecting via cavity are formed through the contact level dielectric layer; depositing a metal fill material on the first metal barrier liner and on the second metal barrier liner; as well as Portions of the first metal barrier liner, the second metal barrier liner, and the metal fill material are removed from above a horizontal plane including a top surface of the contact-level dielectric layer.

39. The method of claim 36, further comprising: forming a memory opening through the alternating stack; as well as A memory opening filling structure is formed in the memory opening, and the memory opening filling structure includes a corresponding vertical semiconductor channel and a corresponding vertical memory element stack, wherein the at least one semiconductor material layer includes at least one source level semiconductor material layer contacting an end portion of the vertical semiconductor channel.

40. The method of claim 39, further comprising: forming a first metal interconnect structure embedded in a first dielectric material layer over the alternating stacks and the integrated via and pad structure; forming a first bonding pad on the first metal interconnect structure; bonding an assembly including the at least one semiconductor material layer, the alternating stack, the first dielectric material layer, and the first bonding pad to a second bonding pad located on a semiconductor die, the semiconductor die including a second substrate, a semiconductor device, a second metal interconnect structure embedded in the second dielectric material layer; removing the first substrate; depositing a backside dielectric material layer over a backside of the at least one semiconductor material layer after removing the first substrate; forming an opening through the backside dielectric material layer to expose a planar backside surface of the pad of the integrated via and pad structure using the pad as an etch stop; as well as A backside contact pad structure is formed in the opening and contacts the planar backside surface of the pad.

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