Chip testing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip testing method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductor testing, and the method comprises the steps: building a fool-proof detection mechanism, carrying out the horizontal scanning of a wafer through employing a horizontal movement mode of camera equipment and the fool-proof detection mechanism, obtaining a horizontal wafer, and carrying out the testing of the horizontal wafer. Obtaining the circle center position and diameter of the wafer according to the feature point position of the wafer, a distance calculation formula and the visual identification function of the camera, and obtaining a Map map of the wafer according to the size of each chip and the size of a cutting channel in the wafer, the distance between the chips and the circle center position and the feature point position of the wafer; and acquiring a needle tip deviation angle through the camera, rotating the wafer according to the needle tip deviation angle, updating the Map according to the needle tip deviation angle, and carrying out chip testing according to the Map. According to the invention, the problems of poor compatibility, low automation degree, low production efficiency and low accuracy in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a chip testing method, device, electronic equipment and storage medium. Background Art

[0002] With the rapid development of semiconductor technology, the size and type of chips integrated on wafers are becoming more and more diverse. In the wafer testing process, MAP diagram (test mapping diagram) plays a vital role, which can accurately locate the position of each chip, thereby ensuring the accuracy and efficiency of the test.

[0003] However, in traditional wafer chip testing solutions, the design and application of MAP diagrams have obvious limitations. They are often only compatible with chips of one size and model for testing. When there are chips of multiple sizes on the wafer, it is necessary to establish MAP diagrams for each size of chip separately. This not only greatly reduces production efficiency, but also increases the risk of errors.

[0004] In addition, existing MAP image creation methods, such as manual creation or chip scanning generation, have problems such as high time cost and low precision. Especially in multi-site needle card testing, due to the difference in the needle tip angle between the single-site needle card and the multi-site needle card, the traditional test scheme often requires manual adjustment of the needle card position to align the wafer chip's test pad position, which is not only complicated to operate, but also very easy to introduce errors, seriously affecting the accuracy and efficiency of the test.

[0005] Therefore, a chip testing method is needed that is compatible with chips of multiple sizes, has a high degree of automation, and has high pin mark detection accuracy. Summary of the invention

[0006] Each embodiment of the present invention provides a chip testing method to solve the problem that the prior art is not compatible with chips of multiple sizes, has a low degree of automation, and has low production efficiency and accuracy. The technical solution is as follows: According to one aspect of the present invention, a chip testing method includes: establishing an anti-fool detection mechanism, using a camera to move horizontally and the anti-fool detection mechanism to scan a wafer horizontally to obtain a horizontal wafer; obtaining the center position and diameter of the wafer according to the feature point position of the wafer, a distance calculation formula and the visual recognition function of the camera; obtaining a Map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer; obtaining a needle tip offset angle through a camera, rotating the wafer according to the needle tip offset angle and updating the Map according to the needle tip offset angle, and performing chip testing according to the Map.

[0007] In one of the embodiments, the wafer is horizontally scanned and straightened using the horizontal movement of the camera device and the anti-fool detection mechanism, and the horizontal wafer is obtained by the following steps: the wafer is loaded directly under the camera device through a carrier table, the position of the chip is automatically obtained by the camera device, the horizontal angle of the wafer is adjusted by two-point continuous positioning and slope angle calculation, and the anti-fool detection mechanism is used for verification. If the verification passes, the horizontal wafer is obtained.

[0008] In one embodiment, the slope angle calculation formula is: ; The difference in the longitudinal coordinates refers to the difference between the longitudinal coordinate of the chip during the movement and the initial longitudinal coordinate, and the difference in the horizontal coordinates refers to the difference between the horizontal coordinate of the chip during the movement and the initial horizontal coordinate; the fool-proof detection mechanism is that if the slope angle is less than or equal to the set angle, the horizontal scanning is successful, and if the slope angle is greater than the set angle, the horizontal scanning is performed again.

[0009] In one of the embodiments, the center position and diameter of the wafer are obtained according to the feature point positions of the wafer, the distance calculation formula and the visual recognition function of the camera through the following steps: a two-dimensional coordinate system is constructed with the feature point of the wafer as the origin, and the three edge point positions of the wafer are obtained through the distance calculation formula and the visual recognition function of the camera; the center position and diameter of the wafer are calculated according to the principle of three points forming a circle and the three edge point positions; the position is checked for accuracy according to the size of the wafer and the diameter, and if the position is inaccurate, the center position is recalculated.

[0010] In one embodiment, according to the size of each chip in the wafer and the size of the cutting road, the distance between the chips, and the center position and feature point position of the wafer, obtaining the Map of the wafer is achieved by the following steps: ; ; Among them, X represents the horizontal coordinate of each chip, and Y represents the vertical coordinate of each chip. Represents the horizontal coordinate of the feature point, Represents the ordinate of the feature point, Indicates the horizontal length of the cutting path, Indicates the longitudinal length of the cutting path, represents the lateral length of the chip, Indicates the vertical length of the chip.

[0011] In one of the embodiments, the method further includes the following steps: adding the horizontal coordinate of each chip in the wafer to the horizontal distance between the chips, and adding the vertical coordinate of each chip to the vertical distance between the chips to obtain the position coordinates of each chip; the Map contains the position coordinates of each chip in the wafer.

[0012] In one embodiment, the wafer is rotated according to the needle tip offset angle and the map is updated according to the needle tip offset angle by the following steps: the wafer is horizontally scanned and straightened, the wafer is rotated by the needle tip offset angle by a machine rotation mechanism, and the formula for updating the map according to the needle tip offset angle is as follows: ; ; in, Indicates the needle tip deviation angle.

[0013] According to one aspect of the present invention, a chip testing device comprises: a horizontal scanning module for establishing an anti-fool detection mechanism, using a camera to move horizontally and the anti-fool detection mechanism to perform horizontal scanning on a wafer to obtain a horizontal wafer; a parameter calculation module for obtaining a center position and a diameter of the wafer according to a feature point position of the wafer, a distance calculation formula and a visual recognition function of a camera; a map construction module for obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips and the center position and feature point position of the wafer; a chip testing module for obtaining a needle tip offset angle through a camera, rotating the wafer according to the needle tip offset angle and updating the map according to the needle tip offset angle, and performing chip testing according to the map.

[0014] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein the memory stores computer-readable instructions; the computer-readable instructions are executed by one or more of the processors, so that the electronic device implements a chip testing method as described above.

[0015] According to one aspect of the present invention, a storage medium stores computer-readable instructions, and the computer-readable instructions are executed by one or more processors to implement a chip testing method as described above.

[0016] The beneficial effects brought by the technical solution provided by the present invention are: In the above technical scheme, the present invention first establishes an anti-fool detection mechanism, uses the horizontal movement of the camera equipment and the anti-fool detection mechanism to horizontally scan the wafer to obtain a horizontal wafer, obtains the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera, obtains the Map of the wafer according to the size of each chip in the wafer and the cutting path size, the distance between the chips and the center position and the characteristic point position of the wafer, obtains the needle tip offset angle through the camera, rotates the wafer according to the needle tip offset angle and updates the Map according to the needle tip offset angle, and updates the Map according to the needle tip offset angle. Map is used for chip testing. By combining visual recognition technology with precise calculation, it realizes high automation and precision in wafer detection and positioning. It can automatically generate wafer Map and is compatible with chips of multiple sizes, which greatly simplifies the tedious process of traditional manual mapping and improves the accuracy and timeliness of data processing. It can accurately rotate and adjust the wafer according to the needle tip offset angle and dynamically update the Map, effectively avoiding test errors caused by position deviation and ensuring accurate alignment of chip testing, thereby effectively solving the problems of existing technology being incompatible with chips of multiple sizes, low degree of automation, low production efficiency and low accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] Figure 1 is a flow chart of a chip testing method according to an exemplary embodiment; Figure 2 is a flow chart of a chip testing method shown in an exemplary embodiment; Figure 3 is a schematic diagram of horizontal scanning in a chip testing method shown in another exemplary embodiment; Figure 4 yes Figure 3 Schematic diagram of wafer map in the corresponding embodiment; Figure 5 yes Figure 3 Schematic diagram of needle tip angle deviation in the corresponding embodiment; Figure 6 is a block diagram of a chip testing device according to an exemplary embodiment; Figure 7 is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 8It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0020] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present disclosure refers to the presence of the features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0021] To this end, the present invention provides a chip testing method, which realizes high automation and precision of wafer detection and positioning by combining visual recognition technology and precision calculation, and can effectively solve the problems that the prior art is not compatible with multi-size chips, has low automation, and has low production efficiency and accuracy. The chip testing method is suitable for a chip testing device, which can be an electronic device. A chip testing method in an embodiment of the present invention can be applied to a variety of scenarios, such as chip testing, etc.

[0022] See also Figure 1 , an embodiment of the present invention provides a chip testing method, which is applicable to electronic equipment.

[0023] In the following method embodiments, for ease of description, the execution subject of each step of the method is taken as an electronic device as an example for illustration, but this does not constitute a specific limitation.

[0024] like Figure 1 As shown, the method may include the following steps: Step 110, establish a foolproof detection mechanism, use the horizontal movement of the camera device and the foolproof detection mechanism to horizontally scan the wafer to obtain a horizontal wafer.

[0025] In one possible implementation, a wafer is loaded directly under a camera device via a carrier platform, the position of the chip is automatically acquired by the camera device, the horizontal angle of the wafer is adjusted using two-point continuous positioning and slope angle calculation, and the anti-foolproof detection mechanism is used for verification. If the verification passes, a horizontal wafer is obtained.

[0026] In one possible implementation, the slope angle calculation formula is: ; Among them, the difference in the vertical coordinates refers to the difference between the vertical coordinate of the chip during the movement and the initial vertical coordinate, and the difference in the horizontal coordinates refers to the difference between the horizontal coordinate of the chip during the movement and the initial horizontal coordinate. The anti-foolproof detection mechanism is that if the slope angle is less than or equal to the set angle, the horizontal scan is successful, and if the slope angle is greater than the set angle, the horizontal scan is performed again.

[0027] Step 130, obtaining the center position and diameter of the wafer according to the characteristic point positions of the wafer, the distance calculation formula and the visual recognition function of the camera.

[0028] In one possible implementation, a two-dimensional coordinate system is constructed with the characteristic point of the wafer as the origin. The positions of the three edge points of the wafer are obtained through the distance calculation formula and the visual recognition function of the camera. The center position and diameter of the wafer are calculated based on the principle that three points form a circle and the positions of the three edge points. The accuracy of the position is checked based on the size and diameter of the wafer. If the position is inaccurate, the center position is recalculated.

[0029] Step 150, obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer.

[0030] In a possible implementation, the specific calculation formula is as follows: ; ; Among them, X represents the horizontal coordinate of each chip, and Y represents the vertical coordinate of each chip. Represents the horizontal coordinate of the feature point, Represents the ordinate of the feature point, Indicates the horizontal length of the cutting path, Indicates the longitudinal length of the cutting path, represents the lateral length of the chip, Indicates the vertical length of the chip.

[0031] In a possible implementation, the position coordinates of each chip are obtained by adding the horizontal coordinate of each chip in the wafer to the horizontal distance between the chips, and adding the vertical coordinate of each chip to the vertical distance between the chips.

[0032] Among them, the Map contains the location coordinates of each chip in the wafer.

[0033] Step 170, obtaining the needle tip offset angle through a camera, rotating the wafer according to the needle tip offset angle, updating the map according to the needle tip offset angle, and performing chip testing according to the map.

[0034] In a possible implementation, the wafer is horizontally scanned and straightened, and the wafer is rotated by the needle tip offset angle through the machine rotation mechanism. The formula for updating the map according to the needle tip offset angle is as follows: ; ; in, Indicates the needle tip deviation angle.

[0035] Through the above process, the embodiment of the present invention first establishes an anti-fool detection mechanism, uses the horizontal movement of the camera equipment and the anti-fool detection mechanism to horizontally scan the wafer to obtain a horizontal wafer, obtains the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera, obtains the Map of the wafer according to the size of each chip in the wafer and the cutting path size, the distance between the chips, and the center position and characteristic point position of the wafer, obtains the needle tip offset angle through the camera, rotates the wafer according to the needle tip offset angle, and updates the Map according to the needle tip offset angle, based on the wafer. By combining visual recognition technology with precise calculations to test chips according to the map, a high degree of automation and precision in wafer detection and positioning is achieved. The ability to automatically generate wafer maps and be compatible with chips of multiple sizes greatly simplifies the tedious process of traditional manual mapping and improves the accuracy and timeliness of data processing. The wafer can be precisely rotated and adjusted according to the needle tip offset angle and the map can be dynamically updated, effectively avoiding test errors caused by position deviations and ensuring accurate alignment of chip tests, thereby effectively solving the problems of existing technologies being incompatible with chips of multiple sizes, having a low degree of automation, and having low production efficiency and accuracy.

[0036] In an exemplary embodiment, the present invention provides a chip testing method for performing chip testing.

[0037] like Figure 2 As shown, the following steps may be specifically included: Step S001, the wafer is scanned horizontally.

[0038] Specifically, the wafer is loaded onto a wafer stage directly below the camera, and then the camera automatically obtains the position of the chip to perform wafer scanning, using two points and continuous positioning directions to achieve automatic horizontal scanning of the wafer.

[0039] In one possible implementation, the leftmost chip on the wafer is used as the first reference point, and the wafer is continuously moved to the right and then to the left. During the movement, the slope angle is calculated using a formula, and the level of the wafer is adjusted through multiple verification calculations until the wafer reaches a horizontal scanning straight state.

[0040] Furthermore, the chip position is obtained by moving back and forth multiple times, and the formula is applied again to calculate the accuracy of its rotation angle multiple times to ensure the accuracy of the wafer level, and an anti-fool detection mechanism is established to ensure the accuracy and precision of the wafer horizontal scanning.

[0041] Specifically, the fool-proof detection mechanism verification is that when the angle obtained by the calculation formula is less than 0.0001°, the wafer is successfully scanned horizontally. When the angle obtained by the calculation formula is greater than 0.0001°, the secondary verification mechanism is enabled and adjustments are made again. After the adjustment is completed, the formula is applied to verify whether the slope angle meets the requirements.

[0042] Among them, the angle 0.0001° is an open window, which can be input and defined according to requirements.

[0043] Step S002, forming the center of the wafer and the position of the characteristic points.

[0044] Specifically, the wafer has a special feature point (this feature point can be located anywhere on the wafer), which is mainly used for positioning in the yellow light development and other processes in the front-end process. In this step, the position of this feature point is used to construct a corresponding map of the center position of the wafer and the distribution position of each chip on the wafer.

[0045] This feature point can be defined as being located at any position on the wafer, and a two-dimensional coordinate system is constructed on this feature point. On this basis, the feature point position can be calculated through relevant formulas and the visual recognition function of the camera to obtain the edge position of the wafer corresponding to this feature point. Then, the actual center position of the wafer can be obtained based on the principle of three points forming a circle.

[0046] Step S003, calculating the chip size map positions of all wafers.

[0047] Specifically, the correct chip position can be directly calculated by combining the wafer size, chip size specifications on the wafer and chip cutting path size, and the center position and feature point position of step S002. The actual position map coordinate information position of all chips can be obtained in turn through the calculation formula.

[0048] Furthermore, based on the position of the feature points on the wafer, the size of each wafer chip is calculated, and a map is generated that shows the position of each chip on the wafer.

[0049] Step S004, generating a Map of multi-size wafers / single-size wafers.

[0050] Specifically, in a single-size wafer, the positions of all chips can be directly calculated through the formula. In the case of multi-size wafers, the actual position is calculated based on the chip parameters of the first size first, and then the Map coordinate information position of the multi-size wafer is calculated based on the distance between its different sizes.

[0051] Step S005, identifying the angle of the probe holder tip and the angle of the needle holder tip.

[0052] Specifically, during the multi-site pin card test, the pin card tip angle detection is first performed, mainly by obtaining the pin tip position angle through a camera. After the pin card offset angle is obtained, the wafer is rotated through the machine chuck plate rotation mechanism to adjust the pin card offset angle.

[0053] Furthermore, since there will be a certain deviation in the position of the chip after rotation, it is necessary to recalculate the chip map position to obtain the actual chip testing position during multi-site needle card testing.

[0054] Step S006: forming a wafer map.

[0055] Specifically, the wafer Map is calculated using the unique feature point position of the wafer, and this feature point is used as the origin position of the wafer to calculate the chip position in four directions. Based on the two-dimensional coordinate system, the actual position of each chip can be obtained, and finally the Map calculation of the entire wafer chip and the actual chip measurement position calculation after increasing the rotation angle of the needle card tip are completed, thereby obtaining the Map position of the wafer chip.

[0056] Through the above process, the embodiment of the present invention significantly improves the efficiency and accuracy of wafer testing, and is compatible with Map testing of chips of multiple sizes. Through the algorithm formula, chips of all sizes are successfully integrated into the same Map map, thereby greatly shortening the time for Map establishment, improving the operation rate and production capacity, and reducing the abnormality rate when manually establishing the Map. The algorithm formula is used to realize automatic generation of the Map diagram, which corresponds one-to-one with the wafer chip, greatly reducing the risk of manual intervention. In the process of automatic generation of the Map diagram by the algorithm, the angle difference of the needle tip of the needle card can be detected in advance, and this difference can be synchronously implanted into the Map diagram. During the test, the system can automatically adjust the needle tip piercing position according to the position information in the Map, ensuring the high consistency of the test piercing needle marks, thereby improving the accuracy and reliability of the test.

[0057] In another exemplary embodiment, the present invention provides a chip testing method for performing chip testing.

[0058] like Figure 3 As shown, the camera first automatically obtains the position of the chip to perform wafer scanning. Two points and continuous positioning are used to achieve automatic horizontal scanning of the wafer. During the movement, the formula is used: ; The slope angle is calculated and the wafer level is adjusted through multiple verification calculations, and a foolproof detection mechanism is established to ensure the accuracy and precision of wafer straightening. The foolproof detection mechanism verification is as follows: Verification formula: ; When the angle obtained by the calculation formula is less than 0.0001°, it means that the wafer has been successfully scanned horizontally. When the angle obtained by the calculation formula is greater than 0.0001°, the secondary verification mechanism is activated at this time, and the horizontal angle is fine-tuned again. After the adjustment is completed, the formula is applied to verify whether the slope angle meets the requirements.

[0059] like Figure 4 As shown in the figure, each wafer has a special feature point. This feature point position is used to construct the corresponding map of the center position of the wafer and the distribution position of each chip on the wafer. The feature point can be defined as , and this feature point can be located at any position on the wafer, and a two-dimensional coordinate system is constructed on this feature point. On this basis, the feature point position can be calculated through relevant formulas and the visual recognition function of the camera to obtain the edge position of the wafer corresponding to this feature point. Then, the actual center position of this wafer can be obtained based on the principle of three points forming a circle. .

[0060] Horizontal distance: ; Vertical distance: ; The above formula can be used to calculate the positions of the three edge points of the wafer, and then the center position of the wafer and the position of the feature point corresponding to the center of the circle can be directly calculated based on the principle that three points form a circle, thereby completing the calculation of the center position and feature point position of the Map.

[0061] At the feature point Position, respectively to the left , right direction and upward direction , set three edge positions and feature point positions Must be in The coordinates of the center of the circle can be derived from the formula of three points forming a circle. And the diameter of the circle d, and then according to the size specifications of the wafer, for example: the diameter of an 8-inch wafer is =200mm, the test method to check whether the wafer diameter derived by the formula corresponds to the actual wafer diameter is as follows: The distance between the center of the circle and the right point is: The diameter of this circle is ,when or When the center position is not accurate, the center position is derived again by the formula. The center position of this circle is accurate.

[0062] Furthermore, the chip size X: , chip size Y: . Chip cutting path size X: , chip cutting path size Y: .

[0063] Horizontal calculation formula: ; Vertical calculation formula: ; And through this calculation formula, the actual location map coordinate information of all chips can be calculated in turn. Compared with the existing technology, the manual map creation step is eliminated, which improves work efficiency and accuracy.

[0064] Furthermore, in a single-size wafer, the above formula can be used to directly calculate the location of all chips. For multi-size wafers, the actual location of the chip is calculated based on the first-size chip parameter, and then the distance between different sizes is calculated. , , the coordinates of chips of all sizes are obtained, and the calculation formula is as follows: Horizontal calculation formula: ; Vertical calculation formula: ; Thus, the map coordinate information position of wafers of multiple sizes can be calculated. Compared with the existing technology, the existing technology is only compatible with chip sizes of a single size, while this solution is compatible with chip sizes of multiple sizes and has high compatibility.

[0065] like Figure 5 As shown in the figure, during the multi-site pin card test, the pin card tip angle detection is first performed, mainly by obtaining the pin tip position through the camera to obtain the pin card offset angle. After that, the wafer is rotated and offset by the Chuck plate rotation mechanism. , and the wafer is first horizontally scanned and straightened before rotation, and then the wafer is rotated .

[0066] Furthermore, since there will be a certain deviation in the position of the chip after rotation, it is necessary to recalculate the chip map position. The actual position of the chip after the needle tip angle is rotated is calculated mainly through the following formula: Angle calculation formula θ: ; The calculation formula of chip X-direction deviation distance after rotation angle: ; The calculation formula of chip X-direction deviation distance after rotation angle: ; Finally, the actual chip test position during multi-site pin card testing is obtained according to the following formula: X direction: ; Y direction: ; Compared with the existing technology, this solution can automatically adjust the angle position of the needle card and automatically calculate the Map coordinates of the actual needle insertion position of each chip, thereby reducing the manual difference when manually adjusting the angle position of the needle card and improving the automation level of the machine.

[0067] Furthermore, the wafer map is estimated using the unique feature point position of the wafer, and the feature point is used as the origin position of the wafer to estimate the chip position in four directions.

[0068] Based on the two-dimensional coordinate system, the calculation method is as follows: X positive direction is: ..... ; X positive direction is: ..... ; X negative direction is: ..... ; X negative direction is: ..... .

[0069] The negative direction is when moving in the opposite direction of the origin, it can be a negative value, and the actual position can be a positive value. n represents the number of the chip, from which the actual position of each chip can be obtained as follows: ( , ) Finally, the Map calculation of the entire wafer chip and the actual chip piercing position calculation after increasing the rotation angle of the needle card tip are completed, thereby obtaining the Map position of the wafer chip.

[0070] Through the above process, the embodiment of the present invention utilizes the camera equipment to scan the wafer horizontally, which not only greatly improves the detection coverage and efficiency, but also ensures the comprehensiveness and accuracy of the wafer image data acquisition. Through the application of the characteristic point position and distance calculation formula, the center position and diameter of the wafer can be accurately determined, laying a solid foundation for subsequent operations. According to the size of each chip and cutting path on the wafer and the distance between them, the wafer Map is automatically generated in combination with the center and characteristic point position information, which greatly simplifies the cumbersome process of traditional manual mapping and improves the accuracy and timeliness of data processing. In addition, the needle tip offset angle is captured in real time by the camera, and the wafer is accurately rotated and adjusted and the Map is dynamically updated accordingly, which effectively avoids the test error caused by position deviation, ensures the accurate alignment of the chip test, not only optimizes the test process, but also significantly improves the reliability and yield of the wafer test.

[0071] The following is an embodiment of the device of the present invention, which can be used to perform a chip testing method involved in the present invention. For details not disclosed in the embodiment of the device of the present invention, please refer to the method embodiment of a chip testing method involved in the present invention.

[0072] See also Figure 6 , a chip testing device 800 is provided in an embodiment of the present invention.

[0073] The device 800 includes but is not limited to: a horizontal scanning module 810 , a parameter calculation module 830 , a map construction module 850 and a chip testing module 870 .

[0074] Among them, the horizontal straightening module 810 is used to establish an anti-fool detection mechanism, and uses the horizontal movement of the camera device and the anti-fool detection mechanism to horizontally straighten the wafer to obtain a horizontal wafer.

[0075] The parameter calculation module 830 is used to obtain the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera.

[0076] The map construction module 850 is used to obtain a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer.

[0077] The chip testing module 870 is used to obtain the needle tip offset angle through a camera, rotate the wafer according to the needle tip offset angle, update the map according to the needle tip offset angle, and perform chip testing according to the map.

[0078] It should be noted that the chip test provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the chip testing device will be divided into different functional modules to complete all or part of the functions described above.

[0079] In addition, the chip testing device provided in the above embodiment and an embodiment of a chip testing method belong to the same concept, wherein the specific manner in which each module performs an operation has been described in detail in the method embodiment and will not be repeated here.

[0080] Figure 7 The present invention schematically illustrates the structure of an electronic device according to an exemplary embodiment.

[0081] It should be noted that the electronic device is only an example adapted to the present invention and cannot be considered to provide any limitation on the scope of use of the present invention. The electronic device cannot be interpreted as requiring dependence on or having Figure 7 One or more components of exemplary electronic device 2000 are shown.

[0082] The hardware structure of the electronic device 2000 may vary greatly due to differences in configuration or performance, such as Figure 7 As shown, the electronic device 2000 includes: a power supply 210 , an interface 230 , at least one memory 250 , and at least one central processing unit (CPU) 270 .

[0083] Specifically, the power supply 210 is used to provide operating voltage for each hardware device on the electronic device 2000 .

[0084] The interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted by the present invention, the interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input-output interface 235, and at least one USB interface 237, etc. Figure 7 As shown, this is not intended to be a specific limitation.

[0085] The memory 250 is a carrier for storing resources, which may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 251, an application 253 and data 255, etc. The storage method may be temporary storage or permanent storage.

[0086] Among them, the operating system 251 is used to manage and control various hardware devices and application programs 253 on the electronic device 2000 to enable the central processor 270 to calculate and process the massive data 255 in the memory 250. It can be WindowsServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.

[0087] The application program 253 is a computer-readable instruction that performs at least one specific task based on the operating system 251, and may include at least one module ( Figure 7 (not shown), each module may respectively include computer-readable instructions for the electronic device 2000. For example, the chip testing device may be regarded as an application 253 deployed in the electronic device 2000.

[0088] The data 255 may be signal information, etc., stored in the memory 250 .

[0089] The central processor 270 may include one or more processors and is configured to communicate with the memory 250 through at least one communication bus to read the computer-readable instructions stored in the memory 250, thereby realizing the operation and processing of the mass data 255 in the memory 250. For example, a chip testing method is completed by the central processor 270 reading a series of computer-readable instructions stored in the memory 250.

[0090] In addition, the present invention can also be implemented by hardware circuits or hardware circuits combined with software. Therefore, the implementation of the present invention is not limited to any specific hardware circuits, software, or a combination of the two.

[0091] See also Figure 8 In an embodiment of the present invention, an electronic device 4000 is provided. The electronic device 400 may include: a desktop computer, a laptop computer, a server, etc. with sensor recognition capability.

[0092] exist Figure 8 In the embodiment, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0093] The data interaction between the processor 4001 and the memory 4003 can be realized through at least one communication bus 4002. The communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0094] Optionally, the electronic device 4000 may further include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception, etc. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0095] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0096] The memory 4003 can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program instructions or codes in the form of instructions or data structures and can be accessed by the electronic device 400, but is not limited to this.

[0097] Computer-readable instructions are stored in the memory 4003 , and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002 .

[0098] The computer-readable instructions are executed by one or more processors 4001 to implement a chip testing method in the above embodiments.

[0099] In addition, an embodiment of the present invention provides a storage medium on which computer-readable instructions are stored. The computer-readable instructions are executed by one or more processors to implement a chip testing method as described above.

[0100] A computer program product is provided in an embodiment of the present invention. The computer program product includes computer-readable instructions. The computer-readable instructions are stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, so that the electronic device implements a chip testing method as described above.

[0101] Compared with the related art, the present invention has the following beneficial effects: 1. The present invention first establishes a foolproof detection mechanism, uses a camera device to move horizontally and the foolproof detection mechanism to horizontally scan a wafer to obtain a horizontal wafer, obtains the center position and diameter of the wafer according to the characteristic point position of the wafer, a distance calculation formula and the visual recognition function of the camera, obtains a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips and the center position and characteristic point position of the wafer, obtains a needle tip offset angle through a camera, rotates the wafer according to the needle tip offset angle and updates the map according to the needle tip offset angle, and updates the map according to the map. The chip test is carried out by combining visual recognition technology with precise calculation to achieve high automation and precision in wafer detection and positioning. It can automatically generate wafer Map and is compatible with multi-size chips, which greatly simplifies the tedious process of traditional manual mapping and improves the accuracy and timeliness of data processing. It can accurately rotate and adjust the wafer according to the needle tip offset angle and dynamically update the Map, effectively avoiding test errors caused by position deviation and ensuring accurate alignment of chip testing, thereby effectively solving the problems of existing technology incompatibility with multi-size chips, low degree of automation, low production efficiency and accuracy.

[0102] 2. The present invention is compatible with multi-size chip Map testing: all sizes of chips are generated in the same Map through an algorithm formula, which greatly reduces the time for Map establishment, improves the operation rate and production capacity, and reduces the abnormality rate when manually establishing the Map.

[0103] 3. The present invention has a high degree of automation: it can realize automatic generation of Map diagrams according to relevant algorithm formulas, which correspond one-to-one with the chips on the wafer, reducing the risk of manual intervention and improving the automation level of the test; the needle mark detection accuracy is high: when the Map diagram is automatically generated, the angle difference of the needle card needle tip is pre-detected, and the generated angle difference is synchronously implanted into the Map diagram, thereby ensuring a high consistency of the needle tip piercing position during the test and improving the accuracy of the test.

[0104] 4. The present invention can improve test efficiency: there is no need to re-establish a map for chips of different sizes, saving time and labor costs and improving overall test efficiency; reduce test errors: the high degree of automation and high precision of needle mark detection together reduce test errors caused by manual operation and improve test reliability; support multi-SITE testing: it includes a needle tip angle detection and adjustment mechanism for multi-SITE needle card testing, ensuring accuracy during multi-SITE testing.

[0105] 5. The present invention has a wide range of application scenarios: it is suitable for all semiconductor manufacturing companies that need to perform wafer testing, regardless of the size and type of chips they produce.

[0106] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0107] The above descriptions are only some embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip testing method, characterized in that: The method comprises: Establishing a foolproof detection mechanism, using a camera device to move horizontally and the foolproof detection mechanism to horizontally scan the wafer to obtain a horizontal wafer; Obtaining the center position and diameter of the wafer according to the characteristic point position of the wafer, a distance calculation formula and a visual recognition function of a camera; Obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer; The needle tip offset angle is acquired through a camera, the wafer is rotated according to the needle tip offset angle, the map is updated according to the needle tip offset angle, and the chip test is performed according to the map.

2. A chip testing method as claimed in claim 1, characterized in that: The method of using the camera device to move horizontally and the fool-proof detection mechanism to horizontally straighten the wafer to obtain the horizontal wafer includes: The wafer is loaded directly under the camera device via a carrier platform, the position of the chip is automatically acquired by the camera device, the horizontal angle of the wafer is adjusted by two-point continuous positioning and slope angle calculation, and the anti-foolproof detection mechanism is used for verification. If the verification passes, a horizontal wafer is obtained.

3. A chip testing method as claimed in claim 2, characterized in that: The slope angle calculation formula is: ； The difference in the ordinate refers to the difference between the ordinate of the chip during the movement and the initial ordinate, and the difference in the abscissa refers to the difference between the abscissa of the chip during the movement and the initial abscissa; The foolproof detection mechanism is that if the slope angle is less than or equal to the set angle, the horizontal straightening is successful, and if the slope angle is greater than the set angle, the horizontal straightening is performed again.

4. A chip testing method as claimed in claim 1, characterized in that: The method of obtaining the center position and diameter of the wafer according to the characteristic point position of the wafer, the distance calculation formula and the visual recognition function of the camera includes: A two-dimensional coordinate system is constructed with the characteristic point of the wafer as the origin, and the positions of three edge points of the wafer are obtained by using a distance calculation formula and a visual recognition function of a camera; The center position and diameter of the wafer are calculated based on the principle of three points forming a circle and the positions of the three edge points; The accuracy of the position is checked according to the size and diameter of the wafer, and if the position is inaccurate, the center position is recalculated.

5. A chip testing method as claimed in claim 1, characterized in that: The method of obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer includes: The specific calculation formula is as follows: ； ； Among them, X represents the horizontal coordinate of each chip, and Y represents the vertical coordinate of each chip. Represents the horizontal coordinate of the feature point, Represents the ordinate of the feature point, Indicates the horizontal length of the cutting path, Indicates the longitudinal length of the cutting path, represents the lateral length of the chip, Indicates the vertical length of the chip.

6. A chip testing method as claimed in claim 5, characterized in that: The method further comprises: The position coordinates of each chip in the wafer are obtained by adding the horizontal coordinate of each chip in the wafer to the horizontal distance between each chip, and adding the vertical coordinate of each chip to the vertical distance between each chip; the Map contains the position coordinates of each chip in the wafer.

7. A chip testing method as claimed in claim 1, characterized in that: The step of rotating the wafer according to the needle tip offset angle and updating the Map according to the needle tip offset angle includes: The wafer is horizontally scanned and straightened, and the wafer is rotated by the needle tip offset angle through the machine rotation mechanism. The formula for updating the map according to the needle tip offset angle is as follows: ； ； in, Indicates the needle tip deviation angle.

8. A chip testing device, characterized in that: The device comprises: A horizontal straightening module is used to establish a foolproof detection mechanism, and use a camera device to move horizontally and the foolproof detection mechanism to perform horizontal straightening on the wafer to obtain a horizontal wafer; A parameter calculation module, used to obtain the center position and diameter of the wafer according to the characteristic point position of the wafer, a distance calculation formula and a visual recognition function of a camera; A map construction module, for obtaining a map of the wafer according to the size of each chip in the wafer and the size of the cutting path, the distance between the chips, and the center position and feature point position of the wafer; The chip testing module is used to obtain the needle tip offset angle through a camera, rotate the wafer according to the needle tip offset angle, update the map according to the needle tip offset angle, and perform chip testing according to the map.

9. An electronic device, characterized in that: include: at least one processor and at least one memory, wherein: The memory has computer-readable instructions stored thereon; The computer-readable instructions are executed by one or more of the processors, so that the electronic device implements a chip testing method as described in any one of claims 1 to 7.

10. A storage medium having computer-readable instructions stored thereon, characterized in that: The computer-readable instructions are executed by one or more processors to implement a chip testing method according to any one of claims 1 to 7.

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