Techniques for beam expansion in monolithic glass substrates

Abstract

The subject matter of the present invention is a technique for beam expansion in a monolithic glass substrate. Techniques for beam expansion in a monolithic glass substrate are disclosed. In an illustrative embodiment, a lens in a glass substrate may be formed using a laser or by changing the refractive index or as part of a two-step etch process. A seam may be prepared and etched dividing the glass substrate into two parts, one of which will be part of an optical plug and one of which will be part of an optical receptacle. The optical plug has a cavity into which an optical fiber may be placed. In use, a lens in the glass substrate of the optical plug collimates light from the optical fiber into a beam. When the optical plug is paired with the optical receptacle, the light beam is aligned to a waveguide and a lens in the optical receptacle. The large-sized light beam relaxes alignment tolerances for optical plugs and receptacles.

Description

Background Art

[0001] Photonic integrated circuits (PICs) can be used for several applications such as communications. Efficiently and inexpensively aligning optics to couple light into and out of PICs can be a challenge. Methods such as attaching optical fiber arrays to PICs can be slow, may not be compatible with conventional semiconductor packaging processes, and can cause significant yield and throughput issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is an isometric view of a system including a fiber optic plug inserted into an assembly having a glass substrate, a photonic integrated circuit (PIC) die, and an electronic integrated circuit (EIC) die mounted thereon.

[0003] Figure 2 yes Figure 1 A top-down view of the system.

[0004] Figure 3 yes Figure 1 A cross-sectional view of one embodiment of a system.

[0005] Figure 4 yes Figure 1 A cross-sectional view of one embodiment of a system.

[0006] Figure 5 is a simplified flow chart of at least one embodiment of a method for manufacturing a system including an optical plug and an optical receptacle for the optical fiber plug.

[0007] Figure 6 is Figure 5 One embodiment of the method comprises a stage for preparing a glass substrate.

[0008] Figure 7 is Figure 5 One embodiment of the method comprises a stage for preparing a glass substrate.

[0009] Figure 8 is Figure 5 One embodiment of the method comprises a stage for preparing a glass substrate.

[0010] Fig. 9 is Figure 5 One embodiment of the method comprises a stage for preparing a glass substrate.

[0011] Fig.10 is Figure 5 One embodiment of the method comprises a stage for preparing a glass substrate.

[0012] Fig.11 is Figure 5One embodiment of the method comprises a stage glass substrate and a PIC die.

[0013] Fig.12 is Figure 5 One embodiment of the method comprises a stage glass substrate and a PIC die.

[0014] Fig.13 is a top view of a wafer and die that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0015] Fig.14 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0016] Figures 15A-15D is a perspective view of example planar, gate-all-around, and stacked gate-all-around transistors.

[0017] Fig.16 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0018] Fig.17 is a block diagram of an example electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0019] In one illustrative embodiment disclosed herein, an optical plug and an optical receptacle may be formed in part from a monolithic glass substrate. The optical plug and / or the optical receptacle may include a lens to collimate light from an optical fiber and / or a waveguide and / or to focus light into an optical fiber and / or a waveguide. In an illustrative embodiment, the lens is integral with the monolithic glass substrate and formed simultaneously, improving alignment between the lenses.

[0020] In some embodiments, a laser may be used to create some or all of the features of an optical plug and / or an optical receptacle. For example, a laser may be used to modify the refractive index of a glass substrate to form a waveguide and / or a lens in the glass substrate. Additionally or alternatively, a laser may be used to perform selective laser induced etching to selectively remove a portion of the glass substrate to form features such as cavities for optical fibers, alignment features for photonic integrated circuit (PIC) dies, or lenses on the surface of the optical plug and / or optical receptacle.

[0021] As used herein, the phrase "communicatively coupled" refers to the ability of a component to send or receive signals to or from another component. The signal may be any type of signal, such as an input signal, an output signal, or a power signal. A component may send or receive signals to or from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components include: integrated circuit dies in the same package that communicate via an embedded bridge in a package substrate; and integrated circuit components attached to a printed circuit board that send or receive signals to or from other integrated circuit components or electronic devices attached to the printed circuit board.

[0022] In the following description, specific details are set forth, but embodiments of the technology described herein may be implemented without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this description. Phrases such as "an embodiment," "various embodiments," "some embodiments," and the like may include features, structures, or characteristics, but not every embodiment necessarily includes a particular feature, structure, or characteristic.

[0023] Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third", etc. describe a common object and indicate that different instances of similar objects are being referred to. Such adjectives do not imply that the objects so described must be in a given order either in time or in space, in rank, or in any other way. "Connected" may indicate that an element is in direct physical or electrical contact, and "coupled" may indicate that an element cooperates or interacts, but they may or may not be in direct physical and electrical contact. In addition, as used with respect to embodiments of the present disclosure, the terms "include", "include", "have", etc. are synonymous. Terms modified by the word "substantially" include arrangements, orientations, spacings, or positions that are slightly different from the meaning of the unmodified terms. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may deviate from the central axis of the through hole by a few degrees. In another example, a substrate component feature (such as a through width) described as having substantially a listed size may vary within a few percent of the listed size.

[0024] It will be understood that in the examples further shown and described below, the figures may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source / drain regions, electrodes, etc. having orthogonal (e.g., vertical) boundaries, the embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 degrees or 10 degrees of orthogonality) due to the manufacturing methods used to create such devices or for other reasons.

[0025] Reference is now made to the drawings, which are not necessarily drawn to scale, wherein similar or identical numbers may be used to designate identical or similar parts in different drawings. The use of similar or identical numbers in different drawings does not mean that all drawings including similar or identical numbers constitute a single or identical embodiment. Similar numbers with different letter suffixes may represent different instances of similar parts. The drawings generally illustrate various embodiments discussed in this document by way of example but not by way of limitation.

[0026] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding thereof. However, it will be apparent that novel embodiments can be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate their description. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0027] As used herein, in the context of a first layer or component being located on a second layer or component, the phrase "located on..." means that the first layer or component is physically attached to the second layer or component directly (with no layers or components between the first layer or component and the second layer or component) or is physically attached to the second layer or component using one or more intervening layers or components.

[0028] As used herein, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there are no layers or components between the stated adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0029] Reference now Figure 1-4 In one embodiment, the system 100 includes an optical plug 116 , an optical receptacle 118 , a photonic integrated circuit (PIC) die 110 , an electronic integrated circuit (EIC) die 112 , and a circuit board 114 . Figure 1 shows a perspective view of system 100, Figure 2 shows a top-down view of the system 100, Figure 3 shows a cross-sectional view of one embodiment of the system 100, and Figure 4A cross-sectional view of one embodiment of the system 100 is shown. In the illustrative embodiment, the optical receptacle 118 includes a glass substrate 102. The glass substrate 102 is mounted on a PIC die 110, the PIC die 110 is mounted on an EIC die 112, and the EIC die 112 is mounted on a circuit board 114. In the illustrative embodiment, an optical plug 116 mates with the optical receptacle 118. An array 108 of optical fibers 106 is connected to the glass substrate 104 of the optical plug 116.

[0030] In one embodiment, Figure 3 As shown in FIG. 1 , each optical fiber 106 is positioned within a cavity defined in the glass substrate 104. Each optical fiber 106 is aligned to a lens 310 defined in the glass substrate 104. Figure 3 As seen from an angle of , the glass substrate 104 includes an array of lenses 310 extending into and out of the page. Regions of the glass substrate 104 corresponding to the lenses 310 have a different refractive index than the bulk of the glass substrate 104. The lenses 310 can be embodied as regions having a fixed difference in refractive index relative to the bulk of the glass substrate 104, having one or more curved surfaces that collimate light from the optical fiber 106 and / or focus light into the optical fiber 106. Additionally or alternatively, the lenses 310 can be embodied as regions having a range of different refractive indices, such as a gradient index (or GRIN) lens. For each optical fiber 106, the optical receptacle 118 has a corresponding lens 310 defined in the glass substrate 102 and a waveguide 304 defined in the glass substrate 102.

[0031] In the illustrated embodiment, light from each optical fiber 106 may be collimated by a lens 310 in the optical plug 116 into a beam 308. The beam 308 may then be focused by a lens 310 in the optical receptacle 118 into the waveguide 304. In some embodiments, as shown in FIG. Figure 3 As shown in FIG. 3 , there may be a cavity defined between glass substrate 104 and glass substrate 102, wherein light beam 308 passes through the air between glass substrate 104 and glass substrate 102. In other embodiments, there may be no cavity, and light beam 308 may pass directly from glass substrate 104 to glass substrate 102.

[0032] In another embodiment, if Figure 4, each optical fiber 106 is aligned to a lens 402 defined in a surface of a glass substrate 104. The glass substrate 104 has a curved surface that forms a lens 402 that can collimate light from the optical fiber 106 or focus light into the optical fiber 106. For each optical fiber 106, the optical receptacle 118 has a corresponding lens 402 defined in a surface of the glass substrate 102 and a waveguide 304 defined in the glass substrate 102. The waveguide 304 starts at a point in the glass substrate 102 so that the lens 310 focuses the collimated light beam 308 into the waveguide 304.

[0033] Similar to the lens 310 described above, in the illustrative embodiment, light from each optical fiber 106 may be collimated by a lens 402 in the optical plug 116 into a light beam 308. The light beam 308 may then be focused by a lens 402 in the optical receptacle 118 to the waveguide 304. In the illustrative embodiments described above, both the optical plug 116 and the optical receptacle 118 use either a bulk lens 310 defined in the glass substrates 102, 104 or a lens 402 defined in the surface of the glass substrates 102, 104. Additionally or alternatively, the optical plug 116 and the optical receptacle 118 may use different lenses 310, 402 and / or may use a combination of two lenses 310, 402, either for different optical fibers 106 or for the same optical fiber 106, to increase the overall focusing strength.

[0034] It should be realized that Figure 3 The lens 310 and Figure 4 4, the lenses 310, 402 are monolithic with respect to the rest of the corresponding glass substrates 104, 102. As discussed in more detail below, ultrafast lasers can be used to directly write the lenses 310 and / or waveguides 304 into the glass substrates 104, 102 to form the lenses 310. Additionally or alternatively, the lenses 402 can be formed directly on the surface of the glass substrates 104, 102 using, for example, two-step laser induced etching. In an illustrative embodiment, as discussed in more detail below, the glass substrates 102, 104 can be formed from the same mother glass substrate 600 (see Figure 6). Lasers can be used to form structures such as lenses 310, 402 and waveguide 304 on the same bulk glass substrate 600 in the same time period, reducing or eliminating potential misalignment. Because the diameter of the beam 308 is much larger than the diameter of the beam in the optical fiber 106 or waveguide 304, the alignment tolerance for, for example, 1 dB loss is much higher using a collimated beam 308 rather than direct coupling from the optical fiber 106 to the waveguide 304. For example, if the beam 308 is expanded from a 9 micron waist to an 80 micron waist in the optical fiber 106, for a 1 dB loss, the translation alignment tolerance can be relaxed from about 2 microns to about 20 microns, while the tilt tolerance is tightened from about 2 degrees to about 0.2 degrees. In addition, the relatively large size of the beam 308 makes the coupling less sensitive to dust or other contaminants on the surface of the glass substrates 102, 104 and potentially improves yield.

[0035] In the illustrative embodiment, the glass substrate 102 is mated with the PIC die 110 such that the waveguide 304 defined in the glass substrate 102 is aligned with and butt-coupled to the waveguide 306 defined in the PIC die 110. The PIC die 110 may be made of any suitable material, such as silicon. In the illustrative embodiment, the waveguide 306 may be a silicon waveguide embedded in a silicon oxide cladding. The PIC die 110 may include any suitable number of waveguides 306, such as 1-1024. In the illustrative embodiment, the waveguide 306 in the PIC die 110 is edge-coupled to the waveguide 304. In other embodiments, the waveguide 304 may be coupled to the waveguide 306 in a different manner, such as using evanescent wave coupling or vertical coupling.

[0036] At the interface between the glass substrate 102 and the PIC die 110, one or more alignment features 312 may be present. The alignment features 312 may include, for example, V-grooves in the glass substrate 102 and the PIC die 110 to align the glass substrate 102 relative to the PIC die 110. The alignment features 312 also align the waveguides 304 in the glass substrate 102 to the waveguides 306 in the PIC die 110.

[0037] The PIC die 110 is configured to generate, detect and / or manipulate light. The PIC die 110 may include active or passive optical components, such as splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, etc. The PIC die 110 may send and receive electrical signals to and from the EIC die 112 via solder bumps 302. Additionally or alternatively, the solder bumps 302 may provide power to the PIC die 110. The PIC die 110 may send and receive optical signals to and from the optical receptacle 118 and the optical plug 116 via waveguides 306.

[0038] The EIC die 112 may include any suitable electronic integrated circuit components, such as resistors, capacitors, inductors, transistors, etc. The EIC die 112 may include any suitable analog and / or digital circuit modules, such as processors, memories, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), etc. In some embodiments, the system 100 may be embodied as a router, a switch, a network interface controller, and / or the like. In such embodiments, the EIC die 112 and / or the PIC die 110 may include a network interface controller circuit module to process, parse, route, etc. network packets sent and received by the system 100. For example, a packet may be sent through the optical fiber 106 of the optical plug 116. The packet may be received and / or processed at the PIC die 110 and / or the EIC die 112. Additionally or alternatively, the packet may be sent from the PIC die 110 and / or the EIC die 112 to the optical fiber 106 in the optical plug 116 to be sent to a remote device.

[0039] The illustrative circuit board 114 can be made of ceramic, glass, and / or organic-based materials (such as FR-4) with glass fibers and resins. The circuit board 114 can have any suitable length or width, such as 10-500 mm. The circuit board 114 can have any suitable thickness, such as 0.2-5 mm. The circuit board 114 can support additional components, such as additional photonic or electronic integrated circuit components, processor units, memory devices, accelerator devices, etc.

[0040] The illustrative glass substrates 102, 104 are silica glass. In other embodiments, the substrates 102, 104 may be made of any suitable material that may be crystalline, non-crystalline, amorphous, etc., such as molten silicon, borosilicate, sapphire, yttrium aluminum garnet, etc. The glass substrates 102, 104 may be, for example, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silicon dioxide, molten silicon dioxide. The glass substrates 102, 104 may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The glass substrates 102, 104 may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The glass substrates 102, 104 may include at least 20-40% silicon by weight, at least 20-40% oxygen by weight, and at least 5% aluminum by weight. For example, some embodiments of the glass substrates 102, 104 may include, for example, at least 20-23% silicon and at least 20-26% oxygen by weight.

[0041] The glass substrates 102, 104 may have any suitable length or width, such as 10-500 mm. The glass substrates 102, 104 may have any suitable thickness, such as 0.2-5 mm. The glass substrate 102 of the optical receptacle 118 may include optical elements, such as fan-outs, splitters, couplers, combiners, filters, etc. In some embodiments, the glass substrate 102 may include active optical elements, such as optical amplifiers, lasers, photodetectors, modulators, etc. The optical plug 116 and / or the optical receptacle 118 may include additional components for aligning and / or retaining the optical plug 116, such as alignment grooves, clips, tabs, etc. In use, the optical plug 116 may be inserted into the optical receptacle 118. In doing so, the lenses 310, 402 are positioned to couple light from the optical fiber 106 into the waveguide 306 and vice versa. The relatively large size of the beam 308 takes into account the relatively large tolerance of the displacement between the glass substrate 104 and the glass substrate 102.

[0042] The optical plug 116 may include any suitable number of optical fibers 106 and lenses 310 , 402 , and the glass substrate 102 may include any suitable number of waveguides 304 and lenses 310 , 402 , such as 1-1024 optical fibers 106 and / or waveguides 304 and corresponding lenses 310 , 402 .

[0043] The light in the optical fiber 106 and waveguides 304, 306 may be of any suitable wavelength, such as 400-2000 nanometers. In the illustrative embodiment, the light in the optical fiber 106 and waveguides 304, 306 is, for example, 1200-1600 nanometers, and in particular, may be 1290-1330 nanometers. For example, the intensity of the cross section of the light beam drops to 1 / e of the peak intensity. 2 The lenses 310, 402 can collimate the light into a beam 308 of any suitable diameter, such as 20-500 microns, as measured at a point. In some embodiments, the optical fibers 106, lenses 310, 402, and waveguides 304 can be arranged in a two-dimensional array to increase channel density.

[0044] Reference now Figure 5 , in one embodiment, a flow chart of a method 500 for creating a system 100 having an optical plug 116 and an optical receptacle 118. The method 500 may be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of the method 500. Such a machine may include, for example, a memory, a processor, a data storage device, etc. The memory and / or the data storage device may store instructions that, when executed by the machine, cause the machine to perform some or all of the steps of the method 500. The method 500 may use any suitable set of techniques used in semiconductor and / or photonic processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, selective laser etching, thermal processing, flip chip, layer transfer, magnetron sputtering deposition, pulsed laser deposition, etc. It should be appreciated that the method 500 is only one embodiment of a method of creating one embodiment of the system 100, and other methods may be used to create any suitable embodiment of the system 100. In some embodiments, the steps of the method 500 may be performed in an order different from the order shown in the flowchart.

[0045] The method 500 begins at block 502 where a single glass substrate 600 is modified using one or more lasers. Figure 6 A single glass substrate 600 is shown in FIG. Figure 7 and Figure 8600 after modification. In block 504, the waveguide 304 is written directly into the glass substrate 600, such as by using an ultrafast laser to modify the refractive index of a portion of the glass substrate 600. In block 506, a seam 704 is prepared between the glass substrates 102, 104 that are to become separated. The seam 704 may be prepared using a laser in the first step of a two-step etching process. The laser may induce changes in the area of ​​the glass substrate exposed to the laser to make the area more susceptible to being etched. The laser used to change the refractive index in block 504 may be the same laser as the laser used to prepare the area such as the seam 704 for etching, or a different laser.

[0046] In block 508, the region 702 is prepared to create a cavity in which the optical fiber 106 will be positioned. In block 510, the alignment features 312 and the interface region 706 of the substrate 102 may be prepared for etching.

[0047] In block 512, in some embodiments, Figure 7 As shown in FIG. 1 , one or more lenses 310 may be formed in the glass substrates 102, 104. The lenses 310 may be formed using a laser to modify the refractive index of a region of the glass substrate 102, 104, similar to how the waveguide 304 may be written. The region of the lens 310 may have a fixed difference in refractive index compared to the rest of the glass substrate 102, 104. Additionally or alternatively, the region of the lens 310 may have a spatially varying difference in refractive index compared to the rest of the glass substrate 102, 104, considering a GRIN lens to be formed. For example, laser parameters such as pulse energy, pulse duration, pulse repetition rate, etc. may be varied, resulting in a variable, controllable change in the refractive index.

[0048] Additionally or alternatively, at block 514, in some embodiments, as Figure 8 As shown in FIG. 1 , one or more lenses 402 may be fabricated in glass substrates 102, 104. A seam 704 between glass substrates 102, 104 may include a curved region that will form a lens 402 when the seam region 704 is etched away.

[0049] In block 516, Fig. 9 and Fig.10, features in the substrates 102, 104 may be etched away. In an illustrative embodiment, the seam 704 between the glass substrates 102, 104 may be etched away in box 518. Any suitable etchant may be used, such as sodium hydroxide (NaOH), potassium hydroxide (KOH), or hydrofluoric acid (HF). A cavity 902 for each optical fiber 106 may be etched in box 520. Alignment features 312 may be etched in box 522. In some embodiments, surface lenses 402 may be etched in box 524. In an illustrative embodiment, the lenses 402 on the surface of the glass substrates 102, 104 may be etched simultaneously with the seams 704 in box 518. Since the lenses 310 having a modified refractive index are embedded in the glass substrates 102, 104, the etchant cannot reach them. For that reason, when the glass substrates 102, 104 are exposed to the etchant, the lenses 310 will not be etched.

[0050] In block 526, various surfaces of the substrates 102, 104 may be polished. For example, surfaces defining the lens 402, surfaces where the waveguide 304 terminates, surfaces defining the alignment features 312, etc. may be polished. Any suitable polishing technique may be used, such as laser, mechanical, and / or chemical polishing.

[0051] In block 528, Fig.11 and Fig.12 As shown in FIG. 5 , the glass substrate 102 is mounted with the PIC die 110. In block 530, the optical fiber 106 may be inserted into the cavity 902 of the glass substrate 104. The optical fiber 106 may be fixed in place using, for example, epoxy.

[0052] Fig.13 1 is a top view of a wafer 1300 and die 1302 (e.g., any suitable die such as PIC die 110 or EIC die 112) that may be included in any of the systems 100 disclosed herein. Wafer 1300 may be comprised of semiconductor material and may include one or more die 1302 having integrated circuit structures formed on a surface of wafer 1300. Individual die 1302 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, wafer 1300 may undergo a singulation process in which die 1302 are separated from one another to provide discrete “chips” of an integrated circuit product. Die 1302 may be any of the dies 110, 112 disclosed herein. Die 1302 may include one or more transistors (e.g., discussed below). Fig.14Some of the transistors 1440 of the present invention), supporting circuit modules for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 1300 or die 1302 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1302. For example, a memory array formed by multiple memory devices may be formed in conjunction with a processor unit (e.g., Fig.17 The processor unit 1702 of the dies 110, 112 may be formed on the same die 1302 as the processor unit 1702 of the dies 110, 112 or on other logic configured to store information in a memory device or execute instructions stored in a memory array. Various systems in the system 100 disclosed herein may be manufactured using die-to-wafer assembly techniques, where some of the dies 110, 112 are attached to a wafer 1300 including other of the dies 110, 112 and the wafer 1300 is subsequently singulated.

[0053] Fig.14 1 is a cross-sectional side view of an integrated circuit device 1400 that can be included in any of the systems 100 disclosed herein (e.g., in any of the dies 110, 112). One or more of the integrated circuit devices 1400 can be included in one or more of the dies 1302 ( Fig.13 ). The integrated circuit device 1400 may be formed on a die substrate 1402 (eg Fig.13 1300) and may be included in a die (e.g. Fig.13 The die substrate 1402 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1402 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials may be used to form the die substrate 1402, which may or may not be combined with silicon, and the alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as groups II-VI, III-V, or IV may also be used to form the die substrate 1402. Although several examples of materials that may form the die substrate 1402 are described herein, any material that may serve as the basis for the integrated circuit device 1400 may be used. The die substrate 1402 may be a singulated die (e.g. Fig.13 of a die 1302) or a wafer (e.g. Fig.13 A portion of chip 1300).

[0054] The integrated circuit device 1400 may include one or more device layers 1404 disposed on a die substrate 1402. The device layer 1404 may include features of one or more transistors 1440 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1402. The transistor 1440 may include, for example, one or more source and / or drain (S / D) regions 1420, a gate 1422 for controlling the flow of current between the S / D regions 1420, and one or more S / D contacts 1424 for routing electrical signals to / from the S / D regions 1420. The transistor 1440 may include additional features that are not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1440 is not limited to Fig.14 The types and configurations depicted in the drawings and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and wrap-around or all-around gate transistors such as nanoribbon, nanosheet, or nanowire transistors.

[0055] Figures 15A-15D 15 is a simplified perspective view of example planar, FinFET, all-around gate, and stacked all-around gate transistors. Figures 15A-15D The transistor illustrated in FIG. 15A and 15B . The isolation region 1514 separates the source and drain regions of the transistor from other transistors and from a bulk region 1518 of a substrate 1516 .

[0056] Fig.15A is a perspective view of an example planar transistor 1500 including a gate 1502 that controls current flow between a source region 1504 and a drain region 1506. The transistor 1500 is planar because the source region 1504 and the drain region 1506 are planar relative to a substrate surface 1508.

[0057] Fig. 15B is a perspective view of an example FinFET transistor 1520 including a gate 1522 that controls current flow between a source region 1524 and a drain region 1526. Transistor 1520 is non-planar because source region 1524 and drain region 1526 comprise a "fin" that extends upward from substrate surface 1508. Because gate 1522 surrounds three sides of the semiconductor fin that extends from source region 1524 to drain region 1526, transistor 1520 can be considered a tri-gate transistor. Fig. 15BOne S / D fin is illustrated extending through the gate 1522 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0058] Fig. 15C is a perspective view of a gate-all-around (GAA) transistor 1540 including a gate 1542 that controls current flow between a source region 1544 and a drain region 1546. The transistor 1540 is non-planar because the source region 1544 and the drain region 1546 are elevated from the substrate surface 1508.

[0059] Fig.15D 1560 is a perspective view of a GAA transistor 1560 including a gate 1562 that controls the flow of current between multiple elevated source regions 1564 and multiple elevated drain regions 1566. Transistor 1560 is a stacked GAA transistor because the gate controls the flow of current between multiple elevated S / D regions stacked on top of each other. Transistors 1540 and 1560 are considered to be all-around gate transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 1548 and 1568 of transistors 1540 and 1560, respectively), transistors 1540 and 1560 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors.

[0060] refer to Fig.14 , transistor 1440 may include a gate 1422 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric material.

[0061] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0062] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal depending on whether transistor 1440 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0063] For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0064] In some embodiments, when viewed as a cross-section of transistor 1440 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1402 and two sidewall portions substantially perpendicular to the top surface of die substrate 1402. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1402 and not including a sidewall portion substantially perpendicular to the top surface of die substrate 1402. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0065] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0066] The S / D regions 1420 may be formed within the die substrate 1402 adjacent to the gates 1422 of the respective transistors 1440. For example, the S / D regions 1420 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1402 to form the S / D regions 1420. An annealing process to activate the dopants and cause them to diffuse further into the die substrate 1402 may follow the ion implantation process. In the latter process, the die substrate 1402 may first be etched to form recesses at the locations of the S / D regions 1420. An epitaxial deposition process may then be performed to fill the recesses with the material used to make the S / D regions 1420. In some implementations, the S / D regions 1420 may be made using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 1420. In further embodiments, the S / D region 1420 may be formed using one or more layers of metals and / or metal alloys.

[0067] The device layer 1404 may be provided with one or more interconnect layers (in Fig.14 1406-1410) to route electrical signals such as power and / or input / output (I / O) signals to and / or from devices (e.g., transistors 1440) of device layer 1404. For example, conductive features (e.g., gates 1422 and S / D contacts 1424) of device layer 1404 may be electrically coupled to interconnect structures 1428 of interconnect layers 1406-1410. One or more interconnect layers 1406-1410 may form a metallization stack (also referred to as an "ILD stack") 1419 of integrated circuit device 1400.

[0068] Interconnect structures 1428 may be arranged within interconnect layers 1406-1410 to route electrical signals according to a variety of designs; in particular, the arrangements are not limited to Fig.14 The specific configuration of interconnect structure 1428 is depicted in FIG. Fig.14 A particular number of interconnect layers 1406 - 1410 are depicted in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0069] In some embodiments, the interconnect structure 1428 may include wires 1428a and / or vias 1428b filled with a conductive material such as a metal. The wires 1428a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 1402 on which the device layer 1404 is formed. For example, the wires 1428a may route electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 1428b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the surface of the die substrate 1402 on which the device layer 1404 is formed. In some embodiments, the vias 1428b may electrically couple wires 1428a of different interconnect layers 1406-1410 together.

[0070] like Fig.14 14, the interconnect layers 1406-1410 may include a dielectric material 1426 disposed between interconnect structures 1428. In some embodiments, the dielectric material 1426 disposed between interconnect structures 1428 in different ones of the interconnect layers 1406-1410 may have different compositions; in other embodiments, the composition of the dielectric material 1426 between different interconnect layers 1406-1410 may be the same. The device layer 1404 may also include a dielectric material 1426 disposed between the transistor 1440 and the bottom layer of the metallization stack. The dielectric material 1426 included in the device layer 1404 may have a different composition than the dielectric material 1426 included in the interconnect layers 1406-1410; in other embodiments, the composition of the dielectric material 1426 in the device layer 1404 may be the same as the dielectric material 1426 included in any one of the interconnect layers 1406-1410.

[0071] A first interconnect layer 1406 (referred to as metal 1 or "M1") may be formed directly on the device layer 1404. In some embodiments, as shown, the first interconnect layer 1406 may include wires 1428a and / or vias 1428b. The wires 1428a of the first interconnect layer 1406 may be coupled to contacts (e.g., S / D contacts 1424) of the device layer 1404. The vias 1428b of the first interconnect layer 1406 may be coupled to the wires 1428a of the second interconnect layer 1408.

[0072] A second interconnect layer 1408 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1406. In some embodiments, the second interconnect layer 1408 may include vias 1428b to couple wires 1428a of the second interconnect layer 1408 with wires 1428a of the third interconnect layer 1410. Although wires 1428a and vias 1428b are structurally depicted with lines within the respective interconnect layers for clarity, in some embodiments, wires 1428a and vias 1428b may be structurally and / or materially contiguous (e.g., filled simultaneously during a dual damascene process).

[0073] A third interconnect layer 1410 (referred to as Metal 3 or "M3") (and additional interconnect layers, as needed) may be formed successively on the second interconnect layer 1408 according to similar techniques and configurations as described with respect to the second interconnect layer 1408 or the first interconnect layer 1406. In some embodiments, interconnect layers "higher up" (i.e., farther from the device layer 1404) in the metallization stack 1419 in the integrated circuit device 1400 may be thicker than interconnect layers lower in the metallization stack 1419, with lines 1428a and vias 1428b in higher interconnect layers being thicker than lines and vias in lower interconnect layers.

[0074] The integrated circuit device 1400 may include a solder resist material 1434 (eg, polyimide or a similar material) and one or more conductive contacts 1436 formed on the interconnect layers 1406-1410. Fig.14 , the conductive contact 1436 is illustrated as taking the form of a bonding pad. The conductive contact 1436 can be electrically coupled to the interconnect structure 1428 and the conductive contact 1436 can be configured to route the electrical signal of the (one or more) transistors 1440 to an external device. For example, a solder joint can be formed on one or more conductive contacts 1436 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1400 to another component (e.g., a printed circuit board). The integrated circuit device 1400 may include additional or alternative structures to route electrical signals from the interconnect layers 1406-1410; for example, the conductive contact 1436 may include other similar features (e.g., pillars) that route electrical signals to external components. As appropriate, the conductive contact 1436 may be used as the conductive contact 302.

[0075] In some embodiments where the integrated circuit device 1400 is a double-sided die, the integrated circuit device 1400 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1404. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1406-1410 to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1404 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1400 from the conductive contacts 1436. These additional conductive contacts may serve as the conductive contacts 302, as appropriate.

[0076] In other embodiments in which the integrated circuit device 1400 is a double-sided die, the integrated circuit device 1400 may include one or more through silicon vias (TSVs) through the die substrate 1402; these TSVs may contact the device layer(s) 1404 and may provide a conductive path between the device layer(s) 1404 and additional conductive contacts (not shown) on the side of the integrated circuit device 1400 opposite the conductive contacts 1436. These additional conductive contacts may serve as conductive contacts 302, as appropriate. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 1400 opposite the conductive contacts 1436 to the transistor 1440 and any other components integrated into the die 1400, and the metallization stack 1419 may be used to route I / O signals from the conductive contacts 1436 to the transistor 1440 and any other components integrated into the die 1400.

[0077] Multiple integrated circuit devices 1400 may be stacked using one or more TSVs in each stacked device that provide a connection between one device in the device to any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide a connection between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0078] Fig.1616 is a cross-sectional side view of an integrated circuit device assembly 1600 that may include any of the systems 100 disclosed herein. In some embodiments, the integrated circuit device assembly 1600 may be the system 100. The integrated circuit device assembly 1600 includes a plurality of components disposed on a circuit board 1602 (which may be a motherboard, a system board, a main board, etc.). The integrated circuit device assembly 1600 includes components disposed on a first side 1640 of the circuit board 1602 and an opposing second side 1642 of the circuit board 1602; typically, the components may be disposed on one or both sides 1640 and 1642. Any of the integrated circuit components discussed below with reference to the integrated circuit device assembly 1600 may take the form of any suitable embodiment in the embodiments of the system 100 disclosed herein.

[0079] In some embodiments, circuit board 1602 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by conductive vias. Each metal layer comprises conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1602 (optionally in combination with other metal layers). In other embodiments, circuit board 1602 may be a non-PCB substrate. In some embodiments, circuit board 1602 may be, for example, circuit board 114. Fig.16 The integrated circuit device assembly 1600 illustrated in FIG. 1 includes a package-on-interposer structure 1636 coupled to a first side 1640 of a circuit board 1602 via a coupling component 1616. The coupling component 1616 can electrically and mechanically couple the package-on-interposer structure 1636 to the circuit board 1602 and can include solder balls (e.g., Fig.16 ), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. As appropriate, coupling component 1616 can be used as any of the illustrated or described coupling components for substrate assemblies or substrate assembly components described herein.

[0080] The package-on-interposer structure 1636 may include an integrated circuit component 1620 coupled to an interposer 1604 via a coupling component 1618. The coupling component 1618 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1616. Fig.16A single integrated circuit component 1620 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1604; indeed, additional interposers may be coupled to interposer 1604. Interposer 1604 may provide an intervening substrate for bridging circuit board 1602 and integrated circuit components 1620.

[0081] Integrated circuit component 1620 may be a device including one or more integrated circuit dies (eg, Fig.13 The tube core 1302, Fig.14 The integrated circuit device 1400 of the present invention is a packaged or unpackaged integrated circuit product of an integrated circuit device 1400) and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are sealed in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 1620, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1604. The integrated circuit component 1620 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 1620 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0082] In embodiments where the integrated circuit component 1620 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0083] In addition to including one or more processor units, the integrated circuit component 1620 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the integrated circuit dies may be formed by a packaging substrate, one or more silicon interposers, one or more silicon bridges (such as a silicon interposer) embedded in the packaging substrate, or a plurality of silicon interposers. Embedded multi-die interconnect bridge (EMIB)) or a combination thereof to provide interconnection between dies.

[0084] Typically, interposer 1604 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1604 can couple integrated circuit component 1620 to a collection of ball grid array (BGA) conductive contacts of coupling component 1616 for coupling to circuit board 1602. Fig.16 In the embodiment illustrated in FIG. 1 , integrated circuit component 1620 and circuit board 1602 are attached to opposite sides of interposer 1604; in other embodiments, integrated circuit component 1620 and circuit board 1602 may be attached to the same side of interposer 1604. In some embodiments, three or more components may be interconnected by way of interposer 1604.

[0085] In some embodiments, the interposer 1604 may be formed as a PCB including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1604 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 1604 may be formed of an alternative rigid or flexible material, which may include the same materials described above for use with semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1604 may include metal interconnects 1608 and vias 1610, including but not limited to through-hole vias 1610-1 (extending from the first side 1650 of the interposer 1604 to the second side 1654 of the interposer 1604), blind vias 1610-2 (extending from the first side 1650 or the second side 1654 of the interposer 1604 to the internal metal layer), and buried vias 1610-3 (connecting the internal metal layer).

[0086] In some embodiments, interposer 1604 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1604 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 1604 to an opposite second side of interposer 1604.

[0087] The interposer 1604 may further include embedded devices 1614, which include both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1604. The package-on-interposer structure 1636 may take the form of any package-on-interposer structure known in the art.

[0088] The integrated circuit device assembly 1600 may include an integrated circuit component 1624 coupled to the first side 1640 of the circuit board 1602 via a coupling component 1622. The coupling component 1622 may take the form of any of the embodiments discussed above with reference to the coupling component 1616, and the integrated circuit component 1624 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1620.

[0089] Fig.16 The integrated circuit device assembly 1600 illustrated in FIG. 1 includes a package-on-package structure 1634 coupled to a second side 1642 of a circuit board 1602 by a coupling component 1628. The package-on-package structure 1634 may include an integrated circuit component 1626 and an integrated circuit component 1632 coupled together by a coupling component 1630 such that the integrated circuit component 1626 is disposed between the circuit board 1602 and the integrated circuit component 1632. The coupling components 1628 and 1630 may take the form of any of the embodiments of the coupling component 1616 discussed above, and the integrated circuit components 1626 and 1632 may take the form of any of the embodiments of the integrated circuit component 1620 discussed above. The package-on-package structure 1634 may be configured according to any of the package-on-package structures known in the art.

[0090] Fig.17 1 is a block diagram of an example electrical device 1700 that may include one or more of the systems 100 disclosed herein. For example, any suitable component of the components of the electrical device 1700 may include one or more of the integrated circuit device assembly 1600, the integrated circuit component 1620, the integrated circuit device 1400, or the integrated circuit die 1302 disclosed herein, and may be arranged in any of the systems 100 disclosed herein. Fig.171700, but any one or more of these components may be omitted or duplicated when appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1700 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0091] Additionally, in various embodiments, the electrical device 1700 may not include Fig.17 1700, but the electrical device 1700 may include an interface circuit module for coupling to one or more components. For example, the electrical device 1700 may not include the display device 1706, but may include a display device interface circuit module (e.g., a connector and a driver circuit module) to which the display device 1706 may be coupled. In another set of examples, the electrical device 1700 may not include the audio input device 1724 or the audio output device 1708, but may include an audio input or output device interface circuit module (e.g., a connector and a supporting circuit module) to which the audio input device 1724 or the audio output device 1708 may be coupled.

[0092] The electrical device 1700 may include one or more processor units 1702 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1702 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, a processor unit may be referred to as an XPU (or xPU).

[0093] The electrical device 1700 may include a memory 1704, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1704 may include memory located on the same integrated circuit die as the processor unit 1702. This memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0094] In some embodiments, the electrical device 1700 may include one or more processor units 1702 that are heterogeneous or asymmetric with another processor unit 1702 in the electrical device 1700. There may be various differences between the processing units 1702 in the system in terms of a range of quality metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetries and heterogeneities between the processor units 1702 in the electrical device 1700.

[0095] In some embodiments, the electrical device 1700 may include a communication component 1712 (e.g., one or more communication components). For example, the communication component 1712 may manage wireless communications for transmitting data to and from the electrical device 1700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0096] The communication component 1712 can implement any of a plurality of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects together with any modifications, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also referred to as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standards. The communication component 1712 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1712 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1712 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication component 1712 can operate according to other wireless protocols. The electrical device 1700 may include an antenna 1722 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0097] In some embodiments, the communication component 1712 can manage wired communications, such as electrical, optical or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1712 can include multiple communication components. For example, the first communication component 1712 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1712 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication component 1712 can be dedicated to wireless communications, and the second communication component 1712 can be dedicated to wired communications.

[0098] The electrical device 1700 may include a battery / power circuit module 1714. The battery / power circuit module 1714 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of the electrical device 1700 to an energy source separate from the electrical device 1700 (e.g., AC line power).

[0099] The electrical device 1700 may include a display device 1706 (or a corresponding interface circuit module, as discussed above). The display device 1706 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0100] The electrical device 1700 may include an audio output device 1708 (or a corresponding interface circuit module, as discussed above). The audio output device 1708 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0101] The electrical device 1700 may include an audio input device 1724 (or a corresponding interface circuit module, as discussed above). The audio input device 1724 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1700 may include a global navigation satellite system (GNSS) device 1718 (or a corresponding interface circuit module, as discussed above), such as a global positioning system (GPS) device. As is known in the art, the GNSS device 1718 can communicate with a satellite-based system and can determine the geographic location of the electrical device 1700 based on information received from one or more GNSS satellites.

[0102] The electrical device 1700 may include other output devices 1710 (or corresponding interface circuit modules, as discussed above). Examples of other output devices 1710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0103] The electrical device 1700 may include other input devices 1720 (or corresponding interface circuit modules, as discussed above). Examples of other input devices 1720 may include: an accelerometer; a gyroscope; a compass; an image capture device (e.g., a monoscopic or stereoscopic camera); a trackball; a trackpad; a touchpad; a keyboard; a cursor control device such as a mouse, a stylus, a touch screen; a proximity sensor; a microphone; a barcode reader; a quick response (QR) code reader; an electrocardiogram (ECG) sensor; a PPG (photoplethysmogram) sensor; a galvanic skin response sensor; any other sensor; or a radio frequency identification (RFID) reader.

[0104] The electrical device 1700 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1700 may be any other electronic device that processes data. In some embodiments, the electrical device 1700 may include multiple discrete physical components. Given the range of devices that the electrical device 1700 may appear as in various embodiments, in some embodiments, the electrical device 1700 may be referred to as a computing device or a computing system.

[0105] Example

[0106] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more and any combination of the examples described below.

[0107] Example 1 includes a device comprising: a monolithic glass substrate, the monolithic glass substrate including one or more waveguides defined in the glass substrate; and one or more lenses defined in the glass substrate, wherein each of the one or more lenses is to collimate light from each of the one or more waveguides, wherein each of the one or more lenses is defined at least in part by a varying refractive index in the monolithic glass substrate.

[0108] Example 2 includes the subject matter of Example 1, and wherein each of the one or more lenses is a gradient index (GRIN) lens.

[0109] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein each of the one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

[0110] Example 4 includes the subject matter of any of Examples 1-3, and wherein the one or more waveguides include at least four waveguides.

[0111] Example 5 includes the subject matter of any of Examples 1-4, and further includes a photonic integrated circuit (PIC) die paired with a glass substrate, wherein one or more waveguides are defined in the PIC die, wherein respective ones of the one or more waveguides of the glass substrate are butt-coupled to respective ones of the one or more waveguides of the PIC die.

[0112] Example 6 includes the subject matter of any of Examples 1-5, and further includes an electronic integrated circuit (EIC) die paired with the PIC die.

[0113] Example 7 includes the subject matter of any of Examples 1-6, and further includes a circuit board, wherein the EIC die is mounted on the circuit board.

[0114] Example 8 includes the subject matter of any of Examples 1-7, and further includes an optical receptacle comprising a glass substrate.

[0115] Example 9 includes the subject matter of any of Examples 1-8, and further includes: an optical plug mated with an optical receptacle, the optical plug comprising a second monolithic glass substrate, the second monolithic glass substrate comprising one or more cavities defined in the second glass substrate; and one or more lenses defined in the second glass substrate and one or more optical fibers disposed in the one or more cavities, wherein each of the one or more lenses of the second glass substrate is to collimate light from each of the one or more optical fibers.

[0116] Example 10 includes the subject matter of any of Examples 1-9, and wherein the one or more lenses in the glass substrate and the one or more lenses in the second glass substrate are to couple light from the one or more optical fibers to the one or more waveguides.

[0117] Example 11 includes a device comprising: a monolithic glass substrate including one or more cavities defined in the glass substrate; and one or more lenses defined in the glass substrate and one or more optical fibers disposed in the one or more cavities, wherein each of the one or more lenses is to collimate light from each of the one or more optical fibers.

[0118] Example 12 includes the subject matter of Example 11, and wherein individual lenses of the one or more lenses are defined at least in part by a varying refractive index in a monolithic glass substrate.

[0119] Example 13 includes the subject matter of any of Examples 11 and 12, and wherein each of the one or more lenses is a gradient refractive index (GRIN) lens.

[0120] Example 14 includes the subject matter of any of Examples 11-13, and wherein each of the one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

[0121] Example 15 includes the subject matter of any of Examples 11-14, and wherein each of the one or more lenses is defined at least in part by a curved surface of a surface of the monolithic glass substrate.

[0122] Example 16 includes the subject matter of any of Examples 11-15, and wherein the one or more optical fibers include at least four waveguides.

[0123] Example 17 includes the subject matter of any of Examples 11-16, and further includes an optical plug comprising a glass substrate.

[0124] Example 18 includes the subject matter of any of Examples 11-17, and further includes an optical receptacle mated with an optical plug, the optical receptacle comprising: a second monolithic glass substrate, the second monolithic glass substrate comprising one or more waveguides defined in the second glass substrate; and one or more lenses defined in the second glass substrate, wherein each of the one or more lenses of the second glass substrate is to collimate light from each of the one or more waveguides, wherein each of the one or more lenses of the second glass substrate is defined at least in part by a varying refractive index in the monolithic glass substrate.

[0125] Example 19 includes the subject matter of any of Examples 11-18, and wherein the one or more lenses in the glass substrate and the one or more lenses in the second glass substrate are to couple light from the one or more optical fibers to the one or more waveguides.

[0126] Example 20 includes a method comprising: writing one or more waveguides in a glass substrate using a laser; forming a first set of one or more lenses and a second set of one or more lenses in the glass substrate using a laser; creating one or more cavities for optical fibers in the glass substrate; and creating a seam in the glass substrate, wherein creating the seam comprises preparing the seam for etching using a laser and etching the seam using an etchant, wherein the seam separates the glass substrate into a glass substrate for an optical plug and a glass substrate for an optical receptacle, wherein the glass substrate for the optical plug has one or more cavities defined therein, wherein the glass substrate for the optical plug includes a first set of one or more lenses, wherein each lens in the first set of one or more lenses is positioned to collimate light from an optical fiber placed in a corresponding cavity in the one or more cavities, wherein the glass substrate for the optical receptacle has one or more waveguides defined therein, wherein the glass substrate for the optical plug includes a second set of one or more lenses, wherein each lens in the second set of one or more lenses is positioned to collimate light from each of the one or more waveguides.

[0127] Example 21 includes the subject matter of Example 20, and wherein forming a first set of one or more lenses and a second set of one or more lenses includes using a laser to write to individual lenses in the first set of one or more lenses and the second set of one or more lenses to change the refractive index of a region of the glass substrate.

[0128] Example 22 includes the subject matter of any of Examples 20 and 21, and wherein each lens in the first set of one or more lenses and the second set of one or more lenses is a gradient refractive index (GRIN) lens.

[0129] Example 23 includes the subject matter of any of Examples 20-22, and wherein each lens in the first set of one or more lenses and the second set of one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

[0130] Example 24 includes the subject matter of any of Examples 20-23, and wherein each lens of a first set of one or more lenses is defined at least in part by a curved surface of a surface of a glass substrate for an optical plug, and wherein each lens of a second set of one or more lenses is defined at least in part by a curved surface of a surface of a glass substrate for an optical receptacle.

Claims

1. A device comprising: A single-piece glass substrate, the single-piece glass substrate comprising: one or more waveguides defined in the glass substrate; and one or more lenses defined in the glass substrate, wherein each of the one or more lenses is to collimate light from each of the one or more waveguides, Wherein, each of the one or more lenses is defined at least in part by a varying refractive index in the monolithic glass substrate.

2. The device according to claim 1, wherein: Each lens of the one or more lenses is a gradient index (GRIN) lens.

3. The device of claim 1, wherein: Each of the one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

4. The device of claim 1, wherein: The one or more waveguides include at least four waveguides.

5. The device of any one of claims 1 to 4, further comprising a photonic integrated circuit (PIC) die paired with the glass substrate, wherein: defining one or more waveguides in the PIC die, Wherein, each of the one or more waveguides of the glass substrate is butt-coupled to each of the one or more waveguides of the PIC die.

6. The apparatus of claim 5, further comprising an electronic integrated circuit (EIC) die mated with the PIC die.

7. The apparatus of claim 6, further comprising a circuit board, wherein the EIC die is mounted on the circuit board.

8. The apparatus of any one of claims 1 to 4, further comprising an optical receptacle comprising the glass substrate.

9. The device of claim 8, further comprising an optical plug mated with the optical receptacle, the optical plug comprising: A second monolithic glass substrate, the second monolithic glass substrate comprising: one or more cavities defined in the second glass substrate; and one or more lenses defined in the second glass substrate, and one or more optical fibers disposed in the one or more cavities, Each of the one or more lenses of the second glass substrate is to collimate light from each of the one or more optical fibers.

10. The device of claim 9, wherein: The one or more lenses in the glass substrate and the one or more lenses in the second glass substrate are to couple light from the one or more optical fibers to the one or more waveguides.

11. A device comprising: A single-piece glass substrate, the single-piece glass substrate comprising: one or more cavities defined in the glass substrate; and one or more lenses defined in the glass substrate, and one or more optical fibers disposed in the one or more cavities, Each of the one or more lenses is configured to collimate light from each of the one or more optical fibers.

12. The device of claim 11, wherein: Each of the one or more lenses is defined at least in part by a varying refractive index in the monolithic glass substrate.

13. The apparatus of claim 12, wherein: Each lens of the one or more lenses is a gradient index (GRIN) lens.

14. The apparatus of claim 12, wherein: Each of the one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

15. The apparatus of claim 11, wherein: Each of the one or more lenses is defined at least in part by a curvature of a surface of the monolithic glass substrate.

16. The apparatus of claim 11, wherein: The one or more optical fibers include at least four waveguides.

17. The apparatus of any one of claims 11 to 16, further comprising an optical plug, the optical plug comprising the glass substrate.

18. The apparatus of claim 17, further comprising an optical receptacle mated with the optical plug, the optical receptacle comprising: A second monolithic glass substrate, the second monolithic glass substrate comprising: one or more waveguides defined in the second glass substrate; and one or more lenses defined in the second glass substrate, wherein each of the one or more lenses of the second glass substrate is to collimate light from each of the one or more waveguides, Wherein, each of the one or more lenses of the second glass substrate is defined at least in part by a varying refractive index in the single glass substrate.

19. The apparatus of claim 18, wherein: The one or more lenses in the glass substrate and the one or more lenses in the second glass substrate are to couple light from the one or more optical fibers to the one or more waveguides.

20. A method comprising: writing one or more waveguides in a glass substrate using a laser; forming a first set of one or more lenses and a second set of one or more lenses in the glass substrate using a laser; creating one or more cavities in the glass substrate for optical fibers; as well as creating a seam in the glass substrate, wherein creating the seam includes using a laser to prepare the seam for etching and etching the seam with an etchant, wherein the seam separates the glass substrate into a glass substrate for an optical plug and a glass substrate for an optical receptacle, wherein the glass substrate for the optical plug has the one or more cavities defined therein, wherein the glass substrate for the optical plug includes a first set of the one or more lenses, wherein each lens of the first set of the one or more lenses is positioned to collimate light from an optical fiber placed in a corresponding cavity of the one or more cavities, wherein the glass substrate for the optical receptacle has the one or more waveguides defined therein, wherein the glass substrate for the optical plug comprises a second set of the one or more lenses, wherein each lens of the second set of one or more lenses is positioned to collimate light from each of the one or more waveguides.

21. The method of claim 20, wherein: Forming the first set of one or more lenses and the second set of one or more lenses includes using the laser to write individual lenses of the first set of one or more lenses and the second set of one or more lenses to change a refractive index of a region of the glass substrate.

22. The method of claim 21, wherein: Each lens in the first set of one or more lenses and the second set of one or more lenses is a gradient index (GRIN) lens.

23. The method of claim 21, wherein: Each lens of the first set of one or more lenses and the second set of one or more lenses is defined by a region having a fixed difference in refractive index relative to the bulk of the glass substrate.

24. The method of claim 20, wherein: each lens of the first set of one or more lenses is defined at least in part by a curved surface of a surface of the glass substrate for the optical plug, Wherein, each lens of the second set of one or more lenses is defined at least in part by a curved surface of a surface of the glass substrate for the optical receptacle.

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