Display panel

Abstract

Embodiments of the present application disclose a display panel, comprising a plurality of sub-pixels arranged in an array, further comprising a substrate and a shielding electrode; the sub-pixel is located on the substrate, and the shielding electrode is located between the substrate and the sub-pixel; wherein the sub-pixel comprises a pixel electrode, at least a part of the shielding electrode is located in an opening area of the sub-pixel, a first side edge of the shielding electrode and a first side edge of the pixel electrode do not overlap, the first side edge of the shielding electrode is a side edge of the shielding electrode close to a non-opening area of the sub-pixel, and the first side edge of the pixel electrode is a side edge of the pixel electrode close to the non-opening area. In the non-opening area of the sub-pixel, the first side edge of the shielding electrode and the first side edge of the pixel electrode do not overlap, which can effectively avoid the electric field effect between the shielding electrode and the pixel electrode, prevent the liquid crystal from being disordered, and further improve the light output efficiency.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] Current liquid crystal displays (LCDs) typically use metal as the array-side common electrode to reduce the impact of parasitic capacitance on the display. However, the opacity of the metal layer reduces the light-emitting area, thus lowering transmittance. To address this, the transparent shielding and storage electrode (TSS) structure, by adding a transparent electrode (TSS ITO layer) to replace part of the original metal electrode, serves as both a storage capacitor and a shielding electrode. This reduces pixel dark areas, increases aperture ratio, and ultimately improves panel transmittance.

[0003] However, the superposition of the TSS ITO layer with other metal layers can lead to complex edge fields in the pixel structure, causing disorder in the liquid crystal arrangement and resulting in suboptimal light output. Summary of the Invention

[0004] The embodiments of this application provide a display panel to at least solve the technical problem that in existing pixel structures, the edge field of the pixel structure becomes complex due to the superposition of metal layers, causing disorder in the liquid crystal arrangement and resulting in unsatisfactory light output.

[0005] Embodiments of this application provide a display panel, the display panel including a plurality of sub-pixels arranged in an array, the display panel further including: a substrate, the sub-pixels being located on the substrate; a shielding electrode, the shielding electrode being located between the substrate and the sub-pixels; wherein, the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in an opening region of the sub-pixel, a first side of the shielding electrode and a first side of the pixel electrode do not overlap, the first side of the shielding electrode being a side of the shielding electrode near the non-opening region of the sub-pixel, and the first side of the pixel electrode being a side of the pixel electrode near the non-opening region.

[0006] In one embodiment, the non-opening region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-opening region; wherein the distance from the first side of the shielding electrode to the via is greater than the distance from the first side of the pixel electrode to the via.

[0007] In one embodiment, the distance L1 between the first side of the shielding electrode and the via satisfies the following range: L1≥5μm.

[0008] In one embodiment, the display panel further includes a common electrode, the common electrode including a common electrode trace, the common electrode trace being located between the substrate and the shielding electrode, and the common electrode trace being located at the boundary between the opening area and the non-opening area; wherein, the distance from the first side of the common electrode trace to the via is less than the distance from the first side of the shielding electrode to the via, and the first side of the common electrode trace is the side of the common electrode trace away from the via.

[0009] In one embodiment, the non-opening region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-opening region; wherein the distance from the first side of the shielding electrode to the via is less than the distance from the first side of the pixel electrode to the via.

[0010] In one embodiment, the display panel further includes a data line disposed between adjacent sub-pixels, the data line being located between the substrate and the shielding electrode, wherein the orthographic projection of the data line on the substrate partially overlaps with the orthographic projection of the frame of the pixel electrode on the substrate in the width direction of the data line.

[0011] In one embodiment, the overlap width between the orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate is set to L2, and the pixel interval between two adjacent sub-pixels is L3. The ratio of L3 to L2 satisfies: L3 / L2 > 1.6.

[0012] In one embodiment, the overlap width L2 between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode border on the substrate satisfies the following range: L2≤3μm.

[0013] In one embodiment, the pixel spacing L3 between two adjacent sub-pixels satisfies the following range: L3 ≥ 5 μm.

[0014] In one embodiment, the display panel further includes a color resist layer disposed on the side of the shielding electrode near the substrate.

[0015] The beneficial effects provided by the embodiments of this application include at least the following:

[0016] This application provides a display panel including a plurality of sub-pixels arranged in an array, a substrate, and a shielding electrode. The sub-pixels are located on the substrate, and the shielding electrode is located between the substrate and the sub-pixels. Each sub-pixel includes a pixel electrode, and at least a portion of the shielding electrode is located in the opening region of the sub-pixel. The first side of the shielding electrode and the first side of the pixel electrode do not overlap. The first side of the shielding electrode is the side of the shielding electrode closest to the non-opening region of the sub-pixel, and the first side of the pixel electrode is the side of the pixel electrode closest to the non-opening region. In this application embodiment, the sub-pixel can be a rectangular structure. Metal traces such as thin-film transistors (TFTs) and common electrodes are generally disposed in the short side region of the sub-pixel. The voltage difference between the transparent shielding electrode (TSS ITO) and the pixel electrode can cause edge electric field disturbance on the short side of the sub-pixel. Therefore, in the non-opening region of the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap. That is, the shielding electrode is moved up or down to avoid the pixel electrode at the via, which can effectively avoid the electric field effect between the shielding electrode and the pixel electrode, prevent liquid crystal sorting disorder, and thus improve light extraction efficiency.

[0017] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a display panel provided in an optional embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the structure of a sub-pixel provided in an optional embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the structure of the boundary region between the opening and non-opening regions of a sub-pixel provided in an optional embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the pixel structure of a display panel provided in an optional embodiment of this application;

[0022] Figure 5 yes Figure 4 A schematic diagram of the AA section;

[0023] Figure 6 This is a schematic diagram of the structure of the spacing region between adjacent sub-pixels provided in an optional embodiment of this application;

[0024] Figure 7 This is a cross-sectional schematic diagram of the spacing region between adjacent sub-pixels provided in an optional embodiment of this application;

[0025] Figure 8This is a simulation diagram illustrating the alignment improvement effect provided in an optional embodiment of this application;

[0026] Figure 9 This is a simulation diagram illustrating a color shift improvement effect provided in an optional embodiment of this application;

[0027] Figure 10 This is a schematic diagram of the structure of a display terminal provided in an optional embodiment of this application.

[0028] Explanation of reference numerals in the attached figures

[0029] 1. Display panel;

[0030] 10, Substrate; 11, Subpixel; A, Aperture area; B, Non-aperture area; 111, Common electrode trace; 1111, First side of common electrode trace; 112, Shielding electrode; 1121, First side of shielding electrode; 113, Pixel electrode; 1130, First side of pixel electrode; 1131, First main branch; 1132, Second main branch; 1133, First branch; 1134, Second branch; 1135, Pixel electrode border; 114, First metal layer; 1141, First trace; 1142, Data line; 115, Via; 116, Color resist layer; 1161, First color resist layer; 1162, Second color resist layer; 117, Liquid crystal;

[0031] 20. Color filter substrate;

[0032] 2. Display terminal;

[0033] 3; Terminal main body. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0035] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0036] The directional terms used in this application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this application, and not for limiting the scope of protection of this application.

[0037] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and this application does not limit the dimensions and thicknesses of each component.

[0038] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0039] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0040] Reference Figure 1 As shown, an embodiment of this application provides a display panel 1, including a display area AA and a non-display area NA disposed on a substrate 10. The display area AA includes a plurality of sub-pixels 11 arranged in an array. Each sub-pixel 11 corresponds to one of the three colors: red, green, and blue. In this embodiment, a rectangular sub-pixel structure is used as an example for explanation.

[0041] The display panel 1 of this application adopts a vertical alignment (VA) technology-driven architecture. (See reference...) Figure 1 and Figure 5 As shown, the display panel 1 includes an array substrate 10, a liquid crystal layer 117, and an opposing substrate 20 (which may be a color filter substrate) arranged sequentially. The common electrode on the opposing substrate 20 and the pixel electrode on the array substrate 10 form a vertical electric field after being connected to different voltages, thereby driving the liquid crystal in the liquid crystal layer 117 to deflect and thus realize the display of the image.

[0042] Reference Figure 2 and Figure 3 As shown, the display panel 1 further includes: a substrate 10, with sub-pixels 11 located on the substrate 10; and a shielding electrode 112 located between the substrate 10 and the sub-pixels 11. The sub-pixels 11 include a pixel electrode 113, at least a portion of the shielding electrode 112 is located in the opening region A of the sub-pixels 11, the first side 1121 of the shielding electrode 112 and the first side 1131 of the pixel electrode 113 do not overlap, the first side 1121 of the shielding electrode 112 is the side of the shielding electrode 112 near the non-opening region B of the sub-pixels 11, and the first side 1130 of the pixel electrode is the side of the pixel electrode 113 near the non-opening region B.

[0043] In this embodiment, metal traces such as TFTs and common electrodes are generally located in the non-aperture area of ​​the sub-pixel. The voltage difference between the transparent shielding electrode (TSS ITO) and the pixel electrode can cause edge electric field disturbance on the short side of the sub-pixel. Therefore, in the short side region of the sub-pixel (which can be understood as the non-aperture area B), the complex terrain of the short side of the sub-pixel can be improved by the staggered design of each film layer, and the influence of the complex edge electric field on the center electric field of the normal display area can be reduced. In this embodiment, in the non-aperture area B of the sub-pixel, the first side 1121 of the shielding electrode and the first side 1130 of the pixel electrode do not overlap. That is, the shielding electrode is moved up or down to avoid the pixel electrode at the via, which can effectively avoid the electric field effect between the shielding electrode 112 and the pixel electrode 113, prevent liquid crystal sorting disorder, and thus improve light extraction efficiency.

[0044] In an optional embodiment, the non-opening region B includes a thin-film transistor 116, and the pixel electrode 113 is connected to the thin-film transistor 116 through a via 115 located in the non-opening region B; wherein, the distance from the first side 1121 of the shielding electrode to the via 115 is greater than the distance from the first side 1131 of the pixel electrode to the via 115.

[0045] In an optional embodiment, the distance L1 between the first side 1121 of the shielding electrode and the via 115 satisfies the following range: L1 ≥ 5 μm. For example, L1 can be set to 5 μm, 6 μm, or 7 μm, etc., so that by moving the shielding electrode 112 up or down to avoid the pixel electrode 113 at the via 115, the electric field effect between the shielding electrode and the pixel electrode can be effectively avoided, preventing liquid crystal sorting disorder, thereby improving light extraction efficiency.

[0046] The shielding electrode 112 can be a TSS transparent electrode, which can be used in vertically aligned liquid crystal displays (VA-LCDs) to replace traditional shielding and storage metal electrodes. The shielding electrode 112 can be a full-surface metal layer with holes punched in the opening areas and partially non-opening areas of the sub-pixels. Its main purpose is to improve the transmittance and optical efficiency of the display, thereby achieving energy savings. In traditional liquid crystal displays, the shielding and storage electrodes are usually made of metal materials, which absorb some light and reduce the transmittance of the display. The TSS transparent electrode, by using a transparent material, reduces light absorption, thereby improving transmittance.

[0047] In an optional embodiment, the display panel 1 further includes a common electrode, which includes a common electrode trace 111 located between the substrate 10 and the shielding electrode 112, and located at the boundary between the opening region A and the non-opening region B; wherein the distance from the first side 1111 of the common electrode trace to the via 115 is less than the distance from the first side 1121 of the shielding electrode to the via 115, and the first side 1111 of the common electrode trace is the side of the common electrode trace 111 away from the via 115.

[0048] Reference Figure 2 and Figure 3 As shown, in an optional embodiment, the pixel electrode 113 includes a pixel electrode border 1135, a first main stem 1131 disposed along the length direction of the sub-pixel 11 (as shown in the Y direction), one or more second main stems 1132 disposed perpendicular to the first main stem 1131, a plurality of first branches 1133, and second branches 1134 connected to the first branches. The first main stem 1131 and the second main stem 1132 divide the sub-pixel 11 into a multi-domain region. The first branches 1133 are arranged parallel to each other and spaced apart in each domain region at a preset angle. The orthographic projection of the portion of the first branch 1133 that connects to the second branch 1134 on the substrate 10 does not overlap with the orthographic projection of the shielding electrode 1121 on the substrate 10.

[0049] It should be noted that the sub-pixel 11 in this embodiment is a multi-domain pixel, such as a four-domain, six-domain, or eight-domain pixel, which can be selected according to the actual application, and this application does not limit it. In this embodiment, a four-domain sub-pixel is used as an example for description in conjunction with the accompanying drawings. That is, the pixel electrode 113 in this embodiment includes a first main branch 1131 and a second main branch 1132 perpendicular to the first main branch 1131, dividing the sub-pixel 11 into four regions.

[0050] By using a staggered design for each film layer, the complex topography of the short side of the sub-pixel (which can be understood as the non-aperture region B) can be improved, and the influence of the complex edge electric field of the short side on the center electric field of the normal display area can be reduced. The orthographic projection of the part where the first branch 1133 and the second branch 1134 meet on the substrate 10 does not overlap with the orthographic projection of the common electrode trace 111 on the substrate 10. That is, the corner of the pixel electrode 113 in the short side region of the sub-pixel (refer to...) Figure 3 The pixel electrode (as shown in the elliptical dashed box) is staggered from the common electrode trace 111, which can effectively avoid the electric field effect between the pixel electrode and the common electrode, prevent liquid crystal sorting disorder, and thus improve light extraction efficiency.

[0051] Continue to refer to Figure 2 and Figure 3As shown, in an optional embodiment, the display panel further includes a first metal layer 114, which is disposed between the common electrode trace 111 and the shielding electrode 112. The first metal layer 114 includes a first trace 1141 disposed on the sub-pixel 11, and the first trace 1141 is connected to the second branch 1134 of the pixel electrode through a via 115; wherein, the orthographic projection of the portion of the first branch 1133 of the pixel electrode that is in contact with the second branch 1134 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0052] By designing the staggered layers, the complex topography of the non-aperture area B of the sub-pixel can be improved, and the influence of the complex edge electric field of the short side of the non-aperture area B on the center electric field of the normal display area can be reduced. The orthographic projection of the part where the first branch 1133 and the second branch 1134 meet on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10. That is, the pixel electrode 113 is staggered from the via 115 at the corner of the non-aperture area of ​​the sub-pixel. This can effectively prevent the pixel electrode 113 from forming a complex edge electric field between the position of the via 115 and the first trace 1141 of the first metal layer 114 and the second branch 1134 of the pixel electrode, thus preventing liquid crystal sorting disorder and improving light extraction efficiency.

[0053] In an alternative embodiment, the orthographic projection of the shielding electrode 112 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0054] In an alternative embodiment, the orthographic projection of the common electrode trace 111 on the substrate 10 does not overlap with the orthographic projection of the via 115 on the substrate 10.

[0055] By staggering the shielding electrode 112 or the common electrode trace 111 with the via 115, the formation of complex edge electric fields between multiple film layers can be effectively avoided, preventing liquid crystal sorting disorder and thus improving light extraction efficiency.

[0056] In an optional embodiment, the first side 1121 of the shielding electrode and the first side 1111 of the common electrode trace are in a first direction (e.g. Figure 3 The spacing distance (as shown in the Y direction) ranges from 1 to 3 μm. By shifting the TSS downwards or upwards, the electric field at the short edge can be controlled, thus reducing the dark fringes at the short edge.

[0057] Figure 4 This is a schematic diagram of the pixel structure of a display panel provided in an optional embodiment of this application. Figure 5 yes Figure 4 The schematic diagram of the AA section should be noted. Figure 4 What is shown is a single sub-pixel. Figure 5 This diagram shows a cross-sectional view of the adjacent long edges of two adjacent sub-pixels. (Refer to...) Figure 4 and Figure 5 As shown, the first metal layer 114 also includes data lines 1142 disposed between adjacent sub-pixels. The gap between the data lines 1142 and the pixel electrodes 113 between adjacent sub-pixels is too large; for example, the horizontal distance between the data lines 1142 and the left and right pixel electrodes 113 is approximately 1.4 μm. A lateral electric field exists between the shielding electrode 1121 and the pixel electrodes 113, causing the liquid crystal 117 between the data lines 1142 and the pixel spacing to deflect, resulting in light leakage from the pixels and consequently causing color shift in the panel.

[0058] To solve the above problems, refer to Figures 2 to 7 As shown, in this embodiment of the application, the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 partially overlap in the width direction of the data line 1142.

[0059] In one embodiment, the non-aperture region includes a thin-film transistor 116, and the pixel electrode 113 is connected to the thin-film transistor 116 through a via 115 located in the non-aperture region B. The distance from the first side 1121 of the shielding electrode to the via 115 is less than the distance from the first side 1131 of the pixel electrode to the via 115. The edge of the shielding electrode 112 near the via 115 is offset from the edge of the pixel electrode 113 near the via 115. Moving the shielding electrode 112 upwards or downwards to avoid the pixel electrode 113 at the via 115 effectively avoids the electric field effect between the shielding electrode 112 and the pixel electrode 113, preventing liquid crystal sorting disorder and thus improving light extraction efficiency.

[0060] In one embodiment, the display panel 1 further includes a data line 1142 disposed between adjacent sub-pixels 11. The data line 1142 is located between the substrate 10 and the shielding electrode 112. The orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the frame 1135 of the pixel electrode on the substrate 10 partially overlap in the width direction of the data line 1142.

[0061] In one embodiment, the overlap width between the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 is set to L2, and the pixel spacing between two adjacent sub-pixels 11 is set to L3. The ratio of L3 to L2 satisfies: L3 / L2 > 1.6. By controlling the range of the ratio of L2 to L3, for example, setting the ratio to 1.65, 1.7, 1.75, etc., the disordered tilting of the liquid crystal under the TSS electric field can be reduced, making the azimuth angle of the liquid crystal closer to 45°, optimizing the alignment dark lines, and thus improving the transmittance Tr%. As shown in Table 1 below, when L3 / L2 > 1.6, Tr% is effectively improved, from 4.46% to 4.75%.

[0062] Table 1

[0063] Penetration rate Before improvement After improvement Tr％ 4.46％ 4.75％

[0064] Provided that L3 / L2 > 1.6, or even without considering the ratio of L3 / L2, the transmittance of the display panel can be improved and color shift reduced by setting the value ranges of L2 and L3 respectively.

[0065] Continue to refer to Figure 6 and Figure 7 As shown, in one embodiment, the overlap width L2 between the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 satisfies the following range: L2 ≤ 3 μm. In an optional embodiment, the overlap width between the trunk portion and the data line can also be adjusted by widening the width L4 of the data line 1142. Optionally, the overlap width between the orthographic projection of the data line 1142 on the substrate 10 and the border 1135 of the pixel electrode (equivalent to...) is... Figure 6 The overlap width L2 of the orthographic projection of the Trunk portion shown on the substrate can be less than or equal to 3 μm, for example, set to 1.5 to 3 μm.

[0066] In one embodiment, the pixel spacing L3 between two adjacent sub-pixels 11 satisfies the following range: L3 ≥ 5 μm. (Refer to...) Figure 7 As shown, in an optional embodiment, the pixel spacing L3 between two adjacent sub-pixels can be greater than or equal to 5μm, for example, set to 5μm, 6μm, or 7μm, and the width of the data line 1142 can be greater than the pixel spacing between two adjacent sub-pixels. By setting an appropriate pixel spacing, color shift problems caused by color resist interfering with adjacent sub-pixels due to process fluctuations can be avoided.

[0067] The first branch 1133 of the pixel electrode 113 can be connected together at the edge to form a vertically elongated trunk structure, namely the frame 1135 of the aforementioned pixel electrode. (See reference...) Figure 6 As shown within the dashed box, the entire pixel electrode 113 can also be understood as a single rectangular ITO electrode, containing parallel, spaced-apart cutouts within the segmented multi-domain regions. In this embodiment, the trunk width can be appropriately reduced, for example, by setting the trunk width to 2.5 to 4 μm, so that the trunk portion further overlaps with the width direction of the data line 1142. By using a suitable trunk width, the dark lines caused by the edge field of the long side of the sub-pixel can be improved, resulting in a larger light-emitting area in the normal display area, thereby improving the light extraction efficiency.

[0068] Choosing an appropriate trunk width can effectively reduce interference between signal lines. Too narrow a width may exacerbate electromagnetic interference between signal lines, while too wide a width may increase the complexity and cost of the circuit board. Simultaneously, when designing data lines, ensure they completely block edge light leakage. This can be achieved through an overlay design between the data line and the pixel, where the data line covers the edge of the pixel to prevent light leakage. With an overlay design, the data line can completely block edge light leakage, reducing light leakage from the edges and thus improving display quality. Furthermore, ensure the distance between pixels is appropriate to avoid color resistivity crosstalk caused by excessive proximity. In display panels, color resistivity crosstalk refers to color interference between different pixels due to resistance variations. Optimizing the distance between pixels can reduce this interference. On one hand, appropriate pixel spacing can reduce color resistivity crosstalk caused by process fluctuations, ensuring display stability. On the other hand, during manufacturing, process fluctuations may cause changes in resistance and capacitance, thus affecting display quality. Proper design can reduce the impact of these fluctuations on display quality.

[0069] During the design process, this application embodiment determines the optimal trunk width and data line layout through simulation and testing. This ensures the data lines completely cover the pixel edges, reducing light leakage. Based on actual test results, the distance between pixels (which can be understood as the distance between adjacent sub-pixels) is adjusted to ensure good display performance under different grayscale levels and viewing angles. Referring to Table 2 below, when the overlap width L2 of the orthographic projection of the data line 1142 on the substrate 10 and the orthographic projection of the pixel electrode border 1135 on the substrate 10 satisfies L2≤3μm and the pixel spacing L3≥5μm, the contrast ratio viewing angle is effectively improved. Contrast ratio viewing angle (CR) refers to the change in contrast of a display under different viewing angles. Contrast ratio is the ratio of brightness when the display shows the brightest (white) to the darkest (black) image. High contrast ratio means clearer images and more vivid colors. CR(-30) represents the contrast ratio value measured at a -30 degree viewing angle. -30-degree and +30-degree viewing angles refer to positions deviating 30 degrees to the left or right from directly in front of the monitor. A higher contrast ratio indicates that the monitor maintains good contrast and image quality even at a -30-degree viewing angle. In this embodiment, reasonable pixel spacing values ​​are set. The CR(-30) before improvement is 38.8%, and the CR(-30) after improvement is 55.4%. The CR(+30) before improvement is 37.3%, and the CR(+30) after improvement is 54.9%, indicating a significant improvement in contrast and image quality at a -30-degree viewing angle.

[0070] Table 2

[0071] Contrast View Before improvement After improvement CR(-30) 38.80％ 55.40％ CR(+30) 37.30％ 54.90％

[0072] Reference Figure 8 and Figure 9 As shown, Figure 8 The figure shown is a simulation diagram illustrating the alignment improvement effect provided in an optional embodiment of this application. Figure 9 The diagram shown is a simulation illustration of the color shift improvement effect provided in an optional embodiment of this application. It can be seen that the display panel structure provided in this embodiment effectively improves the dark patterns and color shift on the short and long sides of the pixels, and the images displayed in the light-emitting areas are all normal images.

[0073] Reference Figure 5 As shown, in an optional embodiment, the display panel further includes an amorphous silicon layer 118 disposed on the side of the data line 1142 near the substrate 10; wherein, between adjacent sub-pixels 11, the orthographic projection of the data line 1142 on the substrate 10 covers the orthographic projection of the amorphous silicon layer 118 on the substrate 10.

[0074] In one embodiment, the display panel further includes a color resist layer 116 disposed on the side of the shielding electrode 112 near the substrate 10.

[0075] In this embodiment, the color resist layer 116 may include multiple red, green, and blue color resists. Each color resist in the layer is used to convert white light into the corresponding colored light. In the display area, one color resist is correspondingly assigned to one sub-pixel 11, as shown below. Figure 7 As shown, the color resist layers of two adjacent sub-pixels are of different colors. For example, color resist layers 1161 and 1162 can be blue and red, or green and red, respectively. Sub-pixel 11 with red color resist is a red sub-pixel, sub-pixel 11 with green color resist is a green sub-pixel, and sub-pixel 11 with blue color resist is a blue sub-pixel. Color resist layer 116 is typically composed of tiny red, green, and blue (RGB) filters, which are precisely placed on each sub-pixel of the liquid crystal panel. Each sub-pixel corresponds to a color, and by controlling the color and brightness of the light passing through that sub-pixel, a full-color image is ultimately formed. The structure of the color resist layer typically includes: filters, made of organic dyes or inorganic pigments, used to filter light of specific wavelengths; a black matrix, disposed between the filters, used to absorb excess light, prevent interference between colors, and improve the contrast and clarity of the display; and a protective layer, covering the filters and the black matrix, to prevent physical damage and environmental influences.

[0076] It should be understood that in this embodiment, the display panel 1 is a COA (Color Filter on Array) architecture panel, and the color filter substrate 20 is disposed opposite the substrate 10 (Array substrate). By setting the display panel 1 as a COA architecture panel, the color resist layer 116 and the pixel electrode 113 can be disposed on the same substrate 10, thereby avoiding the loss of aperture ratio caused by the alignment deviation of the two substrates when the color resist layer 116 and the pixel electrode 113 are disposed on different substrates. That is, the use of the COA architecture helps to increase the alignment accuracy of the color resist layer 116 and the pixel electrode 113, and improve the aperture ratio of the display panel 1.

[0077] The display panel in this embodiment may further include an insulating layer, a passivation layer, or a planarization layer disposed between different metal layers. The insulating layer may be composed of inorganic materials, such as glass, quartz, ceramic, alumina, boron nitride, magnesium oxide, calcium silicate, borate glass, etc. The passivation layer may be formed using inorganic materials, such as silicon nitride. The planarization layer is used to smooth the substrate surface to reduce surface roughness and unevenness, thereby providing better conditions for subsequent manufacturing processes. The materials for the planarization layer typically include oxides, nitrides, polycrystalline silicon, polymers, etc. The selection of these materials depends on the required electrical, mechanical, and chemical properties. The manufacturing processes for the planarization layer include chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, spraying, etc. These processes ensure that the planarization layer is uniformly distributed on the substrate, forming a smooth surface. In this embodiment, the planarization layer is used to ensure the uniformity and consistency of the display panel.

[0078] The shielding electrode 112 and the pixel electrode 113 can be transparent metals, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0079] Reference Figure 9 As shown, another embodiment of this application also provides a display terminal 2, including a display panel 1 and a terminal body 3 as described in any of the above embodiments, wherein the display panel 1 and the terminal body 3 are integrated into one unit. The terminal body 3 may include a backlight module, which is disposed on the side of the substrate 10 of the display panel 1 facing away from the color resist layer 116. The backlight module is used to provide a light source for the display panel 1.

[0080] The display terminal can be any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0081] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, The display panel includes multiple sub-pixels arranged in an array, and the display panel also includes: A substrate, wherein the sub-pixels are located on the substrate; A shielding electrode is located between the substrate and the sub-pixel; Wherein, the sub-pixel includes a pixel electrode, at least a portion of the shielding electrode is located in the opening region of the sub-pixel, the first side of the shielding electrode and the first side of the pixel electrode do not overlap, the first side of the shielding electrode is the side of the shielding electrode closer to the non-opening region of the sub-pixel, and the first side of the pixel electrode is the side of the pixel electrode closer to the non-opening region. The display panel also includes a data line disposed between adjacent sub-pixels. The data line is located between the substrate and the shielding electrode. The orthographic projection of the data line on the substrate and the orthographic projection of the frame of the pixel electrode on the substrate partially overlap in the width direction of the data line. The overlap width between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode border on the substrate is set to L2, and the pixel spacing between two adjacent sub-pixels is set to L3. The ratio of L3 to L2 satisfies the following relationship: L3 / L2 > 1.6; The overlap width L2 between the orthographic projection of the data line on the substrate and the orthographic projection of the pixel electrode frame on the substrate satisfies: L2≤3μm; The value range of the pixel spacing L3 between two adjacent sub-pixels satisfies: L3≥5μm.

2. The display panel according to claim 1, characterized in that, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; The distance from the first side of the shielding electrode to the via is greater than the distance from the first side of the pixel electrode to the via.

3. The display panel according to claim 2, characterized in that, The distance L1 between the first side of the shielding electrode and the via satisfies the following range: L1≥5μm.

4. The display panel according to claim 2, characterized in that, The display panel further includes a common electrode, which includes a common electrode trace located between the substrate and the shielding electrode, and located at the boundary between the opening area and the non-opening area; Wherein, the distance from the first side of the common electrode trace to the via is less than the distance from the first side of the shielding electrode to the via, and the first side of the common electrode trace is the side of the common electrode trace away from the via.

5. The display panel according to claim 1, characterized in that, The non-aperture region includes a thin-film transistor, and the pixel electrode is connected to the thin-film transistor through a via located in the non-aperture region; Wherein, the distance from the first side of the shielding electrode to the via is less than the distance from the first side of the pixel electrode to the via.

6. The display panel according to any one of claims 1 to 5, characterized in that, The display panel also includes a color resist layer, which is disposed on the side of the shielding electrode near the substrate.

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