Reconfigurable computing architecture-oriented file compiling method and software development tool chain

Abstract

The invention relates to a reconfigurable computing architecture-oriented file compiling method and a software development tool chain, and the method comprises the following steps of: performing language translation processing on an initial compiling program file by adopting a language compiler in a pre-designed software development tool chain to obtain an intermediate representation file; and compiling the intermediate representation file by adopting a reconfigurable computing architecture compiler in the software development tool chain to obtain an executable file for execution of the reconfigurable computing architecture. According to the method, the initial compiling program file is efficiently compiled into the executable file for the reconfigurable computing architecture, so that the execution efficiency of codes is improved, the advantages of the reconfigurable computing architecture are fully utilized, the development and operation environment is more flexible, and the software development requirements are met.

Description

Technical Field

[0001] The present application relates to the field of software compilation technology, and in particular to a file compilation method and a software development tool chain for a reconfigurable computing architecture. Background Art

[0002] In today's software development and computing fields, with the rapid development of technology, the diversity of programming languages ​​and hardware architectures is becoming increasingly significant. In order to meet the performance requirements of different application scenarios, hybrid programming languages ​​are increasingly widely used. These languages ​​combine multiple programming paradigms, allowing developers to flexibly use the advantages of various languages. The current hybrid programming languages ​​are suitable for commonly used hardware architectures.

[0003] However, for some specific hardware architectures, compilation requires a lot of time and effort, and the development efficiency is low. Summary of the invention

[0004] Based on this, it is necessary to provide a file compilation method and software development tool chain for reconfigurable computing architecture that can improve development efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a file compilation method for a reconfigurable computing architecture. The method comprises:

[0006] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0007] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0008] In one embodiment, the intermediate representation file includes a specified portion of code and a remaining portion of code, and the intermediate representation file is compiled using a reconfigurable computing architecture compiler in a software development tool chain to obtain an executable file, including:

[0009] Obtaining the operating functions and architecture parameters of the reconfigurable computing architecture;

[0010] Replace the specified part of the code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture;

[0011] Compiling the remaining codes to obtain a second assembly code of the host machine of the reconfigurable computing architecture;

[0012] The first assembly code and the second assembly code are subjected to file conversion processing to obtain an executable file.

[0013] In one embodiment, the above-mentioned compiling process of the remaining part of the code to obtain the second assembly code of the host machine of the reconfigurable computing architecture includes:

[0014] Get the system parameters of the host machine;

[0015] Compile the remaining codes according to the system parameters to obtain the spare assembly code;

[0016] The spare assembly codes are optimized respectively to obtain second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0017] In one embodiment, the language compiler in the pre-designed software development tool chain is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file, including:

[0018] Parsing the initial compiler file to obtain an initial abstract syntax tree;

[0019] Correct the initial abstract syntax tree to obtain a target abstract syntax tree;

[0020] Perform code translation on the target abstract syntax tree to obtain an intermediate representation file.

[0021] In one embodiment, the code translation process of the target abstract syntax tree to obtain an intermediate representation file includes:

[0022] Perform code translation on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes;

[0023] Mapping the structure of each target abstract syntax tree to obtain multiple intermediate file structures; the intermediate file structure includes at least one of a function, a variable, and a control flow structure;

[0024] The intermediate codes and the intermediate file structures are integrated to obtain an intermediate representation file.

[0025] In one embodiment, the method further comprises:

[0026] A reconfigurable computing architecture compiler in a software development tool chain is used to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

[0027] In one embodiment, the method further comprises:

[0028] The driver program in the dynamic link library is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0029] In one embodiment, the method further comprises:

[0030] Using the model compiler in the dynamic link library chain to generate an initial compiler file;

[0031] Or, receive an initial compiler file input by the user.

[0032] In a second aspect, the present application also provides a file compilation device for a reconfigurable computing architecture. The device includes:

[0033] A translation module is used to use a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0034] The compilation module is used to compile the intermediate representation file using the reconfigurable computing architecture compiler in the software development tool chain to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0035] In a third aspect, the present application also provides a software development tool chain, which includes a language compiler, a reconfigurable computing architecture compiler, a model compiler and a driver;

[0036] A language compiler is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0037] A reconfigurable computing architecture compiler is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute;

[0038] Model compiler, used to generate initial compiler files;

[0039] A driver is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0040] In a fourth aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0041] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0042] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0043] In a fifth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0044] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0045] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0046] In a sixth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0047] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0048] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0049] The above-mentioned file compilation method and software development tool chain for reconfigurable computing architecture use a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file; and use a reconfigurable computing architecture compiler in the software development tool chain to compile the intermediate representation file to obtain an executable file for reconfigurable computing architecture execution. This application efficiently compiles the initial compiler file into an executable file for the reconfigurable computing architecture, thereby improving the execution efficiency of the code, making full use of the advantages of the reconfigurable computing architecture to make the development and operation environment more flexible and meet the needs of software development. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 An application environment diagram of a file compilation method for a reconfigurable computing architecture in one embodiment;

[0051] Figure 2 A schematic diagram of a flow chart of a file compilation method for a reconfigurable computing architecture in one embodiment;

[0052] Figure 3 A schematic diagram of a process for obtaining an executable file in an embodiment;

[0053] Figure 4 A schematic diagram of a flow chart of obtaining a second assembly code in one embodiment;

[0054] Figure 5 A schematic diagram of a process of obtaining an intermediate representation file in one embodiment;

[0055] Figure 6 A schematic diagram of a process of obtaining an intermediate representation file in another embodiment;

[0056] Figure 7 A structural block diagram of a file compiling device for a reconfigurable computing architecture in one embodiment;

[0057] Figure 8 is a block diagram of the internal structure of a software development tool chain in one embodiment;

[0058] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] First of all, before specifically introducing the technical solution of the embodiments of the present application, the technical background based on the embodiments of the present application is introduced.

[0061] The software development tool chain of the related technology has the following defects:

[0062] Complexity and high learning curve: The software development tool chain of related technologies usually requires familiarity with complex hardware description languages ​​or low-level programming models, which has high technical requirements for developers and a steep learning curve.

[0063] Insufficient performance and energy efficiency optimization: The optimization techniques of related technologies still have limitations in improving the performance and energy efficiency of applications, especially for complex reconfigurable intelligent computing application scenarios, which require more effective optimization methods.

[0064] Debugging and verification difficulties: Due to the complexity and parallelism of reconfigurable intelligent computing architectures, debugging and verifying applications are often challenging, and better debugging tools and verification methods are needed to improve development efficiency and application reliability.

[0065] Insufficient software-hardware co-design: The software development tool chain of related technologies is usually designed for software developers or hardware engineers alone, lacking effective software-hardware co-design methods, resulting in difficulties and inefficiency in software-hardware integration.

[0066] Lack of universality and standardization: The software development tool chains of related technologies are often designed for specific reconfigurable intelligent computing architectures or vendor platforms. They lack universality and standardization, making it difficult to port and deploy applications on different platforms.

[0067] Low development efficiency: Due to the complexity and limitations of the existing tool chain, the software development process often takes a lot of time and effort, resulting in low development efficiency, which affects the promotion and application of reconfigurable intelligent computing technology.

[0068] Especially in the tool chain design of compiler and driver software, the following problems may exist:

[0069] Complexity and high learning curve: The software development tool chain of related technologies usually requires familiarity with complex hardware description languages ​​or low-level programming models, which has high technical requirements for developers and a steep learning curve.

[0070] Insufficient performance and energy efficiency optimization: The optimization techniques of related technologies still have limitations in improving the performance and energy efficiency of applications, especially for complex reconfigurable intelligent computing application scenarios, which require more effective optimization methods.

[0071] Debugging and verification difficulties: Due to the complexity and parallelism of reconfigurable intelligent computing architectures, debugging and verifying applications are often challenging, and better debugging tools and verification methods are needed to improve development efficiency and application reliability.

[0072] Insufficient software-hardware co-design: The software development tool chain of related technologies is usually designed for software developers or hardware engineers alone, lacking effective software-hardware co-design methods, resulting in difficulties and inefficiency in software-hardware integration.

[0073] Lack of universality and standardization: The software development tool chains of related technologies are often designed for specific reconfigurable intelligent computing architectures or vendor platforms. They lack universality and standardization, making it difficult to port and deploy applications on different platforms.

[0074] Low development efficiency: Due to the complexity and limitations of the existing tool chain, the software development process often takes a lot of time and effort, resulting in low development efficiency, which affects the promotion and application of reconfigurable intelligent computing technology.

[0075] Based on this, the present application provides a file compilation method and software development tool chain for a reconfigurable computing architecture, aiming to solve the above-mentioned technical problems.

[0076] The file compilation method for a reconfigurable computing architecture provided in the embodiment of the present application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers. The terminal 102 uses the language compiler in the pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file; the reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file for the reconfigurable computing architecture execution. Among them, the terminal 102 can be but is not limited to various personal computers, laptops, smart phones and tablets. The server 104 can be implemented with an independent server or a server cluster consisting of multiple servers.

[0077] In an exemplary embodiment, Figure 2 As shown, a file compilation method for a reconfigurable computing architecture is provided, and the method is applied to Figure 1 The terminal in is taken as an example to illustrate, including the following S201 to S202. Among them:

[0078] S201, using a language compiler in a pre-designed software development tool chain to perform language translation processing on an initial compiler file to obtain an intermediate representation file.

[0079] In the embodiment of the present application, first, the developer writes the initial program file (called source code file) using a high-level programming language (such as C++, Python or other domain-specific languages) in a pre-designed software development tool chain. The process is as follows: Source code writing: The developer writes the source code to define the program logic, data structure and functional modules.

[0080] Language compiler call: By calling the language compiler in the software development tool chain, the source code file is passed to the compiler for processing. The compiler will perform syntax analysis and semantic analysis on the source code, perform necessary optimization operations, and finally generate an intermediate representation file.

[0081] Intermediate representation file generation: The intermediate representation file is an intermediate form used in the next compilation step to facilitate more optimization and adaptation to the target platform.

[0082] S202, using the reconfigurable computing architecture compiler in the software development tool chain to compile the intermediate representation file to obtain an executable file.

[0083] Among them, the executable file is a file used for execution of the reconfigurable computing architecture.

[0084] In an embodiment of the present application, after obtaining the intermediate representation file, the following operations are performed: Reconfigurable computing architecture compiler call: The reconfigurable computing architecture compiler in the software development tool chain is used to pass the intermediate representation file as input for further optimization compilation.

[0085] Target architecture optimization: The reconfigurable computing architecture compiler analyzes the intermediate representation file and performs optimization processing for a specific reconfigurable computing architecture (such as data parallelization, pipeline optimization, etc.), and finally generates an efficient executable file. Executable file generation: The generated executable file is highly optimized and suitable for the reconfigurable computing architecture, with better execution efficiency and resource utilization.

[0086] The above-mentioned file compilation method for reconfigurable computing architecture uses a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file; and uses a reconfigurable computing architecture compiler in the software development tool chain to compile the intermediate representation file to obtain an executable file for reconfigurable computing architecture execution. This application efficiently compiles the initial compiler file into an executable file for the reconfigurable computing architecture, thereby improving the execution efficiency of the code, making full use of the advantages of the reconfigurable computing architecture to make the development and operation environment more flexible and meet the needs of software development.

[0087] In an exemplary embodiment, based on the above embodiment, see Figure 3 The intermediate representation file of the embodiment of the present application includes a specified part of the code and the remaining part of the code. The embodiment of the present application involves a process of compiling the intermediate representation file using a reconfigurable computing architecture compiler in a software development tool chain to obtain an executable file, including the following S301 to S304. Among them:

[0088] S301, obtaining the operating function and architecture parameters of the reconfigurable computing architecture.

[0089] In the embodiment of the present application, after the system is started, the program code given by the user is first analyzed to extract the operation functions and corresponding architecture parameters related to the reconfigurable computing architecture to form a preliminary operation plan. For example, for an image processing program, the operation function of image filtering and its related parameters such as the convolution kernel size, input and output data format, etc. may be extracted.

[0090] S302, replacing a designated portion of code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture.

[0091] In the embodiment of the present application, based on the extracted running function and architecture parameters, the system replaces a specific code segment with an implementation suitable for the reconfigurable computing architecture, for example, replacing conventional array calculations with instructions using hardware parallel processing. The first assembly code generated by this process can maximize the computing power of the reconfigurable architecture.

[0092] S303, compile the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture.

[0093] In the embodiment of the present application, for the code segments that have not been replaced, the system uses traditional compilation means to process and generate a second assembly code suitable for the host machine. This step ensures the integrity and functionality of the program and ensures that all the codes that have not been replaced can still be executed normally during operation.

[0094] S304, performing file conversion processing on the first assembly code and the second assembly code to obtain an executable file.

[0095] In the embodiment of the present application, the generated first assembly code and the second assembly code are merged and formatted, and output as an executable file. This file can be run on a specific reconfigurable computing architecture and contains various functions of the host machine.

[0096] The embodiments of the present application effectively convert the original program into an executable form suitable for a reconfigurable computing architecture, and can significantly improve the running efficiency of the program on the reconfigurable computing platform.

[0097] In an exemplary embodiment, based on the above embodiment, see Figure 4 The embodiment of the present application relates to a process of compiling the remaining part of the code to obtain a second assembly code of the host machine of the reconfigurable computing architecture, including the following S401 to S403. Among them:

[0098] S401, obtaining system parameters of the host machine.

[0099] In the embodiment of the present application, a query module for the host machine is used to obtain system parameters, which may include CPU architecture information, memory size, operating system type and version, available hardware acceleration resources, etc.

[0100] Specific implementation process: query the API interface provided by the host operating system to obtain the current system information. Store the obtained system parameters in a data structure for subsequent processing.

[0101] S402, compile the remaining code according to the system parameters to obtain a spare assembly code.

[0102] In the embodiment of the present application, the remaining code is compiled based on the acquired host system parameters to obtain the spare assembly code.

[0103] Specific implementation process:

[0104] Use the host machine's compiler to select appropriate compilation options based on system parameters to optimize code efficiency. Input the remaining code into the compiler and generate alternate assembly code based on the configuration of system parameters.

[0105] S403, optimizing the spare assembly codes respectively to obtain second assembly codes.

[0106] The optimization process includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0107] In the embodiment of the present application, the generated standby assembly code is optimized to obtain a second assembly code. The optimization includes but is not limited to the following methods: Loop optimization: Optimize the loop structure in the code by expanding, merging, and eliminating invalid loops. Inline function optimization: Embed frequently called small functions into the call location to avoid the overhead of function calls. Dead code elimination: Clear no longer used or invalid code to reduce code size and improve execution efficiency.

[0108] Specific implementation process: Analyze the loop structure in the assembly code, apply the loop optimization algorithm to identify and optimize the loop instructions. For the functions identified as suitable for inline optimization, process them one by one and replace them with inline codes. Scan the entire assembly code, mark and remove dead code segments, and reduce the size of the generated assembly file.

[0109] The embodiment of the present application can effectively compile and optimize the code according to the actual operating environment of the host machine, thereby generating an efficient second assembly code. This process not only improves the execution efficiency of the reconfigurable computing architecture, but also enables the generated code to run more smoothly and efficiently on the target host machine, which is particularly suitable for computing environments with limited resources or high performance requirements.

[0110] In an exemplary embodiment, based on the above embodiment, see Figure 5 The embodiment of the present application relates to a process of using a language compiler in a pre-designed software development tool chain to perform language translation processing on an initial compiler file to obtain an intermediate representation file, including the following S501 to S503. Among them:

[0111] S501, parsing the initial compiler file to obtain an initial abstract syntax tree.

[0112] In the embodiment of the present application, the initial compiler code is first read from the source code file, and the corresponding parser is called for parsing to generate an initial abstract syntax tree (AST). This tree structure represents the various grammatical components of the code and their hierarchical relationships. For example, for the following simple arithmetic expression: a = b + c. The parser will generate a corresponding AST, in which the nodes represent operators, operands, and assignment relationships.

[0113] S502: Correct the initial abstract syntax tree to obtain a target abstract syntax tree.

[0114] In the embodiment of the present application, the system will perform a series of semantic correction processes on the initial abstract syntax tree. These processes may include type checking, constraint verification, and unification of code style. By traversing the initial AST, the system identifies structures that do not conform to the language specification, corrects them, and finally generates the target abstract syntax tree.

[0115] For example, if illegal operations are found on variables of different types in the AST, the system will automatically adjust these nodes to ensure type consistency and generate a new target AST to avoid potential runtime errors.

[0116] S503, performing code translation processing on the target abstract syntax tree to obtain an intermediate representation file.

[0117] In the embodiment of the present application, after generating the target abstract syntax tree, the system will perform code translation processing on it, that is, converting the target AST into an intermediate representation file. The intermediate representation is a platform-independent, optimization-potential abstract layer that can be further compiled and optimized on different target machine architectures. During this process, the system analyzes each node in the target AST and generates the corresponding intermediate representation code according to specific translation rules. This intermediate representation may include information such as basic blocks and control flow graphs, laying the foundation for the subsequent compilation optimization stage.

[0118] The embodiments of the present application significantly improve the accuracy and robustness of the compiler through code parsing, correction and translation, which not only improves the quality of the initial code, but also provides a solid foundation for subsequent intermediate representation processing and final code generation, helping to maximize code execution efficiency.

[0119] In an exemplary embodiment, based on the above embodiment, see Figure 6 The embodiment of the present application relates to a process of performing code translation processing on a target abstract syntax tree to obtain an intermediate representation file, including the following S601 to S603. Among them:

[0120] S601, performing code translation processing on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes.

[0121] In an embodiment of the present application, code translation is performed on multiple nodes of a target abstract syntax tree (AST) to obtain multiple intermediate codes.

[0122] Specific implementation process: traverse each node of the target AST and identify different grammatical structures (such as method calls, operators, conditional judgments, etc.). For each node type, translate it into the corresponding intermediate code representation, for example, function call nodes are translated into call instructions, and intermediate calculation nodes are translated into arithmetic operation instructions. The translated intermediate codes are stored in a list or array to form multiple intermediate codes.

[0123] S602, mapping processing is performed on the structure of each target abstract syntax tree to obtain multiple intermediate file structures.

[0124] The intermediate file structure includes at least one of a function, a variable and a control flow structure.

[0125] In the embodiment of the present application, mapping processing is performed on the structure of each target abstract syntax tree to obtain multiple intermediate file structures.

[0126] Specific implementation process: Analyze each translated intermediate code to identify the functions, variables and control flow structures (such as loops, branches, etc.) involved. Use a mapping algorithm to organize these identified structures into a specific intermediate file structure. The generated intermediate file structure includes not only the declaration and definition of the function, but also the declaration of the variable and the information of the control flow structure.

[0127] S603, integrating each intermediate code and each intermediate file structure to obtain an intermediate representation file.

[0128] The embodiment of the present application integrates and processes each intermediate code and each intermediate file structure to finally obtain an intermediate representation file.

[0129] Specific implementation process: Pair and integrate the generated multiple intermediate codes with the corresponding intermediate file structures. Generate a central intermediate representation file that contains all intermediate codes and their associated file structure information. Ensure that the format of the intermediate representation file meets the requirements of subsequent processing to facilitate subsequent compilation, optimization or code generation.

[0130] The embodiments of the present application can efficiently generate an intermediate representation file from the target abstract syntax tree, ensuring high quality and high efficiency of code translation, laying a good foundation for subsequent code optimization and generation stages, and is particularly suitable for compiler design that improves multi-language support and cross-platform compatibility.

[0131] In an exemplary embodiment, based on the above embodiment, the method of the embodiment of the present application also includes: using a reconfigurable computing architecture compiler in a software development tool chain to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

[0132] In the embodiment of the present application, the user first needs to provide the first assembly code for the reconfigurable computing architecture. These codes are usually preliminary implementations of specific functional modules or algorithms, and may use semantics for specific hardware. Code input can be completed through file import, network request or direct editing interface.

[0133] Next, based on the compiler in the software development tool chain, the system will parse and optimize the first assembly code. The compiler here not only supports basic assembly instruction set parsing, but also can identify instructions and optimization strategies unique to the reconfigurable computing architecture.

[0134] During the processing, the compiler will: Parse the first assembly code: Initialize and structurally analyze the input assembly code to establish an internal representation. Optimize the code: Improve code performance according to the specified optimization criteria, such as inline optimization, dead code elimination, and loop optimization. Generate dynamic link library: Convert the optimized code into dynamic link library format to meet the requirements of dynamic loading and execution.

[0135] Finally, after the compiler's conversion process, the final dynamic link library file will be output. The system will provide corresponding feedback, including the path, size and related compilation information of the generated DLL file.

[0136] The embodiment of the present application can efficiently generate a dynamic link library, so that developers can more intuitively use the characteristics of reconfigurable computing. This method not only simplifies the development process, but also improves code reusability and execution efficiency, and is suitable for a variety of high-performance computing scenarios.

[0137] In an exemplary embodiment, based on the above embodiment, the method of the embodiment of the present application further includes: using a driver in the dynamic link library to drive the reconfigurable computing architecture to call the dynamic link library.

[0138] The main steps of the embodiment of this application are as follows:

[0139] Creation and management of dynamic link libraries:

[0140] Developers design and implement multiple functional modules, which are encapsulated in a dynamic link library. Each module is responsible for a specific computing task, such as image processing, signal analysis, etc. The DLL is loaded at runtime, allowing the caller to use the functions of this library without recompiling.

[0141] Writing drivers: Develop corresponding drivers based on the characteristics of the reconfigurable computing architecture. The driver is responsible for managing the loading of dynamic link libraries, function calls, and data transmission. The driver can identify user requests and call the corresponding DLL function module.

[0142] Calling and scheduling:

[0143] The system dynamically selects the computing resources that need to be reconstructed based on the input parameters and loads the corresponding dynamic link library through the driver.

[0144] The driver initiates calls to various functional modules in the DLL library to implement the required computing tasks.

[0145] Resource allocation and reconstruction:

[0146] According to the calling requirements of the DLL, the driver dynamically configures the resources of the reconfigurable computing architecture, such as activating different FPGA modules, allocating storage space, etc. Once the computing task is completed, the driver can reconfigure the computing architecture to adapt to the new task scheduling requirements.

[0147] The embodiment of the present application uses the driver in the dynamic link library, which not only reduces the repeated coding work of the software, but also improves the flexibility of development. Users can update or replace the modules in the dynamic link library at any time according to their needs without modifying the entire application, which greatly improves the adaptability and efficiency of the reconfigurable computing architecture.

[0148] In an exemplary embodiment, based on the above embodiment, the method of the embodiment of the present application further includes: using a model compiler in a dynamic link library chain to generate an initial compiler file; or, receiving an initial compiler file input by a user.

[0149] An implementation method of the present application embodiment:

[0150] First, the system initializes a model compiler in a dynamic link library chain. The compiler is configured to support different programming models and languages ​​and can receive multiple parameters to ensure flexibility. Then, the compiler generates the necessary parameters for the initial compiler file based on the preset model information and compilation options. These parameters include: programming language type; input / output data type; model feature settings.

[0151] The user can issue instructions through the graphical user interface or command line interface to call the model compiler to generate the initial compiler program file. The compiler will generate the corresponding compiler program file based on the input parameters and store it in the specified directory.

[0152] Another implementation method of the present application embodiment:

[0153] The system provides an interface or API for users to input the initial compiler file. Users can select local files or upload them through the network. Once the initial compiler file input by the user is received, the system will check the legality and integrity of the file through the parsing tool. This process includes verifying the file format, checking syntax errors, etc. If the initial compiler file input by the user is legal, the system will call the model compiler to process it to generate the final dynamic link library (DLL). The process includes: compiling and optimizing program files; building dynamic link libraries; outputting generation results and feedback information.

[0154] The two paths provided in the embodiments of the present application (generation through model compiler and user input) can effectively simplify the DLL generation process and provide users with flexible operation methods. Developers can quickly generate the required compiler according to actual needs, reducing learning costs and development time, and improving development efficiency and code quality.

[0155] In an exemplary embodiment, based on the above embodiment, the method of the embodiment of the present application further includes the following steps:

[0156] Step 1: Generate an initial compiler file using a model compiler in a dynamic link library chain; or, receive an initial compiler file input by a user;

[0157] Step 2: Use a language compiler in a pre-designed software development tool chain to parse the initial compiler file to obtain an initial abstract syntax tree; perform correction processing on the initial abstract syntax tree to obtain a target abstract syntax tree;

[0158] Step 3: Translate multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes; map the structure of each target abstract syntax tree to obtain multiple intermediate file structures;

[0159] Step 4: Integrate each intermediate code and each intermediate file structure to obtain an intermediate representation file;

[0160] Step 5: Use the reconfigurable computing architecture compiler in the software development tool chain to obtain the operating function and architecture parameters of the reconfigurable computing architecture; replace the specified part of the code according to the operating function and the architecture parameters to obtain the first assembly code for the reconfigurable computing architecture;

[0161] Step 6: Obtain system parameters of the host machine; compile the remaining code according to the system parameters to obtain a backup assembly code; optimize the backup assembly code respectively to obtain a second assembly code;

[0162] Step 7: Perform file conversion processing on the first assembly code and the second assembly code to obtain an executable file;

[0163] Step 8: using a reconfigurable computing architecture compiler in a software development tool chain to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library;

[0164] Step 9: Use the driver program in the dynamic link library to drive the reconfigurable computing architecture to call the dynamic link library.

[0165] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0166] Based on the same inventive concept, the embodiment of the present application also provides a file compilation device for a reconfigurable computing architecture for implementing the file compilation method for a reconfigurable computing architecture involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more embodiments of the file compilation device for a reconfigurable computing architecture provided below can refer to the limitations of the file compilation method for a reconfigurable computing architecture above, and will not be repeated here.

[0167] In one embodiment, Figure 7 As shown, a file compilation device 700 for a reconfigurable computing architecture is provided, comprising:

[0168] The translation module 701 is used to use a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0169] The compilation module 702 is used to compile the intermediate representation file using the reconfigurable computing architecture compiler in the software development tool chain to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0170] In one embodiment, the intermediate representation file includes a specified portion of code and a remaining portion of code, and the compiling module includes:

[0171] A data acquisition unit, used to acquire the operation function and architecture parameters of the reconfigurable computing architecture;

[0172] A first code determination unit is used to replace a specified portion of code according to an operation function and an architecture parameter to obtain a first assembly code for a reconfigurable computing architecture;

[0173] A second code determination unit is used to compile the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture;

[0174] The file conversion unit is used to perform file conversion processing on the first assembly code and the second assembly code to obtain an executable file.

[0175] In one embodiment, the second code determination unit includes:

[0176] The parameter acquisition subunit is used to obtain the system parameters of the host machine;

[0177] The spare code determination subunit is used to compile the remaining code according to the system parameters to obtain the spare assembly code;

[0178] The code optimization subunit is used to optimize the spare assembly codes respectively to obtain the second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0179] In one embodiment, the translation module includes:

[0180] A file parsing unit, used for parsing the initial compiler file to obtain an initial abstract syntax tree;

[0181] A grammar correction unit, used for correcting the initial abstract syntax tree to obtain a target abstract syntax tree;

[0182] The code translation unit is used to perform code translation processing on the target abstract syntax tree to obtain an intermediate representation file.

[0183] In one embodiment, the code translation unit includes:

[0184] An intermediate code determination subunit is used to perform code translation processing on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes;

[0185] The structure determination subunit is used to map the structure of each target abstract syntax tree to obtain multiple intermediate file structures; the intermediate file structure includes at least one of a function, a variable and a control flow structure;

[0186] The integration subunit is used to integrate various intermediate codes and various intermediate file structures to obtain intermediate representation files.

[0187] In one embodiment, the above device further comprises:

[0188] The link library determination unit is used to convert the first assembly code of the reconfigurable computing architecture using the reconfigurable computing architecture compiler in the software development tool chain to obtain a dynamic link library.

[0189] In one embodiment, the above device further comprises:

[0190] The driving unit is used to drive the reconfigurable computing architecture to call the dynamic link library using a driver program in the dynamic link library.

[0191] In one embodiment, the above device further comprises:

[0192] The file generating unit is used to generate an initial compiler file by using a model compiler in a dynamic link library chain; or, the file receiving unit is used to receive an initial compiler file input by a user.

[0193] Each module in the above-mentioned file compilation device for reconfigurable computing architecture can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0194] In one embodiment, the present application also provides a software development tool chain, such as Figure 8 As shown, the software development tool chain includes a language compiler (DSL compiler), a reconfigurable computing architecture compiler (CGRA compiler), a model compiler (AI compiler) and a driver.

[0195] The language compiler is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file; the reconfigurable computing architecture compiler is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the execution of the reconfigurable computing architecture; the model compiler is used to generate the initial compiler file; the driver is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0196] Specifically, the language compiler performs language translation processing on the initial compiler file to generate an intermediate representation file (IR). The language compiler includes grammar design, error handling, DSL compiler front end, semantic analysis, Parallel Patterns, IR design and support, IR Transformation, data flow analysis, loop optimization, parallel computing optimization and memory management.

[0197] The high-level language code written by the user, such as C / C++, Python, etc., is parsed by the language compiler and translated into an intermediate representation file. The intermediate representation file is an architecture-independent representation format that facilitates subsequent processing.

[0198] In the programming model for reconfigurable intelligent computing, concepts such as parallel computing, data flow processing, and task scheduling are usually involved to fully utilize the parallelism and flexibility of reconfigurable hardware. The programming model provides developers with an abstract, easy-to-understand and easy-to-use way to describe the parallelism and data flow of applications, so that developers can develop and optimize applications more conveniently. We designed a domain-specific language (DSL) embedded in the classic programming paradigm to describe the structure and behavior of programs. In the software tool chain for reconfigurable intelligent computing, IR plays the role of a bridge connecting different compiler stages and is the basis for compilers to optimize, transform, and generate target code. It is an intermediate representation that is independent of the hardware architecture and can flexibly represent the characteristics of different programming models and hardware architectures, thereby achieving unified optimization and transformation of different programming models and hardware architectures. At the same time, we will introduce a variety of identifiers at the DSL and IR levels to help the back-end compiler map and optimize the target hardware platform, so that it can generate efficient target code.

[0199] The reconfigurable computing architecture compiler further compiles the intermediate representation file to obtain an executable file. The reconfigurable computing architecture compiler can include: DFG docking, routing node layering, node mapping priority sorting, node topology, row and column register mapping, priority sorting pruning, local register autobiography and pre-mapping.

[0200] The compiler is responsible for optimizing the intermediate representation file and generating executable files for reconfigurable computing architectures (such as FPGAs) in the background. The executable files contain instruction sets for specific hardware and can be directly executed by the reconfigurable computing architecture.

[0201] The specific process includes: program preprocessing: sub-loop processing: eliminating or making special processing to sub-loops to ensure that CGRA is mappable; function processing: eliminating functions called in the loop body (embedded or equivalent code).

[0202] DFG generation: Front-end: Get llvm ir through llvm front-end. Generation: Perform DFG conversion on llvm ir without sub-loops and output equivalent DFG. Optimization: Optimization aims to reduce nodes and generate DFG runtime beats.

[0203] DFG mapping: CGRA structure: read CGRA structure, interconnection and other information through json file. TEC: Since the TEC structure is fixed, it is not stored and is only judged by interconnection. MAPPING: Find the subgraph isomorphism under the minimum II through VF3. Finally, generate assembly code.

[0204] Model compiler, used to generate initial compiler files. Model compiler can include: front end, middle end and back end.

[0205] Users can use the model compiler to create an initial compiled program file that matches the hardware characteristics according to application requirements. This process supports modeling and simulation to ensure that the generated program file can be efficiently executed on the reconfigurable computing architecture.

[0206] The upper layer of the AI ​​compiler is connected to various mainstream open source AI models (multiple front ends), while the back end can be connected to different hardware platforms (CUDA-NV GPU; OPENCL; LLVM-CPU) and specific chips (A100, AMD MI100).

[0207] After unifying different model inputs into IR of a higher abstraction level, it will perform a series of optimizations and function implementations. Some of these functions are not related to hardware but only to the algorithm model itself: such as removing redundant operators, fusing operators (such as conv+prelu), peephole optimization (converting conv1*1 to matmul operator), etc. Some are directly related to hardware features: such as operator fusion (conv+add (needs hardware support) add+add (SIMD chips such as NPU do not support direct fusion)), memory optimization (different chips have different sizes of on-chip memory, and the data size is different when tiling; some chip memories use multiple banks to increase bandwidth, in which case bankconflict needs to be avoided as much as possible), and graph segmentation (when the chip has a large on-chip memory, the model can be segmented into n subgraphs, and the overall intermediate outputs of some subgraphs remain in the on-chip memory. Reducing data in and out of DDR can effectively reduce power consumption and latency). The AI ​​compiler needs to perform these optimizations hierarchically and gradually, optimizing while lowering the IR abstraction level, and then lowering it, and then optimizing it again, until it is connected to the backend software stack.

[0208] Driver, which drives the reconfigurable computing architecture to call the dynamic link library. The driver may include: CGRA MCU subsystem driver, resource management thread, and Linux application.

[0209] The driver interacts with the interface of the reconfigurable computing architecture, allowing the executable file to dynamically load the required dynamic link library (DLL). The driver is responsible for calling library functions and managing resources to achieve fast data processing and computing task allocation.

[0210] For example, in a certain application scenario, developers need to implement an image processing algorithm. First, the corresponding initial compiler file is generated through the model compiler. Then, it is translated into an intermediate representation file using a language compiler. Then, with the help of the reconfigurable computing architecture compiler, the intermediate representation file is compiled into an executable file, which is finally run on the reconfigurable computing architecture, and the driver calls the acceleration module in the dynamic link library to complete the image processing task.

[0211] The software development tool chain of the embodiment of the present application realizes the full-process compilation and management from the language layer to the hardware layer, greatly improving the development efficiency of the reconfigurable computing architecture. Through the use of intermediate representation files and the call of dynamic link libraries, it systematically supports the needs of developers and enhances scalability and modularity.

[0212] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a file compilation method for a reconfigurable computing architecture is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0213] Those skilled in the art will understand that Fig. 9The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0214] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0215] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0216] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0217] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0218] Obtaining the operating functions and architecture parameters of the reconfigurable computing architecture;

[0219] Replace the specified part of the code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture;

[0220] Compiling the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture;

[0221] The first assembly code and the second assembly code are subjected to file conversion processing to obtain an executable file.

[0222] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0223] Get the system parameters of the host machine;

[0224] Compile the remaining codes according to the system parameters to obtain the spare assembly code;

[0225] The spare assembly codes are optimized respectively to obtain second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0226] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0227] Parsing the initial compiler file to obtain an initial abstract syntax tree;

[0228] Correct the initial abstract syntax tree to obtain a target abstract syntax tree;

[0229] Perform code translation on the target abstract syntax tree to obtain an intermediate representation file.

[0230] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0231] Perform code translation on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes;

[0232] Mapping the structure of each target abstract syntax tree to obtain multiple intermediate file structures; the intermediate file structure includes at least one of a function, a variable, and a control flow structure;

[0233] The intermediate codes and the intermediate file structures are integrated to obtain an intermediate representation file.

[0234] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0235] A reconfigurable computing architecture compiler in a software development tool chain is used to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

[0236] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0237] The driver program in the dynamic link library is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0238] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0239] Using the model compiler in the dynamic link library chain to generate an initial compiler file;

[0240] Or, receive an initial compiler file input by the user.

[0241] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0242] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0243] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0244] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0245] Obtaining the operating functions and architecture parameters of the reconfigurable computing architecture;

[0246] Replace the specified part of the code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture;

[0247] Compiling the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture;

[0248] The first assembly code and the second assembly code are subjected to file conversion processing to obtain an executable file.

[0249] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0250] Get the system parameters of the host machine;

[0251] Compile the remaining codes according to the system parameters to obtain the spare assembly code;

[0252] The spare assembly codes are optimized respectively to obtain second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0253] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0254] Parsing the initial compiler file to obtain an initial abstract syntax tree;

[0255] Correct the initial abstract syntax tree to obtain a target abstract syntax tree;

[0256] Perform code translation on the target abstract syntax tree to obtain an intermediate representation file.

[0257] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0258] Perform code translation on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes;

[0259] Mapping the structure of each target abstract syntax tree to obtain multiple intermediate file structures; the intermediate file structure includes at least one of a function, a variable, and a control flow structure;

[0260] The intermediate codes and the intermediate file structures are integrated to obtain an intermediate representation file.

[0261] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0262] A reconfigurable computing architecture compiler in a software development tool chain is used to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

[0263] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0264] The driver program in the dynamic link library is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0265] In one embodiment, the method further comprises:

[0266] Using the model compiler in the dynamic link library chain to generate an initial compiler file;

[0267] Or, receive an initial compiler file input by the user.

[0268] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0269] Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file;

[0270] The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for the reconfigurable computing architecture to execute.

[0271] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0272] Obtaining the operating functions and architecture parameters of the reconfigurable computing architecture;

[0273] Replace the specified part of the code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture;

[0274] Compiling the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture;

[0275] The first assembly code and the second assembly code are subjected to file conversion processing to obtain an executable file.

[0276] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0277] Get the system parameters of the host machine;

[0278] Compile the remaining codes according to the system parameters to obtain the spare assembly code;

[0279] The spare assembly codes are optimized respectively to obtain second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

[0280] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0281] Parsing the initial compiler file to obtain an initial abstract syntax tree;

[0282] Correct the initial abstract syntax tree to obtain a target abstract syntax tree;

[0283] Perform code translation on the target abstract syntax tree to obtain an intermediate representation file.

[0284] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0285] Perform code translation on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes;

[0286] Mapping the structure of each target abstract syntax tree to obtain multiple intermediate file structures; the intermediate file structure includes at least one of a function, a variable, and a control flow structure;

[0287] The intermediate codes and the intermediate file structures are integrated to obtain an intermediate representation file.

[0288] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0289] A reconfigurable computing architecture compiler in a software development tool chain is used to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

[0290] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0291] The driver program in the dynamic link library is used to drive the reconfigurable computing architecture to call the dynamic link library.

[0292] In one embodiment, the method further comprises:

[0293] Using the model compiler in the dynamic link library chain to generate an initial compiler file;

[0294] Or, receive an initial compiler file input by the user.

[0295] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0296] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0297] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0298] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A file compilation method for a reconfigurable computing architecture, characterized in that: The method comprises: Using a language compiler in a pre-designed software development tool chain to perform language translation processing on the initial compiler file to obtain an intermediate representation file; The reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for execution of the reconfigurable computing architecture.

2. The method according to claim 1, characterized in that The intermediate representation file includes a specified portion of code and a remaining portion of code, and the reconfigurable computing architecture compiler in the software development tool chain is used to compile the intermediate representation file to obtain an executable file, including: Obtaining the operating functions and architecture parameters of the reconfigurable computing architecture; Performing a replacement process on the specified portion of code according to the running function and the architecture parameter to obtain a first assembly code for the reconfigurable computing architecture; Compiling the remaining code to obtain a second assembly code of the host machine of the reconfigurable computing architecture; File conversion is performed on the first assembly code and the second assembly code to obtain the executable file.

3. The method according to claim 2, characterized in that The compiling of the remaining part of the code to obtain the second assembly code of the host machine of the reconfigurable computing architecture includes: Obtaining system parameters of the host machine; Compile the remaining code according to the system parameters to obtain a spare assembly code; The spare assembly codes are optimized respectively to obtain the second assembly codes, wherein the optimization includes at least one of loop optimization, inline function optimization, and dead code elimination.

4. The method according to claim 1, characterized in that: The language compiler in the pre-designed software development tool chain is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file, including: Parsing the initial compiler file to obtain an initial abstract syntax tree; Correcting the initial abstract syntax tree to obtain a target abstract syntax tree; The target abstract syntax tree is subjected to code translation processing to obtain the intermediate representation file.

5. The method according to claim 4, characterized in that The code translation process is performed on the target abstract syntax tree to obtain the intermediate representation file, including: Performing code translation processing on multiple nodes of the target abstract syntax tree to obtain multiple intermediate codes; Mapping the structure of each target abstract syntax tree to obtain a plurality of intermediate file structures; the intermediate file structure includes at least one of a function, a variable and a control flow structure; The intermediate codes and the intermediate file structures are integrated to obtain the intermediate representation file.

6. The method according to claim 2, characterized in that The method further comprises: The reconfigurable computing architecture compiler in the software development tool chain is used to convert the first assembly code of the reconfigurable computing architecture to obtain a dynamic link library.

7. The method according to claim 6, characterized in that The method further comprises: The driver program in the dynamic link library is used to drive the reconfigurable computing architecture to call the dynamic link library.

8. The method according to claim 7, characterized in that The method further comprises: Using the model compiler in the dynamic link library chain to generate the initial compiler file; Or, receiving the initial compiler file input by a user.

9. A software development tool chain, characterized in that: The software development tool chain includes a language compiler and a reconfigurable computing architecture compiler; The language compiler is used to perform language translation processing on the initial compiler file to obtain an intermediate representation file; The reconfigurable computing architecture compiler is used to compile the intermediate representation file to obtain an executable file; the executable file is a file used for execution by the reconfigurable computing architecture.

10. The software development tool chain according to claim 9, characterized in that: The software development tool chain also includes a model compiler and a driver; The model compiler is used to generate the initial compiler file; The driver is used to drive the reconfigurable computing architecture to call a dynamic link library.

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