Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: after a first cache set of a data cache region is fully written, writing all data into a blank first entity block of a data storage region; performing read-back detection on the first entity block, and determining the total number of error pages; judging whether the total number of the wrong pages exceeds a first preset threshold value or not; and if not, obtaining target data corresponding to the error page from the first cache set, and writing the target data into the second cache set. According to the method, the reliability and the performance of a storage system are obviously improved through a multi-level threshold judgment mechanism, error page detection and a flexible data rewriting strategy.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a memory management method and a memory controller of a storage device equipped with a rewritable non-volatile memory module. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] In modern solid-state drives (SSDs), a hybrid management method is often used to balance cost, capacity, and performance. This method divides part of the multi-layer cell (TLC) storage area and uses it as a single-layer cell (SLC). Although SLC has a smaller capacity, it has a faster read and write speed. Data is first written to the SLC cache in SLC mode. When the data stored in the SLC cache reaches the amount of data for a TLC data block, the data will be transferred to the TLC unit. However, data written in TLC mode is more prone to errors than in SLC mode, which may reduce data reliability. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems and to design a memory management method that greatly improves the data reliability of the SSD through real-time detection and dynamic adjustment.

[0005] One or more embodiments of the present invention provide a memory management method for a memory controller of a storage device configured with a rewritable non-volatile memory module. The method comprises: after a first cache set among multiple cache sets in a data cache area of ​​the rewritable non-volatile memory module is full, writing all first data of the first cache set from the first cache set to a blank first physical block among multiple physical blocks in a data storage area of ​​the rewritable non-volatile memory module, wherein the data capacity of the first cache set is consistent with the data capacity of the first physical block; performing a readback test on the first physical block to determine the total number of error pages in the first physical block; determining whether the total number of error pages exceeds a first preset threshold; if the total number of error pages does not exceed the first preset threshold, obtaining target data corresponding to the error page in the first data from the first cache set, and writing the target data to a second cache set among the multiple cache sets.

[0006] Based on the above, this method reduces the block merging operation during data transfer by matching the data capacity of the first cache set with the capacity of the first physical block; and then avoids the performance overhead caused by performing detection on all data blocks by selectively performing readback detection only on unstable areas. When it is detected that the number of error pages is within the threshold range, only the data of the error pages is rewritten, and there is no need to migrate the entire block of data. At the same time, the error data is rewritten to the SLC cache area instead of the TLC area, avoiding the problem of repeated writing in unstable storage locations. This mechanism significantly improves the data writing speed while ensuring data reliability.

[0007] In one or more embodiments of the present invention, if the total number of the error pages exceeds the first preset threshold, a blank second physical block is selected from the multiple physical blocks, and the first data is written from the first cache set to the second physical block.

[0008] In one or more embodiments of the present invention, the method further includes: after rewriting the target data from the first cache set to the second physical block, if the total number of error pages corresponding to the target data in the second physical block exceeds the first preset threshold, rewriting the target data from the first cache block to another second physical block, and accumulating the number of rewrites of the target data; if the number of rewrites exceeds the incompatibility threshold, allocating multiple first-type physical blocks of the first type in the data storage area, and writing the target data to the multiple first-type physical blocks, wherein the multiple physical blocks in the data storage area are of the second type.

[0009] In one or more embodiments of the present invention, before determining whether the total number of the error pages exceeds the first preset threshold, the method further includes: determining whether the total number of the error pages exceeds a second preset threshold; if the total number of the error pages does not exceed the second preset threshold, determining whether the total number of the error pages exceeds the first preset threshold; and if the total number of the error pages exceeds the second preset threshold, directly selecting a blank second physical block from the multiple physical blocks without determining whether the total number of the error pages exceeds the first preset threshold, and writing the first data from the first cache set to the second physical block.

[0010] In one or more embodiments of the present invention, if the total number of error pages exceeds the second preset threshold, the method further includes: accumulating the number of exceptions corresponding to the first physical block by 1; and when the number of exceptions exceeds a third preset threshold, classifying the first physical block as a bad block.

[0011] In one or more embodiments of the present invention, before determining whether the total number of error pages exceeds the first preset threshold, the method further includes: identifying the second cache set sorted after the first cache set; and setting the total number of multiple blank physical pages currently remaining in the second cache set to the first preset threshold.

[0012] In one or more embodiments of the present invention, each cache set of the data cache area has a plurality of first storage units of a first type, wherein each first storage unit stores 1 bit of data, wherein each physical block of the data storage area has a plurality of second storage units of a second type, wherein each second storage unit stores N bits of data, N being a positive integer greater than 1, wherein a first number of the plurality of first storage units of each cache set is equal to N times a second number of the plurality of second storage units of each physical block.

[0013] In one or more embodiments of the present invention, the method further includes: determining whether the first physical block belongs to one of a plurality of unstable physical blocks, wherein the plurality of unstable physical blocks are pre-set; and in response to determining that the first physical block belongs to the unstable physical block group, performing a read back test on the first physical block to determine the total number of error pages in the first physical block.

[0014] In one or more embodiments of the present invention, after determining the error page in the first physical block, the method further includes: recording a data state sample of the target data corresponding to the error page; accumulating the number of errors corresponding to the data state sample by 1; and when the number of errors of the data state sample exceeds an error data state sample threshold value, recording the data state sample as an unstable data state sample, and setting the write data that conforms to the data state sample to always be written to a stable data storage area.

[0015] In one or more embodiments of the present invention, the method further includes: when selecting a blank second physical block from the multiple physical blocks, selecting a blank physical block with the best quality as the second physical block according to the pre-recorded quality parameters of each physical block, wherein the quality parameters include: the number of times data is written, the number of erase cycles or the bit error rate.

[0016] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; and a processor electrically connecting to the memory interface control circuit. The processor is configured to: after a first cache set in a plurality of cache sets in a data cache area of ​​the rewritable non-volatile memory module is full, write all first data of the first cache set from the first cache set to a blank first physical block in a plurality of physical blocks in a data storage area of ​​the rewritable non-volatile memory module, wherein the data capacity of the first cache set is consistent with the data capacity of the first physical block; perform a readback test on the first physical block to determine the total number of error pages in the first physical block; determine whether the total number of the error pages exceeds a first preset threshold; and if the total number of the error pages does not exceed the first preset threshold, obtain target data corresponding to the error page in the first data from the first cache set, and write the target data to a second cache set in the plurality of cache sets.

[0017] Based on the above, the memory management method and memory controller provided by the embodiment of the present invention timely discover the error page in the storage area corresponding to the second type storage unit through readback detection, and dynamically adjust the preset threshold based on the capacity of the remaining data cache area corresponding to the first type storage unit, thereby realizing an adaptive error handling strategy: when the number of error pages is small, only the error page is rewritten to reduce the resource consumption of data movement, and when there are many errors, a higher quality physical block corresponding to the second type storage unit is selected for whole block rewriting, thereby improving the reliability of the storage device. At the same time, by identifying error-prone data patterns and specially handling unstable storage areas, the system can preventively adjust the storage strategy, effectively extending the life of the storage device while improving data reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0019] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0020] Figure 2 is a block diagram of different storage areas of a rewritable non-volatile memory module according to an embodiment of the present invention;

[0021] Figure 3is a flowchart of a memory management method according to an embodiment of the present invention;

[0022] Figure 4 It is a schematic diagram showing storing target data corresponding to an error page in another cache set according to a comparison result according to an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram showing re-storing data to another physical block according to a comparison result according to an embodiment of the present invention.

[0024] Description of Figure Numbers

[0025] 10: Host system

[0026] 20: Storage device

[0027] 211: First processor

[0028] 110: Second processor

[0029] 120: Host memory

[0030] 130: Data transmission interface circuit

[0031] 210: Memory controller

[0032] 212: Data management circuit

[0033] 213: Memory interface control circuit

[0034] 214: Buffer memory

[0035] 220: Rewritable non-volatile memory module

[0036] 230: Connecting interface circuit

[0037] 221, 221(1) to 221(N): cache set

[0038] 222, 222(1) to 222(M): Entity block

[0039] S310-S350: Process steps of the memory management method

[0040] BP10~BP17, BP20~BP27: physical pages of the cache set

[0041] DP10~DP17, DP20~DP27: Physical pages of physical blocks

[0042] A41~A46、A51~A56:arrow

[0043] TD1: Target Data

[0044] DD1: First Data DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0047] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0048] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0049] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0050] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0051] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0052] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0053] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0054] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform data reading operations to implement the data reading method provided by the present invention. The control instructions / program codes corresponding to the data reading method can be further implemented as a circuit unit in the form of hardware to implement the data reading method provided by the present invention.

[0055] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0056] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0057] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units (also called physical blocks) of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (data can be read from multiple storage units in one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0058] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0059] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0060] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0061] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various preset thresholds, various mapping tables, index tables, valid data tables), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 216. In one embodiment, the memory controller 210 can establish one or more write mapping tables in the buffer memory 214 to indicate the target physical address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 can also be configured outside the memory controller 210. Alternatively, the buffer memory 214 can be configured inside and outside the memory controller 210.

[0062] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0063] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes (Plane), and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage groups (also called physical bytes or bytes), and each storage group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage group. It should be noted that the present invention is not limited to the size of each physical page and logical page. Each storage group has multiple storage cells (also called storage cells, Memory Cell).

[0064] Figure 2 FIG. 1 is a block diagram of different storage areas of a rewritable non-volatile memory module. Figure 2 As shown, the rewritable non-volatile memory module 220 includes a data cache area 221 and a data storage area 222. The data cache area 221 includes a plurality of cache sets, such as a cache set 221 (1), a cache set 221 (2), ..., a cache set 221 (N). The data storage area 222 includes a plurality of physical blocks, such as a physical block 222 (1), a physical block 222 (2), ..., a physical block 222 (M).

[0065] In this embodiment, each physical page of each cache set (such as 221(1), 221(2), ..., 221(N)) of the data cache area 221 has a plurality of first storage cells of the first type, wherein each first storage cell stores 1 bit of data. This structure is generally referred to as a single-level cell (SLC) storage mode. The SLC mode has a higher read and write speed and a lower error rate, and is suitable for use as a data cache.

[0066] In contrast, each physical page of each physical block of the data storage area 222 (such as 222 (1), 222 (2), ..., 222 (M)) has a plurality of second storage cells of the second type, wherein each second storage cell stores N bits of data, where N is a positive integer greater than 1. This structure is generally referred to as a multi-level cell (MLC) storage mode, and when N is equal to 3, it is specifically referred to as a triple-level cell (TLC) storage mode. The MLC (N = 2) or TLC mode has a higher storage density, but a slower read and write speed, and a relatively higher error rate. N can also be a value greater than 3, corresponding to a larger number of storage cells.

[0067] It is worth noting that in this embodiment, the first number of the plurality of first storage units of each cache set is equal to N times the second number of the plurality of second storage units of each physical block. This design ensures the data correspondence when the data is converted from the SLC mode to the MLC mode (N=2) or the TLC mode (N=3), for example. In other words, the amount of data in each cache set of the data cache area 221 will be equal to the amount of data in each physical block of the data storage area 222, so as to facilitate the data exchange efficiency.

[0068] In one embodiment, the data writing process is, for example:

[0069] (a) Externally written data is first written into a cache set (such as 221 ( 1 )) in the data cache area 221 .

[0070] (b) When the cache set 221 ( 1 ) is full, the controller writes all the data in the cache set 221 ( 1 ) into a blank physical block (such as 222 ( 1 )) in the data storage area 222 .

[0071] (c) The controller may perform a read back test on the physical block 222 ( 1 ) to determine whether there are any uncorrectable error pages.

[0072] In one embodiment, the error handling mechanism is, for example:

[0073] (a) The controller determines the total number of faulty pages in physical block 222(1).

[0074] (b) The controller determines whether the total number of error pages exceeds a preset threshold (eg, a first preset threshold or a second preset threshold).

[0075] (c) Based on the judgment result, the controller determines the subsequent data processing method.

[0076] In one embodiment, since the data cache area 221 and the data storage area 222 use different storage modes (SLC vs MLC / TLC), data format conversion may be required when data is written from the cache set 221 ( 1 ) to the physical block 222 ( 1 ).

[0077] In one embodiment, during the readback detection process, the memory controller 210 may use error detection and correction (ECC) technology to identify and repair possible data errors written to the physical block 222 (1). In more detail, for the data written to the physical block 222 (1), the memory controller 210 first reads the data to be detected and its ECC check bits from the physical block 222 (1) to the internal buffer, and then uses the LDPC (Low Density Parity Check) decoder to calculate the relationship between the check bits and the data bits through the check matrix to perform error detection and correction. The memory controller 210 will count the number of error bits for each page. When the number of error bits of a page exceeds the LDPC error correction capability, the page will be marked as an error page and its physical address will be recorded. Finally, the total number of error pages is counted and compared with a preset threshold. If the error can be corrected and the number of error pages is within the threshold range, it is updated to the corrected data, otherwise the data needs to be rewritten.

[0078] In one embodiment, the preset threshold may be dynamically adjusted according to factors such as the usage status and remaining capacity of the memory to optimize storage performance and reliability.

[0079] Through this storage architecture and management method, the present invention can fully utilize the high-speed reading and writing characteristics of the SLC mode and the high-capacity characteristics of the MLC / TLC mode (for the convenience of explanation, TLC is taken as an example below), while ensuring data reliability, while improving the overall performance and capacity utilization of the storage device.

[0080] Figure 3 The figure is a flowchart of a memory management method according to an embodiment of the present invention.

[0081] like Figure 3 As shown, the method comprises the following steps:

[0082] Step S310: After a first cache set among the multiple cache sets in the data cache area of ​​the rewritable non-volatile memory module 2220 is filled, the memory controller 210 (or the processor 211) writes all the first data of the first cache set from the first cache set to a blank first physical block among the multiple physical blocks in the data storage area of ​​the rewritable non-volatile memory module. It should be noted that the data capacity of each first cache set is consistent with the data capacity of each first physical block.

[0083] In this step, the memory controller 210 first detects whether the first cache set in the data cache area is full. When the first cache set is full, the memory controller 210 transfers all the first data in the first cache set to a blank first physical block in the data storage area. This process realizes the conversion of data from the SLC mode to the MLC / TLC mode (TLC is used as an example below), effectively improving the storage density.

[0084] Step S320: the memory controller 210 performs a read-back test on the first physical block to determine the total number of error pages in the first physical block.

[0085] After the data is written to the first physical block, the memory controller immediately performs a readback test operation. The purpose of this step is to verify the integrity and correctness of the data and identify possible error pages. The controller records the total number of error pages detected that cannot be error-corrected, providing a basis for subsequent data processing decisions.

[0086] Step S330: the memory controller 210 determines whether the total number of the error pages exceeds a first preset threshold.

[0087] In this step, the memory controller 210 compares the total number of detected error pages with a first preset threshold that is set dynamically.

[0088] The following first describes a method for dynamically setting the first preset threshold:

[0089] In one embodiment, before determining whether the total number of error pages exceeds the first preset threshold, the method further includes dynamically setting the first preset threshold, the steps are as follows: obtaining the second cache set in the data cache area except the first cache set; setting the total number of the currently remaining blank multiple physical pages of the second cache set as the first preset threshold. It should be noted that, in one embodiment, the second cache set may also be another cache set that is accumulating cache data.

[0090] Step S340: If the total number of the error pages does not exceed the first preset threshold, the memory controller 210 obtains target data corresponding to the error pages in the first data from the first cache set, and writes the target data to a second cache set among the multiple cache sets.

[0091] When the total number of error pages is within the first preset threshold (indicating that the target data corresponding to the error page can be directly stored in the remaining blank space of the next cache set), the memory controller adopts this selective rewrite strategy. It only extracts the target data corresponding to the error page from the first cache set, and rewrites these data to another cache set (for example, the second cache set sorted after the first cache set), and updates the mapping information of the corresponding target data in the logical-to-physical address mapping table accordingly. This method can effectively correct errors while minimizing data movement and improving system efficiency.

[0092] In one embodiment, the memory controller 210 may further dynamically adjust the first preset threshold according to factors such as the usage time and the number of write times of the memory to adapt to the aging process of the memory.

[0093] In one embodiment, in addition to counting the number of error pages, the memory controller 210 may also analyze the distribution pattern of the errors to identify potential system-level problems.

[0094] In one embodiment, when the memory controller 210 performs a data rewrite or migration operation, the system may maintain a temporary backup to prevent data loss caused by unexpected situations during the process.

[0095] In one embodiment, when selecting a new physical block for data rewriting, the memory controller 210 may consider the usage frequency of each block to achieve wear leveling and extend the overall life of the memory.

[0096] Through this storage management method, the present invention can optimize storage performance and space utilization while ensuring data reliability. The method minimizes the risk of data loss through intelligent error detection and processing mechanisms, and achieves a good balance between efficiency and reliability through selective rewriting and whole block migration strategies.

[0097] The following combination Figure 4 The details of step S340 in the technical solution of the present invention are described in detail.

[0098] Figure 4 is a schematic diagram of storing the target data of the corresponding error page in another cache set according to the comparison result. Figure 4 As shown, the process involves transferring data from the first cache set 221 ( 1 ) to the first physical block 222 ( 1 ), and then rewriting part of the data to the second cache set 221 ( 2 ) according to the read-back detection result.

[0099] First, in step S310, the memory controller 210 writes all the data (BP10 to BP17) in the first cache set 221(1) into the corresponding data pages (DP10 to DP17) in the first physical block 222(1). This process is indicated by arrow A41.

[0100] Next, in step S320, the memory controller 210 performs a read-back test on the first physical block 222(1). Figure 4 As shown, this process is indicated by arrow A42. In this example, the read-back test result shows that DP12 and DP14 are error pages (indicated by diagonal lines in the figure).

[0101] In step S330 , the memory controller 210 determines whether the total number of error pages exceeds a first preset threshold. As indicated by arrow A44 , based on the readback detection, the memory controller 210 determines that the total number of error pages of the first physical block 222 ( 1 ) is 2.

[0102] In addition, as indicated by arrow A43 , the memory controller 210 recognizes that the number of remaining blank physical pages of the next cache set 221 ( 2 ) (or the cache set that is accumulating cache data) is 4, and dynamically sets the first preset threshold to 4.

[0103] Next, as shown by arrow A45, the memory controller 210 compares the number of error pages with the first preset threshold and determines that the number of error pages does not exceed the first preset threshold. That is, the target data corresponding to the error page of the cache set 221 (1) can be stored in the cache set 221 (2).

[0104] As indicated by arrow A46, the memory controller 210 can identify that the target data corresponding to the error pages DP12 and DP14 in the cache set 221 (1) are stored in the physical pages BP12 and BP14, and read out and store the target data into two blank physical pages (e.g., BP24 and BP25) of the cache set 221 (2).

[0105] During the writing process, the memory controller 210 may update the relevant mapping table (not shown) to record the new location of the target data. For example, in one embodiment, after writing the target data to the blank target physical page of the second cache set, the memory controller 210 updates the target mapping information corresponding to the target data in the logical-to-physical mapping table according to the physical address of the target physical page.

[0106] In one embodiment, when writing the target data into the second cache set 221 ( 2 ), the memory controller 210 may apply a data compression algorithm to optimize space utilization.

[0107] In one embodiment, in addition to rewriting the erroneous data, the memory controller 210 may also analyze possible causes of the error, such as whether it is caused by a specific type of data pattern or memory cell characteristics.

[0108] In one embodiment, based on the error pattern, the memory controller 210 may adjust future data allocation strategies to allocate error-prone data patterns to more reliable storage areas.

[0109] For example, in one embodiment, after determining the error page in the first physical block, the memory management method also includes: recording a data state sample of the target data corresponding to the error page; accumulating the number of errors corresponding to the data state sample by 1; and when the number of errors of the data state sample exceeds the error data state sample threshold value, recording the data state sample as an unstable data state sample, and setting the write data that conforms to the data state sample to always be written to the stable data storage area.

[0110] In more detail, after determining the error page in the first entity block, the method further includes the following steps:

[0111] (1) Recording data patterns: The memory controller 210 records the data patterns of the target data corresponding to the error page. Data patterns can be understood as characteristic patterns or attributes of data, such as the bit pattern of data, data type, data update frequency, etc. Data patterns: refers to specific characteristics or patterns of data that may affect the performance or stability of data in the storage medium. For example, certain specific bit patterns may be more likely to cause errors in specific types of storage cells. Data patterns are, for example: (1) the length of consecutive identical bit values ​​(such as 8 or more consecutive "1"s or "0"s); (2) the alternating frequency of different bit values ​​(such as the ratio of "1010" to "0101"); (3) the density of "1" in the data (the proportion of the number of "1"s in each page).

[0112] (2) Accumulating the number of errors: For each identified data pattern, the memory controller 210 maintains a corresponding error counter. Whenever an error associated with a particular data pattern is found, the memory controller 210 accumulates the number of errors corresponding to the data pattern by 1. This statistical method allows the memory controller 210 to track the error tendency of different types of data.

[0113] (3) Determine and mark unstable data patterns: The memory controller 210 sets an error data pattern threshold value (this value can be set based on the overall performance requirements of the system and the acceptable error rate). When the number of errors of a data pattern exceeds this threshold value, the memory controller 210 records the data pattern as an unstable data pattern. This process can help the system identify which types of data are more prone to errors.

[0114] (4) Adjusting the storage strategy: Once a data state is marked as unstable, the memory controller 210 will set a new storage strategy. Specifically, the memory controller 210 will always write all write data that conforms to this unstable data state (for example, including future or existing write data that conforms to this data state) to the stable data storage area. The stable data storage area refers to a storage area that is set or determined to have a higher reliability, or a plurality of physical blocks / buffer blocks that are more stable or have stronger error correction capabilities in the memory. For example, the stable data storage area refers to a storage area (including a plurality of physical blocks) in the memory that meets any of the following conditions: (1) According to the bit error rate (BER) statistics, in the past read and write operations, the BER of the storage area continues to remain below the BER preset threshold; (2) The number of program / erase cycles (P / E cycles) of the storage area is relatively low, for example, the cumulative number of cycles does not exceed 30% or other percentages of the rated life; (3) During the regular flash memory scanning process, the number of ECC error correction bits of the storage area is always kept below the corresponding preset threshold. In another embodiment, the stable data storage area may also be an area in the data storage area that is assembled using a plurality of first-type physical blocks (such as SLC physical blocks) corresponding to the first-type storage units.

[0115] In one embodiment, the memory controller 210 may use a machine learning algorithm to automatically classify and identify different data patterns to improve the accuracy and efficiency of the analysis.

[0116] In one embodiment, the error data pattern threshold may be dynamically adjusted according to the overall performance of the system and the aging degree of the storage medium to meet the needs of different stages.

[0117] By implementing the above-mentioned data pattern-based management method, the present invention can control the data storage strategy more finely. This method can not only improve the reliability of data storage, but also optimize the use of storage resources. By identifying and specially processing error-prone data types, the system can actively prevent potential data errors, thereby improving the stability and life of the overall storage system. At the same time, this method also provides a kind of adaptive capability for the storage system, which can continuously optimize its storage strategy according to actual usage to meet the needs of different types of data and storage environments.

[0118] In addition, based on the above specific description of step S340, the present invention realizes an efficient error handling mechanism. By rewriting only the data corresponding to the error page instead of the entire data block, the overhead of data movement is greatly reduced and the overall efficiency of the system is improved. At the same time, rewriting this data into the cache set in SLC mode also improves the reliability of the data. This method optimizes the performance and life of the storage system while ensuring data integrity.

[0119] Please come back Figure 3 .

[0120] Step S350: If the total number of the error pages exceeds the first preset threshold, the memory controller 210 selects a blank second physical block from the plurality of physical blocks, and writes the first data from the first cache set to the second physical block.

[0121] When the number of error pages exceeds the first preset threshold, the memory controller takes more aggressive measures. It selects a new blank physical block (second physical block) from the data storage area, rewrites the entire first data set from the first cache set to the new physical block, and updates the corresponding mapping information in the logical-to-physical address mapping table accordingly. Although this method increases the overhead of the write operation, it can ensure the integrity and reliability of the data.

[0122] Figure 5 FIG. 1 is a schematic diagram of re-storing data to another physical block according to a comparison result according to an embodiment of the present invention. Figure 5 The details of step S350 in the technical solution of the present invention are described in detail. Figure 5 The process of how the system processes data when the number of error pages exceeds the first preset threshold is demonstrated.

[0123] First, in step S310, the memory controller 210 writes all the data (BP10 to BP17) in the first cache set 221(1) to the corresponding data pages (DP10 to DP17) in the first physical block 222(1). This process is indicated by arrow A51.

[0124] Next, in step S320, the memory controller 210 performs a read-back test on the first physical block 222(1). Figure 5 As shown, this process is represented by arrow A52. In this example, the detection result shows that DP12, DP14 and DP17 are error pages (represented by diagonal lines in the figure).

[0125] In step S330, the memory controller 210 determines whether the total number of error pages exceeds a first preset threshold. As indicated by arrow A54, based on the readback detection, the memory controller 210 determines that the total number of error pages of the first physical block 222(1) is 3.

[0126] In addition, as indicated by arrow A53 , the memory controller 210 recognizes that the number of remaining blank physical pages of the next cache set 221 ( 2 ) is 2, and dynamically sets the first preset threshold to 2.

[0127] Next, as shown by arrow A55, the memory controller 210 compares the number of error pages with the first preset threshold, and determines that the number of error pages exceeds the first preset threshold, that is, the target data of the error page corresponding to the cache set 221(1) cannot be stored in the cache set 221(2), but the first data of the cache set 221(1) can be stored in the new blank physical block 222(2).

[0128] That is, since the number of error pages exceeds the first preset threshold, the memory controller 210 performs the following operations:

[0129] A blank second physical block 222 ( 2 ) is selected from the plurality of physical blocks.

[0130] The memory controller 210 rewrites the first data DD1 (ie, all data BP10 to BP17 in the first cache set 221 ( 1 )) to the corresponding data pages ( DP20 to DP27 ) in the second physical block 222 ( 2 ). This process is indicated by arrow A56 .

[0131] During the writing process, the memory controller 210 updates the relevant mapping table to record the new location of the data. For example, in one embodiment, after writing the first data to the second physical block, the memory controller 210 updates the first mapping information corresponding to the first data in the logical-to-physical mapping table according to the physical address of the second physical block.

[0132] In one embodiment, after the memory controller 210 rewrites the target data from the first cache set to the second physical block, the memory controller 210 performs a readback test on the second physical block. If the test finds that the total number of error pages corresponding to the target data in the second physical block exceeds a first preset threshold, the memory controller 210 performs the following operations:

[0133] First, the memory controller 210 attempts to rewrite the target data to another second physical block to seek a better storage location.

[0134] The memory controller 210 then records and accumulates the number of rewrites of the target data. This count is used to track the write compatibility of specific data (eg, target data).

[0135] When the number of rewrites of the target data exceeds the incompatibility threshold, the memory controller 210 recognizes that the specific data may be fundamentally incompatible with the storage mode of the second physical block (e.g., the second type storage unit). At this time, the memory controller 210 will specifically allocate some physical blocks of the first type (e.g., SLC mode) (also called first type physical blocks) in the data storage area and write the target data into these first type physical blocks.

[0136] For example, the operation process can be:

[0137] Detecting an error page in a second physical block of a second type storage unit, and obtaining target data to be rewritten;

[0138] Cumulative number of target data rewrites;

[0139] Determine whether the number of rewrites exceeds the incompatibility threshold;

[0140] Allocate storage area (first type physical block) in SLC mode when necessary;

[0141] Write the target data into the corresponding (first type physical block).

[0142] Through this mechanism, the system can identify data patterns that are incompatible with the second type of storage mode (e.g., TLC storage mode) and provide a more stable storage environment for it, thereby avoiding repeated errors and invalid rewrites. This method is particularly suitable for processing specific data that is unstable in the second type of mode.

[0143] In one embodiment, when selecting the second physical block 222(2), the memory controller 210 may consider multiple factors, such as the number of erase times of the block, the previous error rate, etc., to select the optimal target block. For example, when selecting the blank second physical block from the plurality of physical blocks, the memory controller 210 selects the blank physical block with the best quality as the second physical block according to the quality parameter of each physical block recorded in advance. The quality parameter includes: the number of times data is written, the number of erase cycles, or the bit error rate.

[0144] In one embodiment, the first physical block 222 ( 1 ) may be marked as requiring further inspection or maintenance, and the memory controller 210 may schedule it to be erased or further reliability tested at an appropriate time.

[0145] Through this method, the present invention realizes an effective recovery mechanism when data reliability is seriously damaged. By rewriting the entire data block into a new physical block, the system can effectively solve multiple page errors caused by storage medium aging or other system-level problems. Although this method may increase write overhead in the short term, it can significantly improve data integrity and system reliability in the long run. At the same time, by updating the mapping table in a timely manner, the system ensures the continuity and correctness of data access.

[0146] In one embodiment, the memory management method further comprises the following steps:

[0147] (1) Determining physical block stability: The memory controller 210 determines whether the first physical block is one of a plurality of unstable physical blocks (for example, after writing the first data from the first cache set to the first physical block). These unstable physical blocks are pre-set and may be determined based on a variety of factors, such as the number of erases and writes, previous error rates, test results during manufacturing, etc. Unstable physical blocks: refer to memory blocks that exhibit a high error rate or instability in storage operations. These blocks may have a reliability below average due to manufacturing defects, overuse, or other factors.

[0148] (2) Targeted readback detection: If it is determined that the first physical block belongs to the unstable physical block group, the memory controller 210 will immediately perform a readback detection on the first physical block to determine the total number of error pages in the first physical block. This targeted detection strategy can detect potential data errors more quickly, so that corrective measures can be taken in a timely manner. In other words, the memory controller 210 does not perform a readback detection on all written physical blocks to avoid adding excessive system delays.

[0149] More specifically, in one embodiment, the method introduces a selective readback detection mechanism, which specifically includes the following steps:

[0150] (1) Initialization phase: When the storage system is initialized or maintained regularly, the memory controller 210 will perform a comprehensive scan of the entire Flash memory. During this process, the system will preliminarily analyze the distribution information of unstable areas in the Flash, including but not limited to instabilities at the chip enable (CE), plane, page, and frame levels.

[0151] (2) Determination of unstable areas:

[0152] The memory controller 210 uses two methods to determine the unstable region:

[0153] (2.1) Using the mapping information that comes with the flash memory when it leaves the factory. This information may contain the manufacturer's initial assessment of the quality of the storage unit.

[0154] (2.2) By performing read and write tests on each area, the memory controller 210 counts the probability of abnormal data appearing. This method can capture areas that show instability in actual use.

[0155] (3) Unstable area records:

[0156] Based on the above determination results, the memory controller 210 maintains an unstable region list, which may include identifiers of CEs, Planes, Pages, or Frames that are identified as unstable.

[0157] (4) Selective readback detection:

[0158] When performing a read back check, the memory controller 210 refers to the unstable region list and performs a detailed read back check only on regions marked as unstable, while for stable regions, a lighter check is used or the check is skipped entirely.

[0159] (5) Dynamic update mechanism:

[0160] The memory controller 210 will periodically update the unstable region list to adapt to the characteristics of memory performance changing over time. This may include:

[0161] (5.1) Add the newly discovered unstable regions to the list.

[0162] (5.2) Re-evaluate and possibly remove from the list areas where stability has been restored.

[0163] By implementing this selective readback detection mechanism, this method can significantly increase the data writing speed while maintaining effective monitoring of critical areas. The advantages of this method include:

[0164] Improved write performance: By reducing unnecessary read-back detection, the overall write speed is greatly improved.

[0165] Precise monitoring: Focus resources on unstable areas that need the most attention, improving the efficiency of error detection.

[0166] Extend memory life: By promptly identifying and managing unstable areas, write operations can be better distributed to avoid overuse of problem areas.

[0167] Dynamic adaptation: A regular update mechanism ensures that the system can adapt to changes in memory performance over time.

[0168] On the other hand, in one embodiment, the present invention also introduces a multi-level threshold judgment mechanism and an abnormal statistical strategy to achieve more sophisticated error management and storage block life monitoring. In more detail, after performing a readback test on the first physical block, the method further includes the following steps:

[0169] (1) Multi-level threshold judgment: Before judging whether the total number of error pages exceeds the first preset threshold, the memory controller 210 first judges whether the total number of error pages exceeds the second preset threshold. The second preset threshold here can be determined by experiment. When the second preset threshold is exceeded, the memory controller 210 will consider that there is a problem with the physical characteristics of the corresponding physical block (in the traditional method, if the second preset threshold is exceeded, the memory controller 210 can mark / classify the corresponding physical block as a bad block), and directly perform subsequent processing.

[0170] (2) Conditional judgment and processing:

[0171] If the total number of error pages does not exceed the second preset threshold, the memory controller 210 continues to determine whether it exceeds the first preset threshold, and executes a corresponding error handling strategy according to the result.

[0172] If the total number of error pages exceeds the second preset threshold, the memory controller 210 skips the comparison with the first preset threshold and directly takes more radical measures: selects a blank second physical block from multiple physical blocks and rewrites the first data from the first cache set to the second physical block.

[0173] (3) Abnormal statistics and bad block management:

[0174] When the total number of error pages exceeds the second preset threshold, in addition to performing the data rewriting operation, the memory controller 210 also:

[0175] (3.1) The number of exceptions corresponding to the first entity block is increased by 1. This counter is used to track the long-term performance of the entity block.

[0176] (3.2) Check whether the accumulated number of exceptions exceeds the third preset threshold. If so, the memory controller 210 classifies the first physical block as a bad block. The third preset threshold: the upper limit of the number of exceptions used to determine whether a physical block should be classified as a bad block. Bad blocks: refers to those storage blocks that are determined by the system to be no longer suitable for storing data due to frequent errors or other reasons. In other words, by using the accumulative number of exceptions, the method provides some additional buffering opportunities for physical blocks whose total number of error pages exceeds the second preset threshold, so as to avoid being directly classified as bad blocks.

[0177] By implementing this multi-level threshold judgment and abnormal statistics management method, the present invention can achieve the following advantages:

[0178] Refined error management: By introducing multiple thresholds, the system can take different levels of response measures according to the severity of the error, which not only ensures the reliability of data but also avoids performance loss caused by overreaction.

[0179] Improved response speed: For serious errors (exceeding a second preset threshold), the system can quickly take radical corrective actions without additional judgment, thereby reducing the risk of data corruption.

[0180] Long-term reliability monitoring: By tracking the number of anomalies for each physical block, the system can identify storage areas where performance is gradually degrading and take preventive measures before the problem becomes serious.

[0181] Adaptive performance: This approach allows the system to dynamically adjust its error handling strategy based on actual operating conditions, allowing the storage system to maintain optimal performance in different usage stages and environments.

[0182] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code is executed in a processor of a host system, the processor executes the steps of the above storage device management method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0183] Based on the above, the memory management method and memory controller provided by the embodiment of the present invention timely discover the error page in the storage area corresponding to the second type storage unit through readback detection, and dynamically adjust the preset threshold based on the capacity of the remaining data cache area corresponding to the first type storage unit, thereby realizing an adaptive error handling strategy: when the number of error pages is small, only the error page is rewritten to reduce the resource consumption of data movement, and when there are many errors, a higher quality physical block corresponding to the second type storage unit is selected for whole block rewriting, thereby improving the reliability of the storage device. At the same time, by identifying error-prone data patterns and specially handling unstable storage areas, the system can preventively adjust the storage strategy, effectively extending the life of the storage device while improving data reliability.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applicable to a memory controller of a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: After a first cache set among multiple cache sets in the data cache area of ​​the rewritable non-volatile memory module is full, writing first data of the first cache set from the first cache set to a blank first physical block among multiple physical blocks in the data storage area of ​​the rewritable non-volatile memory module, wherein the data capacity of the first cache set is consistent with the data capacity of the first physical block; Performing a readback test on the first physical block to determine a total number of error pages in the first physical block; Determining whether the total number of the error pages exceeds a first preset threshold; and If the total number of the error pages does not exceed the first preset threshold, target data corresponding to the error pages in the first data is acquired from the first cache set, and the target data is written into a second cache set among the multiple cache sets.

2. The memory management method according to claim 1, characterized in that: If the total number of the error pages exceeds the first preset threshold, a blank second physical block is selected from the plurality of physical blocks, and the first data is written from the first cache set to the second physical block.

3. The memory management method according to claim 2, characterized in that: The method further comprises: After rewriting the target data from the first cache set to the second physical block, if the total number of error pages corresponding to the target data in the second physical block exceeds the first preset threshold, rewriting the target data from the first cache block to another second physical block, and accumulating the number of rewrites of the target data; If the number of rewrites exceeds an incompatible threshold, a plurality of first-type physical blocks of a first type are allocated in the data storage area, and the target data is written to the plurality of first-type physical blocks, wherein the plurality of physical blocks in the data storage area are of a second type.

4. The memory management method according to claim 2, characterized in that: Before determining whether the total number of the error pages exceeds the first preset threshold, the method further includes: Determining whether the total number of the error pages exceeds a second preset threshold; If the total number of the error pages does not exceed the second preset threshold, determining whether the total number of the error pages exceeds the first preset threshold; and If the total number of the error pages exceeds a second preset threshold, without determining whether the total number of the error pages exceeds the first preset threshold, directly select a blank second physical block from the multiple physical blocks, and write the first data from the first cache set to the second physical block.

5. The memory management method according to claim 4, characterized in that: If the total number of the error pages exceeds the second preset threshold, the method further includes: Accumulate the number of abnormalities corresponding to the first physical block by 1; and When the number of abnormalities exceeds a third preset threshold, the first physical block is classified as a bad block.

6. The memory management method according to claim 2, characterized in that: Before determining whether the total number of the error pages exceeds the first preset threshold, the method further includes: Acquire the second cache set except the first cache set in the data cache area; The total number of the plurality of blank physical pages currently remaining in the second cache set is set as the first preset threshold.

7. The memory management method according to claim 1, characterized in that: in Each cache set of the data cache area has a plurality of first storage units of a first type, wherein each first storage unit stores 1 bit of data, Each physical block of the data storage area has a plurality of second storage units of a second type, wherein each second storage unit stores N bits of data, where N is a positive integer greater than 1. The first number of the plurality of first storage units in each cache set is equal to N times the second number of the plurality of second storage units in each physical block.

8. The memory management method according to claim 1, characterized in that: The performing a readback test on the first physical block to determine the total number of error pages in the first physical block includes: determining whether the first physical block is one of a plurality of unstable physical blocks, wherein the plurality of unstable physical blocks are preset; and In response to determining that the first physical block belongs to the unstable physical block group, a read-back test is performed on the first physical block to determine a total number of error pages in the first physical block.

9. The memory management method according to claim 1, characterized in that: After determining the error page in the first physical block, the method further includes: Recording a data pattern of the target data corresponding to the error page; Accumulate the number of errors corresponding to the data pattern by 1; and When the number of errors of the data pattern exceeds an error data pattern threshold, the data pattern is recorded as an unstable data pattern, and the write data matching the data pattern is set to always be written into a stable data storage area.

10. The memory management method according to claim 2, characterized in that: The method further comprises: When selecting the blank second physical block from the plurality of physical blocks, a blank physical block with the best quality is selected as the second physical block according to the pre-recorded quality parameter of each physical block, The quality parameters include: The number of times data is written, the number of erase cycles, or the bit error rate.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: After a first cache set in a plurality of cache sets in a data cache area of ​​the rewritable non-volatile memory module is full, writing all first data of the first cache set from the first cache set to a blank first physical block in a plurality of physical blocks in a data storage area of ​​the rewritable non-volatile memory module, wherein the data capacity of the first cache set is consistent with the data capacity of the first physical block; Performing a readback test on the first physical block to determine a total number of error pages in the first physical block; Determining whether the total number of the error pages exceeds a first preset threshold; and If the total number of the error pages does not exceed the first preset threshold, target data corresponding to the error pages in the first data is acquired from the first cache set, and the target data is written into a second cache set among the multiple cache sets.

12. The memory controller according to claim 11, wherein: in If the total number of the error pages exceeds the first preset threshold, a blank second physical block is selected from the plurality of physical blocks, and the first data is written from the first cache set to the second physical block.

13. The memory controller according to claim 12, wherein: The processor is also configured to: After rewriting the target data from the first cache set to the second physical block, if the total number of error pages corresponding to the target data in the second physical block exceeds the first preset threshold, rewriting the target data from the first cache block to another second physical block, and accumulating the number of rewrites of the target data; If the number of rewrites exceeds an incompatible threshold, a plurality of first-type physical blocks of a first type are allocated in the data storage area, and the target data is written to the plurality of first-type physical blocks, wherein the plurality of physical blocks in the data storage area are of a second type.

14. The memory controller according to claim 12, wherein: Before determining whether the total number of the error pages exceeds the first preset threshold, the processor is further configured to: Determining whether the total number of the error pages exceeds a second preset threshold; If the total number of the error pages does not exceed the second preset threshold, determining whether the total number of the error pages exceeds the first preset threshold; as well as If the total number of the error pages exceeds a second preset threshold, without determining whether the total number of the error pages exceeds the first preset threshold, directly select a blank second physical block from the multiple physical blocks, and write the first data from the first cache set to the second physical block.

15. The memory controller according to claim 14, wherein: If the total number of the error pages exceeds the second preset threshold, the processor is further configured to: Accumulate the number of exceptions corresponding to the first entity block by 1; as well as When the number of abnormalities exceeds a third preset threshold, the first physical block is classified as a bad block.

16. The memory controller according to claim 12, wherein: Before determining whether the total number of the error pages exceeds the first preset threshold, the processor is further configured to: Acquire the second cache set except the first cache set in the data cache area; The total number of the plurality of blank physical pages currently remaining in the second cache set is set as the first preset threshold.

17. The memory controller according to claim 11, wherein: in Each cache set of the data cache area has a plurality of first storage units of a first type, wherein each first storage unit stores 1 bit of data, Each physical block of the data storage area has a plurality of second storage units of a second type, wherein each second storage unit stores N bits of data, where N is a positive integer greater than 1. The first number of the plurality of first storage units in each cache set is equal to N times the second number of the plurality of second storage units in each physical block.

18. The memory controller according to claim 11, wherein: The processor is also configured to: determining whether the first physical block is one of a plurality of unstable physical blocks, wherein the plurality of unstable physical blocks are preset; as well as In response to determining that the first physical block belongs to the unstable physical block group, a read-back test is performed on the first physical block to determine a total number of error pages in the first physical block.

19. The memory controller according to claim 11, wherein: After determining the error page in the first physical block, the processor is further configured to: Recording a data pattern of the target data corresponding to the error page; Accumulate the number of errors corresponding to the data pattern by 1; as well as When the number of errors of the data pattern exceeds an error data pattern threshold, the data pattern is recorded as an unstable data pattern, and the write data matching the data pattern is set to always be written into a stable data storage area.

20. The memory controller according to claim 12, wherein: The processor is also configured to: When selecting the blank second physical block from the plurality of physical blocks, a blank physical block with the best quality is selected as the second physical block according to the pre-recorded quality parameter of each physical block, The quality parameters include: The number of times data is written, the number of erase cycles, or the bit error rate.

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