Realization method and device for reordering cache, equipment, medium and program product

Abstract

The invention provides an implementation method, device and equipment for reordering cache, a medium and a program product. The method comprises the following steps: acquiring N decoding instructions; one idle table item in each first group is distributed to each decoding instruction in sequence; wherein the first groups are groups containing idle table entries in the ROB, the number of the first groups is K, N is smaller than or equal to K, and N and K are integers larger than 1. Therefore, on the basis of grouping the table entries of the ROB, the capacity of the ROB and the performance of the processor can be improved by respectively distributing the idle table entries belonging to different groups for the plurality of decoding instructions.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a method, device, equipment, medium and program product for implementing a reorder cache. Background Art

[0002] For a superscalar processor, instructions are executed out-of-order (OoO). In order to ensure that the instructions executed out-of-order can be completed and submitted correctly, a reorder buffer (ROB) is introduced.

[0003] In the related art, ROB is implemented using a one-dimensional queue structure, which is essentially a first-in-first-out (FIFO) table, in which instruction-related information is stored. During the instruction commit phase, because instructions are executed out of order, the instruction identification document (IID) of the ROB of the submitted instruction is not necessarily submitted in sequence. Therefore, the instruction needs to be compared with all entries in the ROB. It is difficult to increase the capacity of the ROB without affecting the performance of the central processing unit (CPU) when implementing the ROB using a one-dimensional queue structure, which limits the performance of the CPU. Summary of the invention

[0004] To overcome the problems existing in the related art, the present disclosure provides a method, apparatus, device, medium and program product for implementing a reorder cache to improve the capacity of the ROB and the performance of the processor.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for implementing a reorder cache is provided, comprising: obtaining N decoding instructions; allocating a free table entry in each first group to each decoding instruction in turn; wherein the first group is a group containing free table entries in the ROB, the number of the first groups is K, N≤K, and N and K are integers greater than 1.

[0006] In some embodiments, a free table entry in each first group is assigned to each decoding instruction in turn, including: determining the first position indicated by the tail pointer in the ROB; assigning the free table entry indicated by the first position to the first decoding instruction among N decoding instructions; for non-first decoding instructions, assigning the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions; wherein 1≤i≤N-1 and i is an integer, and the free table entries indicated by the first position and the i-th position after the first position are in different first groups.

[0007] In some embodiments, for non-first decoding instructions, after allocating the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions, the above method also includes: determining the second position indicated after the tail pointer is incremented by N; updating the first position to the second position.

[0008] In some embodiments, before obtaining N decoding instructions, the above method also includes: determining the relationship between the total number of free table entries contained in the first group and the number of groups G contained in the ROB, wherein G is an integer greater than 1 and G≥K; when the total number of free table entries is less than G, sending a pause signal to the instruction decoding queue so that the instruction decoding queue can pause outputting decoding instructions; wherein, the instruction decoding queue is used to output decoding instructions.

[0009] In some embodiments, the above method also includes: determining M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, wherein the L instructions to be submitted are instructions that have been executed among T decoded instructions, T is the total number of unreleased instructions determined in this release process, M≤L≤T, T≥N and M, L, T are all integers greater than 1; according to the table entry identification information corresponding to the M instructions to be released, releasing the table entries corresponding to each instruction to be released in turn.

[0010] In some embodiments, M instructions to be released that meet the release conditions in this release process are determined from L instructions to be submitted, including: obtaining L instructions to be submitted; marking the submission identifier of the table item corresponding to each instruction to be submitted as a first value according to the table item identification information corresponding to each instruction to be submitted; and determining the instructions to be submitted corresponding to multiple consecutive table items whose submission identifier is the first value as M instructions to be released.

[0011] In some embodiments, based on the table entry identification information corresponding to M instructions to be released, the table entry corresponding to each instruction to be released is released in sequence, including: determining the third position indicated by the head pointer in the ROB; determining the release order of the table entries corresponding to the M instructions to be released based on the table entry identification information corresponding to the M instructions to be released; based on the third position and the release order, releasing the table entry corresponding to the first instruction to be released among the M instructions to be released; for non-first instruction to be released, releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position; wherein 1≤j≤M-1 and j is an integer.

[0012] In some embodiments, for non-first instruction to be released, after releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position, the above method also includes: determining the fourth position indicated by the head pointer after incrementing by M; updating the third position to the fourth position.

[0013] In some embodiments, before determining M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, the above method also includes: determining the relationship between L and the number of groups G contained in the ROB, where G is an integer greater than 1 and G≥K; when L exceeds G, sending a retirement pause signal to the execution queue so that the execution queue can pause outputting instructions to be submitted; wherein the execution queue is used to output instructions to be submitted.

[0014] According to a second aspect of an embodiment of the present disclosure, a device for implementing a reorder cache is provided, comprising: an acquisition module configured to acquire N decoding instructions; an allocation module configured to allocate a free table entry in each first group to each decoding instruction in turn; wherein the first group is a group containing free table entries in a reorder cache ROB, the number of the first groups is K, N≤K, and N and K are integers greater than 1.

[0015] In some embodiments, the allocation module is configured to perform the following steps: determine the first position indicated by the tail pointer in the ROB; allocate the free table entry indicated by the first position to the first decoding instruction among N decoding instructions; for non-first decoding instructions, allocate the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions; wherein 1≤i≤N-1 and i is an integer, and the free table entries indicated by the first position and the i-th position after the first position are in different first groups.

[0016] In some embodiments, the above-mentioned device also includes: a first determination module, configured to, for a non-first decoding instruction, allocate the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions, and determine the second position indicated by the tail pointer after incrementing by N; a first update module, configured to update the first position to the second position.

[0017] In some embodiments, the above-mentioned device also includes: a second determination module, configured to determine the relationship between the total number of free table entries contained in the first group and the number of groups G contained in the ROB before obtaining N decoding instructions, wherein G is an integer greater than 1 and G≥K; a first sending module, configured to send a pause signal to the instruction decoding queue when the total number of free table entries is less than G, so that the instruction decoding queue can pause outputting decoding instructions; wherein the instruction decoding queue is used to output decoding instructions.

[0018] In some embodiments, the above-mentioned device also includes: a third determination module, configured to determine M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, wherein the L instructions to be submitted are instructions that have been executed among T decoded instructions, T is the total number of unreleased instructions determined in this release process, M≤L≤T, T≥N and M, L, T are all integers greater than 1; a release module, configured to release the table entries corresponding to each instruction to be released in turn according to the table entry identification information corresponding to the M instructions to be released.

[0019] In some embodiments, the third determination module is configured to perform the following steps: obtain L instructions to be submitted; mark the submission identifier of the table item corresponding to each instruction to be submitted as a first value based on the table item identification information corresponding to each instruction to be submitted; and determine the instructions to be submitted corresponding to multiple consecutive table items with the submission identifier as the first value as M instructions to be released.

[0020] In some embodiments, the release module is configured to perform the following steps: determine the third position indicated by the head pointer in the ROB; determine the release order of the table entries corresponding to the M instructions to be released based on the table entry identification information corresponding to the M instructions to be released; release the table entry corresponding to the first instruction to be released among the M instructions to be released based on the third position and the release order; for non-first instruction to be released, release the table entry of the j+1th instruction to be released indicated by the jth position after the third position; wherein 1≤j≤M-1 and j is an integer.

[0021] In some embodiments, the above-mentioned device also includes: a fourth determination module, configured to determine the fourth position indicated by the head pointer after incrementing by M after releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position for non-first instruction to be released; and a second update module, configured to update the third position to the fourth position.

[0022] In some embodiments, the above-mentioned device also includes: a fifth determination module, configured to determine the relationship between L and the number of groups G contained in the ROB before determining the M instructions to be released that meet the release conditions in this release process from the L instructions to be submitted, wherein G is an integer greater than 1 and G≥K; a second sending module, configured to send a retirement pause signal to the execution queue when L exceeds G, so that the execution queue can pause outputting the instructions to be submitted; wherein the execution queue is used to output the instructions to be submitted.

[0023] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, comprising: a processor; and a memory for storing computer programs or instructions; wherein the processor executes the computer program or instructions to implement the steps in any one of the reordering cache implementation methods in the first aspect above.

[0024] According to a fourth aspect of an embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided, wherein the storage medium stores a computer program or instructions. When the computer program or instructions in the storage medium are executed by a processor, the steps in any one of the reorder cache implementation methods in the first aspect described above are implemented.

[0025] According to a fifth aspect of an embodiment of the present disclosure, a computer program product is provided, comprising a computer program or instructions, which, when executed by a processor, implements the steps in any one of the reorder cache implementation methods in the first aspect.

[0026] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0027] Obtain N decoding instructions; sequentially allocate one free table entry in each first group to each decoding instruction; wherein the first group is a group containing free table entries in the ROB, the number of the first group is K, N≤K, and N and K are integers greater than 1. In this way, on the basis of grouping the table entries of the ROB, by respectively allocating free table entries belonging to different groups to multiple decoding instructions, the capacity of the ROB and the performance of the processor can be improved.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0030] Figure 1 is a schematic diagram of a process of a table entry allocation phase in a related technology according to an exemplary embodiment;

[0031] Figure 2 is a schematic diagram of a process of a table entry release phase in a related technology according to an exemplary embodiment;

[0032] Figure 3 is a schematic diagram of a table entry grouping process according to an exemplary embodiment;

[0033] Figure 4 is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment;

[0034] Figure 5 is a schematic diagram showing a life cycle of a decoding instruction in a processor according to an exemplary embodiment;

[0035] Figure 6is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment;

[0036] Figure 7 is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment;

[0037] Figure 8 is a block diagram of a device for implementing a reorder cache according to an exemplary embodiment;

[0038] Fig. 9 is a structural block diagram of an electronic device 900 according to an exemplary embodiment;

[0039] Fig.10 is a block diagram of a server 1000 according to an exemplary embodiment. DETAILED DESCRIPTION

[0040] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0041] A superscalar processor executes instructions out of order. To maintain the seriality of instruction execution results, a final stage, called the commit stage, is usually added to the pipeline of the superscalar processor. When an instruction reaches the commit stage of the pipeline, it is marked as completed in the ROB.

[0042] In the related art, ROB is implemented by using a one-dimensional queue structure during the design process. The following describes the table entry allocation phase and table entry release phase of ROB implemented by using a one-dimensional queue structure:

[0043] Figure 1 FIG. 1 is a process diagram of a table entry allocation phase in a related technology according to an exemplary embodiment. When an instruction is distributed in the dispatch phase (Dispatch), an idle entry is allocated to the instruction in the ROB at the same time, and then the tail pointer is incremented. Figure 1 As shown in (a), assume that the one-dimensional queue contains A entries in total, and the entry identifiers of these A entries are: 0, 1, 2, ..., A-2, A-1, where the head pointer points to the entry identified as 0, and the tail pointer points to the entry identified as A-2. When the entry identified as A-2 is assigned to an instruction, the tail pointer will be incremented, and the tail pointer will point to the entry identified as A-1 after being updated, and the position of the head pointer remains unchanged, as shown in Figure 1As shown in (b) in .

[0044] It can be understood that the element in the one-dimensional queue pointed to (also referred to as the indication) by the head pointer (also referred to as the read pointer) is used to identify the position of the current entry to be released. In the operation of the queue, the dequeue operation (i.e., releasing the entry from the queue) is performed from the position indicated by the head pointer, so the position of the head pointer determines the data of the next dequeue operation. The element in the one-dimensional queue pointed to by the tail pointer (also referred to as the write pointer) is used to identify the position of the currently available free entry. In the operation of the queue, the enqueue operation (i.e., allocating entries to instructions) is performed from the position indicated by the head pointer, so the position of the tail pointer determines the data of the next enqueue operation.

[0045] Figure 2 The following is a process diagram of a table entry release phase in a related technology according to an exemplary embodiment. After instructions are continuously distributed into the ROB, when an instruction needs to be submitted after execution, the entry in the ROB is popped out from the head pointer position, the corresponding table entry is released, and then the head pointer is incremented. Figure 2 As shown in (a) in the figure, assume that the one-dimensional queue contains A entries in total, and the entry identifiers of these A entries are: 0, 1, 2, ..., A-2, A-1, where the head pointer points to the entry identified as 0, and the tail pointer points to the entry identified as A-2. When the entry identified as 0 is released, the head pointer will be incremented, and the head pointer will point to the entry identified as 1 after being updated, and the tail pointer position remains unchanged, as shown in Figure 2 As shown in (b) in .

[0046] It should be noted that: Figure 1 and Figure 2 The number of entries, the position of the head pointer, and the position of the tail pointer shown in are only for exemplary description and are not limited in this embodiment of the present disclosure.

[0047] The ROB implemented using the one-dimensional queue structure is essentially a first-in, first-out queue, which stores relevant information of at least one instruction, such as the type, result, destination register and exception type of at least one instruction. ROB is mainly responsible for retiring instructions and restoring resources when refresh occurs. The size of the ROB window determines the CPU's out-of-order execution capability. The more entries in the ROB, the stronger its performance.

[0048] In addition, during the instruction submission phase, because instructions are executed out of order in the CPU, the IID of the ROB of the instruction to be submitted is not necessarily submitted in order. Therefore, the instruction to be submitted needs to be compared with all the entries in the ROB. The ROB implemented with a one-dimensional queue structure is equivalent to a central address memory (CAM). When implemented in the back end, it is difficult to increase the capacity of the ROB without affecting the performance of the CPU, which limits the performance of the CPU.

[0049] Based on this, the embodiment of the present disclosure implements ROB through a group design method. Assuming that the number of entries in ROB is A, these entries can be evenly divided into G groups, each group is a block (also called bank), and the number of entries in each bank is A / G. In this way, implementing ROB through a group design method can increase the upper limit of ROB capacity and the performance space of CPU, and can also simplify the backend implementation, so that the CPU can reach a higher design frequency.

[0050] In some embodiments, for the above grouping process, the ROB may be divided into G groups in advance, or before the ROB entry allocation phase, or at other times, which is not limited in the embodiments of the present disclosure.

[0051] In some embodiments, the above grouping process may be executed by a processor. In some instances, the grouping process may be triggered manually or after receiving a grouping instruction, which is not limited in the embodiments of the present disclosure.

[0052] Figure 3 FIG. 1 is a schematic diagram showing a process of grouping table entries according to an exemplary embodiment. Figure 3 As shown, the entries of the ROB are divided into G groups, namely: bank 0, bank 1, bank 2, ..., bank G-1. The identifiers of each entry are numbered starting from the bottom position of the rightmost column (from left to right), and the entry identifiers from bottom to top are 0, 1, ... G-1, the bottom position of the column to the left of the column is numbered G, and the remaining positions are numbered in sequence, and the top position of the leftmost column is numbered A-1.

[0053] It should be noted that: Figure 3 The number of entries, the number of groups of entry groups, and the method of numbering entries shown in are only exemplary descriptions and are not limited in the embodiments of the present disclosure.

[0054] Figure 4 FIG. 1 is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment. Figure 4As shown, the method mainly includes the following steps:

[0055] In step 401, N decoding instructions are obtained.

[0056] In step 402, one free table entry in each first group is allocated to each decoding instruction in turn.

[0057] Here, the first group is a group containing free entries in the ROB, and the number of the first group is K, N≤K, and N and K are integers greater than 1. The first group can be independently implemented in a parallel structure in physical implementation.

[0058] In some embodiments, for step 401, the N decoded instructions may be decoded instructions sent by the instruction decode queue to the ROB, or may be valid decoded instructions determined by the processor from decoded instructions sent by the instruction decode queue to the ROB, which is not limited in the embodiments of the present disclosure. Since the table entry allocation process may be executed multiple times, such as multiple times according to the clock cycle, step 401 may be executed multiple times when N≤K is satisfied.

[0059] In some embodiments, for step 402, in order to ensure the seriality of the instruction execution results in the processor, a free table entry needs to be allocated for each decoded instruction. At the same time, based on the multiple groups of ROB implemented by grouping design, K first groups containing free table entries in the multiple groups can be determined. Since N≤K, a free table entry in a different first group can be allocated to each decoded instruction. Then, a free table entry in each first group is allocated to each decoded instruction in turn, so that the free table entry corresponding to each decoded instruction is in a different first group. Since each first group can be independently implemented in a parallel structure, the capacity of the ROB can be increased.

[0060] In the embodiment of the present application, N decoding instructions are obtained, and then one free table entry in each first group is sequentially allocated to each decoding instruction; wherein the first group is a group containing free table entries in the ROB, and the number of the first group is K, N≤K, and N and K are integers greater than 1. In this way, on the basis of grouping the table entries of the ROB, by respectively allocating free table entries belonging to different groups to multiple decoding instructions, the capacity of the ROB and the performance of the processor can be improved.

[0061] Figure 5 FIG. 1 is a schematic diagram showing a decoding instruction existence cycle in a processor according to an exemplary embodiment. Figure 5As shown: the existence cycle of a decoded instruction in a processor may include the following processes: instruction decode queue (IDQ), distribution phase, issue queue (IssueQ), execution (EX) phase and ROB. Among them, the instruction decode queue is used to store instructions to be executed by the processor, such as decoded instructions; the distribution phase is used to allocate free entries of the ROB for each decoded instruction in the instruction decode queue and to implement other functions; the issue queue is used to send the decoded instructions after the distribution phase to the execution phase; the execution phase is used to execute the received decoded instructions; the ROB is used to allocate free entries for the decoded instructions in the distribution phase, and to release the entries corresponding to the instructions to be submitted sent in the execution phase, etc. It should be noted that Figure 5 The process shown in the figure is only for illustrative purposes and is not specifically limited in the present disclosure.

[0062] In some embodiments, step 402 may include: step a, determining the first position indicated by the tail pointer in the ROB; step b, allocating the free table entry indicated by the first position to the first decoding instruction among N decoding instructions; step c, for non-first decoding instructions, allocating the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions.

[0063] Here, 1≤i≤N-1 and i is an integer, and the free entries indicated by the first position and the i-th position after the first position are in different first groups.

[0064] It can be understood that the position pointed to by the tail pointer is used to identify the position of the currently available free table entry. Therefore, by determining the first position indicated by the tail pointer in the ROB, the position of the currently available free table entry in the ROB can be determined. Then the free table entry indicated by the first position is assigned to the first decoding instruction among the N decoding instructions. For non-first decoding instructions among the N decoding instructions, the free table entry indicated by the i-th position after the first position can be assigned to the i+1-th decoding instruction among the N decoding instructions. In this way, the free table entries corresponding to each decoding instruction are in different first groups. Since each first group can be independently implemented in a parallel structure, the capacity of the ROB and the performance of the processor can be improved.

[0065] In one example, for non-first decoding instructions among N decoding instructions, the free table entry indicated by the first position after the first position can be assigned to the second decoding instruction among the N decoding instructions, the free table entry indicated by the second position after the first position can be assigned to the third decoding instruction among the N decoding instructions, ..., and the free table entry indicated by the N-1th position after the first position can be assigned to the Nth decoding instruction among the N decoding instructions.

[0066] In some embodiments, in step 402, one free table entry in each first group is assigned to each decoding instruction in turn, and it may also include: assigning any free table entry in each first group to each decoding instruction in turn, so as to ensure that the free table entries corresponding to each decoding instruction are in different first groups.

[0067] In an example, assuming that N is 4 and K is 6, any free table entries in any 4 of the 6 first groups can be allocated to the 4 decoding instructions in sequence.

[0068] In one example, assuming that N is 4 and K is 6, any free table entry in the first of the 6 first groups can be assigned to the first of the 4 decoding instructions, any free table entry in the second of the 6 first groups can be assigned to the second of the 4 decoding instructions, any free table entry in the third of the 6 first groups can be assigned to the third of the 4 decoding instructions, and any free table entry in the fourth of the 6 first groups can be assigned to the fourth of the 4 decoding instructions.

[0069] In some embodiments, the order of the first group can be determined based on the number of free table entries contained therein, or based on identification information of the first group (such as an identification number), or based on other methods, which is not limited in the embodiments of the present disclosure.

[0070] In some embodiments, the order of the N decoding instructions can be determined according to the order in which the decoding instructions are acquired, or according to the identification information (such as an identification number) of the decoding instructions, or according to other methods, which is not limited in the embodiments of the present disclosure.

[0071] In some embodiments, in step 402, other allocation methods may also be used to allocate a free table entry in each first group to each decoding instruction in turn, as long as the free table entry corresponding to each decoding instruction is in a different first group. The embodiments of the present disclosure are not limited to this.

[0072] In some embodiments, in step c included in step 402, for non-first decoding instruction, after allocating the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions, the above method also includes: determining the second position indicated by the tail pointer after incrementing by N; updating the first position to the second position.

[0073] It can be understood that after the free table entry indicated by the i-th position after the first position is allocated to the i+1-th decoding instruction among the N decoding instructions, each of the N decoding instructions is allocated a free table entry this time, and then the first position indicated by the tail pointer also needs to be updated to facilitate the allocation of the free table entries of the decoding instructions obtained subsequently. Based on this, the tail pointer is incremented by N, and the second position indicated by the tail pointer after the increment by N can be obtained, that is: the N-th position after the first position, and then the first position is updated to the second position, and the position indicated by the second position is the position of the free table entry that is available next time after the free table entry allocation this time. In this way, through the above-mentioned updating method, it is beneficial to the next free table entry allocation and can improve the efficiency of free table entry allocation.

[0074] In some embodiments, before obtaining N decoded instructions through step 401, the method further includes: determining the relationship between the total number of free entries contained in the first group and the number of groups G contained in the ROB; when the total number of free entries is less than G, sending a pause signal to the instruction decoding queue so that the instruction decoding queue pauses outputting decoded instructions. Here, G is an integer greater than 1 and G≥K, and the instruction decoding queue is used to output decoded instructions.

[0075] It can be understood that a counter can be deployed inside the ROB to count the total number of free table entries contained in multiple first groups. For example, each time a newly entered decoded instruction is assigned a free table entry, the counter is decremented, and each time an instruction is successfully retired (i.e., a table entry is released), the counter is incremented. In this way, automatic counting can be achieved; a counter can also be deployed in each first group to count the number of free table entries contained in each first group to determine the total number of free table entries contained in multiple first groups. The total number of free table entries contained in the first group can also be determined by other means, and the embodiments of the present disclosure are not limited to this.

[0076] In the above case, the total number of free table entries included in the first group can be determined by the above method, and then the total number is compared with the number of groups G included in the ROB to obtain the size relationship between the two. When the total number of free table entries is less than G, it means that the total number of free table entries is not sufficient. At this time, the processor sends a pause signal to the instruction decoding queue, so that the instruction decoding queue can pause outputting decoding instructions after receiving the pause signal. This method can avoid outputting too many decoding instructions, thereby avoiding the inability to allocate free table entries for these decoding instructions.

[0077] In some embodiments, before obtaining N decoding instructions through step 401, the above method also includes: determining the relationship between the total number of free table entries contained in the first group and the number of groups G contained in the ROB; when the total number of free table entries is greater than or equal to G, obtaining a group of decoding instructions, and determining N valid decoding instructions from this group of decoding instructions.

[0078] It can be understood that when the total number of free table entries is greater than or equal to G, it means that the total number of free table entries is sufficient. At this time, a group of decoded instructions can be obtained from the instruction decode queue, and the number of valid decoded instructions included in the group of decoded instructions can be counted, so that multiple valid decoded instructions are determined as N decoded instructions. In this way, through the above process, invalid decoded instructions can be screened out, and there is no need to allocate free table entries for invalid decoded instructions in the future, which can improve the processing efficiency of the processor.

[0079] In some embodiments, each decoding instruction may carry valid identification information indicating whether it is valid, and the processor may determine whether the decoding instruction is a valid decoding instruction through the identification information. In one example, if the valid identification information is 1, the decoding instruction may be determined to be a valid decoding instruction; if the valid identification information is 0, the decoding instruction may be determined to be an invalid decoding instruction.

[0080] In some embodiments, after step 402, the above method also includes: step d, determining M instructions to be released that meet the release conditions in this release process from the L instructions to be submitted; step e, releasing the table entries corresponding to each instruction to be released in turn according to the table entry identification information corresponding to the M instructions to be released.

[0081] Here, the L instructions to be submitted are the instructions that have been executed among the T decoded instructions, T is the total number of unreleased instructions determined during this release process, M≤L≤T, T≥N, and M, L, and T are all integers greater than 1. The release condition can be understood as the conditions that need to be met for the instruction to be submitted to be released, which may include but is not limited to the submission identifiers of the table items corresponding to the instruction to be submitted and the instructions to be submitted before the instruction to be submitted are all first values. The table item identification information may include the number of the table item, the location of the table item, etc.

[0082] Here, since step 401 can be executed multiple times, step d can also be executed multiple times. Considering that not every decoded instruction acquired can be released, there may be a situation in which the decoded instructions acquired in the previous time or the previous times have not been released during this release process. Therefore, T can be the number of valid instructions that have not been executed in the ROB during this release process. T can be obtained by summing the number of instructions that have not been released during this release process (that is, the number of decoded instructions acquired this time) and the number of instructions that have not been released before this release process; it can also be determined by subtracting the total number of decoded instructions acquired before this release process from the number of instructions that have been released before this release process. The present disclosure does not limit this.

[0083] It can be understood that after each decoded instruction is assigned an idle table entry in a different first group, the decoded instruction will become a pending instruction after passing through the transmission queue and the execution stage. Since the release of the pending instruction needs to meet the release condition, the processor can determine the M pending instructions that meet the release condition in this release process from the L pending instructions according to the submission identifier of the table entry corresponding to the pending instruction. After determining the M pending instructions, the release order corresponding to each pending instruction can be determined according to the table entry identification information corresponding to the M pending instructions, so that the table entry corresponding to each pending instruction can be released in sequence according to the release order. In this way, the retirement of instructions can be realized in sequence in the above manner, and it is convenient to allocate idle table entries for subsequent decoded instructions.

[0084] In some embodiments, in the above process, step d, determining M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, may include: step d1, obtaining L instructions to be submitted; step d2, marking the submission identifier of the table item corresponding to each instruction to be submitted as a first value based on the table item identification information corresponding to each instruction to be submitted; step d3, determining the instructions to be submitted corresponding to multiple consecutive table items whose submission identifier is the first value as M instructions to be released.

[0085] Here, the first numerical value may be 1 or other numerical values, which is not limited in the embodiment of the present disclosure.

[0086] It can be understood that the execution stage can execute N decoding instructions in sequence. When multiple decoding instructions are executed, the processor can obtain L instructions to be submitted from the execution stage. Since each decoding instruction is assigned an idle table entry in a different first group in the distribution stage, each decoding instruction corresponds to an idle table entry. Correspondingly, each instruction to be submitted also corresponds to an entry. Then, according to the table entry identification information corresponding to each instruction to be submitted, the first group in which the table entry corresponding to the table entry identification information is located can be determined, so that the table entry identification information is compared with the table entry identification information of each table entry in the first group, so that the table entry corresponding to the table entry identification information can be determined. Based on this, the commit identifier (commit valid ID, VID) of the table entry corresponding to each instruction to be submitted is marked as a first value, which can distinguish the table entry of the instruction to be submitted from the table entries of other instructions, and determine which table entries are the table entries corresponding to the instruction to be submitted. At the same time, since the instruction release (i.e. retirement) needs to be released in sequence, the instructions to be submitted corresponding to multiple consecutive table entries with the commit identifier as the first value can be determined as M instructions to be released. Thus, the above method can determine the instructions to be released that meet the release conditions from the instructions to be submitted, and the number of table entry identification information that needs to be compared is reduced compared to the ROB implemented by the one-dimensional queue. Therefore, the above process is simple and efficient, and can also avoid errors in the instruction release process.

[0087] In some embodiments, step e, according to the table entry identification information corresponding to the M instructions to be released, sequentially releasing the table entry corresponding to each instruction to be released, may include: step e1, determining the third position indicated by the head pointer in the ROB; step e2, according to the table entry identification information corresponding to the M instructions to be released, determining the release order of the table entries corresponding to the M instructions to be released; step e3, according to the third position and the release order, releasing the table entry corresponding to the first instruction to be released among the M instructions to be released; step e4, for non-first instructions to be released, releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position. Here, 1≤j≤M-1 and j is an integer.

[0088] It can be understood that the position pointed to by the head pointer is used to identify the position of the current entry to be released. Therefore, the position of the current entry to be released in the ROB can be determined by determining the third position indicated by the head pointer in the ROB. Since the entry identification information corresponds to the instruction to be released, the entries are distributed in sequence during the distribution stage. Then, according to the entry identification information corresponding to the M instructions to be released, the release order of the entries corresponding to the M instructions to be released can be determined. Then, according to the third position and the release order, the entry corresponding to the first instruction to be released among the M instructions to be released (i.e., the entry indicated by the third position) is first released. For non-first instructions to be released, the entry of the j+1th instruction to be released indicated by the jth position after the third position can be released. In this way, the entries corresponding to the M instructions to be released can be released in sequence.

[0089] In one example, for non-first decoding instructions among M decoding instructions, the table entry of the second instruction to be released indicated by the first position after the third position can be released, the table entry of the third instruction to be released indicated by the second position after the third position can be released,..., and the table entry indicating the Mth instruction to be released at the M-1th position after the third position can be released.

[0090] In one example, if the entry identification information (such as the entry number) corresponding to M instructions to be released is increasing in sequence, and the entry numbers of the free entries allocated to these M instructions to be released in the distribution phase are also increasing in sequence, then according to the entry numbers corresponding to the M instructions to be released, the release order of the entries corresponding to the M instructions to be released can be determined as follows: the entries with smaller entry numbers are released first, and the entries with larger entry numbers are released later.

[0091] In some embodiments, in step e4 in step e, according to the table entry identification information corresponding to M instructions to be released, for instructions other than the first instruction to be released, after releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position, the above method also includes: determining the fourth position indicated by the head pointer after incrementing by M; updating the third position to the fourth position.

[0092] It can be understood that after the entry of the j+1th instruction to be released indicated by the jth position after the third position is released, the entries corresponding to the M instructions to be released are all released this time, so the third position indicated by the head pointer also needs to be updated to facilitate the release of the entries corresponding to the subsequent instructions to be released. Based on this, the head pointer is incremented by M, and the fourth position indicated by the head pointer after the increment by M can be obtained, that is: the Mth position after the third position, and then the third position is updated to the fourth position, and the position indicated by the fourth position is the position of the next releasable entry after the release of this entry. In this way, through the above-mentioned updating method, it is beneficial to the release of the next entry, and the efficiency of the entry release can be improved.

[0093] In some embodiments, in step d, before determining M instructions to be released that meet the release conditions in this release process from the L instructions to be submitted, the method further includes: determining the relationship between L and the number of groups G included in the ROB; when L exceeds G, sending a retirement suspension signal to the execution queue so that the execution queue can suspend outputting the instructions to be submitted. Here, the execution queue is used to output the instructions to be submitted.

[0094] It can be understood that the number L of instructions to be submitted is compared with the number G of groups contained in the ROB to obtain the size relationship between the two. When L exceeds G, the entry cannot be released. At this time, the processor sends a retirement pause signal to the execution queue, so that the execution queue can pause outputting instructions to be submitted after receiving the retirement pause signal. This method can avoid outputting too many instructions to be submitted, thereby avoiding the inability to retire the instructions to be submitted normally.

[0095] In some embodiments, in step d, before determining M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, the method further includes: determining the relationship between L and the number of groups G included in the ROB; when L does not exceed G, determining M instructions to be released that meet the release conditions in this release process from the L instructions to be submitted.

[0096] The above method is described below with reference to a specific example.

[0097] Figure 6 FIG. 1 is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment. Figure 6 As shown, the main Figure 4 The steps involved in the free entry allocation process in the embodiment are described in detail. The process mainly includes the following steps:

[0098] In step 601, the total number of free entries contained in the first group is determined.

[0099] In step 602, it is determined whether the total number of free entries is less than G.

[0100] If yes, go to step 603; if no, go to step 604.

[0101] In step 603, a pause signal is sent to the instruction decoding queue.

[0102] In step 604, N decoded instructions are obtained.

[0103] In step 605, the free table entry indicated by the first position is allocated to the first decoded instruction among the N decoded instructions.

[0104] In step 606, for non-first decoded instructions, the free table entry indicated by the i-th position after the first position is allocated to the i+1-th decoded instruction among the N decoded instructions.

[0105] In step 607, the second position indicated by the tail pointer after incrementing by N is determined.

[0106] In step 608, the first position is updated to the second position.

[0107] Figure 7 FIG. 1 is a flow chart showing a method for implementing a reorder cache according to an exemplary embodiment. Figure 7 As shown, the main Figure 6 The table entry release process after the free table entry allocation process in the embodiment is described, and the process mainly includes the following steps:

[0108] In step 7001, L instructions to be submitted are obtained.

[0109] In step 7002, it is determined whether L exceeds the number of groups G contained in the ROB.

[0110] If yes, execute step 7003; if no, execute step 7004.

[0111] In step 7003, a retirement pause signal is sent to the execution queue.

[0112] In step 7004, according to the entry identification information corresponding to each instruction to be submitted, the submission identification of the entry corresponding to each instruction to be submitted is marked as a first value.

[0113] In step 7005, the instructions to be submitted corresponding to a plurality of consecutive table entries whose submission identifiers are the first value are determined as M instructions to be released.

[0114] In step 7006, a third position indicated by the head pointer in the ROB is determined.

[0115] In step 7007, the release order of the entries corresponding to the M instructions to be released is determined according to the entry identification information corresponding to the M instructions to be released.

[0116] In step 7008, according to the third position and the release order, the entry corresponding to the first instruction to be released among the M instructions to be released is released.

[0117] In step 7009, for instructions other than the first instruction to be released, the entry of the j+1th instruction to be released indicated by the jth position after the third position is released.

[0118] In step 7010, the fourth position indicated by the head pointer after incrementing by M is determined.

[0119] In step 7011, the third position is updated to the fourth position.

[0120] Based on the same inventive concept, an embodiment of the present disclosure provides a device for implementing a reorder cache to execute the above-mentioned method for implementing the reorder cache. Figure 8 FIG. 1 is a block diagram of a device for implementing a reorder cache according to an exemplary embodiment. Figure 8 As shown, the device mainly includes: an acquisition module 801, configured to acquire N decoding instructions; an allocation module 802, configured to allocate a free table entry in each first group to each decoding instruction in turn; wherein the first group is a group containing free table entries in the reorder cache ROB, the number of the first groups is K, N≤K and N and K are integers greater than 1.

[0121] In some embodiments, the allocation module 802 is configured to perform the following steps: determine the first position indicated by the tail pointer in the ROB; allocate the free table entry indicated by the first position to the first decoding instruction among N decoding instructions; for non-first decoding instructions, allocate the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions; wherein 1≤i≤N-1 and i is an integer, and the free table entries indicated by the first position and the i-th position after the first position are in different first groups.

[0122] In some embodiments, the above-mentioned device also includes: a first determination module, configured to, for a non-first decoding instruction, allocate the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among N decoding instructions, and determine the second position indicated by the tail pointer after incrementing by N; a first update module, configured to update the first position to the second position.

[0123] In some embodiments, the above-mentioned device also includes: a second determination module, configured to determine the relationship between the total number of free table entries contained in the first group and the number of groups G contained in the ROB before obtaining N decoding instructions, wherein G is an integer greater than 1 and G≥K; a first sending module, configured to send a pause signal to the instruction decoding queue when the total number of free table entries is less than G, so that the instruction decoding queue can pause outputting decoding instructions; wherein the instruction decoding queue is used to output decoding instructions.

[0124] In some embodiments, the above-mentioned device also includes: a third determination module, configured to determine M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, wherein the L instructions to be submitted are instructions that have been executed among T decoded instructions, T is the total number of unreleased instructions determined in this release process, M≤L≤T, T≥N and M, L, T are all integers greater than 1; a release module, configured to release the table entries corresponding to each instruction to be released in turn according to the table entry identification information corresponding to the M instructions to be released.

[0125] In some embodiments, the third determination module is configured to perform the following steps: obtain L instructions to be submitted; mark the submission identifier of the table item corresponding to each instruction to be submitted as a first value based on the table item identification information corresponding to each instruction to be submitted; and determine the instructions to be submitted corresponding to multiple consecutive table items with the submission identifier as the first value as M instructions to be released.

[0126] In some embodiments, the release module is configured to perform the following steps: determine the third position indicated by the head pointer in the ROB; determine the release order of the table entries corresponding to the M instructions to be released based on the table entry identification information corresponding to the M instructions to be released; release the table entry corresponding to the first instruction to be released among the M instructions to be released based on the third position and the release order; for non-first instruction to be released, release the table entry of the j+1th instruction to be released indicated by the jth position after the third position; wherein 1≤j≤M-1 and j is an integer.

[0127] In some embodiments, the above-mentioned device also includes: a fourth determination module, configured to determine the fourth position indicated by the head pointer after incrementing by M after releasing the table entry of the j+1th instruction to be released indicated by the jth position after the third position for non-first instruction to be released; and a second update module, configured to update the third position to the fourth position.

[0128] In some embodiments, the above-mentioned device also includes: a fifth determination module, configured to determine the relationship between L and the number of groups G contained in the ROB before determining the M instructions to be released that meet the release conditions in this release process from the L instructions to be submitted, wherein G is an integer greater than 1 and G≥K; a second sending module, configured to send a retirement pause signal to the execution queue when L exceeds G, so that the execution queue can pause outputting the instructions to be submitted; wherein the execution queue is used to output the instructions to be submitted.

[0129] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0130] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, which can be used to implement the above-mentioned method for implementing the reordering cache. Fig. 9 1 is a block diagram of an electronic device 900 according to an exemplary embodiment. For example, the electronic device 900 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0131] Reference Fig. 9 , the electronic device 900 may include one or more of the following components: a processing component 902 , a memory 904 , a power component 906 , a multimedia component 908 , an audio component 910 , an input / output (I / O) interface 912 , a sensor component 914 , and a communication component 916 .

[0132] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with at least one of display, phone calls, data communications, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0133] The memory 904 is configured to store various types of data to support operations on the electronic device 900. Examples of such data include at least one of the following: instructions for any application or method operating on the device electronic device 900, contact data, phone book data, messages, pictures, and videos. The memory 904 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disk.

[0134] The power supply component 906 provides power to various components of the electronic device 900. The power supply component 906 may include at least one of the following: a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0135] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0136] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC), and when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 904 or sent via the communication component 916. In some embodiments, the audio component 910 also includes a speaker for outputting audio signals.

[0137] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0138] The sensor assembly 914 includes one or more sensors for providing various aspects of status assessment for the electronic device 900. For example, the sensor assembly 914 can detect the open / closed state of the electronic device 900, the relative positioning of the components, such as the display and keypad of the electronic device 900, and the sensor assembly 914 can also detect the position change of the electronic device 900 or a component in the electronic device 900, the presence or absence of contact between the user and the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and the temperature change of the electronic device 900. The sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 914 may also include a light sensor, such as a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 914 may also include, but is not limited to, at least one of the following: an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, and a temperature sensor.

[0139] The communication component 916 is configured to facilitate communication between the electronic device 900 and other devices in a wired or wireless manner. The electronic device 900 can access a wireless network based on a communication standard, such as Wi-Fi, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0140] In an exemplary embodiment, the electronic device 900 can be implemented by one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), controllers, microcontrollers, microprocessors or other electronic components.

[0141] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including executable instructions or a computer program, which can be executed by a processor 920 of the electronic device 900 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0142] A non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of a mobile terminal, enables the mobile terminal to execute any one of the above-mentioned methods for implementing the reorder cache in the embodiments of the present disclosure. For example, the method includes: obtaining N decoding instructions; sequentially allocating a free table entry in each first group to each decoding instruction; wherein the first group is a group containing free table entries in the ROB, the number of the first group is K, N≤K, and N and K are integers greater than 1.

[0143] The embodiment of the present disclosure provides a computer program product, which includes: a computer program or executable instructions, which are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or executable instructions from the computer-readable storage medium, and the processor executes the computer program or executable instructions, so that the computer device executes any one of the above-mentioned methods for implementing the reorder cache in the embodiment of the present disclosure.

[0144] Based on the same inventive concept, an embodiment of the present disclosure provides a server, which can be used to implement the above-mentioned reordering cache implementation method. Fig.10 FIG. 1 is a block diagram of a server 1000 according to an exemplary embodiment. Fig.10 , the server 1000 includes a processing component 1022, which further includes one or more processors, and a memory resource represented by a memory 1032 for storing instructions that can be executed by the processing component 1022, such as an application. The application stored in the memory 1032 may include one or more modules, each of which corresponds to a set of instructions. In addition, the processing component 1022 is configured to execute instructions to perform any of the above-mentioned methods for implementing the reorder cache. For example, the method includes: obtaining N decoded instructions; allocating a free table entry in each first group to each decoded instruction in turn; wherein the first group is a group containing free table entries in the ROB, and the number of the first groups is K, N≤K, and N and K are integers greater than 1.

[0145] The server 1000 may also include a power supply component 1026 configured to perform power management of the server 1000, a wired or wireless network interface 1050 configured to connect the server 1000 to a network, and an input / output (I / O) interface 1058. The server 1000 may operate an operating system stored in the memory 1032, such as Windows Server™, Mac OS X™, Unix™ Linux™, FreeBSD™, or the like.

[0146] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0147] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for implementing a reorder cache, characterized in that: include: Get N decoded instructions; Allocating one free table entry in each first group to each decoding instruction in turn; The first group is a group containing free entries in the reorder buffer ROB, the number of the first group is K, N≤K, and N and K are integers greater than 1.

2. The method according to claim 1, characterized in that The step of sequentially allocating an idle table entry in each first group to each decoding instruction comprises: Determining a first position indicated by a tail pointer in the ROB; Allocating the free table entry indicated by the first position to the first decoded instruction among the N decoded instructions; For a non-first decoding instruction, allocating the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among the N decoding instructions; Wherein, 1≤i≤N-1 and i is an integer, and the free table entries indicated by the first position and the i-th position after the first position are in different first groups.

3. The method according to claim 2, characterized in that After allocating the free table entry indicated by the i-th position after the first position to the i+1-th decoding instruction among the N decoding instructions for the non-first decoding instruction, the method further includes: Determine a second position indicated by the tail pointer after it is incremented by N; The first position is updated to the second position.

4. The method according to claim 1, characterized in that: Before obtaining N decoding instructions, the method further includes: Determine a relationship between the total number of free entries included in the first group and the number of groups G included in the ROB, where G is an integer greater than 1 and G≥K; When the total number of free entries is less than G, a pause signal is sent to the instruction decoding queue so that the instruction decoding queue pauses outputting decoding instructions; Wherein, the instruction decoding queue is used to output decoded instructions.

5. The method according to claim 1, characterized in that The method further comprises: Determine M instructions to be released that meet the release conditions in this release process from L instructions to be submitted, wherein the L instructions to be submitted are instructions that have been executed among T decoded instructions, T is the total number of unreleased instructions determined in the current release process, M≤L≤T, T≥N, and M, L, and T are all integers greater than 1; According to the entry identification information corresponding to the M instructions to be released, the entry corresponding to each instruction to be released is released in sequence.

6. The method according to claim 5, characterized in that The determining of M instructions to be released that meet the release conditions in the current release process from the L instructions to be submitted includes: Obtain the L instructions to be submitted; According to the table entry identification information corresponding to each instruction to be submitted, marking the submission identification of the table entry corresponding to each instruction to be submitted as a first value; The instructions to be committed corresponding to a plurality of consecutive table entries whose commit identifiers are the first value are determined as the M instructions to be released.

7. The method according to claim 5, characterized in that The step of releasing the table entry corresponding to each instruction to be released in sequence according to the table entry identification information corresponding to the M instructions to be released includes: determining a third location indicated by the head pointer in the ROB; Determine a release order of the table entries corresponding to the M instructions to be released according to the table entry identification information corresponding to the M instructions to be released; According to the third position and the release order, releasing the entry corresponding to the first instruction to be released among the M instructions to be released; For instructions other than the first instruction to be released, releasing the entry of the j+1th instruction to be released indicated by the jth position after the third position; Wherein, 1≤j≤M-1 and j is an integer.

8. The method according to claim 7, characterized in that After releasing the entry of the j+1th instruction to be released indicated by the jth position after the third position for the non-first instruction to be released, the method further includes: Determine a fourth position indicated by the head pointer after the head pointer is incremented by M; The third position is updated to the fourth position.

9. The method according to claim 5, characterized in that Before determining M instructions to be released that meet the release condition in this release process from the L instructions to be submitted, the method further includes: Determine the relationship between L and the number of groups G included in the ROB, where G is an integer greater than 1 and G ≥ K; When L exceeds G, a retirement pause signal is sent to the execution queue so that the execution queue can pause outputting instructions to be submitted; The execution queue is used to output instructions to be submitted.

10. A device for implementing a reorder cache, characterized in that: include: An acquisition module configured to acquire N decoding instructions; An allocation module configured to allocate one free table entry in each first group to each decoding instruction in turn; The first group is a group containing free entries in the reorder buffer ROB, the number of the first group is K, N≤K, and N and K are integers greater than 1.

11. An electronic device, characterized in that: include: processor; Memory for storing computer programs or instructions; The processor executes the computer program or instructions to implement the steps of the method according to any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium storing a computer program or instruction, characterized in that: When the computer program or instructions in the storage medium are executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

13. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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