Multipath parallel fast Fourier transform hardware computing architecture

Abstract

The invention discloses a multi-channel parallel fast Fourier transform hardware computing architecture, which comprises an ADC (Analog to Digital Converter) chip for converting an analog signal into a digital signal; the serial-to-parallel module is connected to the ADC chip, and the serial-to-parallel module converts the received data stream into P paths of parallel data streams; the P N-point FFT calculation cores are connected to the serial-to-parallel module, and each N-point FFT calculation core is used for receiving one path of parallel data flow and carrying out FFT calculation processing on the received data; the P rotating modules are respectively connected to one corresponding N-point FFT calculation core, and each rotating module is used for rotating the calculation result of the N-point FFT calculation core; and the P-point FFT module is connected to the plurality of rotation modules, and the P-point FFT module performs P-point FFT calculation on the rotation results of the P rotation modules and then outputs an FFT result. According to the multi-path parallel fast Fourier transform hardware computing architecture, parallel computing of multiple paths of data streams can be achieved, and the fast Fourier transform hardware computing acceleration effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of fast Fourier transform, and in particular to a hardware computing architecture of multi-channel parallel fast Fourier transform. Background Art

[0002] Fast Fourier Transform (FFT) is a common algorithm in digital signal processing. It converts signals from the time domain to the frequency domain, which is conducive to further analysis of the components and properties of the signal.

[0003] In the field of high-speed digital signal processing applications, the sampling rate of high-precision analog to digital converter (ADC) chips is extremely high, often reaching above GHz, while the internal operating frequency of the hardware computing circuit that implements digital signal processing can only reach the order of 10^2MHz. Therefore, when the ADC data collected by the high-precision ADC enters the hardware computing circuit for processing, the data is either processed at a downsampled rate or input in the form of multiple parallel data streams. However, downsampling the data is bound to cause a loss in the amount of information carried by the signal, such as bandwidth compression. When it is necessary to implement a high-precision digital signal processing algorithm, the ADC data is usually organized into multiple data streams in parallel for processing.

[0004] The existing FFT hardware computing circuit intellectual property core (IP) is designed for single-channel data stream operations. If multiple data streams want to implement FFT, they need to be converted to a single data stream before calculation. However, the computing throughput of this solution is very low. Therefore, a multi-channel parallel fast Fourier transform method is very meaningful.

[0005] The present invention realizes a multi-channel parallel, high-throughput fast Fourier transform hardware computing architecture, which can realize parallel computing of multiple data streams and achieve the fast Fourier transform hardware computing acceleration effect. Summary of the invention

[0006] The present invention provides a multi-channel parallel fast Fourier transform hardware computing architecture to solve the above-mentioned technical problems, and specifically adopts the following technical solutions:

[0007] A multi-channel parallel fast Fourier transform hardware computing architecture, comprising:

[0008] ADC chip, used to convert analog signals into digital signals;

[0009] A serial-to-parallel module, connected to the ADC chip, the serial-to-parallel module converts the received data stream into P parallel data streams;

[0010] P N-point FFT calculation cores are connected to the serial-to-parallel module, and each of the N-point FFT calculation cores is used to receive a parallel data stream and perform FFT calculation processing on the received data;

[0011] P rotation modules, each connected to a corresponding N-point FFT calculation core, each of the rotation modules being used to perform a rotation operation on a calculation result of the N-point FFT calculation core;

[0012] A P-point FFT module is connected to the plurality of rotation modules, and performs P-point FFT calculation on the rotation results of the P rotation modules and then outputs an FFT result.

[0013] Furthermore, the serial-to-parallel module converts the received data stream into P parallel data streams according to time extraction.

[0014] Furthermore, the interface of the N-point FFT calculation core is set to Pipelined Streaming form, which accepts input in the form of data stream and outputs FFT results in natural order.

[0015] Furthermore, the P-point FFT module performs a first-level data reordering and a two-level radix-2 butterfly operation on the data to output an FFT result.

[0016] Furthermore, the multi-channel parallel fast Fourier transform hardware computing architecture also includes:

[0017] a rotation factor ROM, connected to each of the rotation modules respectively, and used for inputting the rotation factor to the rotation module;

[0018] The rotation module performs a multiplication operation on a calculation result of the N-point FFT calculation kernel and a received rotation factor.

[0019] Furthermore, the multi-channel parallel fast Fourier transform hardware computing architecture also includes:

[0020] A control module is connected to the rotation factor ROM and is used to control the rotation factor ROM to output a corresponding rotation factor according to a frame index of data output by the N-point FFT calculation core in a current cycle.

[0021] Furthermore, the sampling rate of the ADC chip is 1.2 GHz, and the length of a frame of the signal to be processed is 16384 points. The serial-to-parallel module converts the received data stream into 4 parallel data streams at a rate of 300 MSPS. The 4 parallel data streams are respectively input into the N-point FFT calculation cores under the same clock domain, where N is 4096, and 4 FFT results of 4096 points are calculated.

[0022] The invention is beneficial in that it provides a multi-channel parallel fast Fourier transform hardware computing architecture, which has the advantages of multi-channel parallelism and high throughput, and can calculate FFT results in real time in the face of high-speed input data streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 It is the timing waveform diagram of data flow inside the hardware computing circuit;

[0025] Figure 2 A schematic diagram of the computing architecture when a multi-channel parallel FFT is implemented inside a hardware computing circuit;

[0026] Figure 3 A schematic diagram of a multi-channel parallel fast Fourier transform hardware computing architecture of the present invention;

[0027] Figure 4 The data butterfly operation flow chart of the 4-point FFT module;

[0028] Figure 5 This is the overall data flow diagram of FFT. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0030] Assume that the sampling rate of the ADC data is f s , the internal operating frequency of the hardware calculation circuit is f clk , and f s =Pf clk , where P∈Z + If the sampling rate is f s The number of FFT window points of the signal is The ADC data is extracted in time into P data streams for parallel processing, and the number of points in each stream is N. Let n = Pn N +n P :

[0031] x(n)=x(Pn N+n P ) N ∈[0,N-1],n P ∈[0,P-1]

[0032] Indicates the nth P The nth data stream N points.

[0033] Use the sequence number (n N ,n P ) describes x(Pn N +n P ), the timing waveform of the data flow inside the hardware computing circuit is as follows Figure 1 As shown, P data streams flow in parallel.

[0034] Since the total number of signal points N fs =P×N is a composite number, so N fs The discrete Fourier transform (DFT) of a point can be decomposed and calculated according to the Cooley-Tukey mixed basis algorithm. Let n = Pn N +n P , k = Nk P +k N , where n N ,k N ∈[0,N-1],n P ,k P ∈[0,P-1].

[0035]

[0036] Substitute n = Pn N +n P , k = Nk P +k N :

[0037]

[0038] Analyze the above formula, let can be regarded as x(Pn N +n P ) of N points. Multiply by the rotation factor get Finally got That is X' N Therefore, the process of multi-channel parallel FFT calculation can be decomposed into three steps with reference to the above algorithm: perform N-point FFT transformation on each data channel, multiply by the rotation factor, and perform P-point FFT transformation on each data channel in each cycle.

[0039]

[0040] When multi-channel parallel FFT is implemented in the hardware computing circuit, the computing architecture is as follows Figure 2 As shown. The input signal is divided into P data streams according to time extraction. Each of the P data streams is first input into an FFT calculation module of a universal serial data stream interface to perform N-point FFT calculation. The result is multiplied by the rotation factor. After P-way parallel calculation processing, the output at this time is still P data streams. The P data of each cycle of the P data stream is input into an FFT calculation module of a universal parallel data interface to perform P-point FFT calculation to obtain the calculation result in the form of P data. Therefore, the final output data is also in the form of P data streams, where the kth P The data stream is the Nkth data stream of the final FFT result. P To Nkth P +N-1 data.

[0041] Based on the above analysis, the present application proposes a multi-channel parallel fast Fourier transform hardware computing architecture, including: an ADC chip, a serial-to-parallel module, P N-point FFT computing cores, P rotation modules, a P-point FFT module, a rotation factor ROM and a control module, wherein the serial-to-parallel module, P N-point FFT computing cores, P rotation modules, a P-point FFT module, a rotation factor ROM and a control module are arranged in an FPGA.

[0042] The ADC chip is used to convert analog signals into digital signals. The serial-to-parallel module is connected to the ADC chip, and the serial-to-parallel module converts the received data stream into P parallel data streams. P N-point FFT calculation cores are connected to the serial-to-parallel module, and each N-point FFT calculation core is used to receive a parallel data stream and perform FFT calculation processing on the received data. P rotation modules are respectively connected to a corresponding N-point FFT calculation core, and each rotation module is used to perform a rotation operation on the calculation result of the N-point FFT calculation core. The P-point FFT module is connected to multiple rotation modules, and the P-point FFT module performs P-point FFT calculation on the rotation results of the P rotation modules and outputs the FFT result. The rotation factor ROM is respectively connected to each rotation module, and is used to input the rotation factor to the rotation module. The rotation module performs a multiplication operation on the calculation result of the N-point FFT calculation core and the received rotation factor. The control module is connected to the rotation factor ROM, and is used to control the rotation factor ROM to output the corresponding rotation factor according to the frame index of the data output by the N-point FFT calculation core in the current cycle.

[0043] Taking an ADC chip with a sampling rate of 1.2 GHz and a field programmable gate array (FPGA) with an operating frequency of 300 MHz as an example of computing hardware, the length of a frame of the signal to be processed is 16384 points.

[0044] The hardware computing architecture of the specific embodiment is as follows Figure 3 As shown, it includes an ADC chip, a serial-to-parallel module, four 4096-point FFT calculation cores (FFT IPs), a control module, a rotation factor ROM, four rotation modules, and a 4-point FFT module.

[0045] The calculation process of the hardware computing architecture of the specific embodiment for performing multi-channel parallel FFT is as follows:

[0046] The 1.2GSPS rate data stream is reduced to 4 parallel data streams at a rate of 300MSPS through the serial-to-parallel module and extracted in time.

[0047] The four parallel data streams are input into four FFT IPs in the same clock domain respectively, and the FFT results of 4096 points of the four data streams are calculated.

[0048] The 4-way FFT results are input into the rotation module and multiplied by the rotation factors. The rotation factors are stored in the on-chip ROM. The corresponding rotation factors for each cycle are output through the control module and provided to the rotation module.

[0049] The rotation result enters the 4-point FFT module of the parallel data interface and outputs the final result in a pipeline.

[0050] The ADC chip converts external analog signals into digital signals and provides them to the internal circuit of the FPGA for calculation. The input of the serial-to-parallel module is a single data stream with a clock frequency of 1.2GHz. The output is 4 data streams with a clock frequency of 300MHz. The FFT IP is a general-purpose IP core used to calculate FFT. Its interface is set to Pipelined Streaming. It can accept input in the form of data streams and output FFT results in natural order. The control module controls the rotation factor ROM to output the corresponding rotation factor according to the frame index of the data output by the FFT IP in the current cycle. The rotation module performs the multiplication operation of the FFT IP result and the rotation factor. The input of the 4-point FFT module is 4 data, and it outputs the FFT results of 4 points after several cycles. Figure 4 This is the data butterfly operation flow chart of the 4-point FFT module. After one level of data reordering and two levels of radix-2 butterfly operation, the 4-point FFT result is obtained.

[0051] like Figure 5As shown in the figure, it is the overall data flow diagram of FFT. Each data stream first enters the 4096-point FFT calculation core, and the output natural order result is multiplied by the rotation factor to obtain 4 intermediate result data streams. The data stream generates 4 points of data in each cycle, and a 4-point FFT is performed on the 4 points generated in each cycle to obtain 4 points of data, as shown in the figure. Figure 5 Finally, the FFT results of 16384 points are arranged in natural order as follows:

[0052] X(0,0),…,X(4096,0),X(0,1),…,X(4096,1),X(0,2),…,X(4096,2)

[0053] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A multi-channel parallel fast Fourier transform hardware computing architecture, characterized in that: Include: ADC chip, used to convert analog signals into digital signals; A serial-to-parallel module, connected to the ADC chip, the serial-to-parallel module converts the received data stream into P parallel data streams; P N-point FFT calculation cores are connected to the serial-to-parallel module, and each of the N-point FFT calculation cores is used to receive a parallel data stream and perform FFT calculation processing on the received data; P rotation modules, each connected to a corresponding N-point FFT calculation core, each of the rotation modules being used to perform a rotation operation on a calculation result of the N-point FFT calculation core; A P-point FFT module is connected to the plurality of rotation modules, and performs P-point FFT calculation on the rotation results of the P rotation modules and then outputs an FFT result.

2. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 1, characterized in that: The serial-to-parallel module converts the received data stream into P parallel data streams according to time extraction.

3. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 1, characterized in that: The interface of the N-point FFT calculation core is set to Pipelined Streaming form, which accepts input in the form of data stream and outputs FFT results in natural order.

4. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 1, characterized in that: The P-point FFT module performs a first-level data reordering and a two-level radix-2 butterfly operation on the data to output an FFT result.

5. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 1, characterized in that: The multi-channel parallel fast Fourier transform hardware computing architecture also includes: a rotation factor ROM, connected to each of the rotation modules respectively, and used for inputting the rotation factor to the rotation module; The rotation module performs a multiplication operation on a calculation result of the N-point FFT calculation kernel and a received rotation factor.

6. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 5, characterized in that: The multi-channel parallel fast Fourier transform hardware computing architecture also includes: A control module is connected to the rotation factor ROM and is used to control the rotation factor ROM to output a corresponding rotation factor according to a frame index of data output by the N-point FFT calculation core in a current cycle.

7. The multi-channel parallel fast Fourier transform hardware computing architecture according to claim 1, characterized in that: The sampling rate of the ADC chip is 1.2 GHz, and the length of one frame of the signal to be processed is 16384 points. The serial-to-parallel module converts the received data stream into 4 parallel data streams at a rate of 300 MSPS. The 4 parallel data streams are respectively input into the N-point FFT calculation cores under the same clock domain, where N is 4096, and 4 FFT results of 4096 points are calculated.

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