Embedded mainboard multi-interface data conversion device

Abstract

The invention provides a multi-interface data conversion device for an embedded mainboard, which relates to the technical field of interface data conversion, and is characterized in that a support vector machine algorithm, a dynamic signal quality detection technology and a self-adaptive signal processing technology are introduced, the quality of an input signal is evaluated in real time, and a signal processing path is dynamically adjusted according to an evaluation result; and the signal processing accuracy and response speed are improved. The adaptive signal processing module dynamically adjusts processing parameters by using error signals and input signals, so that high precision and high robustness of signal processing are realized, different signal environments can be flexibly handled, the overall performance and reliability of the system are improved, the balance between response speed and processing precision is realized, and the service life of the system is prolonged. Therefore, the overall processing capacity and flexibility of the device are improved, and a solid technical foundation is provided for efficient operation of the system.

Description

Technical Field

[0001] The invention relates to the technical field of interface data conversion, in particular to an embedded mainboard multi-interface data conversion device. Background Art

[0002] In modern embedded systems, multi-interface data conversion devices are widely used in various electronic devices and systems to process and convert input signals of different formats. However, traditional signal recognition and processing methods, such as rule-based classification and simple threshold judgment, often perform poorly in processing complex and changeable signal environments. These methods usually lack adaptive capabilities and cannot effectively cope with the diversity and dynamic changes of input signals, resulting in insufficient accuracy of signal classification and processing robustness. In addition, traditional signal processing systems are difficult to achieve dynamic detection of signal quality and adaptive adjustment of processing strategies. If a more complex signal processing method is used, it will cause a waste of computing power when the quality of the input signal is high, affecting the overall response time of the system. If a simpler signal processing method is used, it will cause a decrease in processing accuracy when the quality of the input signal is low. It is difficult to achieve a balance between response time and processing accuracy, which in turn causes a decrease in the overall performance and stability of the system.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The object of the present invention is to provide an embedded motherboard multi-interface data conversion device to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] An embedded motherboard multi-interface data conversion device, specifically comprising:

[0007] A signal recognition module, wherein the signal recognition module is electrically connected to the signal analysis module and the signal comparison module respectively, and is preset with a deep learning algorithm, and is used to receive input signals of different formats, identify and classify the input signals, and send the identified and classified input signals to the signal analysis module and the signal comparison module respectively;

[0008] A signal analysis module, which is electrically connected to the signal processing module and is preset with a detection algorithm for detecting the signal quality of the input signal and sending the input signal to different units of the signal processing module according to the detection result;

[0009] A signal processing module, the signal processing module is electrically connected to the signal output module and the signal comparison module, and is preset with different signal processing algorithms, all of which are used to filter and remove noise from the input signal to generate an output signal;

[0010] A signal comparison module, the signal comparison module is used to generate an error signal according to the input signal and the output signal, and send the error signal to the signal processing module to adjust the model parameters in the signal processing algorithm;

[0011] The signal output module is connected to the main board body signal and is used to send the output signal to the main board body for subsequent processing.

[0012] Preferably, the signal processing module includes a first processing unit and a second processing unit, the first processing unit and the second processing unit are arranged in parallel and are respectively preset with different signal processing algorithms.

[0013] Preferably, the signal comparison module has two input terminals, one of which is electrically connected to the output terminal of the signal identification module for receiving the input signal after identification and classification, and the other input terminal is electrically connected to the output terminal of the signal processing module for receiving the output signal after filtering and denoising, and the output terminal of the signal comparison module is electrically connected to the input terminal of the signal processing module for sending an error signal;

[0014] The relationship between the input signal, output signal and error signal is expressed as:

[0015] X er =X sr -X sc

[0016] Where I er ,I sr ,I sc They represent the error signal, input signal and output signal respectively.

[0017] Preferably, the deep algorithm in the signal recognition module is a support vector machine algorithm, and the logic for identifying and classifying the input signal is:

[0018] Collect sample data in various signal formats for normalization, and divide the normalized sample data into a training set and a validation set;

[0019] Construct a support vector machine algorithm model, substitute the sample data in the training set into the support vector machine algorithm model for training, and use the validation set to validate the support vector machine algorithm model. The optimization objective function of the support vector machine algorithm is expressed as:

[0020]

[0021] The constraints for optimizing the objective function in the support vector machine algorithm are:

[0022] y i (w·x i +b)≥1-ξ i

[0023] Where w represents the weight vector, C represents the penalty parameter, N represents the total number of input data, ξ i represents the slack variable, x i Represents the input data, y i represents the classification label of the input data, and b represents the bias;

[0024] The weight vector and bias are solved by the gradient descent method to generate the final support vector machine algorithm model, and the support vector machine algorithm is used to process the collected input signal. The support vector machine algorithm model is expressed as:

[0025]

[0026] in Represents a classification prediction.

[0027] Preferably, the logic for detecting the quality of the input signal is:

[0028] A high-pass filter is used to remove the DC component of the input signal, and then the input signal is normalized, and the normalized input signal is divided into M sub-signals;

[0029] Perform fast Fourier transform on each sub-signal, calculate the power spectrum density of each sub-signal, calculate the total power and noise power of the input signal, and generate the signal-to-noise ratio of the input signal. The calculation methods are as follows:

[0030]

[0031] Where X(f) represents the Fourier transform value of the input signal, P(f) represents the power spectrum density at frequency f, and P n , P s represent the noise power and total power respectively, f n (min), f n (max) represent the preset lower and upper limits of noise frequency, respectively, f s (min), f s (max) represent the preset lower and upper limits of the input signal frequency, respectively, and S represents the signal-to-noise ratio of the input signal;

[0032] When the signal-to-noise ratio of the input signal is greater than the preset signal-to-noise threshold, the input signal is considered to have poor quality;

[0033] When the signal-to-noise ratio of the input signal is less than or equal to a preset signal-to-noise threshold, the input signal is considered to have good quality.

[0034] Preferably, when the input signal quality is poor, the input signal is sent to the first processing unit, and when the data signal quality is good, the input signal is sent to the second processing unit.

[0035] Preferably, the calculation method of the signal processing algorithm in the first processing unit is:

[0036]

[0037] Where X sc (n) represents the nth output signal, represents the vector representation of the nth input signal, Represents the coefficient vector of the nth iteration of the filter, where the iteration method of the coefficient vector is:

[0038]

[0039] Where μ(n) represents the step coefficient at the nth iteration, which is calculated from the error signal and the input signal, and μ∈(0,1), e(n-1) represents the error of the n-1th output signal, and the calculation methods are:

[0040]

[0041] e(n-1)=X sc (n-1)-X0

[0042] Where X er (n-1) represents the n-1th error signal, X sr (n-1) represents the n-1th input signal, and X0 represents the preset standard signal.

[0043] Preferably, the calculation method of the signal processing algorithm in the second processing unit is:

[0044]

[0045] Where P(n) represents the length of the observation window corresponding to the nth output signal, which is calculated from the error signal and the input signal as follows:

[0046]

[0047] in Indicates rounding up the number in the brackets.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] The present invention solves the problem that traditional methods perform poorly in complex signal environments by introducing support vector machine algorithms, dynamic signal quality detection and adaptive signal processing technology. The support vector machine algorithm can significantly improve the accuracy of input signal recognition and classification, ensuring that the subsequent processing module receives accurately classified signals. The signal quality detection module evaluates the quality of the input signal in real time through high-pass filtering, fast Fourier transform and signal-to-noise ratio calculation, and dynamically adjusts the signal processing path according to the evaluation results, thereby improving the accuracy and response speed of signal processing. The adaptive signal processing module uses error signals and input signals to dynamically adjust processing parameters, achieves high accuracy and high robustness of signal processing, can flexibly respond to different signal environments, achieves a balance between response speed and processing accuracy, improves the overall performance and reliability of the system, thereby enhancing the overall processing capacity and flexibility of the device, and provides a solid technical foundation for the efficient operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0052] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] Example:

[0054] See also Figure 1 , the present invention provides a technical solution:

[0055] An embedded mainboard multi-interface data conversion device specifically comprises: a signal identification module, a signal analysis module, a signal processing module, a signal comparison module, and a signal output module.

[0056] The signal recognition module is electrically connected to the signal analysis module and the signal comparison module respectively, and is preset with a deep learning algorithm. It adopts a high-performance microcontroller STM32F407VG equipped with a deep learning accelerator K210 to receive input signals of different formats, identify and classify the input signals, and send the identified and classified input signals to the signal analysis module and the signal comparison module respectively.

[0057] The signal analysis module is electrically connected to the signal processing module and has a preset detection algorithm. It uses a high-performance microcontroller STM32F407VG equipped with a high-pass filter MAX7403 to detect the signal quality of the input signal and send the input signal to different units of the signal processing module according to the detection results.

[0058] The signal processing module is electrically connected to the signal output module and the signal comparison module, and includes a first processing unit and a second processing unit. The first processing unit and the second processing unit are arranged in parallel and are respectively preset with different signal processing algorithms. Both use the TMS320C6748 series digital signal processor to filter and denoise the input signal to generate an output signal.

[0059] The signal comparison module adopts a 74LS83 series digital subtractor, which is used to generate an error signal according to the input signal and the output signal, and send the error signal to the signal processing module to adjust the model parameters in the signal processing algorithm. The signal comparison module has two input terminals, one of which is electrically connected to the output terminal of the signal recognition module for receiving the input signal after recognition and classification, and the other input terminal is electrically connected to the output terminal of the signal processing module for receiving the output signal after filtering and denoising. The output terminal of the signal comparison module is electrically connected to the input terminal of the signal processing module for sending the error signal.

[0060] The signal output module is connected to the main board signal. A Bluetooth module can be used for remote data interaction, or a data interface can be used for data interaction in the form of a cable to send the output signal to the main board for subsequent processing.

[0061] By setting up a signal analysis module to detect the signal quality of the input signal and sending the input signal to different processing units for processing according to the different signal qualities, different denoising strategies can be provided for the system, and the processing requirements of different signals can be flexibly responded to, so as to improve the overall processing capability and flexibility of the system. By setting up a signal comparison module to form self-feedback, real-time error feedback and adjustment can be achieved, and dynamic signal changes can be better responded to, so as to improve the performance and accuracy of the overall system.

[0062] The relationship between the input signal, output signal, and error signal is expressed as:

[0063] X er =X sr -X sc

[0064] Where I er ,I sr ,I sc They represent the error signal, input signal and output signal respectively.

[0065] The deep algorithm in the signal recognition module is the support vector machine algorithm, and the logic for identifying and classifying the input signal is:

[0066] Collect sample data in various signal formats for normalization, and divide the normalized sample data into a training set and a validation set;

[0067] Construct a support vector machine algorithm model, substitute the sample data in the training set into the support vector machine algorithm model for training, and use the validation set to validate the support vector machine algorithm model. The optimization objective function of the support vector machine algorithm is expressed as:

[0068]

[0069] Express Minimize to find a hyperplane with the largest distance from the nearest data point, while penalizing misclassified points. That is, the corresponding penalty term, which is calculated by penalizing the number of misclassified points (that is, the slack variable ξ i ), the degree of misclassification can be controlled.

[0070] The constraints for optimizing the objective function in the support vector machine algorithm are:

[0071] y i (w·x i +b)≥1-ξ i

[0072] This constraint states that for each data point (x i ,y i ), the output of the classifier w·x i +b must satisfy its label y i , minus the slack variables, specifically:

[0073] If a data point is correctly classified and lies outside the interval, then ξ i =0;

[0074] If a data point is misclassified or lies within the interval, then ξ i >0.

[0075] Where w represents the weight vector, C represents the penalty parameter, N represents the total number of input data, ξ i represents the slack variable, x i Represents the input data, y i represents the classification label of the input data, and b represents the bias.

[0076] Finally, the gradient descent method is used to solve the weight vector and bias to generate the final support vector machine algorithm model, and the support vector machine algorithm is used to process the collected input signal. The support vector machine algorithm model is expressed as:

[0077]

[0078] in Represents a classification prediction.

[0079] In this step, by collecting sample data in various signal formats and normalizing them, and using SVM to classify the input signals, the accuracy of signal recognition can be significantly improved, ensuring that the subsequent processing modules receive accurately classified signals. Compared with traditional signal recognition methods (rule classification, threshold judgment, etc.), it can significantly improve the accuracy and robustness of signal classification, enhance the system's adaptability and overall performance, provide a high-quality data foundation for subsequent signal analysis, processing, comparison and output modules, and promote the efficient operation of the entire embedded motherboard multi-interface data conversion device.

[0080] The logic for detecting the quality of the input signal is:

[0081] A high-pass filter is used to remove the DC component of the input signal, and then the input signal is normalized, and the normalized input signal is divided into M sub-signals;

[0082] Perform fast Fourier transform on each sub-signal, calculate the power spectrum density of each sub-signal, calculate the total power and noise power of the input signal, and generate the signal-to-noise ratio of the input signal. The calculation methods are as follows:

[0083]

[0084] Where X(f) represents the Fourier transform value of the input signal, P(f) represents the power spectrum density at frequency f, and P n , P s represent the noise power and total power respectively, f n (min), f n (max) represent the preset lower and upper limits of noise frequency, respectively, f s (min), f s (max) represent the preset lower and upper limits of the input signal frequency, respectively, and S represents the signal-to-noise ratio of the input signal;

[0085] When the signal-to-noise ratio of the input signal is greater than the preset signal-to-noise threshold, the input signal is considered to have poor quality;

[0086] When the signal-to-noise ratio of the input signal is less than or equal to a preset signal-to-noise threshold, the input signal is considered to have good quality.

[0087] When the quality of the input signal is poor, the input signal is sent to the first processing unit, and when the quality of the data signal is good, the input signal is sent to the second processing unit.

[0088] In this step, the signal quality of the input signal is detected in advance, and the subsequent signal propagation direction can be dynamically adjusted. That is, when the signal quality is poor, the input signal is sent to the first processing unit for processing to improve the precision and accuracy of signal processing. When the signal quality is good, the input signal is sent to the second processing unit for processing to reduce the overall computing resources of the system and improve the response speed. Through this dynamic adjustment processing strategy, the overall performance and reliability of the system can be improved, thereby effectively promoting the efficient operation of the entire embedded motherboard multi-interface data conversion device.

[0089] The calculation method of the signal processing algorithm in the first processing unit is:

[0090]

[0091] Where X sc (n) represents the nth output signal, represents the vector representation of the nth input signal, Represents the coefficient vector of the nth iteration of the filter, where the iteration method of the coefficient vector is:

[0092]

[0093] Where μ(n) represents the step coefficient at the nth iteration, which is calculated from the error signal and the input signal, and μ∈(0,1), e(n-1) represents the error of the n-1th output signal, and the calculation methods are:

[0094]

[0095] e(n-1)=X sc (n-1)-X0

[0096] Where X er (n-1) represents the n-1th error signal, X sr (n-1) represents the n-1th input signal, and X0 represents the preset standard signal.

[0097] In this model, the step size parameter is used to control the amplitude of the coefficient adjustment in each iteration. The larger the value of the step size parameter, the faster the adjustment, but it may cause the model to be unstable; the smaller the value of the step size parameter, the slower the adjustment, but the better the stability. Therefore, the step size parameter is dynamically adjusted through the error signal and the input signal. It can be understood that the error signal is the difference between the output signal and the input signal, which reflects the change in the input signal after processing. The larger the change, the step size parameter needs to be increased to increase the adjustment speed of the model. On the contrary, the smaller the change, the step size parameter needs to be reduced to improve the stability of the model, thereby achieving a balance between adjustment speed and stability, reducing the occurrence of unexpected situations such as slow model response speed and model collapse, and improving the accuracy and robustness of the model. .

[0098] The calculation method of the signal processing algorithm in the second processing unit is:

[0099]

[0100] Where P(n) represents the length of the observation window corresponding to the nth output signal, which is calculated from the error signal and the input signal as follows:

[0101]

[0102] in Indicates rounding up the number in the brackets.

[0103] Similarly, the length of the observation window is also determined by the error signal and the input signal. The larger the change, the larger the observation window needs to be to analyze more data to improve the accuracy of the model. The smaller the change, the smaller the observation window needs to be to increase the response speed of the model and achieve a balance between accuracy and response speed.

[0104] By adopting adaptive filters and window averaging-based signal processing algorithms in the first processing unit and the second processing unit, and dynamically adjusting the step parameters and the observation window length using the error signal and the input signal, the accuracy, response speed and robustness of signal processing can be significantly improved, which helps to better cope with complex and changeable signal environments and provides a solid foundation for improving the performance of the entire embedded motherboard multi-interface data conversion device.

[0105] In summary, the present invention solves the problem that traditional methods perform poorly in complex signal environments by introducing support vector machine algorithms, dynamic signal quality detection and adaptive signal processing technology. The support vector machine algorithm can significantly improve the accuracy of input signal recognition and classification, ensuring that the subsequent processing module receives accurately classified signals. The signal quality detection module evaluates the quality of the input signal in real time through high-pass filtering, fast Fourier transform and signal-to-noise ratio calculation, and dynamically adjusts the signal processing path according to the evaluation results, thereby improving the accuracy and response speed of signal processing. The adaptive signal processing module uses error signals and input signals to dynamically adjust processing parameters, achieves high precision and high robustness of signal processing, can flexibly respond to different signal environments, improves the overall performance and reliability of the system, thereby enhancing the overall processing capacity and flexibility of the device, and provides a solid technical foundation for the efficient operation of the system.

[0106] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0107] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0108] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0109] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. An embedded motherboard multi-interface data conversion device, characterized in that: Specifically include: A signal recognition module, wherein the signal recognition module is electrically connected to the signal analysis module and the signal comparison module respectively, and is preset with a deep learning algorithm, and is used to receive input signals of different formats, identify and classify the input signals, and send the identified and classified input signals to the signal analysis module and the signal comparison module respectively; A signal analysis module, which is electrically connected to the signal processing module and is preset with a detection algorithm for detecting the signal quality of the input signal and sending the input signal to different units of the signal processing module according to the detection result; A signal processing module, the signal processing module is electrically connected to the signal output module and the signal comparison module, and is preset with different signal processing algorithms, all of which are used to filter and remove noise from the input signal to generate an output signal; A signal comparison module, the signal comparison module is used to generate an error signal according to the input signal and the output signal, and send the error signal to the signal processing module to adjust the model parameters in the signal processing algorithm; The signal output module is connected to the main board body signal and is used to send the output signal to the main board body for subsequent processing.

2. The embedded motherboard multi-interface data conversion device according to claim 1, characterized in that: The signal processing module includes a first processing unit and a second processing unit. The first processing unit and the second processing unit are arranged in parallel and are respectively preset with different signal processing algorithms.

3. The embedded motherboard multi-interface data conversion device according to claim 2, characterized in that: The signal comparison module has two input terminals, one of which is electrically connected to the output terminal of the signal identification module for receiving the input signal after identification and classification, and the other input terminal is electrically connected to the output terminal of the signal processing module for receiving the output signal after filtering and denoising, and the output terminal of the signal comparison module is electrically connected to the input terminal of the signal processing module for sending an error signal; The relationship between the input signal, output signal and error signal is expressed as: X er =X sr -X sc Where I er ,I sr ,I sc They represent the error signal, input signal and output signal respectively.

4. The embedded motherboard multi-interface data conversion device according to claim 1, characterized in that: The deep algorithm in the signal recognition module is a support vector machine algorithm, and the logic for identifying and classifying the input signal is: Collect sample data in various signal formats for normalization, and divide the normalized sample data into a training set and a validation set; Construct a support vector machine algorithm model, substitute the sample data in the training set into the support vector machine algorithm model for training, and use the validation set to validate the support vector machine algorithm model. The optimization objective function of the support vector machine algorithm is expressed as: The constraints for optimizing the objective function in the support vector machine algorithm are: y i (w·x i +b) ≥1−ξ i Where w represents the weight vector, C represents the penalty parameter, N represents the total number of input data, ξ i represents the slack variable, x i Represents input data, y i represents the classification label of the input data, and b represents the bias; The weight vector and bias are solved by the gradient descent method to generate the final support vector machine algorithm model, and the support vector machine algorithm is used to process the collected input signal. The support vector machine algorithm model is expressed as: in Represents a classification prediction.

5. The embedded motherboard multi-interface data conversion device according to claim 2, characterized in that: The logic for detecting the quality of the input signal is: A high-pass filter is used to remove the DC component of the input signal, and then the input signal is normalized, and the normalized input signal is divided into M sub-signals; Perform fast Fourier transform on each sub-signal, calculate the power spectrum density of each sub-signal, calculate the total power and noise power of the input signal, and generate the signal-to-noise ratio of the input signal. The calculation methods are as follows: Where X(f) represents the Fourier transform value of the input signal, P(f) represents the power spectrum density at frequency f, and P n , P s represent the noise power and total power respectively, f n (min), f n (max) represent the preset lower and upper limits of noise frequency, respectively, f s (min), f s (max) represent the preset lower and upper limits of the input signal frequency, respectively, and S represents the signal-to-noise ratio of the input signal; When the signal-to-noise ratio of the input signal is greater than the preset signal-to-noise threshold, the input signal is considered to have poor quality; When the signal-to-noise ratio of the input signal is less than or equal to a preset signal-to-noise threshold, the input signal is considered to have good quality.

6. The embedded motherboard multi-interface data conversion device according to claim 5, characterized in that: When the quality of the input signal is poor, the input signal is sent to the first processing unit, and when the quality of the data signal is good, the input signal is sent to the second processing unit.

7. The embedded motherboard multi-interface data conversion device according to claim 6, characterized in that: The calculation method of the signal processing algorithm in the first processing unit is: Where X sc (n) represents the nth output signal, represents the vector representation of the nth input signal, Represents the coefficient vector of the nth iteration of the filter, where the iteration method of the coefficient vector is: Where μ(n) represents the step coefficient at the nth iteration, which is calculated from the error signal and the input signal, and μ∈(0,1), e(n-1) represents the error of the n-1th output signal, and the calculation methods are: e(n-1)=X sc (n-1)-X0 Where X er (n-1) represents the n-1th error signal, X sr (n)-1) represents the n-1th input signal, and X0 represents the preset standard signal.

8. The embedded motherboard multi-interface data conversion device according to claim 7, characterized in that: The calculation method of the signal processing algorithm in the second processing unit is: Where P(n) represents the length of the observation window corresponding to the nth output signal, which is calculated from the error signal and the input signal as follows: in Indicates rounding up the number in the brackets.

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