Method, electronic device and storage medium for semiconductor process device simulation

Abstract

Embodiments of the present disclosure relate to methods, electronic devices, and storage media for simulating semiconductor process devices. A method for simulating semiconductor process devices, wherein the semiconductor process device includes a groove, and the method includes: determining an initial model of an initial structure of the semiconductor process device; determining the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a groove model based on the key dimensions of the groove formed by etching the initial structure and the position coordinates of the predetermined point; and forming a semiconductor process device model based on the initial model and the groove model. The technical solution disclosed in the present disclosure can effectively solve the problem of morphological distortion of the groove in TCAD three-dimensional process simulation, and further improve the accuracy of variable process simulation results.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuits, and more particularly, to methods, electronic devices, and storage media for semiconductor process device simulation. Background Art

[0002] In the field of semiconductor manufacturing technology, selective epitaxial silicon germanium (SiGe) has been widely used in the source / drain regions of P-channel metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) transistors to induce appropriate strain by applying compressive stress in the channel direction, thereby reducing the effective mass and scattering probability of holes in the channel direction, enhancing carrier mobility, and improving the driving current of PMOS devices.

[0003] The strain induced by the selective epitaxial embedded SiGe strain technology depends on the initial trench shape. The sigma-type trench shape is the key factor affecting the compressive stress applied by SiGe to the channel direction and inducing the appropriate strain size.

[0004] In traditional semiconductor process device simulation (Tecnology Computer Aided Design, TCAD for short), the three-dimensional structure of the selective epitaxial embedded silicon germanium trench obtained is still quite different from the actual structure. Summary of the invention

[0005] According to an example embodiment of the present disclosure, a solution for semiconductor process device simulation is provided to at least partially overcome the above or other potential drawbacks.

[0006] According to one aspect of the present disclosure, a method for simulating a semiconductor process device is provided, wherein the semiconductor process device includes a groove, and the method includes: determining an initial model of an initial structure of the semiconductor process device; determining the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a groove model based on a critical dimension of the groove formed by etching the initial structure and the position coordinates of the predetermined point; and forming a semiconductor process device model based on the initial model and the groove model.

[0007] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, and when the instructions are executed by the processor, the device performs an action, the action including: determining an initial model of an initial structure of a semiconductor process device; determining the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a groove model based on the critical dimensions of a groove formed by etching the initial structure and the position coordinates of the predetermined point; and forming a semiconductor process device model based on the initial model and the groove model.

[0008] In some embodiments, the semiconductor process device also includes an active area, a gate, and a shallow trench isolation area, and wherein determining an initial model of an initial structure of the semiconductor process device includes: determining the layout and related dimensions of the active area, the gate, and the shallow trench isolation area; and determining the initial model based on the layout and related dimensions.

[0009] In some embodiments, the position coordinates of the predetermined point include at least the following items: the coordinates of a key point of the active area adjacent to the shallow trench isolation area on the substrate surface of the semiconductor process device; and the coordinates of a key point of the opening position of the trench on the substrate surface of the semiconductor process device.

[0010] In some embodiments, determining a groove model based on a critical dimension of a groove formed by etching an initial structure and a position coordinate of a predetermined point includes: determining a polyhedron model of the groove based on the shape of the groove formed by etching the initial structure; determining the coordinates of each vertex of the polyhedron model based on the position coordinates of a predetermined point on the surface and the critical dimension of the groove; and determining each face of the groove model based on the coordinates of each vertex to form the groove model.

[0011] In some embodiments, each vertex of the polyhedron is respectively located on a top surface, a bottom surface, and a first plane and a second plane between the top surface and the bottom surface which are parallel to each other, wherein determining the coordinates of each vertex of the polyhedron model includes: based on the relative position relationship between each vertex and a predetermined point on the surface and a critical dimension of the groove, determining the coordinates of each vertex on the top surface, the bottom surface, and the first plane and the second plane.

[0012] In some embodiments, the trench is a selective embedded silicon germanium trench with a sigma-type profile, and the trench is located between two gates or between a shallow trench isolation region and a gate.

[0013] In some embodiments, when the trench is located between the shallow trench isolation region and the gate, the method further includes: considering the trench as a sigma-type trench formed with the opening width of the trench between the gates as an initial condition to determine the coordinates of each vertex of the polyhedron model.

[0014] In some embodiments, the coordinates of each vertex are determined based on at least one of the following: active area size; width of the silicon opening at the top of the sigma-type trench; width of the sharp corners at both ends of the middle of the sigma-type trench; depth from the sharp corner in the middle of the sigma-type trench to the silicon surface; critical dimension of the bottom of the sigma-type trench parallel to the X-axis; critical dimension of the bottom of the sigma-type trench parallel to the Y-axis; depth of the sigma-type trench; depth of silicon loss caused by the previous layer process; opening width between gates; and inclination angle of the active area sidewall.

[0015] In some embodiments, forming the semiconductor process device model based on the initial model and the trench model includes: implanting the trench model into the initial model through Boolean operation to form the semiconductor process device model.

[0016] In some embodiments, implanting the trench model into the initial model through Boolean operation includes: deleting a region corresponding to the trench model at a position where the trench is predetermined to be formed in the initial model to generate a cavity; and implanting the trench model into the cavity to form a semiconductor process device model.

[0017] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0018] It will be understood from the following description that the technical solution disclosed in the present invention can effectively solve the problem of morphological distortion of grooves in TCAD three-dimensional process simulation and further improve the accuracy of variable process simulation results.

[0019] The disclosure section is provided to introduce a selection of concepts in a simplified form, which will be further described in the detailed description below. The disclosure section is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a conventional selective epitaxial embedded silicon germanium trench in TCAD three-dimensional process simulation is shown;

[0021] Figure 2 A schematic diagram of a three-dimensional structure of a selective epitaxial embedded silicon germanium trench located between two gates is shown;

[0022] Figure 3 A schematic diagram of a three-dimensional structure of a selective epitaxial embedded silicon germanium trench between a gate and an STI is shown;

[0023] Figure 4 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented;

[0024] Figure 5 A flow chart showing a method for semiconductor process device simulation according to some embodiments of the present disclosure is shown;

[0025] Figure 6 A schematic diagram showing forming an embedded silicon germanium trench according to some embodiments of the present disclosure is shown;

[0026] Figure 7 shows a top view of an embedded silicon germanium trench according to some embodiments of the present disclosure;

[0027] Figure 8 A cross-sectional view of an initial structural model of an embedded silicon germanium trench according to some embodiments of the present disclosure is shown;

[0028] Fig. 9 A schematic diagram showing an active area sidewall of a silicon germanium trench according to some embodiments of the present disclosure;

[0029] Fig.10 shows a cross-sectional view of an embedded silicon germanium trench according to some embodiments of the present disclosure;

[0030] Fig.11 shows a cross-sectional view of an embedded silicon germanium trench according to other embodiments of the present disclosure;

[0031] Fig.12 A schematic diagram showing a polyhedral model of a silicon germanium trench according to some embodiments of the present disclosure is shown;

[0032] Fig.13 Schematic diagrams showing polyhedral models of silicon germanium trenches according to other embodiments of the present disclosure;

[0033] Fig.14 A schematic diagram showing the bottom of a silicon germanium trench according to some embodiments of the present disclosure;

[0034] Fig.15 A schematic diagram showing a modeling process of a silicon germanium trench according to some embodiments of the present disclosure;

[0035] Fig.16 A schematic diagram showing a final model of a silicon germanium trench according to some embodiments of the present disclosure;

[0036] Fig.17 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown.

[0037] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0038] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals may be used in the figures where feasible, and similar or identical reference numerals may represent similar or identical functions. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods described herein may be adopted without departing from the principles of the present disclosure described herein.

[0039] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0040] As mentioned above, in the current TCAD three-dimensional process device simulation, there is still a big difference between the three-dimensional structure and the actual structure. Specifically, in the traditional scheme, the three-dimensional structure of the selective epitaxial embedded silicon germanium trench is usually in the X, Y plane with a sigma shape as a section, extending along the Z axis to obtain a three-dimensional structure, and its structure is simple. However, this method cannot obtain the same three-dimensional structure as the actual process production. Because the existing process structure modeling is implemented by the point drawing method. The point drawing method is to determine the coordinates of each vertex of the sigma profile morphology based on the key dimensions of the sigma (sigma) morphology. The point drawing method generally draws a section and then extends along the Z axis to obtain a three-dimensional structure. Special shapes such as the bottom side cannot be quantitatively described, which leads to distortion of subsequent stress and strain-related process simulation results. It can be seen that in the current TCAD three-dimensional process simulation, the modeling method for accurately forming the same three-dimensional structure as the actual process is still missing.

[0041] Figure 1 The figure shows a schematic diagram of a conventional selective epitaxial embedded silicon germanium trench in TCAD three-dimensional process simulation. Specifically, Figure 1 A in the figure is a three-dimensional structure diagram of a selective epitaxial embedded silicon germanium trench. Figure 1 B in Figure 1 A perspective view of the selective epitaxial embedded SiGe trench shown in Figure A.

[0042] Figure 2 A schematic diagram of a three-dimensional structure of a selectively epitaxial embedded silicon germanium trench located between two gates is shown. Figure 3 The schematic diagram of the selective epitaxial embedded SiGe trench 3D structure between the gate and the shallow trench isolation (STI) region is shown. Depending on the layout, there are two types of boundary conditions in the epitaxial embedded SiGe trench structure. One is Figure 2 The embedded silicon germanium trench between the gate and the gate is shown in FIG. Figure 2 A in FIG. 1 is a three-dimensional structure diagram of the embedded silicon germanium trench. Figure 2 B in FIG. 1 is a perspective view of the silicon germanium trench. Figure 3 The embedded silicon germanium trench described in is located between the STI and the gate. Figure 3 A in FIG. 1 is a three-dimensional structure diagram of the embedded silicon germanium trench. Figure 3 B in FIG. 1 is a perspective view of the silicon germanium trench.

[0043] The above three-dimensional structure obtained in the traditional solution is significantly different from the actual structure. Therefore, in TCAD three-dimensional process simulation, it is necessary to improve the accuracy of the trench structure modeling.

[0044] In view of this, the present disclosure provides an improved solution.

[0045] The embodiment of the present disclosure provides an improved method for semiconductor process device simulation. The method includes: determining an initial model of an initial structure of a semiconductor process device; determining the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a groove model based on the critical dimensions of a groove formed by etching the initial structure and the position coordinates of the predetermined point; and forming a semiconductor process device model based on the initial model and the groove model.

[0046] The embodiments of the present disclosure can perform three-dimensional structural modeling on the groove structure produced based on the actual process (different boundary types, groove sidewalls and bottom morphologies), which can effectively solve the morphology distortion problem in TCAD three-dimensional process simulation and improve the accuracy of simulation results.

[0047] The following will refer to the attached Figures 4 to 17 The embodiments of the present disclosure are described in detail.

[0048] Figure 4 Schematic diagram of an example environment 400 in which embodiments according to the present disclosure can be implemented. Figure 4 As shown, the example environment 400 includes a computing device 410 and a client 420 .

[0049] In some embodiments, the computing device 410 may interact with the client 420. For example, the computing device 410 may receive an input message from the client 420 and output a feedback message to the client 420. In some embodiments, the input message from the client 420 may be data of a semiconductor process device to be simulated. The computing device 410 may perform corresponding mathematical operations on the input data and output corresponding operation results to the client 420.

[0050] In some embodiments, computing device 410 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0051] It should be understood that the structure and function of the example environment 400 are described for exemplary purposes only and are not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. The environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0052] In order to explain the principle of the present disclosure more clearly, the following will refer to Figure 5 Let's describe it in more detail.

[0053] Figure 5 A flow chart of a method 500 for semiconductor process device simulation according to some embodiments of the present disclosure is shown.

[0054] At block 502 , an initial model of an initial structure of a semiconductor process device is determined.

[0055] In some embodiments, the basic structure and size of a semiconductor process device (hereinafter referred to as a device for ease of description) may be determined to construct an initial structural model of the device. In this process, the size of the area to be simulated and its boundary range may be determined first, and then the relevant size may be determined.

[0056] In some embodiments of the present disclosure, an embedded silicon germanium trench in a PMOS transistor is used as an example for description. It should be understood that the embodiments of the present disclosure are not limited thereto, and can also be applied to other devices with similar structures.

[0057] For the embedded SiGe trench, there are two types of boundary cases depending on the layout: (1) the embedded SiGe trench is located between the STI and the gate; (2) the embedded SiGe trench is located between the gate and the gate. The corresponding models can be constructed based on their respective basic structures and their sizes.

[0058] In some embodiments of the present disclosure, the PMOS transistor further includes an active region, a gate, and a shallow trench isolation region. Determining an initial model of an initial structure of a semiconductor process device may include: determining a layout and related dimensions of the active region, the gate, and the shallow trench isolation region; and determining the initial model based on the layout and related dimensions.

[0059] In some embodiments, a conventional method can be used to construct an initial model of the device. In some embodiments, a known initial model can also be used.

[0060] Combine the following Figure 6 The basic process of forming an embedded SiGe trench is introduced. Figure 6 FIG. 2 shows a schematic diagram of forming an embedded silicon germanium trench according to some embodiments of the present disclosure. Figure 6 As shown, in the initial structure of the device on the far left, a gate 604 of polysilicon material is formed on a substrate 602, and a barrier layer (or spacer layer) 606 is coated on the outside of the gate 604. The barrier layer 606 is dry-etched to obtain the initial groove 608 shown in the middle figure. The initial groove 608 is wet-etched to obtain the groove 610 shown in the right figure. The groove 610 is filled with silicon germanium in a subsequent step, that is, an embedded silicon germanium groove is formed. The embedded silicon germanium groove can introduce compressive stress in the channel. Specifically, the lattice constant inside the groove is different from the lattice constant of the surrounding area, and the silicon germanium material will generate compressive stress on the surrounding area, thereby improving the mobility of electrons, thereby achieving the purpose of increasing current.

[0061] Back to Figure 5 Continuing the description, at block 504 , the position coordinates of a predetermined point on the surface of the semiconductor process device are determined based on the initial model.

[0062] There are contact points between different materials in semiconductor devices. These contact points can be used to determine the coordinates of some key points. For this reason, when simulating in process simulation software, the position coordinates of each point can be determined.

[0063] In some embodiments, the position coordinates of the key point on the top plane may be determined based on the position coordinates of the predetermined point on the surface, the opening width between the gates, and the upper silicon opening width of the sigma trench.

[0064] In some embodiments, the position coordinates of the predetermined point may include at least the following items: the coordinates of a key point of the active area adjacent to the shallow trench isolation area on the substrate surface of the semiconductor process device; and the coordinates of a key point of the opening position of the trench on the substrate surface of the semiconductor process device.

[0065] Refer to the following Figure 7 Give a description. Figure 7 A top view of an embedded silicon germanium trench according to some embodiments of the present disclosure is shown. Figure 7 The boxes in the upper left corner with colors stacked from light to dark show silicon dioxide, silicon, polysilicon, and spacer layers, which correspond to Figure 7 The materials have corresponding colors in the middle, for example, the lightest color is silicon dioxide and the darkest color is the spacer layer. Figure 7 The device shown has a substrate composed of silicon material. Figure 7 The two gates 702 of polysilicon material are included, and a trench opening is formed between the two gates. The left dotted line box in the figure represents the first type (type A) of embedded silicon germanium trenches, that is, the embedded silicon germanium trenches located between the STI and the gate mentioned above; the right dotted line box represents the second type (type B) of embedded silicon germanium trenches, that is, the embedded silicon germanium trenches located between the gate and the gate mentioned above. The active area (Active Area, referred to as AA) is shown in the left dotted line box. The width of the active area is AA_Width (that is, the critical dimension of AA along the Y direction), and the length A of the active area is A_Length. The two sides of the gate 702 are spacers. The part of the active area exposed on the substrate surface is rectangular, and its four vertices are O1, O2, O3 and O4. Between the two gates 702, the four vertices of the opening position of the trench adjacent to the gate are O5, O6, O7 and O8. Points O1 to O8 can be called key points on the substrate surface. Figure 7 The active area on the right side is similar to the part in the dashed box on the left side, both of which belong to type A, that is, an embedded silicon germanium trench model between the STI and the gate, where AA_Length_2 is the length of the active area on the right side.

[0066] Refer to the following Figure 8 Give a description. Figure 8 A cross-sectional view of an initial structural model of an embedded silicon germanium trench structure according to some embodiments of the present disclosure is shown. In the initial structural model, the substrate is silicon. STI is shown, i.e., the silicon dioxide portion in the figure. A gate of polysilicon material is provided on the surface of the substrate, and spacer layers are formed on both sides of the gate. Figure 8 The initial structure model shown determines the coordinate values ​​of specific positions of the initial structure. Figure 8 As shown, it is assumed that the silicon dioxide in the STI is at the same level as the silicon (this may be slightly different in reality, but it does not affect the results here). Figure 8 The position coordinates Oi (XOi, YOi, ZOi) of the key points on the silicon surface of the initial structure are shown: O1, O2, O3, O4, O5, O6, O7, O8. The position coordinates of these key points on the silicon surface of the initial structure can be determined based on the initial structure and size parameters. The position coordinates of these key points can be used to subsequently calculate the vertex coordinates of the groove structure model. This is further described later.

[0067] At block 506 , a trench model is determined based on critical dimensions of the trench formed by etching the initial structure and position coordinates of the predetermined points.

[0068] In some embodiments, a polyhedral model of the groove can be determined based on the shape of the groove formed by etching the initial structure; the coordinates of each vertex of the polyhedral model can be determined based on the position coordinates of a predetermined point on the surface and a critical dimension of the groove; and each face of the groove model can be determined based on the coordinates of each vertex, thereby forming a groove model.

[0069] See also Fig. 9 , Fig. 9 Schematic diagram of the active area sidewall of the silicon germanium trench structure according to some embodiments of the present disclosure is shown. Fig. 9 , which shows the inclination angle SWA of the active area sidewall based on the initial structure model. SWA can be used to subsequently calculate the vertex coordinates of the trench structure model. Fig. 9 AA in FIG. 8 represents an active area. Fig. 9 In addition to the STI formed by silicon dioxide material, the area not covered by polysilicon will be etched to form a trench.

[0070] Fig.10 A cross-sectional view of an embedded silicon germanium trench structure according to some embodiments of the present disclosure is shown. Specifically, Fig.10 The cross-sectional view of the embedded silicon germanium trench between the STI and the gate is shown in FIG. The left side 1002 in the figure indicates the STI, and the right side 1004 indicates the active area. Fig.10 Multiple dimensional parameters of the trench (which can be called the critical dimensions of the trench) are shown in the figure, including: active area length AA_Length (AA is along the X direction, AA is close to the STI edge to the gate edge), Sigma_Top_CD, the width of the upper silicon opening of the sigma trench, Sigma_Width, the width of the tip corners at both ends of the middle of the sigma trench, Sigma_Tip_Depth, the depth from the tip corner in the middle of the sigma trench to the silicon surface, Sigma_BCD_X, the CD of the bottom of the sigma trench parallel to the X axis, Sigma_BCD_Y, the depth of the sigma trench, Sigma_Depth, the depth of the silicon loss caused by the previous layer process, Si_loss, and the opening width Trench_Open_CD between the gates. Fig.10 Also shown are the vertices Ai, Bi, Ci and Di in the cross section of the groove.

[0071] The critical dimensions of the sigma morphology can be determined by calculation. Specific calculation methods for these critical dimensions are available in relevant literature, and the values ​​of these critical dimensions can be obtained by searching relevant literature. The critical dimensions of the sigma morphology can also be determined by slicing. Specifically, these dimensional parameters, i.e., the above parameters of the sigma-type groove profile at different layout positions, can be obtained by measuring with a transmission electron microscope (TEM). The X / Y dimensions of the AA exposed in the initial structure are different, and the critical dimensions of the groove morphology in the final X / Y direction will also be different.

[0072] for Fig.10 The embedded SiGe trench between the STI and the gate shown in FIG can be regarded as a sigma-type trench formed with the opening width AA_Length between the gates as the initial condition due to the blocking effect of silicon dioxide. Fig.10 As shown, it is assumed that there is a vertex Bi (i=1, 2) on the left side to facilitate the subsequent calculation using Sigma_Width. Because the opening width will affect the critical size of the sigma morphology, the critical size of the sigma morphology can be calculated based on the opening width.

[0073] See also Fig.11 , Fig.11 sectional views of embedded silicon germanium trench structures according to other embodiments of the present disclosure are shown. Specifically, Fig.11 The cross-sectional view of the embedded silicon germanium trench between the gates is shown in FIG. Fig.10 Various parameters of similar grooves in .

[0074] As mentioned above, according to the three-dimensional structure produced by the actual process production, the three-dimensional structure of the sigma-type silicon germanium trench can be constructed into the following two types of polyhedral models according to different layouts: Type A: The trench is located between the STI and the gate, and its three-dimensional structure of the sigma-type silicon germanium trench can be constructed as follows: Fig.12 The polyhedron model shown; and type B: the trench is located between two gates, and its sigma-type silicon germanium trench three-dimensional structure can be constructed as shown Fig.13 The polyhedron model shown.

[0075] See also Fig.12 , Fig.12 A schematic diagram of a polyhedron model of a silicon germanium trench structure according to some embodiments of the present disclosure is shown. The polyhedron model shown in the figure corresponds to Fig.10 The embedded groove shown in is type A. Fig.12It can be seen that the vertices of the top surface of the polyhedron model are A1, A2, A3 and A4. The vertices of the bottom surface are D1, D2, D3 and D4. The vertices of the middle plane are C1, C2, C3 and C4. These three planes are parallel to each other. In addition, there are two other vertices B3 and B4 in the model. The fact that these three planes are parallel to each other can simplify the calculation of the coordinates of each vertex on the same plane.

[0076] See also Fig.13 , Fig.13 A schematic diagram of a polyhedron model of a silicon germanium trench structure according to some other embodiments of the present disclosure is shown. The polyhedron model shown in the figure corresponds to Fig.11 The embedded groove shown in is type B. Fig.12 compared to, Fig.13 The polyhedron model in the figure has two more vertices, B5 and B6. B5, B6 are located in the same plane as B7, B8.

[0077] Fig.14 A schematic diagram of the bottom of a silicon germanium trench structure according to some embodiments of the present disclosure is shown. Figure 7 The cross section is obtained by cutting in the x direction shown in . Fig.14 The figure shows the bottom CD of the sigma trench parallel to the X-axis: Sigma_BCD_X, the difference between the silicon depth Sigma_Depth of the sigma trench and the silicon loss depth Si_loss caused by the previous layer process, the active area sidewall inclination angle SWA, the angle θ of the left edge of the trench plane as shown in the figure, the active area width AA_Width, and the parameter a which is mainly used for auxiliary calculation, where a= h* ( 1 / tan(SWA) + 1 / tan(θ) ), and the calculation of h is described later.

[0078] After dry etching, wet cleaning and wet etching (for example, tetramethylammonium hydroxide, TMAH) and other processes, an embedded silicon germanium trench with a sigma-type profile can be finally formed. To simplify the model and calculation, this process does not consider the loss of silicon dioxide at the STI boundary and the loss of the gate sidewall caused by the wet etching (TMAH) process. It should be understood that in addition to the use of TMAH as an etchant mentioned above, other alkaline reagents (such as KOH, ammonia NH4OH, etc.) can also be used to replace TMAH for wet etching.

[0079] In some embodiments, according to different layout situations, the coordinates of each vertex of the constructed silicon germanium trench polyhedron model can be calculated, and the vertices can be connected to form faces, thereby forming a three-dimensional polyhedron.

[0080] In some embodiments, two groups of calculation methods can be determined based on the different positions of the embedded silicon germanium trench in the gate and STI to facilitate the calculation of the positive and negative of the relevant data based on the reference point, respectively for the two layouts of the trench. According to the vertices of the three-dimensional structure of the embedded silicon germanium trench, the Z coordinate value of the same horizontal plane is the same, and then the X / Y / Z coordinates of each same horizontal plane are calculated in sequence.

[0081] The sidewall and bottom morphology of the trench is very difficult to model in the process. In some embodiments of the present disclosure, the critical dimensions of the sigma morphology can be calculated based on slices or through literature, so as to realize the construction of the embedded silicon germanium trench three-dimensional structure.

[0082] In some embodiments, each vertex of the polyhedron is respectively located on a top surface, a bottom surface, and a first plane and a second plane between the top surface and the bottom surface which are parallel to each other, wherein determining the coordinates of each vertex of the polyhedron model may include: based on the relative position relationship between each vertex and a predetermined point on the surface and a critical dimension of the groove, determining the coordinates of each vertex on the top surface, the bottom surface, and the first plane and the second plane.

[0083] In some embodiments, the trench is a selective embedded silicon germanium trench with a sigma-type profile, and the trench is located between two gates or between a shallow trench isolation region and a gate.

[0084] In some embodiments, when the trench is located between the shallow trench isolation region and the gate, the method further includes: considering the trench as a sigma-type trench formed with the opening width of the trench between the gates as an initial condition to determine the coordinates of each vertex of the polyhedron model.

[0085] In some embodiments, the coordinates of each vertex located in each horizontal plane of the trench are determined based on at least one of the following: the size of the active area; the width of the silicon opening at the top of the sigma-type trench; the width of the sharp corners at both ends of the middle of the sigma-type trench; the depth from the sharp corner in the middle of the sigma-type trench to the silicon surface; the critical dimension of the bottom of the sigma-type trench parallel to the X-axis; the critical dimension of the bottom of the sigma-type trench parallel to the Y-axis; the depth of the sigma-type trench; the depth of the silicon loss caused by the previous layer process; the opening width between the gates; and the inclination angle of the active area sidewall.

[0086] The following describes the determination Fig.12 The process of calculating the vertex coordinates of the polyhedron model of the SiGe trench structure shown in FIG. As described above, Fig.12 The polyhedron model shown in FIG. 1 is a polyhedron calculation model of type A, ie, a polyhedron model of a trench between the STI and the gate.

[0087] As mentioned above, the X / Y / Z coordinates of each vertex on the same horizontal plane can be calculated in sequence.

[0088] For example, for Ai(X Ai ,Y Ai ,Z Ai ) The vertex coordinate calculation model (i=1, 2, 3, 4) can be calculated as follows:

[0089] Calculation of Ai coordinate point (i=1, 2):

[0090] X Ai =X Oi

[0091] Y Ai =Y Oi

[0092] Z Ai =Z Oi .

[0093] When modeling the device structure, the initial device structure can be determined based on the basic device structure and dimensional parameters (gate spacing, spacer CD, AA width, AA length, STI sidewall inclination, etc.), and then the coordinate positions (x, y, z) of its key positions can be determined.

[0094] Calculation of Ai coordinate point (i=3, 4):

[0095] X Ai =X Oi +1 / 2*(Sigma_Top_CD-AA_Length)

[0096] Y Ai =Y Oi

[0097] Z Ai =Z Oi .

[0098] In some embodiments, the position coordinates of a key point of the first middle plane adjacent to the top plane can be determined based on the position coordinates of a predetermined point on the surface, the width of the sharp corners at both ends of the middle of the sigma trench, the opening width between the gates, the depth from the sharp corner in the middle of the sigma trench to the silicon surface, the inclination angle of the active area side wall, and the depth of the sigma trench.

[0099] For example, for Bi(X Bi ,Y Bi ,Z Bi )Vertex coordinate calculation model (i=1, 2, 3, 4), due to the blocking effect of silicon dioxide, TMAH selectively etches silicon on the side close to STI without consuming silicon dioxide, so silicon will be completely etched and no sidewall sharp angle with a specific angle (54.7° on the 111 face) will be formed. Therefore, Bi does not exist and does not need to be calculated. At this time, i=1,2.

[0100] Bi calculation (i=3, 4):

[0101] X Bi =X Oi +1 / 2*(Sigma_Width-AA_Length)

[0102] Y Bi =Y Oi +(-1)^ i+1 *(Sigma_Tip_Depth-Si_loss) / tan(SWA)

[0103] Z Bi =Z Oi -(Sigma_Tip_Depth-Si_loss);

[0104] The symbol ^ is a power symbol, indicating an exponent.

[0105] In some embodiments, the position coordinates of a key point on a second middle plane adjacent to the bottom surface of the trench structure can be determined based on the position coordinates of a predetermined point on the surface, the opening width between gates, the sigma trench depth, the inclination angle of the active area side wall, and the first height, where the first height is the distance from the bottom surface of the trench to the second middle plane.

[0106] For example, for Ci (X Ci ,Y Ci ,Z Ci )Vertex coordinate calculation model (i=1, 2, 3, 4):

[0107] Calculation of Ci (i=1,2):

[0108] X Ci =X Oi -(Sigma_Depth-Si_loss-h) / tan(SWA)

[0109] Y Ci =Y Oi +(-1)^ i+1 *(Sigma_Depth-Si_loss-h) / tan(SWA)

[0110] Z Ci =Z Oi -(Sigma_Depth-Si_loss-h)

[0111]

[0112] Ci calculation (i=3, 4):

[0113] XCi =X Oi -1 / 2*(AA_Length-Sigma_BCD_X)+h / tan(θ)

[0114] Y Ci =Y Oi +(-1)^ i+1 *(Sigma_Depth-Si_loss-h) / tan(SWA)

[0115] Z Ci =Z Oi -(Sigma_Depth-Si_loss-h).

[0116] The position coordinates of the key points on the bottom surface of the trench structure can be determined based on the position coordinates of the predetermined surface points, the opening width between gates, the CD of the sigma trench bottom, the depth of the sigma trench, and the width of the active area.

[0117] Di(X Di ,Y Di ,Z Di )Vertex coordinate calculation model (i=1,2,3,4)

[0118] Calculation of Di (i=1,2):

[0119] X Di =X Oi +1 / 2*(AA_Length-Sigma_BCD_X)

[0120] Y Di =Y Oi +(-1)^ i *1 / 2*(AA_Width-Sigma_BCD_Y)

[0121] Z Di =Z Oi -(Sigma_Depth-Si_loss)

[0122] Calculation of Di (i=3,4):

[0123] X Di =X Oi -1 / 2*(AA_Length-Sigma_BCD_X)

[0124] Y Di =Y Oi +(-1)^ i *1 / 2*(AA_Width-Sigma_BCD_Y)

[0125] Z Di =ZOi -(Sigma_Depth-Si_loss)

[0126] The following describes the determination Fig.13 The process of calculating the vertex coordinates of the polyhedron model of the silicon germanium trench structure shown in . That is, the calculation of each vertex of the type B polyhedron structure:

[0127] In some embodiments, the position coordinates of the key point of the first intermediate plane adjacent to the top plane may be determined based on the position coordinates of the predetermined surface point, the upper silicon opening width of the sigma trench, and the opening width between gates.

[0128] For example, Ai(X Ai ,Y Ai ,Z Ai )Vertex coordinate calculation model (i=5, 6, 7, 8):

[0129] Calculation of Ai coordinate point (i=5, 6):

[0130] X Ai =X Oi -1 / 2*(Sigma_Top_CD-Trench_Open_CD)

[0131] Y Ai =Y Oi

[0132] Z Ai =Z Oi .

[0133] Calculation of coordinate point Ai (i=7,8):

[0134] X Ai =X Oi +1 / 2*(Sigma_Top_CD-Trench_Open_CD)

[0135] Y Ai =Y Oi

[0136] Z Ai =Z Oi .

[0137] In some embodiments, the position coordinates of a key point of the first middle plane adjacent to the top plane can be determined based on the position coordinates of a predetermined point on the surface, the width of the sharp corners at both ends of the middle of the sigma trench, the opening width between the gates, the depth from the sharp corner in the middle of the sigma trench to the silicon surface, the depth of silicon loss caused by the previous layer process, the inclination angle of the active area side wall, and the depth of the sigma trench.

[0138] Bi(X Bi ,YBi ,Z Bi )Vertex coordinate calculation model (i=5, 6, 7, 8):

[0139] Calculation of Bi (i=5,6):

[0140] X Bi =X Oi -1 / 2*(Sigma_Width-Trench_Open_CD)

[0141] Y Bi =Y Oi +(-1)^ i+1 *(Sigma_Tip_Depth-Si_loss) / tan(SWA)

[0142] Z Bi =Z Oi -(Sigma_Tip_Depth-Si_loss)

[0143] Bi calculation (i=7, 8):

[0144] X Bi =X Oi +1 / 2*(Sigma_Width-Trench_Open_CD)

[0145] Y Bi =Y Oi +(-1)^ i+1 *(Sigma_Tip_Depth-Si_loss) / tan(SWA)

[0146] Z Bi =Z Oi -(Sigma_Tip_Depth-Si_loss).

[0147] In some embodiments, the position coordinates of a key point on a second middle plane adjacent to the bottom surface of the trench structure can be determined based on the position coordinates of a predetermined point on the surface, the opening width between gates, the depth of the sigma trench, the inclination angle of the active area side wall, the depth of silicon loss caused by the previous layer process, and the first height, where the first height is the distance from the bottom surface of the trench to the second middle plane.

[0148] Ci(X Ci ,Y Ci ,Z Ci )Vertex coordinate calculation model (i=5,6,7,8):

[0149] Ci calculation (i=5, 6):

[0150] XCi =X Oi +1 / 2*(Trench_Open_CD-Sigma_BCD_X)-h / tan(θ)

[0151] Y Ci =Y Oi +(-1)^ i+1 *(Sigma_Depth-Si_loss-h) / tan(SWA)

[0152] Z Ci =Z Oi -(Sigma_Depth-Si_loss-h).

[0153] The vertical distance from the bottom of the groove to Ci is h:

[0154]

[0155] Calculation of Ci (b=7,8):

[0156] X Ci =X Oi -1 / 2*(Trench_Open_CD-Sigma_BCD_X)+h / tan(θ)

[0157] Y Ci =Y Oi +(-1)^ i+1 *(Sigma_Depth-Si_loss-h) / tan(SWA)

[0158] Z Ci =Z Oi -(Sigma_Depth-Si_loss-h).

[0159] In some embodiments, the position coordinates of key points on the bottom surface of the trench structure can be determined based on the position coordinates of predetermined surface points, the opening width between gates, the CD of the sigma trench bottom, the sigma trench depth, and the active area width.

[0160] Di(X Di ,Y Di ,Z Di )Vertex coordinate calculation model (i=5,6,7,8):

[0161] Calculation of Di (i=5,6):

[0162] X Di =X Oi +1 / 2*(Trench_Open_CD-Sigma_BCD_X)

[0163] Y Di =Y Oi +(-1)^ i *1 / 2*(AA_Width-Sigma_BCD_Y)

[0164] Z Di =Z Oi -(Sigma_Depth-Si_loss)

[0165] Calculation of Di (i=7,8):

[0166] X Di =X Oi -1 / 2*(Trench_Open_CD-Sigma_BCD_X)

[0167] Y Di =Y Oi +(-1)^ i *1 / 2*(AA_Width-Sigma_BCD_Y)

[0168] Z Di =Z Oi -(Sigma_Depth - Si_loss).

[0169] Because the sharp corner of the sidewall of the sigma morphology of the trench is located below the gate, when it is located at different positions on the left and right of the gate, the positive and negative signs of the relevant calculation formulas in the formula need to be changed, which is achieved by (-1)^ i and (-1)^ i+1 to achieve.

[0170] The above embodiment describes the calculation process of each vertex in the polyhedral model of the groove. It should be understood that the above calculation formula is schematic and the present disclosure is not limited thereto. The formula can be appropriately deformed according to actual needs.

[0171] After determining each vertex, the corresponding vertices are connected to form each face of the polyhedron model, thereby forming a groove model.

[0172] At block 508 , a semiconductor process device model is formed based on the initial model and the trench model.

[0173] In some embodiments of the present disclosure, according to the basic device structure and size parameters, Figure 8The initial structure shown in is used as the initial structure model, that is, an initial model is constructed in the software. Then, according to the calculated groove structure model, the area where the silicon germanium groove polyhedron is superimposed in the initial structure model can be deleted by Boolean operation to obtain the final silicon germanium three-dimensional groove model. In other words, the three-dimensional polyhedron can be implanted into the previously built initial structure by Boolean operation to finally form a silicon germanium three-dimensional groove model.

[0174] In some embodiments, forming the semiconductor process device model based on the initial model and the trench model may include: implanting the trench model into the initial model through Boolean operation to form the semiconductor process device model.

[0175] In some embodiments, implanting the trench model into the initial model through Boolean operation includes: deleting a region corresponding to the trench model at a position where the trench is predetermined to be formed in the initial model to generate a cavity; and implanting the trench model into the cavity to form a semiconductor process device model.

[0176] Fig.15 The schematic diagram of the modeling process of the silicon germanium trench structure according to some embodiments of the present disclosure is shown. That is, first determine the initial structure model of the device shown on the left, then model the trench structure to determine the three-dimensional structure model of the trench structure, and finally merge the initial structure model with the three-dimensional structure model of the trench structure to obtain the final structure model. Fig.16 Give a description.

[0177] Fig.16 A schematic diagram showing a final model of a silicon germanium trench structure according to some embodiments of the present disclosure. Fig.16 The left side shows the final device structure model 1600. The right side shows the three-dimensional structure model 1604 of the trench structure. The three-dimensional structure model 1604 can be perfectly embedded in the cavity 1602 in the device structure model 1600. This can be done by using Boolean operations to delete the area where the initial structure and the silicon germanium trench polyhedron overlap, so as to finally form the silicon germanium three-dimensional trench model.

[0178] Some embodiments of the present disclosure provide methods for semiconductor process device simulation. It should be noted that the examples given in the above embodiments are only for illustrating the solutions of the embodiments of the present disclosure and are not intended to limit the solutions of the present disclosure.

[0179] The three-dimensional structural model of some embodiments of the present disclosure is suitable for three-dimensional modeling of selective embedded sigma-type silicon germanium trenches formed after wet etching.

[0180] In some embodiments of the present disclosure, three-dimensional structure modeling can be performed based on the three-dimensional embedded silicon germanium trench structure produced by actual process production, taking into full consideration the boundary type and bottom corner morphology in the actual process. In addition, an accurate three-dimensional morphology of the embedded silicon germanium trench can be formed, which can effectively solve the morphology distortion problem of the selective epitaxial embedded silicon germanium trench in the TCAD three-dimensional process simulation, and further improve the accuracy of the stress and strain process simulation results.

[0181] The solutions of some embodiments of the present disclosure do not need to form the silicon germanium groove morphology by the point drawing method. The point drawing method requires a lot of calculations. Therefore, the selective embedded silicon germanium groove three-dimensional structure model involved in the present disclosure can realize fast and realistic process structure modeling in TCAD process simulation, obtain the final sigma groove three-dimensional structure, and save time for structure adjustment and optimization.

[0182] An electronic device is also disclosed in an embodiment of the present disclosure. The electronic device includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein, and the instructions, when executed by the processor, cause the device to perform actions, the actions including: determining an initial model of the initial structure of the semiconductor process device; determining the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a groove model based on the critical dimensions of the groove formed by etching the initial structure and the position coordinates of the predetermined point; and forming a semiconductor process device model based on the initial model and the groove model.

[0183] The embodiment of the present disclosure also discloses a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method for simulating a semiconductor process device according to the embodiment of the present disclosure is implemented.

[0184] It should be understood that the embodiments shown in the drawings are only for schematically illustrating the solutions of some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0185] Fig.17 A schematic block diagram of an electronic device according to some exemplary embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0186] like Fig.17 As shown, the device 1700 includes a CPU 1701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1702 or a computer program loaded from a storage unit 1708 into a random access memory (RAM) 1703. In the RAM 1703, various programs and data required for the operation of the device 1700 can also be stored. The CPU 1701, the ROM 1702, and the RAM 1703 are connected to each other via a bus 1704. An input / output (I / O) interface 1705 is also connected to the bus 1704.

[0187] Multiple components in the device 1700 are connected to the I / O interface 1705, including: an input unit 1706, such as a keyboard, a mouse, etc.; an output unit 1707, such as various types of displays, speakers, etc.; a storage unit 1708, such as a disk, an optical disk, etc.; and a communication unit 1709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1709 allows the device 1700 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0188] The various processes and processing described above, such as method 500, may be executed by CPU 1701. For example, in some embodiments, method 500 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 1708. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1700 via ROM 1702 and / or communication unit 1709. When the computer program is loaded into RAM 1703 and executed by CPU 1701, one or more steps in method 500 described above may be performed.

[0189] The scheme according to the embodiment of the present disclosure may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network and / or a wireless network.

[0190] Various embodiments of the present disclosure have been described above, and the above descriptions are exemplary and are only optional embodiments of the present disclosure, not exhaustive, and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel features or any novel combination of features disclosed herein, whether or not it relates to the same scheme in any claim currently claimed for protection. The applicant hereby informs that new claims may be formulated into these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0191] The terms used in this article are selected to best explain the principles of each embodiment, practical application or technical improvement in the market, or to enable other ordinary technicians in the field to understand the embodiments disclosed herein. For those skilled in the art, the present disclosure may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for simulating a semiconductor process device, wherein the semiconductor process device comprises a trench, the method comprising: Determining an initial model of an initial structure of the semiconductor process device; Determine the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; Determining a trench model based on a critical dimension of the trench formed by etching the initial structure and a position coordinate of the predetermined point; as well as Forming a semiconductor process device model based on the initial model and the trench model specifically includes: implanting the trench model into the initial model through Boolean operation to form the semiconductor process device model.

2. The method according to claim 1, wherein the semiconductor process device further comprises an active region, a gate, and a shallow trench isolation region, and wherein determining an initial model of an initial structure of the semiconductor process device comprises: Determining the layout and related dimensions of the active area, the gate, and the shallow trench isolation area; as well as The initial model is determined based on the layout and the associated dimensions.

3. The method according to claim 2, wherein the position coordinates of the predetermined point include at least the following items: Coordinates of key points of the active region adjacent to the shallow trench isolation region at a substrate surface of the semiconductor process device; and The opening position of the trench is the coordinate of a key point on the surface of the substrate of the semiconductor process device.

4. The method according to claim 1, wherein determining the trench model based on the critical dimensions of the trench formed by etching the initial structure and the position coordinates of the predetermined point comprises: determining a polyhedral model of the groove based on the shape of the groove formed by etching the initial structure; Determining the coordinates of each vertex of the polyhedral model based on the position coordinates of the predetermined point on the surface and the critical size of the groove; as well as Each face of the groove model is determined based on the coordinates of each vertex to form the groove model.

5. The method according to claim 4, wherein each vertex of the polyhedron is respectively located on a top surface, a bottom surface, and a first plane and a second plane between the top surface and the bottom surface which are parallel to each other, wherein determining the coordinates of each vertex of the polyhedron model comprises: Based on the relative positional relationship between each vertex and the predetermined point on the surface and the critical dimension of the groove, the coordinates of each vertex on the top surface, the bottom surface, and the first plane and the second plane are determined respectively. 6 . The method according to claim 5 , wherein the trench is a selective embedded silicon germanium trench with a sigma-type profile, and the trench is located between two gates or between a shallow trench isolation region of the semiconductor process device and the gate.

7. The method according to claim 6, wherein in the case where the trench is located between the shallow trench isolation region and the gate, the method further comprises: The trench is regarded as a sigma-type trench formed with the opening width of the trench between the gates as an initial condition, so as to determine the coordinates of each vertex of the polyhedral model.

8. The method according to claim 6 or 7, wherein the coordinates of each vertex are determined based on at least one of the following: Active area size; The width of the silicon opening in the upper part of the sigma-type trench; The width of the sharp corners at both ends of the sigma groove; The depth from the middle corner of the sigma-type trench to the silicon surface; The critical dimension of the bottom of the sigma-shaped groove parallel to the X-axis; The critical dimension of the bottom of the sigma-shaped groove parallel to the Y axis; Sigma groove depth; The depth of silicon loss caused by the previous layer process; The width of the opening between the gates; as well as The inclination angle of the active area sidewall.

9. The method according to claim 1, wherein implanting the groove model into the initial model through Boolean operation comprises: Deleting a region corresponding to the groove model at a position in the initial model where the groove is predetermined to be formed to generate a cavity; as well as The trench pattern is implanted into the cavity to form the semiconductor process device pattern.

10. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions comprising: Determine an initial model of an initial structure of a semiconductor process device; Determine the position coordinates of a predetermined point on the surface of the semiconductor process device based on the initial model; determining a trench model based on a critical dimension of a trench formed by etching the initial structure and a position coordinate of the predetermined point; and Forming a semiconductor process device model based on the initial model and the trench model specifically includes implanting the trench model into the initial model through Boolean operation to form the semiconductor process device model.

11. A computer-readable storage medium having machine-executable instructions stored thereon, and when the machine-executable instructions are executed by a processor, the processor is enabled to implement the method according to any one of claims 1 to 9.

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