A register optimization method, device and storage medium based on constant equivalence

Abstract

The present invention belongs to the technical field of circuit design and optimization, and more specifically, relates to a register optimization method, device and storage medium based on constant equivalence. The method comprises S1, obtaining register groups in circuit design and the type of optimization processing required for each register group; S2, performing constant optimization on the register group according to the type of optimization processing required; S3, updating the circuit design according to the constant optimization result. The present invention solves the problem of increased power consumption and additional hardware resource occupation caused by register group optimization in large-scale integrated circuit design in the prior art.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design and optimization, and more specifically, relates to a register optimization method, device and storage medium based on constant equivalence. Background Art

[0002] With the increase of modern computing needs, register group optimization has become one of the key factors to improve computing system performance. Especially in large-scale integrated circuit design, register group optimization is of great significance for increasing processor speed, reducing power consumption and improving overall efficiency. At the same time, due to technological advancement and the increase of computing needs, how to optimize register groups to improve system performance has become an important research direction.

[0003] Chinese invention patent CN116661860A discloses an OpenMP Offload register optimization method for DCU, including S1: obtaining the running results of other analysis passes; S2: judging the relationship between the number of loop iterations and the number of threads, if the number of threads is greater than the number of loop iterations, then entering the optimization code, otherwise resetting the number of allocated threads to meet the optimization conditions; S3: locating the IR block according to the basic block characteristics; S4: modifying the CFG structure of the IR block to generate a new IR code; S5: calculating a new expansion factor to obtain the optimal expansion factor.

[0004] In actual large-scale integrated circuit design, the efficiency of the register group directly affects the execution efficiency of the processor. Optimizing the register group not only helps to improve system performance, but also reduces power consumption and saves hardware resources. It also has important application value in high-performance computing and embedded systems. However, specific and feasible register group optimization schemes still face many problems and difficulties. On the one hand, in low-power design, it is necessary to balance the relationship between performance and power consumption, and the optimization strategy needs to be precisely adjusted. Although register group optimization can reduce power consumption, if the optimization is not done properly, it may lead to an increase in power consumption. On the other hand, in resource-limited embedded systems and low-cost chips, increasing hardware resources may lead to uneconomical designs. Optimizing the register group may occupy additional hardware resources, for example, to implement more complex control logic.

[0005] In summary, through a reasonable register group optimization strategy, the system performance can be significantly improved, energy consumption can be reduced, and hardware resources can be saved. This is not only of great application value to resource-constrained large-scale integrated circuit design, but also of great significance to the development of high-performance computer systems. Summary of the invention

[0006] The present invention aims to overcome at least one defect of the above-mentioned prior art and provide a register optimization method based on constant equivalence to solve the problem of the shortcomings of the prior art in register group optimization in large-scale integrated circuit design.

[0007] The present invention also provides a register optimization device based on constant equivalence.

[0008] On the other hand, the present invention further provides a computer-readable storage medium storing executable instructions, which, when executed, enable the machine to perform the register optimization method based on constant equivalence as described above.

[0009] The definitions of the terms used in this invention are as follows:

[0010] Register refers to a digital circuit with data storage function, also called a register; it consists of multiple latches and realizes the read and write operations of each bit in the register by controlling different input signals.

[0011] Nor refers to the NOR device in digital circuits. It usually has multiple input signals, and the output signal is equal to the input signal after bitwise "OR" and inversion.

[0012] Add refers to the adder in the digital circuit, which usually contains five pins, of which the three inputs are addend A, addend B and the upper carry signal CIN; the two outputs are the result bit SUM and the lower carry signal COUT.

[0013] Less refers to the comparator in the digital circuit, which is used to compare the size of two numbers. It usually contains four pins, of which the three input pins are pin IN0, pin IN1, pin CIN and output result pin OUT; when pin CIN is 1'b0, it determines whether IN0 is less than IN1, and the output is 1 if it is, otherwise the output is 0; when pin CIN is 1'b1, it determines whether IN0 is less than or equal to IN1, and the output is 1 if it is, otherwise the output is 0.

[0014] The detailed technical scheme of the present invention is as follows:

[0015] A register optimization method based on constant equivalence, the method comprising:

[0016] S1. Obtain the register groups in the circuit design and the type of optimization processing required for each register group;

[0017] The register group in the design refers to a group of registers storing multi-bit data.

[0018] The optimization processing type required for each group of registers refers to the optimization processing type required for each group of registers specified by the designer.

[0019] The present invention provides three types of optimization processing, including: a type in which only nor and add are connected by register; a type in which only less and add are connected by register; and a type in which less and nor are connected by register.

[0020] S2. Perform constant optimization on the register group according to the type of optimization processing required;

[0021] There are only nor and add types for register connection: based on the circuit structure analysis of the data range of the register group, before the maximum value of the register group data range is reached, the add device will continue to perform the +1 operation. When the maximum value of the data range is reached, that is, the output of the nor device is 1, the register group will be assigned an initial value; add continues to perform the +1 operation until the maximum value of the register group data range is reached again, and the cycle continues; when the register group data cycles within the range of initial value to maximum value, the high-order data is always in a state of 0. At this time, the register constant optimization is performed, that is, the register is deleted and replaced with a constant 0.

[0022] For register connection, there are only less and add types: the IN0 input of the less device is the data of the register group, and the IN1 terminal is the input of the circuit. When the data of the register group is less than the maximum value, that is, the input data of the IN1 terminal of the less device, the add device continues to perform the addition operation until the register group data is greater than or equal to the maximum value; at this time, the register group will be assigned an initial value and continue to calculate until it is greater than or equal to the maximum value again, and this cycle will be repeated; when the data range of the register group is from the initial value to the maximum value, the high-order data is always 0, and the register constant optimization is performed at this time.

[0023] For the types of registers connected to less and nor: Based on the circuit structure, no matter the output of the register group meets the conditions of the less device or the nor device, the register group will be assigned an initial value. Therefore, in the process of adding the device +1, the register group data that first meets one of the conditions is the maximum value of the data range. The register group data continuously cycles within the range of the initial value to the maximum value, and the high-order data is always in a state of 0, based on which the register constant optimization is performed.

[0024] The above three types of optimization processing have no order of precedence, but are mutually exclusive.

[0025] If the designer does not specify the type of optimization processing required for the group of registers in S1, an optimization processing type is matched according to the characteristics of the register group; the characteristics of the register group refer to the characteristics of the three connections of nor, add and less, which have been explained in the previous definition of terms.

[0026] If the designer specifies the type of optimization processing required for the group of registers in S1, the optimization is performed directly according to the specified optimization processing type.

[0027] S3. Update the circuit design according to the constant optimization results.

[0028] The updating of the design according to the optimization result also includes, if the circuit design, during the register group optimization process, results in a situation where components in the design have dangling ports, deleting the corresponding irrelevant components.

[0029] In another aspect of the present invention, a device for implementing a register optimization method based on constant equivalence is provided, the device comprising:

[0030] at least one processor; and

[0031] A memory storing instructions, when the instructions are executed by the at least one processor, enables the at least one processor to execute the register optimization method based on constant equivalence as described above.

[0032] In another aspect of the present invention, a machine-readable storage medium is provided, which stores executable instructions. When the instructions are executed, the machine executes the register optimization method based on constant equivalence as described above.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention provides a register optimization method, device and storage medium based on constant equivalence, which classifies the register groups in the design and implements constant optimization in a targeted manner. On the one hand, the scale, complexity, area and power consumption of large-scale integrated circuit design are effectively reduced; on the other hand, the constant value will not cause timing problems due to clock changes, which can better meet the timing constraints of the circuit and improve the timing characteristics of the circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1is a flow chart of a register optimization method based on constant equivalence according to the present invention;

[0036] Figure 2 is a schematic diagram of a register group included in the circuit design of Example 1;

[0037] Figure 3 is a schematic diagram of optimization processing type 1 of Example 1;

[0038] Figure 4 is a schematic diagram of optimization processing type 2 of Example 1;

[0039] Figure 5 is a schematic diagram of optimization processing type 3 of Example 1;

[0040] Figure 6 This is a schematic diagram of the optimization processing type 1 state of Example 1;

[0041] Figure 7 This is a schematic diagram of the optimization processing type 2 state of Example 1;

[0042] Figure 8 This is a schematic diagram of the optimization processing type 3 state of Example 1. DETAILED DESCRIPTION

[0043] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0044] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0045] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0046] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0047] Example 1

[0048] Ginseng Figure 1 , this embodiment provides a register optimization method based on constant equivalence, the method comprising:

[0049] S1. Obtain the register groups in the circuit design and the type of optimization processing required for each register group;

[0050] The register group in the design refers to a group of registers that can store multiple bits of data.

[0051] The optimization processing type required for each group of registers refers to the optimization processing type required for each group of registers specified by the designer.

[0052] Among them, this embodiment provides three types of optimization processing, including: a type in which only nor and add are connected by register; a type in which only less and add are connected by register; and a type in which less and nor are connected by register.

[0053] like Figure 2 As shown, it includes register group A, register group B, register group C, and register group D in the design, and the left IN _ PORT _ 0. IN _ PORT _ 1. IN_PORT_2......IN _ PORT _ m is the input port and CLK is the clock, OUT on the right _ PORT _ 0.OUT _ PORT _ 1. OUT _ PORT _ 2......OUT _ PORT _ n is the output port; the designer specifies that register group A needs to perform only nor and add type optimization processing for register connection, register group B needs to perform only less and add type optimization processing for register connection, and register group C needs to perform less and nor type optimization processing for register connection. Register group D does not specify optimization processing requirements.

[0054] S2. Perform constant optimization on the register group according to the type of optimization processing required;

[0055] After obtaining one of the register groups, determine whether to specify the optimization processing type of the register group; if so, optimize according to the specified optimization processing type; if not, optimize according to the characteristics of the register group;

[0056] The specific implementation process is as follows:

[0057] take out Figure 2 According to the analysis of step 1 in Example 1, the designer specifies the optimization processing type of the register group A as follows: only the nor and add types of optimization processing are used for register connection, such as Figure 3 The optimization processing type shown. The specific examples are as follows:

[0058] There are only nor and add types for register connection: based on the circuit structure analysis of the data range of the register group, before the maximum value of the data range is reached, the add device always performs the +1 operation. When the maximum value of the data range is reached, that is, the output of the nor device is 1, the register group will be assigned an initial value; add continues to perform the +1 operation until the maximum value of the register group data range is reached again, and the cycle continues; when the register group data cycles within the range of initial value to maximum value, the high-order data is always in a state of 0. At this time, the register constant optimization is performed, that is, the register is deleted and replaced with a constant 0.

[0059] Analyzing the data range of the register group based on the circuit structure is a common operation for those skilled in the art. Preferably, based on the idea of ​​the state transition diagram in the digital circuit, the state constituting the loop is deduced from the initial state, and the data range of the register group is confirmed according to the state loop.

[0060] Optimization processing type 1 such as Figure 3 As shown, it shows the optimization of the two-bit register data range, where the upper register is the high bit, the lower register is the low bit, and (Q0Q1) is the state of register group A. When register group A meets the condition equal to binary data 01, the next state will enter 00.

[0061] like Figure 6As shown, let the starting state (Q0Q1) be 10, 10 does not meet the condition of being equal to 01, the arrow is marked as 0, and enter the next state (Q0Q1) 11; 11 does not meet the condition of being equal to 01, the arrow is also marked as 0, and enter the next state (Q0Q1) 00; 00 does not meet the condition of being equal to 01 and enters the next state (Q0Q1) 01; 01 meets the condition of being equal to 01, the arrow is marked as 1, and enters the next state (Q0Q1) 00; the data enters the cycle from 00 to 01, so it can be judged that the data range of register group A is 00~01, and because the high-order register is always in the state of 0, the register can be deleted and replaced with the constant 0.

[0062] take out Figure 2 According to the analysis of S1 in Example 1, the designer specifies the optimization processing type of the register group B as follows: only the less and add types of optimization processing are used for register connections, that is, Figure 4 The optimization processing type shown. The specific examples are as follows:

[0063] For registers that are connected to only less and add types, based on the characteristics of the less device, when the data of the register group is less than the maximum value (another input value of the less device), the add device will continue to perform the sum operation until it is greater than or equal to the maximum value. At this time, the register group will be assigned an initial value and continue to calculate until it is greater than or equal to the maximum value again. Therefore, the data range of the register group is from the initial value to the maximum value. At this time, the high-order data is always 0, and the register constant optimization is performed based on this.

[0064] Optimization processing type 2 such as Figure 4 As shown, it shows the optimization of the two-bit register data range, where the upper register is the high bit, the lower register is the low bit, and (Q0Q1) is the state of register group B. When register group B satisfies greater than or equal to binary data 01, the next state will enter 00.

[0065] like Figure 7As shown, let the starting state (Q0Q1) be 10, 10 meets the condition of being greater than or equal to 01, the arrow is marked as 1, and enter the next state (Q0Q1) 00; 00 does not meet the condition of being greater than or equal to 01, the arrow is marked as 0, and enter the next state (Q0Q1) 01; 01 meets the condition of being greater than or equal to 01, the arrow is marked as 1, and enter the next state (Q0Q1) 00; the data enters the cycle of 00~01. Similarly, the starting state (Q0Q1) is 11, and it will eventually enter the cycle of 00~01. Therefore, it can be determined that the data range of register group B is 00~01, and because the high-order register is always in the state of 0, the register can be deleted and replaced with a constant 0.

[0066] take out Figure 2 According to the analysis of S1 in Example 1, the designer specifies the optimization processing type of the register group C as follows: register connection less and nor type optimization processing, that is, Figure 5 The optimization processing type shown. The specific examples are as follows:

[0067] For the register connection types of LESS and NOR, it is a combination of the above two register connection types. Based on the characteristics of LESS devices and NOR devices, no matter whether the data of the register group meets the conditions of LESS devices or NOR devices, the register group will be assigned an initial value and will continuously cycle within a certain data range. Therefore, the high-order data is always 0, based on which the register constant optimization is performed.

[0068] Figure 5 The display shows the optimization of the two-bit register data range, where the upper register is the high bit, the lower register is the low bit, and (Q0Q1) is the state of register group C. When register group C satisfies greater than or equal to binary data 11 or satisfies equal to 01, the next state will enter 00.

[0069] like Figure 8As shown, let the starting state (Q0Q1) be 10, 10 does not meet the condition of being greater than or equal to 11 or equal to 01, the arrow is marked as 0, and enters the next state (Q0Q1) 11; 11 meets the condition of being greater than or equal to 11, the arrow is marked as 1, and enters the next state (Q0Q1) 00; 00 does not meet the condition of being greater than or equal to 11 or equal to 01, the arrow is marked as 0, and enters the next state (Q0Q1) 01; 01 meets the condition of being equal to 01, the arrow is marked as 1, and enters the state (Q0Q1) 00; the data enters the cycle from 00 to 01, so it can be judged that the data range of register group C is 00~01, and because the high-order register is always in the state of 0, the register can be deleted and replaced with the constant 0.

[0070] Remove the attached Figure 2 According to the analysis of step 1 in Example 1, the designer did not specify the optimization processing type of the register group D. Assume that the structure of register group D is the same as that of the attached Figure 3 As shown in the figure, by analyzing its characteristics, we can directly match the optimization processing type 1, and the specific processing process is the same as register group A.

[0071] S3. Updating the design according to the optimization results, that is, updating the design according to the optimization results means that if the design results in dangling ports of components in the design during the register group optimization process, the corresponding irrelevant components are deleted.

[0072] According to the optimization result of step S2 in Example 1, there is no dangling port in the optimized design, and the register optimization based on constant equivalence is completed.

[0073] Finally, determine whether all register groups have been traversed. If so, complete the register group optimization; if not, continue to obtain the untraversed register groups and continue the optimization.

[0074] Example 2

[0075] This embodiment provides a device for implementing a register optimization method based on constant equivalence, the device comprising:

[0076] at least one processor; and

[0077] A memory storing instructions, when the instructions are executed by the at least one processor, enables the at least one processor to execute the register optimization method based on constant equivalence as described above.

[0078] In this embodiment, the device includes but is not limited to: personal computers, server computers, workstations, desktop computers, laptop computers, notebook computers, mobile computing devices, smart phones, tablet computers, cellular phones, personal digital assistants (PDAs), handheld devices, messaging devices, wearable computing devices, consumer electronic devices, etc.

[0079] Example 3

[0080] This embodiment also provides a computer-readable storage medium storing executable instructions, which, when executed, enable the machine to execute the register optimization method based on constant equivalence as described above.

[0081] Specifically, a system or device equipped with a readable storage medium can be provided, on which software program codes that implement the functions of any of the above-mentioned embodiments are stored, and a computer or processor of the system or device can read and execute instructions stored in the readable storage medium.

[0082] In this case, the program code itself read from the machine-readable medium can realize the function of any one of the above embodiments, and thus the machine-readable code and the machine-readable storage medium storing the machine-readable code constitute part of this specification.

[0083] Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code may be downloaded from a server computer or a cloud via a communication network.

[0084] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0085] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0088] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A register optimization method based on constant equivalence, characterized in that: The method comprises: S1. Obtain the register groups in the circuit design and the type of optimization processing required for each register group; S2. Perform constant optimization on the register group according to the type of optimization processing required; For register connection, there are only nor and add types: based on the circuit structure, the data range of the register group is analyzed. Before the maximum value of the register group data range is reached, the add device will always perform the +1 operation. When the maximum value of the data range is reached, that is, the output of the nor device is 1, the register group will be assigned an initial value; add continues to perform the +1 operation until the maximum value of the register group data range is reached again, and the cycle repeats; when the register group data cycles within the range of the initial value to the maximum value, the high-order data is always 0, and then the register constant optimization is performed; For register connection, there are only less and add types: the IN0 input of the less device is the data of the register group, and the IN1 terminal is the input of the circuit. When the data of the register group is less than the maximum value, that is, the input data of the IN1 terminal of the less device, the add device continues to perform the addition operation until the data of the register group is greater than or equal to the maximum value; at this time, the register group will be assigned an initial value and continue to calculate until it is greater than or equal to the maximum value again, and this cycle will be repeated; when the data range of the register group is from the initial value to the maximum value, the high-order data is always 0, and then the register constant optimization is performed; For the types of registers connected to less and nor: Based on the circuit structure, no matter the output of the register group meets the conditions of the less device or the nor device, the register group will be assigned an initial value; in the process of adding the device +1, the register group data that first meets one of the conditions is the maximum value of the data range; when the register group data continuously cycles within the range of the initial value to the maximum value, the high-order data is always 0, and then the register constant optimization is performed; S3. Update the circuit design according to the results of constant optimization.

2. A register optimization method based on constant equivalence according to claim 1, characterized in that: The three types of optimization processing have no order of precedence, but are mutually exclusive; If the optimization processing type required for the group of registers is not specified in S1, an optimization processing type is matched according to the characteristics of the register group; If the optimization processing type required for the group of registers is specified in S1, optimization is performed according to the specified optimization processing type.

3. A register optimization method based on constant equivalence according to claim 1, characterized in that: The updating of the circuit design according to the result of constant optimization also includes: If the above register group optimization process causes dangling ports in components in the design, delete the corresponding irrelevant components.

4. A device for register optimization method based on constant equivalence, characterized in that: The device comprises: processor; a memory having stored thereon a computer program executable on the processor; Wherein, when the computer program is executed by the processor, the steps of the register optimization method based on constant equivalence as described in any one of claims 1 to 3 are implemented.

5. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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