A design method for a dual-band high-efficiency power amplifier with wide bandwidth ratio

Abstract

The invention relates to the technical field of power amplifiers and discloses a design method for a dual-band high-efficiency power amplifier with a wide frequency ratio, comprising: establishing a first high-efficiency mode based on a drain voltage on a drain current plane of a transistor and a drain current tuned by a second harmonic source impedance, and obtaining a fundamental output power and a drain efficiency in the mode; establishing a second high-efficiency mode based on a drain voltage on a drain current plane of a transistor and a drain current tuned by a second harmonic source impedance; the design method for the dual-band high-efficiency power amplifier with a wide frequency ratio obtains an optimal drain impedance design space according to the fundamental output power and the drain efficiency in the two modes by designing the first high-efficiency mode and the second high-efficiency mode, so as to facilitate the selection of two wide-frequency ratio working frequency bands based on the optimal drain impedance design space and meet the design requirements of the dual-band high-efficiency power amplifier.

Description

Technical Field

[0001] The invention relates to the technical field of power amplifiers, and in particular to a design method for a wide-band ratio dual-band high-efficiency power amplifier. Background Art

[0002] As wireless terminals continue to become popular in consumer and industrial production, various wireless communication standards have emerged in large numbers, and wireless terminals that can simultaneously support multiple communication standards have become an inevitable direction of technological development. However, since the operating frequency bands of various wireless communication standards are different, the multi-frequency transmitter in the wireless terminal must design a transmission link for each operating frequency band, resulting in the problems of large overall size, low efficiency, and high cost of the multi-frequency wireless terminal. The dual-frequency high-efficiency power amplifier can support dual-frequency operation and has high efficiency, and has the potential to solve the design problems of multi-frequency transmitters at the same time.

[0003] However, with the rapid evolution of 5G communications, the operating frequency bands of the new generation of wireless terminals are constantly increasing. At the same time, they must also support traditional low-frequency wireless communication standards. The frequency ratio requirements are increasing accordingly. The existing dual-band high-efficiency power amplifiers have a relatively low operating frequency band. Therefore, the design of a wide-ratio dual-band high-efficiency power amplifier has become a difficult problem that needs to be solved urgently.

[0004] At present, the design of high-efficiency power amplifiers mainly adopts load-pull simulation technology or the high-efficiency mode of traditional waveform engineering to obtain the optimal drain output impedance in the operating frequency band. In particular, the method of constructing a high-efficiency mode using waveform engineering theory can design a relatively large optimal drain output impedance space, which effectively reduces the difficulty of output impedance matching design. Therefore, a variety of methods based on waveform engineering theory to construct high-efficiency modes have been applied to power amplifier design.

[0005] However, in the design of wide-band dual-band high-efficiency power amplifiers, the position distribution and range of the optimal drain output impedance space of the traditional high-efficiency mode in the Smith chart still cannot meet the wide-band dual-band impedance matching requirements. In recent years, foreign teams have proposed J-class, F-class and inverse F-class high-efficiency power amplifiers based on input-output waveform theory design using the nonlinear characteristics of the transistor input end, and subsequently proposed continuous inverse GF-class, continuous GF-class and extended continuous GF-class broadband high-efficiency power amplifiers based on second harmonic source impedance control. These power amplifiers use the method of second input source harmonic impedance tuning to design and expand the impedance design space of the transistor drain. However, using the above-mentioned high-efficiency mode, the impedance design space obtained is still relatively small, and it is difficult to design a wide-band dual-band complex impedance transformation circuit in the area where these impedance design spaces are distributed. Therefore, it is still not suitable for designing wide-band dual-band high-efficiency power amplifiers. Summary of the invention

[0006] In order to solve the above problem that when using the existing high-efficiency mode to design a wide-band dual-band high-efficiency power amplifier, the impedance design space is still relatively small, and it is difficult to design a wide-band dual-band complex impedance conversion circuit in the area where these impedance design spaces are distributed, thereby failing to realize the design problem of a wide-band dual-band high-efficiency power amplifier, the present invention is implemented through the following technical solutions: A design method for a wide-band dual-band high-efficiency power amplifier, comprising the following specific steps:

[0007] S1, based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, establish a first high efficiency mode, and obtain the fundamental output power and drain efficiency in this mode;

[0008] S2, based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, establish a second high efficiency mode, and obtain the fundamental output power and drain efficiency in this mode;

[0009] S3. Obtain the fundamental output impedance and the second harmonic output impedance according to the drain voltage and the drain current on the current plane of the two high-efficiency modes transistors, and determine the optimal drain impedance design space in the two modes according to the requirements of the fundamental output power and the drain efficiency;

[0010] S4, selecting two operating frequency bands, designing a theoretical prototype of a dual-frequency complex impedance conversion circuit at the drain output end of the transistor, so that the fundamental output impedance and the second harmonic output impedance of the corresponding two operating frequency bands on the transistor drain current plane fall within the optimal drain impedance design space;

[0011] S5. For the theoretical prototype of the designed output-end dual-frequency complex impedance conversion circuit, a substrate is selected for microstrip circuit design to obtain a microstrip circuit form of the output-end dual-frequency complex impedance conversion circuit;

[0012] S6, simulating and obtaining the fundamental output impedance and second harmonic output impedance of the circuit composed of the transistor package parasitic parameter equivalent circuit and the output end dual-frequency complex impedance conversion circuit microstrip form in two corresponding working frequency bands, and verifying whether the fundamental output impedance and second harmonic output impedance of the two working frequency bands obtained fall into the optimal drain impedance space, if so, proceed to the next step;

[0013] S7. Based on the two high-efficiency modes, a theoretical prototype of a stable circuit and a theoretical prototype of an input-end dual-frequency complex impedance conversion circuit with second harmonic source impedance control are designed on the basis of the designed output-end dual-frequency complex impedance conversion circuit;

[0014] S8. According to the two selected working frequency bands, for the theoretical prototype of the stable circuit and the theoretical prototype of the designed input-end dual-frequency complex impedance conversion circuit, select the same substrate as in step S5 to perform microstrip circuit design, and obtain the microstrip circuit form of the stable circuit and the input-end dual-frequency complex impedance conversion circuit;

[0015] S9. Simulate and obtain the fundamental impedance and second harmonic impedance of the dual-frequency complex impedance conversion circuit at the input end, and verify whether the fundamental impedance and second harmonic impedance of the two working frequency bands obtained fall within the set range close to the target source impedance. If so, obtain a power amplifier.

[0016] Furthermore, if the fundamental output impedance and the second harmonic output impedance of the two working frequency bands verified in S6 do not fall into the optimal drain impedance space, return to S4 and redesign the theoretical prototype and actual microstrip circuit of the dual-frequency complex impedance transformation circuit at the drain output end of the transistor.

[0017] Furthermore, if the fundamental impedance and the second harmonic impedance of the two working frequency bands verified in S9 do not fall within the set range close to the target source impedance, return to S7 to redesign the theoretical prototype and the actual microstrip circuit of the dual-frequency complex impedance transformation circuit at the input end.

[0018] Furthermore, the drain voltage in the first high efficiency mode is:

[0019]

[0020] Among them, V ds is the drain voltage on the transistor current plane, V dc is the drain supply voltage, V k is the knee voltage, θ is the angular frequency of the voltage waveform, the factor ξ takes values ​​between -1 and 1, and θ1 is used to adjust the phase between the drain voltage and current;

[0021] The drain current tuned by the second harmonic source impedance in the first high efficiency mode is:

[0022]

[0023] Where α is the conduction angle, I P is the peak current, γ is the ratio of the second harmonic source voltage to the fundamental voltage, β is the zero-crossing cutoff angle, i r2 is the real part of the second harmonic drain current;

[0024] The zero-crossing cut-off angle β and the real part of the second harmonic drain current i r2 They are:

[0025]

[0026] Further, the drain fundamental output impedance Z is obtained according to the drain voltage in the first mode, the drain current tuned by the second harmonic source impedance, the zero-crossing cutoff angle and the real part of the second harmonic drain current. 1,mode1 , second harmonic output impedance Z 2,mode1 , fundamental wave output power P out,mode1 and drain efficiency η mode1 :

[0027]

[0028] Furthermore, α, γ, and V are selected. dc 、V k ,I p The value of ξ is obtained to obtain the fundamental output power and drain efficiency of the transistor when the factor ξ is between -1 and 1 and the phase θ1 is between -20° and 20°.

[0029] Furthermore, the drain voltage in the second high efficiency mode is:

[0030]

[0031] Among them, χ takes values ​​between -1 and 1, V ds is the drain voltage on the transistor current plane, V dc is the drain supply voltage, V k is the knee voltage, θ is the angular frequency of the voltage waveform;

[0032] The drain current tuned by the second harmonic source impedance in the second high efficiency mode is:

[0033]

[0034] Among them, the factor δ takes values ​​between -1 and 1, α is the conduction angle, and I P is the peak current, γ is the ratio of the second harmonic source voltage to the fundamental voltage, β is the zero-crossing cutoff angle, i r2 is the real part of the second harmonic drain current.

[0035] Further, the drain fundamental output impedance Z is obtained according to the drain voltage in the second mode, the drain current tuned by the second harmonic source impedance, the zero-crossing cutoff angle and the real part of the second harmonic drain current. 1,mode2 , second harmonic output impedance Z 2,mode2 , fundamental wave output power P out,mode2 and drain efficiency η mode2 :

[0036]

[0037]

[0038] in:

[0039]

[0040] Furthermore, α, γ, and V are selected. dc 、V k ,I p The value of is used to obtain the fundamental output power and drain efficiency when the factor δ is between -1 and 1 and the factor χ is between 0 and 1.

[0041] Furthermore, the design spaces of the fundamental output impedance and the second harmonic output impedance when the drain efficiency is higher than 70% and the fundamental output power is higher than 40 dBm in two high-efficiency modes are respectively selected as the optimal drain impedance design space.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The design method of the wide-band ratio dual-frequency high-efficiency power amplifier designs a first high-efficiency mode and a second high-efficiency mode based on a drain voltage on a transistor drain current plane and a drain current tuned by a second harmonic source impedance, obtains an optimal drain impedance design space according to fundamental wave output power and drain efficiency in the two modes, facilitates selection of two wide-band ratio operating frequency bands based on the optimal drain impedance design space, and designs a wide-band ratio dual-frequency complex impedance conversion circuit to meet the design requirements of the dual-frequency high-efficiency power amplifier. The wide-band ratio dual-frequency high-efficiency power amplifier has a wide range of selectable operating frequencies and is convenient to design. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a normalized drain voltage and current waveform diagram of the first high efficiency mode of the present invention;

[0045] Figure 2 is a diagram of fundamental wave output power and drain efficiency varying with factor ξ and phase θ1 in the first high efficiency mode of the present invention;

[0046] Figure 3 is a normalized drain voltage and current waveform diagram of the second high efficiency mode of the present invention;

[0047] Figure 4 is a diagram of fundamental wave output power and drain efficiency varying with factors χ and δ in the second high efficiency mode of the present invention;

[0048] Figure 5 Schematic diagram of drain impedance design space for two high-efficiency modes in an embodiment of the present invention;

[0049] Figure 6The impedance trajectory diagram of the circuit composed of the theoretical prototype of the dual-frequency complex impedance conversion circuit at the output end and the equivalent circuit of the package parasitic parameters on the drain current end face of the simulation transistor and the microstrip form of the dual-frequency complex impedance conversion circuit at the output end designed in the embodiment of the present invention;

[0050] Figure 7 The stable circuit prototype and the theoretical prototype of the input-end dual-frequency complex impedance conversion circuit designed in the embodiment of the present invention and the impedance trajectory diagram of the corresponding end surface of the microstrip form of the simulated input-end dual-frequency complex impedance conversion circuit looking at the source end;

[0051] Figure 8 A wide-bandwidth dual-band high-efficiency power amplifier circuit and a physical prototype diagram designed in an embodiment of the present invention;

[0052] Fig. 9 Theoretical and simulated voltage and current waveforms obtained at the drain current end face of the transistor in the embodiment of the present invention at the working frequency bands of 0.7 GHz and 2.6 GHz respectively;

[0053] Fig.10 The output power P measured by the prototype in the embodiment of the present invention out , Gain and power added efficiency PAE curves changing with frequency;

[0054] Fig.11 The output power P of the prototype in the embodiment of the present invention is measured at the working frequency bands of 0.6 GHz and 2.64 GHz respectively. out , Gain and power added efficiency PAE with input power P in Change graph. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The embodiment of the design method of the wide-band ratio dual-band high-efficiency power amplifier is as follows:

[0057] A design method for a dual-band high-efficiency power amplifier with a wide bandwidth ratio comprises the following specific steps:

[0058] Based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, the first high-efficiency mode is established to obtain the fundamental output power and drain efficiency in this mode. Since the gate capacitance of the transistor changes with the gate voltage and the drain voltage, various harmonic voltages will be generated at the input end of the transistor under large signals, thereby changing the drain current. Among them, the second harmonic voltage has the greatest impact. Therefore, the drain current expression tuned by the second harmonic source impedance is established.

[0059] The drain voltage in this mode is:

[0060]

[0061] Among them, V ds is the drain voltage on the transistor current plane, V dc is the drain supply voltage, V k is the knee voltage, θ is the angular frequency of the voltage waveform, the factor ξ takes values ​​between -1 and 1, θ1 is used to adjust the phase between the drain voltage and the current, when ξ=±1, the waveform of the drain voltage is approximately a half-wave sine waveform;

[0062] The drain current tuned by the second harmonic source impedance in this mode is:

[0063]

[0064] Where α is the conduction angle, I P is the peak current, γ is the ratio of the second harmonic source voltage to the fundamental voltage, β is the zero-crossing cutoff angle, i r2 is the real part of the second harmonic drain current;

[0065] Zero-crossing cutoff angle β and real part of second harmonic drain current i r2 They are:

[0066]

[0067] from Figure 1 It can be seen that when -0.5≤γ≤0 and α=180°, the normalized drain current waveform is approximately a square wave. As the γ value increases in the range of -0.5 to 0, the depression on the current waveform becomes larger, and the shape of the normalized drain voltage waveform can be significantly changed by adjusting the value of the factor ξ.

[0068] According to the above equations (1)-(4), the drain fundamental output impedance Z in this mode is derived 1,mode1 , second harmonic output impedance Z 2,mode1 , fundamental wave output power P out,mode1 and drain efficiency η mode1 for:

[0069]

[0070] In order to make the drain current a square wave, the second harmonic component in the drain current must be 0, so the second harmonic output impedance must be infinite. From the above equations (5)-(8), in order to achieve the flattest square wave current waveform, set α = 180°, γ = -0.5, V dc =28V, V k =2V, I P =2A, the fundamental output power and drain efficiency vary with the factor ξ and phase θ1 respectively as shown in Figure 2 As shown. Figure 2 It can be seen that when the factor ξ approaches -1 and the phase θ1 approaches -20°, or when the factor ξ approaches 1 and the phase θ1 approaches 20°, the fundamental output power and the drain efficiency approach 41.9 dBm and 83.4%.

[0071] A second high-efficiency mode is established based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, and the fundamental output power and drain efficiency in this mode are obtained;

[0072] The drain voltage in this mode is:

[0073]

[0074] Among them, χ takes values ​​between -1 and 1, V ds is the drain voltage on the transistor current plane, V dc is the drain supply voltage, V k is the knee voltage, θ is the angular frequency of the voltage waveform, and when χ=±1, the drain voltage waveform in this mode is a half-wave sine waveform;

[0075] Based on the nonlinear characteristics of the transistor input, the drain current tuned by the second harmonic source impedance in this mode is:

[0076]

[0077] Among them, the factor δ takes values ​​between -1 and 1, α is the conduction angle, and I P is the peak current, γ is the ratio of the second harmonic source voltage to the fundamental voltage, β is the zero-crossing cutoff angle, i r2 is the real part of the second harmonic drain current. From the above formula (10), it can be seen that the drain current waveform is greatly affected by the factor δ.

[0078] By analyzing the above equations (9) and (10), the drain voltage and drain current waveforms of this mode vary greatly with the factors χ and δ, respectively. The normalized drain voltage waveform and normalized drain current waveform are as follows: Figure 3As shown in FIG. 1 , a waveform with a small overlap can be selected from the combinations of these drain voltages and drain currents to construct a high efficiency mode. Therefore, the drain fundamental output impedance Z in this mode is derived. 1,mode2 , second harmonic output impedance Z 2,mode2 , fundamental wave output power P out,mode2 and drain efficiency η mode2 for:

[0079]

[0080] in:

[0081]

[0082] in:

[0083]

[0084] According to the above equations (15) and (16), as γ changes from -0.5 to -0.1, the fundamental output power decreases, but the theoretical drain efficiency increases. In order to achieve higher efficiency, set α = 180°, γ = -0.1, V dc =28V, V k =2V, I p =2.3A, the fundamental output power and drain efficiency change when -1≤δ≤1 and 0≤χ≤1 as shown in Figure 4 As shown, when the factor δ approaches 1 or the factor χ approaches 1, the fundamental output power and the drain efficiency will approach 42.5 dBm and 83.6%.

[0085] According to the theoretical formulas of the two high-efficiency modes, the design space of the fundamental output impedance and the second harmonic impedance when the drain efficiency is higher than 70% and the fundamental output power is greater than 41dBm is obtained, as shown in Figure 5 As shown. Figure 5 It can be seen that in the first high-efficiency mode, the fundamental output impedance increases with the increase of the imaginary part, the drain efficiency increases, and the second harmonic output impedance is at the open point of the Smith chart. In the second high-efficiency mode, the drain efficiency increases with the increase of the real part of the fundamental output impedance or the increase of the imaginary impedance, and the second harmonic output impedance is a pure imaginary number and is distributed along the edge of the Smith chart. Therefore, both high-efficiency modes have a larger optimal drain impedance design space, and the optimal drain impedance design space of the second high-efficiency mode is larger. In summary, Figure 5 As shown, the design space of the fundamental output impedance and the second harmonic impedance when the drain efficiency is higher than 70% and the fundamental output power is higher than 40dBm is selected as the optimal drain impedance design space.

[0086] In order to verify the feasibility of designing a wideband dual-band high-efficiency power amplifier using the above two high-efficiency modes, Cree's GaN HEMT CGH40010F transistor is selected to design a dual-band high-efficiency power amplifier operating at 0.7 and 2.6 GHz. Based on the two operating frequency bands of 0.7 GHz and 2.6 GHz, the theoretical fundamental output impedance and second harmonic output impedance of the two operating frequency bands on the transistor drain current plane (the impedance of the circuit composed of the transistor package parasitic parameter equivalent circuit and the theoretical prototype of the output dual-band complex impedance transformation circuit) are respectively distributed in the optimal drain impedance design space of the first high-efficiency mode and the second high-efficiency mode. At the same time, in order to achieve the goal of high efficiency, it is necessary to select appropriate fundamental source impedance and second harmonic source impedance Z at the two operating frequency bands of 0.7 GHz and 2.6 GHz respectively. S (obtained by source pulling technique). Select the fundamental output impedance and second harmonic output impedance Z within the optimal drain impedance design space L , fundamental wave source impedance and second harmonic source impedance Z S , as shown in Table 1, where the fundamental source impedance and the second harmonic source impedance Z S is the target source impedance.

[0087] Table 1

[0088]

[0089] Considering the parasitic parameters introduced by the transistor package, the equivalent circuit of the CGH40010F transistor package parasitic parameters is established, and the circuit composed of the theoretical prototype of the designed output dual-frequency complex impedance conversion circuit is as follows: Figure 6 As shown in the figure, the equivalent circuit of the package parasitic parameters of the CGH40010F transistor is known in the art. The theoretical prototype of the designed output dual-frequency complex impedance transformation circuit is composed of eight sections of ideal transmission lines, including one section of ideal transmission line with a characteristic impedance of 56.5Ω and a phase length of 26.3° in series and one section of ideal transmission line with a characteristic impedance of 54.1Ω and a phase length of 31.2° in series; a section with a terminal short-circuited to ground and a characteristic impedance of 78.7 is connected in parallel between the two sections of ideal transmission lines in series. An ideal transmission line with a characteristic impedance of 55Ω and a phase length of 35.2° and two cascaded ideal transmission lines with characteristic impedances of 55Ω and 34Ω and phase lengths of 19.1° respectively; an ideal transmission line with a characteristic impedance of 54.1Ω and a phase length of 31.2° and a 50Ω load impedance are connected in parallel with an ideal transmission line with a terminal short-circuited to ground, a characteristic impedance of 36.5Ω and a phase length of 39.7°, and two cascaded ideal transmission lines with characteristic impedances of 50Ω and 94.7Ω and phase lengths of 42° respectively. It should be noted that the phase length of each ideal transmission line in the theoretical prototype of the dual-frequency complex impedance transformation circuit at the output end is the phase length when the operating frequency is 0.7GHz. Figure 6 As shown in Table 1, the theoretical fundamental output impedance and second harmonic output impedance of the 0.7 GHz operating frequency band (located in the optimal impedance space of the first high efficiency mode) and the theoretical fundamental output impedance and second harmonic output impedance of the 2.6 GHz operating frequency band (located in the optimal impedance space of the second high efficiency mode) are selected. Figure 6 In the figure, Z1 is the fundamental output impedance and Z2 is the second harmonic output impedance.

[0090] Using dielectric constant ε r The theoretical prototype of the dual-frequency complex impedance circuit at the output end is designed as a microstrip circuit. The ADS (Advanced Design System) tool is used to perform electromagnetic simulation on the circuit composed of the package parasitic parameter equivalent circuit of the CGH40010F transistor and the designed output dual-frequency complex impedance transformation circuit microstrip form. Figure 6 The impedance on the transistor drain current plane simulated at frequencies of 0.7 GHz, 1.4 GHz, 2.6 GHz, and 5.2 GHz is given, which basically overlaps with the theoretical drain fundamental output impedance and second harmonic output impedance selected at the two operating frequency bands, ensuring that the designed power amplifier operates in the first high efficiency mode in the 0.7 GHz operating frequency band and in the second high efficiency mode in the 2.6 GHz operating frequency band.

[0091] A stable circuit theoretical prototype is formed by a parallel circuit of a 2.2pF capacitor and a 8.2Ω resistor at the gate input of the transistor and an ideal transmission line with a characteristic impedance of 20Ω and a phase length of 9.8°. The stable circuit theoretical prototype is a conventional circuit. According to the requirements of the two high-efficiency modes, Figure 7 The target source impedance Z at 0.7 GHz, 1.4 GHz, 2.6 GHz and 5.2 GHz is obtained by performing source pulling on the end surface as shown in Table 1. s , and then design the theoretical prototype of the input dual-frequency complex impedance transformation circuit with second harmonic source impedance control, such as Figure 7 As shown, it is ensured that the second harmonic source impedance conditions for the two high efficiency modes are met. Figure 7The theoretical prototype of the dual-frequency complex impedance transformation circuit at the middle input end includes a series-connected ideal transmission line with a characteristic impedance of 75.6Ω and a phase length of 20.1° and a series-connected ideal transmission line with a characteristic impedance of 45.6Ω and a phase length of 3.3°; an ideal transmission line with a terminal short-circuited to ground, a characteristic impedance of 94.2Ω and a phase length of 43.9° and an ideal transmission line with an open terminal, a characteristic impedance of 29.1Ω and a phase length of 35° are connected in parallel between the 50Ω input source impedance and the ideal transmission line with a characteristic impedance of 75.6Ω and a phase length of 20.1°; an ideal transmission line with a terminal short-circuited to ground, a characteristic impedance of 22.8Ω and a phase length of 33.2° and two cascaded ideal transmission lines with characteristic impedances of 80Ω and 49.5Ω respectively and phase lengths of 19.1° are connected in parallel between the two series-connected ideal transmission lines.

[0092] It should be noted that the phase length of each ideal transmission line in the theoretical prototype of the stable circuit and the theoretical prototype of the input-end dual-frequency complex impedance conversion circuit is the phase length when the operating frequency is 0.7GHz. The same F4BM-220 substrate with a thickness of 0.762mm is used to design the theoretical prototype of the stable circuit and the theoretical prototype of the input-end dual-frequency complex impedance circuit into a microstrip circuit form. Figure 7 The designed circuit is given. Through electromagnetic simulation, the source impedances of 0.7 GHz, 1.4 GHz, 2.6 GHz and 5.2 GHz on the specified end face are basically overlapped with the target source impedance. Finally, the circuit and physical prototype of a dual-band high-efficiency power amplifier working at 0.7 and 2.6 GHz are obtained. Figure 8 When the gate voltage of the transistor is -2.9V and the supply voltage is 28V, the drain voltage and current time domain waveforms on the drain current plane of the transistor obtained by simulation and theoretical calculation at the two operating frequency bands of 0.7 and 2.6GHz are shown in the figure below. Fig. 9 As shown, the results show that the waveforms of the two frequency bands are basically consistent with the theoretical ones.

[0093] A single carrier is used as the stimulus to conduct a large signal test on the object, and the measured output power P out , Gain and power efficiency PAE change with frequency as follows Fig.10As shown. In the frequency range of 0.5 to 1 GHz, the excitation power of a single carrier is set to 24.7 dBm. When the test frequency is 0.7 GHz, the output power is 41.9 dBm and the power added efficiency reaches 83.2%. In the frequency range of 2 to 3 GHz, the excitation power of a single carrier is set to 29.7 dBm. When the test frequency is 2.64 GHz, the output power is 40.9 dBm and the power added efficiency reaches 71.9%. The test results show that the prototype achieves the design goal of high efficiency in the two working frequency bands of 0.7 and 2.64 GHz. There is a slight deviation in the target frequency of the high frequency band, which is mainly affected by the circuit processing error.

[0094] Fig.11 The output power P of the designed dual-band high-efficiency power amplifier at 0.7 and 2.64 GHz is given. out , the dynamic change characteristics of gain and power added efficiency PAE with input power. From the results, it can be seen that with the continuous increase of input power, the output power and power added efficiency of the two frequency bands tend to saturation. When the power added efficiency reaches 83.2% and 71.9% in the two frequency bands of 0.7 and 2.64GHz, the gain is 17.2 and 11.2dB respectively.

[0095] Table 2

[0096]

[0097]

[0098] Table 2 shows the performance comparison of the designed dual-band high-efficiency power amplifier and the existing dual-band high-efficiency power amplifiers at home and abroad in recent years. Compared with the dual-band high-efficiency power amplifiers of Comparative Examples 1, 5 and 6, the power added efficiency of the two frequency bands of the designed prototype in this embodiment is significantly higher, and the frequency ratio of the two working frequency bands of the designed prototype is 3.8, which is higher than the frequency ratios of all the dual-band high-efficiency power amplifiers in Comparative Examples 1 to 6.

[0099] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A design method for a dual-band high-efficiency power amplifier with a wide bandwidth ratio, characterized in that: The specific steps include: S1, based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, establish a first high efficiency mode, and obtain the fundamental output power and drain efficiency in this mode; The drain voltage in the first high efficiency mode is: ； in, is the drain voltage on the transistor current plane, is the drain supply voltage, is the knee voltage, is the angular frequency of the voltage waveform, the factor The value is between -1 and 1. Used to adjust the phase between drain voltage and current; The drain current tuned by the second harmonic source impedance in the first high efficiency mode is: ； in, is the conduction angle, is the peak current, is the ratio of the second harmonic source voltage to the fundamental voltage, is the zero-crossing cut-off angle, is the real part of the second harmonic drain current; The zero crossing cut-off angle and the real part of the second harmonic drain current They are: ； ； S2, based on the drain voltage on the drain current plane of the transistor and the drain current tuned by the second harmonic source impedance, establish a second high efficiency mode, and obtain the fundamental output power and drain efficiency in this mode; The drain voltage in the second high efficiency mode is: ； in, The value is between -1 and 1. is the drain voltage on the transistor current plane, is the drain supply voltage, is the knee voltage, is the angular frequency of the voltage waveform; The drain current tuned by the second harmonic source impedance in the second high efficiency mode is: ； Among them, the factor The value is between -1 and 1. is the conduction angle, is the peak current, is the ratio of the second harmonic source voltage to the fundamental voltage, is the zero-crossing cut-off angle, is the real part of the second harmonic drain current; S3. Obtain the fundamental output impedance and the second harmonic output impedance according to the drain voltage and the drain current on the current plane of the two high-efficiency modes transistors, and determine the optimal drain impedance design space in the two modes according to the requirements of the fundamental output power and the drain efficiency; S4, selecting two operating frequency bands, designing a theoretical prototype of a dual-frequency complex impedance conversion circuit at the drain output end of the transistor, so that the fundamental output impedance and the second harmonic output impedance of the corresponding two operating frequency bands on the transistor drain current plane fall within the optimal drain impedance design space; S5. For the theoretical prototype of the designed output-end dual-frequency complex impedance conversion circuit, a substrate is selected for microstrip circuit design to obtain a microstrip circuit form of the output-end dual-frequency complex impedance conversion circuit; S6, simulating and obtaining the fundamental output impedance and second harmonic output impedance of the circuit composed of the transistor package parasitic parameter equivalent circuit and the output end dual-frequency complex impedance conversion circuit microstrip form in two corresponding working frequency bands, and verifying whether the fundamental output impedance and second harmonic output impedance of the two working frequency bands obtained fall into the optimal drain impedance space, if so, proceed to the next step; S7. Based on the theoretical prototype of the dual-frequency complex impedance conversion circuit at the output end, a stable circuit theoretical prototype and a theoretical prototype of the dual-frequency complex impedance conversion circuit at the input end with second harmonic source impedance control are designed according to the two high-efficiency modes; S8. According to the two selected working frequency bands, for the theoretical prototype of the stable circuit and the theoretical prototype of the designed input-end dual-frequency complex impedance conversion circuit, select the same substrate as in step S5 to perform microstrip circuit design, and obtain the microstrip circuit form of the stable circuit and the input-end dual-frequency complex impedance conversion circuit; S9. Simulate and obtain the fundamental impedance and second harmonic impedance of the dual-frequency complex impedance conversion circuit at the input end, and verify whether the fundamental impedance and second harmonic impedance of the two working frequency bands obtained fall within the set range close to the target source impedance. If so, obtain a power amplifier.

2. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 1, characterized in that: If the fundamental output impedance and the second harmonic output impedance of the two working frequency bands verified in S6 do not fall into the optimal drain impedance space, return to S4 and redesign the theoretical prototype and actual microstrip circuit of the dual-frequency complex impedance transformation circuit at the transistor drain output end.

3. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 1, characterized in that: If the fundamental impedance and second harmonic impedance of the two working frequency bands verified in S9 do not fall within the set range close to the target source impedance, return to S7 to redesign the theoretical prototype and actual microstrip circuit of the dual-frequency complex impedance transformation circuit at the input end.

4. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 1, characterized in that: The drain fundamental output impedance is obtained according to the drain voltage in the first mode, the drain current tuned by the second harmonic source impedance, the zero-crossing cutoff angle and the real part of the second harmonic drain current. , Second harmonic output impedance , Fundamental wave output power and drain efficiency : ； ； ； 。 5. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 4, characterized in that: Select α , γ , V dc , V k , I p The value of , get the factor Between -1 and 1, phase Fundamental output power and drain efficiency of the transistor between -20° and 20°.

6. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 1, characterized in that: The drain fundamental output impedance is obtained according to the drain voltage in the second mode, the drain current tuned by the second harmonic source impedance, the zero-crossing cutoff angle and the real part of the second harmonic drain current: , Second harmonic output impedance , Fundamental wave output power and drain efficiency : ； ； ； ； in: ； 。 7. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 6, characterized in that: Select α , γ , V dc , V k , I p The value of , get the factor Between -1 and 1, factor Fundamental output power and drain efficiency between 0 and 1.

8. The design method of a dual-band high-efficiency power amplifier with a wide bandwidth ratio according to claim 1, characterized in that: The design spaces of fundamental output impedance and second harmonic output impedance when the drain efficiency is higher than 70% and the fundamental output power is higher than 40dBm in two high-efficiency modes are selected as the optimal drain impedance design space.

Images