Test method and device and storage medium

Abstract

The invention discloses a test method and device and a storage medium, and the method comprises the steps: bypassing a to-be-tested device through a selector, so as to form a bypass circuit between a data input interface and a data output interface of the to-be-tested device; the observation circuit and the control circuit are arranged in the bypass circuit and a data input channel and a data output channel of the to-be-tested device in a scanning chain mode, the control circuit and the observation circuit are independently arranged, and a clock buffer is inserted into a common clock channel of the control circuit and the observation circuit. The observation circuit does not have a next-stage high-frequency clock path, and the previous-stage high-frequency clock path of the control circuit is simple, so that the time sequence convergence of a register is easy to meet, and when a time sequence violation phenomenon occurs, the time sequence can be accurately controlled by adjusting a clock tree of a clock buffer arranged in the control circuit and the observation circuit. The time sequence conflict problem of the register and the memory can be solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a testing method, device and storage medium. Background Art

[0002] Existing integrated circuit designs contain a large number of memory cells, which can account for 50% or more of the total area. In Design for Testability (DFT) testing, memory built-in-self test (MBIST) circuits are typically used to cover possible memory cell faults. However, these circuits cannot cover faults in the functional path to the memory interface. Therefore, to cover memory interface faults, scan chain testing is typically used for the memory functional path. However, because it is difficult to directly generate scan chain test vectors from the memory to cover surrounding logic faults, memory bypass circuits are added to cover surrounding logic faults. For example, a beat register is added as an observation circuit and control circuit to implement fault testing of the functional path.

[0003] However, in the functional path testing method of the existing memory, the beat register serves as both a control register and an observation register, and there are high-frequency timing convergence paths before and after. In addition, due to the timing coupling with the memory, the timing of the beat register is difficult to converge at high frequencies. Although the timing paths passed by the memory and the beat register are basically the same, the different requirements of the register and the memory for setup time and hold time may lead to timing conflicts. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a test method, device and storage medium, by independently setting the control register and the observation register and inserting a clock buffer on the common clock path. Since the observation register does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control register is simple, it is easy to meet the timing convergence of the register. When a timing violation occurs, the timing conflict problem between the register and the memory can be solved by adjusting the clock tree of the clock buffer set in the register.

[0005] To achieve the above-mentioned object, a first embodiment of the present invention provides a test device, comprising an observation circuit, a control circuit, a selector, and clock buffers respectively provided in the observation circuit and the control circuit; wherein,

[0006] The selector is provided at the data input interface and the data output interface of the device under test, and is used to bypass the device under test to form a bypass circuit between the data input interface and the data output interface; the observation circuit and the control circuit are provided in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain, and the output of the observation circuit serves as one of the inputs of the control circuit;

[0007] The clock buffer is used to adjust the timing of registers in the observation circuit and the control circuit;

[0008] The control circuit is used to output control stimuli to the logic circuits in the data input path and the data output path, so that the logic circuits output corresponding operation result values;

[0009] The observation circuit is used to output the operation result value of the logic circuit, so as to obtain the test result of the corresponding logic circuit by comparing the operation result value with the expected value corresponding to the control stimulus.

[0010] In this embodiment, selectors are provided at the data input interface and data output interface of the device under test. A multiplexer (MUX) is an electronic device that can select and convert multiple input signals into a single output signal. Therefore, when the data input interface and data output interface of the device under test are connected to the selector, the data input and data output paths of the device under test are effectively removed from the original circuit, bypassing the device under test and forming a bypass circuit between the data input interface and data output interface of the device under test. In this case, one of the input data of the selector is the input data transmitted to the device under test by the data input path. In addition to being transmitted to the device under test, the output data of the selector can also be input into the bypass circuit. Thus, the bypass circuit can intercept data from the data input interface of the device under test for subsequent measurement, thereby determining the fault status of the logic circuit of the device under test. The control circuit can also input a control stimulus, thereby enabling the logic circuit after the data output interface to output a corresponding value to the observation circuit for observation. Through this bypass circuit, fault detection of the functional paths of the device under test can be covered, thereby improving the fault detection coverage of the functional paths. In addition, the observation circuit and the control circuit are arranged in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain. By setting the control circuit and the observation circuit independently and inserting a clock buffer on the common clock path of the control circuit and the observation circuit, since the observation circuit does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control circuit is simple, it is easy to meet the timing convergence of the register. When a timing violation occurs, the timing conflict problem between the register and the device under test can be solved by adjusting the clock tree of the clock buffer arranged in the control circuit and the observation circuit.

[0011] In a possible implementation of the first aspect, the test device includes a first control circuit arranged in the bypass circuit, and at least one second control circuit arranged before the logic circuit; the test device includes a first observation circuit arranged in the bypass circuit, and at least one second observation circuit arranged after the logic circuit.

[0012] In this embodiment, there are multiple observation circuits and control circuits. When there are multiple logic circuits in the functional path of the device under test, multiple observation circuits and control circuits can also be set up, so as to cover all logic circuits of the device under test that require fault detection, thereby improving the fault detection coverage of the functional path.

[0013] In a possible implementation manner of the first aspect, each observation circuit includes at least one observation register, and a clock buffer is provided on a common clock path of the observation registers.

[0014] The observation circuit in this embodiment is composed of at least one observation register, and these observation registers have a one-to-many relationship with the clock buffer. That is to say, when there is a timing violation between the observation register and the device under test, only this one clock buffer needs to be adjusted to complete the timing adjustment of all observation registers, so there is no need to adjust the timing of the observation registers one by one. While solving the timing conflict problem between the observation register and the device under test, the efficiency of the timing adjustment can also be improved.

[0015] In a possible implementation manner of the first aspect, each control circuit includes at least one control register, and a clock buffer is provided on a common clock path of the control registers.

[0016] The control circuit in this embodiment is composed of at least one control register. These control registers have a one-to-many relationship with the clock buffer. That is, when there is a timing violation between the control register and the device under test, the timing adjustment of all control registers can be completed by adjusting this one clock buffer, and there is no need to adjust the timing of the control registers one by one. While resolving the timing conflict problem between the control register and the device under test, the efficiency of the timing adjustment can also be improved.

[0017] In a possible implementation manner of the first aspect, in the bypass circuit, the number of observation registers in each observation circuit is equal to the number of control registers in the control circuit.

[0018] In this embodiment, the number of observation registers and control registers corresponds one to one, so that the input data of the SI interface of each observation register can correspond to the input of the SI interface of a control register, one-to-one control, and thus the output control stimulus is also one-to-one corresponding.

[0019] In a possible implementation of the first aspect, the observation register in each observation circuit includes a first observation input terminal, a second observation input terminal and an observation output terminal; wherein the first observation input terminal is used to input the operation result value, and the second observation input terminal is used to input the control stimulus; when the observation register operates in a first state, the observation register is used to capture the input data of the first observation input terminal; when the observation register operates in a second state, the observation output terminal is used to output the input data of the first observation input terminal and the second observation input terminal.

[0020] This embodiment provides a working mode of an observation circuit, through which the observation register can shift the output value of the logic circuit in the functional path for comparison, thereby realizing the observation function, and drawing a conclusion on whether the logic circuit located in front of it is faulty, and can input control stimulus to the corresponding control register through the SI interface of the observation register.

[0021] In a possible implementation of the first aspect, the control register in each control circuit includes a first control input terminal, a second control input terminal and a control output terminal; wherein the second control input terminal is connected to the observation output terminal of the observation register in the corresponding observation circuit; when the control register operates in a first state, the control register is used to capture input data of the first control input terminal; when the control register operates in a second state, the control output terminal is used to output input data of the first control input terminal and the second control input terminal.

[0022] This embodiment provides a control circuit operating method in which a control register can input a desired control stimulus to a logic circuit located behind it, causing the logic circuit to output a corresponding value. An observation circuit then compares the logic circuit output value with the expected value to determine if it is consistent. If not, the logic circuit is deemed faulty. By inputting control stimuli into the control circuit, the fault coverage of the logic circuit can be improved, for example, improving the fault coverage of transition tests while reducing the number of vectors.

[0023] In a possible implementation manner of the first aspect, the first state is a capture state, and the second state is a shift state.

[0024] In this embodiment, by setting the first state to a capture state and the second state to a shift state, the registers in the observation circuit and the control circuit can input or output corresponding data.

[0025] In a possible implementation manner of the first aspect, an inverter is provided in the control register, and the control output end of the control register is connected to the first control input end through the inverter.

[0026] The inverter configuration in this embodiment can increase the number of output flips in the control circuit, such as 0 to 1 or 1 to 0. This flipped data can be input into the logic circuit located after the control circuit to complete the test of the logic circuit. Therefore, the configuration of the inverter can improve fault coverage.

[0027] In a possible implementation of the first aspect, the test device also includes a compression circuit provided in the bypass circuit, wherein the compression circuit is used to receive at least two calculation result values, and compress the at least two calculation result values ​​and send them to the first observation circuit in the bypass circuit, so that the first observation circuit outputs corresponding compressed data.

[0028] The presence of the compression circuit in this embodiment can reduce the layout area of ​​the test equipment. If the device under test has a small number of data input interfaces, such as only one or two, the compression circuit can be omitted and the input data from the data input interfaces can be directly output for subsequent observation operations. However, if the device under test has a large number of data input interfaces, a compression circuit is required to perform a one-or-two data selection operation. After the compression circuit is implemented, the number of observation circuits and control circuits located at its rear end can be reduced, thereby reducing the layout area of ​​the device under test.

[0029] In a possible implementation manner of the first aspect, the number of compression stages of the compression circuit is positively correlated with the number of data input interfaces of the device under test.

[0030] In this embodiment, the compression levels of the compression circuit are arranged according to the number of data input interfaces of the device under test, so that the data compression of the compression circuit is reasonable, while reducing the layout area of ​​the device under test and ensuring the normal output of the input data of the device under test.

[0031] In a possible implementation manner of the first aspect, clock signals of each observation circuit, each control circuit, and the device under test are synchronized.

[0032] In this embodiment, timing synchronization can be achieved by arranging that the clock signal CLK of each observation circuit, each control circuit, and the device under test has the same source.

[0033] In a possible implementation manner of the first aspect, the device under test is a memory.

[0034] To achieve the above object, a second embodiment of the present invention provides a testing method, which is applied to the testing device described in any of the above embodiments, and the method further includes:

[0035] Adjust the working status of all observation circuits and all control circuits;

[0036] When all observation circuits and all control circuits operate in a first state, each observation circuit captures a calculation result value of a corresponding logic circuit, and each control circuit captures input data at its input terminal;

[0037] When all observation circuits and all control circuits operate in the second state, each observation circuit shifts and outputs the captured calculation result value and compares it with the expected value corresponding to the control stimulus to obtain the test result of the corresponding logic circuit; and each control circuit shifts and outputs the corresponding control stimulus to transmit the control stimulus to the corresponding logic circuit.

[0038] This embodiment provides a testing method using the testing equipment described in the above embodiment. With this testing method, since the observation register does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control register is simple, it is easy to meet the timing convergence of the register.

[0039] In a possible implementation of the second aspect, the method includes:

[0040] When it is detected that the device under test and the register meet a timing violation condition, a clock tree of the clock buffer is adjusted.

[0041] In this embodiment, when a timing violation occurs, the timing conflict problem between the register and the memory can be solved by adjusting the clock tree of the clock buffer provided in the register.

[0042] To achieve the above objectives, a third aspect of the present invention provides a computer-readable storage medium having a program stored thereon, which, when called, enables a computer to execute the test method as described in any of the above embodiments.

[0043] Compared with the prior art, the test method, device and storage medium disclosed in the present invention bypass the device under test by using a selector to form a bypass circuit between the data input interface and the data output interface of the device under test, so that the data of the input interface of the data of the device under test can be intercepted through the bypass circuit for subsequent measurement, thereby obtaining the fault condition of the logic circuit of the device under test, and using the control circuit input control stimulus to enable the logic circuit after the data output interface to output the corresponding value to the observation circuit for observation. Through the bypass circuit, the fault detection of the functional path of the device under test can be covered, thereby improving the fault detection coverage of the functional path. In addition, the observation circuit and the control circuit are arranged in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain. By setting the control circuit and the observation circuit independently and inserting a clock buffer on the common clock path of the control circuit and the observation circuit, since the observation circuit does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control circuit is simple, it is easy to meet the timing convergence of the register. When a timing violation occurs, the timing conflict problem between the register and the device under test can be solved by adjusting the clock tree of the clock buffer arranged in the control circuit and the observation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of using MBIST technology to perform fault detection on a memory in the prior art;

[0045] Figure 2 This is a schematic diagram of the application of the selector when using MBIST technology;

[0046] Figure 3 This is a schematic diagram of using a scan chain to perform logic circuit fault detection in the prior art;

[0047] Figure 4 This is a schematic diagram of using a beat register to perform fault detection on a memory function path in the prior art;

[0048] Figure 5 Schematic diagram of the framework of the device under test and the test device provided by the embodiment of the present invention;

[0049] Figure 6 This is a module diagram of a first test device provided by an embodiment of the present invention;

[0050] Figure 7 is a module schematic diagram of a second test device provided by an embodiment of the present invention;

[0051] Figure 8 is a circuit diagram of an observation circuit provided by an embodiment of the present invention;

[0052] Figure 9 is a circuit diagram of a control circuit provided by an embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of a first interface of a device under test provided by an embodiment of the present invention;

[0054] Figure 11 This is a circuit diagram of a first test device provided by an embodiment of the present invention for performing fault detection on a device under test;

[0055] Figure 12 This is a schematic diagram of a second interface of a device under test provided by an embodiment of the present invention;

[0056] Figure 13 is a schematic diagram of a compression circuit provided by an embodiment of the present invention;

[0057] Figure 14 This is a circuit diagram of a second test device provided by an embodiment of the present invention for performing fault detection on a device under test;

[0058] Figure 15 This is a flow chart of a testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0060] The described device under test of the embodiment of the invention realizes in conjunction with scan chain (scan)+bypass (bypass) mode in mbist technology, because mbist technology can only complete the detection of device under test self fault, can't detect for the fault of functional path (data input path and data output path) of device under test, therefore the functional path of device under test can be bypassed (bypass), add scan chain (scan) then, realize the fault detection to device under test functional path.In order to better set forth the principle of work of the embodiment of the invention, mbist technology and scan chain test mode are briefly introduced.

[0061] See also Figure 1 , Figure 1 The invention discloses a schematic diagram of utilizing MBIST technology to carry out fault detection to memory in the prior art. The newly-added MBIST controller module of MBIST generates specific address (ADDR) / chip select (WE) / read-write enable (ME) / data (D) signal, and then inputs the ADDR / WE / ME / D on the original function path of selector (MUX) bypass. The original function path signal of memory is connected on the MUX I0 port, and the ADDR / WE / ME / D that the MBIST controller generates is connected respectively on the MUX I1 port. The S (selection end) of MUX is connected by the BIST_EN signal of controller output, and the memory output Q loopback is connected to the MBIST control. Figure 2 The specific bypass circuit design of ADDR / WE / ME / D signals is given. Since ADDR / D has a multi-bit width design, multiple MUXs need to be inserted. During MBIST testing, by configuring BIST_EN to 1, the MBIST controller outputs ADDR / WE / ME / D to perform read and write operations on the memory, and performs data comparison on the memory output Q. Assuming that the MBIST control output D is 1, the output Q should be expected to be 1 after passing through the output of the memory unit. If the actual value of output Q is 1, which is equal to the expected value, it indicates that the storage function of the memory is normal. If the actual value of output Q is 0, which is different from the expected value, it indicates that the storage function of the memory is abnormal. The same test method is used for the remaining ADDR / WE / ME interfaces. Through this test method, the self-test function of memory unit failure is realized.

[0062] The scan chain connects the output Q of the register to the input SI signal of the next register, so that when SE is 1, a scan chain is formed. The scan chain tests each vector mainly through two processes: shift and capture. During the shift, the SE signal is high, and all registers will be connected together through the Q to SI path. In this way, all registers can be set to the desired value by controlling the scan in (scan input) at the source (this action is control). Then in the capture process, the SE signal is low, and the register will collect the value of the input signal D input. This value is obtained after being assigned a certain input value by the previous combinational logic operation (this action is observation). In the next shift process, SE becomes high. At this time, the previously observed value is shifted to scan out (scan output), and then compared with the expected value. At the same time, scan in will also shift the new value as the next control, and the cycle will continue. For example Figure 3 As shown, if there is only one inverter in the combinational logic 1, register 1 is set to 1 through the shift process. During the shift process, the SI input of register 1 is the output of its own Q. At this time, the Q output of register 1 is 1; through the capture process, register 2 should collect a 0 through the D port (the Q output of register 1 is 1, which is 0 after the action of the inverter and then input to the D of register 2). At this time, the output Q of register 2 should also output 0; through the next shift, register 3 shifts this 0 to scan out for comparison to see if it is 0. If the inverter in the combinational logic 1 is faulty, the value collected by scan out may be 1, so the comparison will be wrong, and it can be determined that there is a problem with the combinational logic 1.

[0063] It's worth noting that register 1's input D has no logic preceding it, so this register only controls the subsequent combinational logic 1 and has no observation function. Register 2 has combinational logic preceding and following it, so it both controls the subsequent combinational logic 2 and observes the preceding combinational logic 1. Register 3 has no combinational logic following it, so it only observes the preceding register 2.

[0064] The existing technology uses a memory bypass circuit to cover the surrounding logic faults, such as Figure 4As shown, a scan chain with tap registers added as observation and control circuits facilitates fault testing of functional paths. The memory's D signal is connected to the tap registers, serving as their inputs. During scan chain testing, these tap registers serve as both observation points for detecting faults at the memory input ports and control points for bypassing the memory's Q output and providing control stimulus. The register CLK is derived from the same source as the memory CLK. Finally, the synchronized tap register output RQ and the memory unit's Q signal are connected to a selector for output selection. By comparing the selector's actual output value with the expected value, the logic circuitry in the memory functional path is tested. Although the memory and registers share the same clock source, this approach does not necessarily resolve timing issues. Timing closure is often difficult to achieve at high-frequency clocks because, in this architecture, the setup and hold timing requirements of the registers and memory differ. This is because the memory and tap registers traverse essentially the same timing path, but their setup and hold requirements differ, potentially leading to timing conflicts. Therefore, it is possible that the timing requirements of the path to the memory are met, but the timing requirements of the path to the register cannot be met. When a timing conflict occurs, if it is at a high frequency, the function (to the memory) timing will often be guaranteed to converge normally first, and the logic timing inserted for testing will be abandoned. As a result, the path to the register will often be abandoned, resulting in the DFT test only covering stuck faults, and no coverage of transition faults. In addition, the test vectors are generated based on the final timing convergence situation. If the timing of this part cannot be converged at the end, then the observation control register cannot be used. The test tool may use other paths to cover this part of the fault, but this is very difficult because there may be no corresponding control and observation points. However, the tool will still try to generate vectors to cover, resulting in an increase in the number of vectors generated by the tool and an increase in the test burden.

[0065] In order to solve the problem of difficult timing convergence in the prior art, the present invention provides a test device 200 using a scan chain and bypass method. The device under test described in the embodiment of the present invention is a memory. The input signal of the device under test 100 is input into a set of registers as an observation circuit, and then a set of registers is created to bypass the output of the device under test as a control circuit. This can decouple the two sets of timing paths and solve the timing conflict problem. Figures 5 and 6 As shown, the test device 200 includes an observation circuit 22 (such as 22a, 22b and 22c), a control circuit 23 (such as 23a, 23b and 23c), a selector 21 (such as 21a and 21b) and a clock buffer respectively provided in the observation circuit 22 and the control circuit 23.

[0066] Specifically, the selector 21 is arranged at the data input interface and the data output interface of the device under test, and the selector 21 is used to bypass the device under test to form a bypass circuit between the data input interface and the data output interface; the observation circuit 22 and the control circuit 23 are arranged in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain.

[0067] Exemplarily, the selector 21 in the embodiment of the present invention is a 2-to-1 selector having two inputs and one output. The bypass of the device under test 100 is realized by the selector 21. The selector 21 includes selectors 21a and 21b. The selector 21a is provided at the data input interface (i.e., D signal interface) of the device under test 100, and the selector 21b is provided at the data output interface (i.e., Q signal interface) of the device under test. When the data input interface is connected to the selector 21a and the data output interface is connected to the selector 21b, it is equivalent to bypassing the device under test 100. The data input path and the data output path of equipment 100 are drawn from original circuit, realize the bypass of device under test, by the effect of selector 21a and 21b, between the data input interface and the data output interface of described device under test 100, form a bypass circuit, at this moment, wherein one road input data of selector 21a is the input data that the data input path is transferred to device under test, another road input data is the output data of mbist controller, and the output data of selector 21a can also be input in the bypass circuit except being able to be delivered to device under test 100. It should be noted that bypass (bypass) is different from main loop, and bypass refers to when function needs, can switch to on another loop and be unlikely to affect the normal operation of load (device under test 100). Device under test 100 is by the data flow path before bypass: data input path-device under test 100-data output path, after bypass, increase a data flow path: data input path-bypass circuit-data output path, utilize this increased data flow path to complete the fault detection to the logical circuit of data input path and data output path in the embodiment of the present invention.

[0068] Exemplarily, when BIST_EN of the selector 21a is 0, the data of the input D of the device under test 100 is the output data of the logic circuit 11a, and now the logic circuits in the data input path and the data output path are fault detected; when BIST_EN of the selector 21a is 1, the data of the input D of the device under test 100 is the output data of the MBIST controller, and now the function of the device under test 100 itself is detected by the MBIST controller; and, when mem_bypass_en of the selector 21b is 0, the output of the selector 21b is the Q output of the device under test 100, and when mem_bypass_en of the selector 21b is 1, the output of the selector 21b is the RQ output of the control circuit 23a. The observation circuit 22a and the control circuit 23a are arranged in the bypass circuit, the control circuit 23b is arranged in the data input path, and the observation circuit 22b is provided with the data output path of the device under test 100.

[0069] For example, since the observation circuit only has an observation function and no subsequent combinational logic to connect it to other register inputs, there's no next-level high-frequency clock path, making it easier to meet register timing closure. This is because register convergence requires considering the timing convergence from the previous-level register to its D-terminal, as well as the timing convergence from its Q output to the next-level register. These two timing analyses must be considered together, and they balance each other. Since the observation circuit lacks combinational logic, it's easier to meet timing closure. Similarly, the control circuit's previous-level high-frequency clock path is simple, making it easier to meet register timing closure.

[0070] Specifically, the output of the observation circuit 22 serves as one of the inputs of the control circuit 23; the control circuit 23 is used to output control excitation to the logic circuit in the data input path and the data output path, so that the logic circuit outputs the corresponding operation result value; the observation circuit 22 is used to output the operation result value of the logic circuit, so as to obtain the test result of the corresponding logic circuit by comparing the operation result value with the expected value corresponding to the control excitation.

[0071] For example, Figure 6The test device 200 shown is used as an example for explanation. A logic circuit 11a is provided in the data input path of the device under test 100, and a logic circuit 11b is provided in the data output path. These two logic circuits can be inverters or other circuits that can perform logical operations. The test device 200 is used to perform fault detection on the logic circuit 11a and the logic circuit 11b. The device under test 100 is bypassed through the selectors 21a and 21b to form a bypass circuit. The bypass circuit is provided with an observation circuit 22a and a control circuit 23a. The input of the logic circuit 11a can be bypassed through the selector to introduce the control circuit 23b, and the output of the logic circuit 11b can be bypassed through the selector to introduce the observation circuit 22b. The control circuits 23a and 23b are used to input control excitation. The control circuit 23b inputs the control excitation to the logic circuit 11a. For example, if the control circuit 23b inputs a signal "1" to the logic circuit 11a, if the logic circuit 11a is an inverter, then the operation result value of the logic circuit 11a is "0" at this time. Then, after the output of the selector 21a, the operation result value of the logic circuit 11a is transmitted to the observation circuit 22a. The observation circuit 22a shifts this operation result value out. The expected output value corresponding to the control excitation "1" is 0. If the actual output value of the observation circuit 22a is also 0, it indicates that the logic circuit 11a has not failed (an inversion operation has been performed). If the actual output value of the observation circuit 22a is 1, it indicates that the logic circuit 11a has failed (no inversion operation has been performed). The control circuit 23a inputs control excitation to the logic circuit 11b. The working principles of the control circuit 23a, the logic circuit 11b and the observation circuit 22b are the same as those described above. By comparing the actual value output by the observation circuit 22b with the expected value, the fault condition of the logic circuit 11b can be known.

[0072] Furthermore, each observation circuit 22 and each control circuit 23 is provided with a clock buffer (clkbuf), which is used to adjust the timing of the registers in the observation circuit 22 and the control circuit 23, and adjust the clock tree of the clock buffer when it is detected that the device under test 100 and the register meet the timing violation condition.

[0073] This embodiment bypasses the device under test (DUT) using a selector to form a bypass circuit between the DUT's data input interface and data output interface. This bypass circuit can then intercept data from the DUT's data input interface for subsequent measurement, thereby determining fault conditions in the DUT's logic circuit. Furthermore, the control circuit can input a control stimulus, causing the logic circuit after the data output interface to output a corresponding value to the observation circuit for observation. This bypass circuit can cover fault detection in all functional paths of the DUT, improving fault detection coverage for these functional paths. Furthermore, the observation circuit and control circuit are provided in the form of a scan chain within the bypass circuit, the DUT's data input path, and the DUT's data output path. By independently providing the control circuit and observation circuit and inserting a clock buffer into their common clock path, register timing closure is easily achieved because the observation circuit lacks a lower-level high-frequency clock path and the control circuit's upper-level high-frequency clock path is simple. Furthermore, when a timing violation occurs, the timing conflict between the register and the DUT can be resolved by adjusting the clock tree of the clock buffers provided in the control circuit and observation circuit.

[0074] Specifically, the clock signals of each observation circuit 22 , each control circuit 23 and the device under test 100 are synchronized.

[0075] In this embodiment, by arranging that the clock signal CLK of each observation circuit 22 , each control circuit 23 and the device under test 100 has the same source, timing synchronization among the three can be achieved.

[0076] Specifically, the test device 200 includes a first control circuit arranged in the bypass circuit, and at least one second control circuit arranged before the logic circuit; the test device 200 includes a first observation circuit arranged in the bypass circuit, and at least one second observation circuit arranged after the logic circuit.

[0077] For example, see Figure 7 , Figure 7 This is a module diagram of the second test device 200 provided in an embodiment of the present invention. Considering that there are multiple logic circuits in the data input path and the data output path of the device under test 100, for each logic circuit, this logic circuit can be bypassed, and then a control circuit is set before the logic circuit, and an observation circuit is set after the logic circuit to realize fault detection of the logic circuit.

[0078] In this embodiment, there are multiple observation circuits and control circuits. When there are multiple logic circuits in the functional path of the device under test, multiple observation circuits and control circuits can also be set up, so as to cover all logic circuits of the device under test that require fault detection, thereby improving the fault detection coverage of the functional path.

[0079] Specifically, each observation circuit 22 includes at least one observation register, with a clock buffer provided on the common clock path of the observation registers. Each observation register in the observation circuit 22 includes a first observation input, a second observation input, and an observation output. The first observation input is used to input the operation result value, and the second observation input is used to input the control stimulus. When the observation register operates in a first state, the observation register is used to capture input data from the first observation input. When the observation register operates in a second state, the observation output is used to output input data from both the first and second observation inputs. The first state is a capture state, and the second state is a shift state.

[0080] For example, see Figure 8 , Figure 8 is a circuit diagram of the observation circuit 22 provided in an embodiment of the present invention, Figure 8The observation circuit 22 shown includes two observation registers, namely Reg11 and Reg12. Reg11 and Reg12 include D, SI, SE, CLK and Q pins respectively, wherein the D pin is the first observation input terminal, used to input the operation result value of the logic circuit in front of it, such as D[0], D[1]; the SI pin is the second observation input terminal, used to input control stimulus, and the tester can decide which data to input. These control stimuli will be transmitted to the control circuit later; the SE pin is used to input the control signal, and Reg11 and Reg12 change their working state (first state or second state) according to the control signal of the SE pin. If the SE signal is low, Reg11 and Reg 12 is in the first state (capture state), the SE signal is high, and Reg11 and Reg12 are in the second state (shift state); the CLK pin is used to input the clock signal MCLK, which is the same as the clock signal input to the CLK pin of the device under test 100; the Q pin is an observation output terminal, used to output the input data of the D pin or the SI pin. For example, when Reg11 and Reg12 are in the first state (capture state), Reg11 and Reg12 capture the input data of the D pin; when Reg11 and Reg12 are in the second state (shift state), the Q pin outputs the input data of the D pin for comparison, and outputs the input data of the SI pin. A clock buffer, Clkbuf1, is located on the common clock path between Reg11 and Reg12. If setup or hold timing violations occur in observation registers Reg11 and Reg12, the clock tree can be lengthened or shortened at Clkbuf1. Two observation registers are connected after Clkbuf1. In most cases, timing violations across multiple control registers or observation registers are consistent: either setup or hold violations. With this shared Clkbuf1, timing violations across multiple observation registers can be addressed by adjusting only this Clkbuf1. For example, if setup timing violations occur in observation registers Reg11 and Reg12, inserting a certain number of Clkbuf1s after this Clkbuf1, thus lengthening the clock tree, can resolve the violations across multiple observation registers without requiring individual processing for each observation register.

[0081] The observation circuit in this embodiment comprises at least one observation register. These observation registers have a one-to-many relationship with clock buffers. This means that when a timing violation occurs between an observation register and the device under test, adjusting the timing of all observation registers is sufficient by adjusting only this one clock buffer. This eliminates the need to adjust the timing of each observation register individually, resolving the timing violation between the observation register and the device under test while also improving resolution efficiency. Furthermore, this embodiment provides an observation circuit operating mode in which the observation register can shift the output value of a logic circuit in a functional path for comparison, thereby implementing an observation function and determining whether the preceding logic circuit is faulty. Furthermore, control stimuli can be input to the corresponding control register via the observation register's SI interface.

[0082] Specifically, each control circuit 23 includes at least one control register, with a clock buffer provided on the common clock path of the control registers. Specifically, the control register in each control circuit 23 includes a first control input, a second control input, and a control output. The second control input is connected to the observation output of the corresponding observation register in the observation circuit. When the control register operates in a first state, the control register is used to capture input data from the first control input. When the control register operates in a second state, the control output is used to output input data from both the first and second control inputs. The first state is a capture state, and the second state is a shift state.

[0083] For example, see Figure 9 , Figure 9 is a circuit diagram of the control circuit 23 provided in an embodiment of the present invention, Figure 9The control circuit 23 shown includes two observation registers, namely Reg21 and Reg22, Reg21 and Reg22 respectively include D, SI, SE, CLK and Q pins, wherein the D pin is the first control input terminal, used to input the output value of the Q pin; the SI pin is the second control input terminal, used to input the control stimulus output by the observation circuit, such as the SI pin of the control register Reg21 is connected to the Q pin of the observation register Reg11, and the SI pin of the control register Reg22 is connected to the Q pin of the observation register Reg12; the SE pin is used to input the control signal, and Reg21 and Reg22 change their working state (first state or second state) according to the control signal of the SE pin, such as the SE signal When the SE signal is low, Reg21 and Reg22 are in the first state (capture state); when the SE signal is high, Reg21 and Reg22 are in the second state (shift state); the CLK pin is used to input the clock signal MCLK, which is the same as the clock signal input by the CLK pin of the device under test 100; the Q pin is a control output terminal, used to output the input data of the D pin or the SI pin. For example, when Reg21 and Reg22 are in the first state (capture state), Reg21 and Reg22 capture the input data of the D pin; when Reg21 and Reg22 are in the second state (shift state), the Q pin outputs the input data of the D pin and the input data of the SI pin. A clock buffer, Clkbuf2, is provided on the common clock path between Reg21 and Reg22. If setup or hold timing violations occur in control registers Reg21 and Reg22, the clock tree can be lengthened or shortened at Clkbuf2. Two control registers are connected behind Clkbuf2. In most cases, timing violations across multiple control registers or observation registers are consistent: either setup or hold violations. With this shared Clkbuf2, timing violations across multiple control registers can be addressed by adjusting only this Clkbuf2. For example, if hold timing violations occur in control registers Reg21 and Reg22, inserting a certain number of Clkbuf2s behind this Clkbuf2, thus lengthening the clock tree, can resolve the violations across multiple control registers without requiring individual processing for each control register.

[0084] The control circuit in this embodiment is composed of at least one control register. These control registers have a one-to-many relationship with the clock buffer. That is, when there is a timing violation between the control register and the device under test, only adjusting this one clock buffer can complete the timing adjustment of all control registers, eliminating the need to adjust the timing of the control registers one by one. This not only solves the timing violation problem between the control register and the device under test, but also improves the efficiency of solving the timing violation problem. In addition, this embodiment provides a control circuit operating method, through which the control register can input the desired control stimulus to the logic circuit located behind it, thereby causing the logic circuit to output the corresponding value. The observation circuit then compares the value output by the logic circuit with the expected value to see if they are consistent. If they are inconsistent, the logic circuit is determined to be faulty. By inputting the control stimulus to the control circuit, the fault coverage of the logic circuit can be improved, such as improving the fault coverage of the transition test and reducing the number of vectors. In addition, due to timing convergence, there is no need to abandon the path to the register, which can improve the fault coverage of the transition test pattern and reduce the number of vectors, thereby reducing the chance of escape during chip testing, improving the yield of chip testing, and reducing unnecessary economic losses caused by escaped faulty chips.

[0085] Furthermore, an inverter is provided in the control register, and the control output end of the control register is connected to the first control input end through the inverter.

[0086] For example, Figure 9 The control circuit shown in FIG21 has an inverter G1 configured on the control register Reg21 and an inverter G2 configured on the control register Reg22. The inverter configuration can increase the number of output flips in the control circuit. Taking inverter G1 as an example, assuming that the output RQ[0] of the Q pin of the control register Reg21 is 0, the flip data input to pin D is 1 under the action of inverter G1. If the output RQ[0] of the Q pin of the control register Reg21 is 1, the flip data input to pin D is 0 under the action of inverter G1. This flip data can be used as a control stimulus input to the logic circuit located behind the control circuit, completing the test of the logic circuit. Therefore, the configuration of the inverter can increase the number of control stimulus outputs, thereby improving the fault coverage rate.

[0087] Specifically, the device under test 100 may have multiple data input interfaces and data output interfaces. For a device under test 100 with a small number of input / output interfaces (e.g., only one or two), when the device under test is bypassed via a selector, the input data of the pin D of the device under test inputted into the bypass circuit can be directly inputted into the observation circuit in the bypass circuit, without the need to compress the input data of this pin D. For a device under test 100 with a large number of input / output interfaces, when the device under test is bypassed via a selector, the input data of the pin D of the device under test inputted into the bypass circuit needs to be compressed before being inputted into the observation circuit in the bypass circuit. In this case, a compression circuit needs to be added to the bypass circuit to compress the input data.

[0088] In the first embodiment, the number of input / output interfaces of the device under test 100 is relatively small, such as only two. Figure 10 , Figure 10 This is a schematic diagram of the first interface of the device under test provided by an embodiment of the present invention. The device under test 100 has two data input interfaces, inputting D[0] and D[1] respectively. In this case, only two selectors are required to be set at the data input interface. Correspondingly, the device under test 100 also has only two data output pins, outputting Q[0] and Q[1] respectively. In this case, only two selectors are required to be set at the data output interface. After the observation circuit and the control circuit are introduced into the bypass circuit, the data input path, and the data output path, the circuit diagram of the test device 200 is as shown in FIG. Figure 11 As shown, Figure 11 This is a circuit diagram of a first test device provided by an embodiment of the present invention for performing fault detection on a device under test. In the bypass circuit, the number of observation registers in each observation circuit is equal to the number of control registers in the control circuit. The D[0] output of the device under test 100 is directly input into pin D of observation register Reg11, and the Q pin of observation register Reg11 is connected to the SI pin of control register Reg21. The D[1] output of the device under test 100 is directly input into pin D of observation register Reg12, and the Q pin of observation register Reg12 is connected to the SI pin of control register Reg22.

[0089] For example, control circuit 23b may have only one control register, which corresponds to logic circuit 11a. Alternatively, control circuit 23b may be identical to control circuit 23a and may also have two control registers, one corresponding to logic circuit 11a and the other corresponding to a logic circuit in another data input path. The same applies to observation circuit 22b. Assume that the fault conditions of logic circuits 11a and 11b are to be detected. First, a control stimulus, such as a signal "1", is input to control circuit 23b. If logic circuit 11a is an inverter, the operation result value of logic circuit 11a is "0". After the output of selector 21a, the operation result value of logic circuit 11a is transmitted to observation register Reg11. Control SE is a low signal. At this time, observation register Reg11 operates in the first state (capture state). Observation register Reg11 captures the operation result value of logic circuit 11a. Then control SE is a high signal. At this time, observation register Reg11 operates in the second state (shift state). The Q pin of observation register Reg11 shifts this operation result value. Since the expected output value corresponding to the control stimulus "1" is 0, if the actual output value of the Q pin of Reg11 is also 0, it indicates that logic circuit 11a has not failed (inversion operation has been performed). If the actual output value of the Q pin of Reg11 is 1, it indicates that logic circuit 11a has failed (inversion operation has not been performed). For fault detection of logic circuit 11b, it is necessary to test it by inputting control stimulus through control register Reg21. At this time, SE needs to be controlled to be a high signal. At this time, both observation register Reg11 and control register Reg21 are working in the second state (shift state). SI pin of Reg11 inputs control stimulus, and then Reg11 shifts SI control stimulus out through Q pin, and inputs this control stimulus from SI pin of control register Reg21. Q pin of Reg21 shifts this control stimulus out again, and through selector 21b (mem_bypass_en is set to 1), this control stimulus is transmitted to logic circuit 11b, and finally the actual output value is compared with the expected value through observation circuit 22b, so that the fault condition of logic circuit 11b can be known.

[0090] In this embodiment, the number of observation registers and control registers corresponds one-to-one, allowing the input data of each observation register's SI interface to correspond to the input of a control register's SI interface, resulting in a one-to-one control and, consequently, a one-to-one correspondence between the output control stimulus. Furthermore, because the device under test 100 has relatively few input / output interfaces, the observation circuit can directly input data from the D pin of the device under test 100, eliminating the need for additional data processing and improving test efficiency.

[0091] In the second embodiment, the device under test 100 has a large number of input / output interfaces, such as 8. Figure 12 , Figure 12 This is a second interface diagram of the device under test provided by an embodiment of the present invention. The device under test 100 has 8 data input interfaces, which respectively input D[0] to D[7]. At this time, only 8 selectors are required to be set at the data input interfaces. Correspondingly, the device under test 100 also has 8 data output pins, which respectively output Q[0] to Q[7]. At this time, only 8 selectors are required to be set at the data output interfaces.

[0092] Specifically, the test device 200 further includes a compression circuit disposed in the bypass circuit. The compression circuit is configured to receive at least two calculation result values, compress the at least two calculation result values, and transmit the compressed data to the first observation circuit in the bypass circuit, so that the first observation circuit outputs corresponding compressed data. The number of compression levels of the compression circuit is positively correlated with the number of data input interfaces of the device under test.

[0093] For example, see Figure 13 , Figure 13 This is a schematic diagram of a compression circuit provided by an embodiment of the present invention. The compression circuit is actually a two-choose-one output circuit composed of an XOR gate. Figure 13The compression circuit shown uses two stages of compression. The first stage compresses eight inputs into four outputs, and the second stage compresses four inputs into two outputs. The greater the number of compression stages, the lower the efficiency. For example, if there are eight combinational logic paths (i.e., eight data input interfaces for the device under test), without compression, the corresponding bypass circuit would require eight observation registers and eight control registers. A single pattern (test) can shift out the information observed by the eight combinational logic paths and compare them simultaneously. With one stage of compression, four observation registers and four control registers are required, requiring two pattern runs, each comparing four input data points. With two stages of compression, two observation registers and two control registers are required, requiring four pattern runs, each comparing two input data points. In the embodiment of the present invention, since the device under test 100 has 8 data input interfaces, a two-level compression is adopted. After D[0] to D[1] are compressed by the two-level compression circuit, each pattern outputs two data, namely Z[0] and Z[1], where Z[0] and Z[1] are one of the data in D[0] to D[1]. It is understandable that if the device under test has 16 data input interfaces, a three-level compression can be adopted, and so on, so as to achieve the purpose of reducing the layout area of ​​the test device 200. Of course, if the layout area of ​​the test device 200 is not reduced, and the test efficiency is to be improved, then for the device under test 100 with a large number of input / output interfaces, the compression circuit can be used instead of data compression, and the same number of observation registers and control registers as the number of interfaces can be used to complete the test.

[0094] For example, the embodiment of the present invention also provides a specific application of the compression circuit in the second embodiment, see Figure 14 , Figure 14 This is a circuit diagram of the second test device provided by the embodiment of the present invention for fault detection of the device under test. Since the compression circuit adopts two-stage compression, the number of observation registers and control registers is 2, and the output Z of the compression circuit is connected to the pin D of the observation register. The working principle of the observation register and the control register can be referred to above. Figure 11The corresponding working principle will not be described in detail here, but it should be noted that since the compression circuit adopts two-level compression, each pattern outputs two data, namely Z[0] and Z[1]. The corresponding observation register also outputs QSI[0] and QSI[1], and the control register also outputs RQ[0] and RQ[1]. Since the device under test 100 has 8 data output interfaces, the inputs of the selectors corresponding to these 8 data output interfaces need to correspond to Z[0] and Z[1] outputted by each pattern. For example, in the first pattern, Z[0]=D[0], Z[1]=D[4], then at this time reg11 selects the selector output corresponding to D[0] in the device under test 100 for comparison, and reg12 selects the selector output corresponding to D[4] in the device under test 100 for comparison; if in the second pattern, Z[0]=D[1], Z[1]=D[5], then reg11 selects the selector output corresponding to D[1] in the device under test 100, and reg12 selects the selector output corresponding to D[5] in the device under test 100, and so on, until all four patterns are completed. At this time, the logic circuits corresponding to all input data of D[0] to D[7] of the device under test 100 have completed fault detection.

[0095] The presence of the compression circuit in this embodiment can reduce the layout area of ​​the test equipment. When the number of interfaces of the data input interface of the device under test is small, such as only 1 or 2, the compression circuit can be omitted and the input data of the data input interface can be directly led out for subsequent observation operations. However, when the number of interfaces of the data input interface of the device under test is large, a compression circuit is required to perform a data two-choice operation. After the compression circuit is set, the number of observation circuits and control circuits located at its rear end can be set to be small, thereby reducing the layout area of ​​the device under test. In addition, in this embodiment, the compression level of the compression circuit is arranged according to the number of interfaces of the data input interface of the device under test, so that the data compression of the compression circuit is reasonable, while reducing the layout area of ​​the device under test, ensuring the normal output of the input data of the device under test.

[0096] The second embodiment of the present invention further provides a test method applied to the above test equipment, see Figure 15 , Figure 15 : is a flow chart of a testing method provided by an embodiment of the present invention, the testing method comprising:

[0097] S1. Adjust the working status of all observation circuits and all control circuits;

[0098] S2. When all observation circuits and all control circuits operate in the first state, each observation circuit captures the operation result value of the corresponding logic circuit, and each control circuit captures the input data of its input terminal;

[0099] S3. When all observation circuits and all control circuits operate in the second state, each observation circuit shifts and outputs the captured calculation result value, and compares it with the expected value corresponding to the control stimulus to obtain the test result of the corresponding logic circuit; and each control circuit shifts and outputs the corresponding control stimulus to transmit the control stimulus to the corresponding logic circuit.

[0100] It is worth noting that the specific working process of the testing method can refer to the working process of the testing device 200 in the above embodiment, which will not be repeated here.

[0101] This embodiment provides a testing method for a test device. With this control method, since the observation register does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control register is simple, it is easy to meet the timing convergence of the register. When a timing violation occurs, the timing violation problem of the register and memory can be resolved by adjusting the clock tree of the clock buffer provided in the register.

[0102] Specifically, the testing method further includes:

[0103] S4. When it is detected that the device under test and the register meet a timing violation condition, adjust the clock tree of the clock buffer.

[0104] This embodiment adjusts the clock tree of the clock buffer to achieve timing convergence of the memory and registers. Due to timing convergence, there is no need to abandon the path to the register during the test process, thereby improving the fault coverage of the transition test pattern and reducing the number of vectors, thereby reducing the probability of escape during the chip test process, improving the yield of chip testing, and reducing unnecessary economic losses caused by escaped faulty chips.

[0105] The third aspect of the present invention further provides a computer-readable storage medium on which a program is stored. When the program is called, the computer executes the test method described in any embodiment of the second aspect.

[0106] It should be noted that the computer-readable storage medium may be an internal storage unit of the apparatus of the aforementioned embodiment, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device of the apparatus of the aforementioned embodiment, such as a plug-in hard disk, smart memory card, secure digital card, flash memory card, etc. Furthermore, the computer-readable storage medium may include both the internal storage unit of the apparatus and an external storage device. The computer-readable storage medium is used to store the aforementioned program as well as other programs and data required by the apparatus. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0107] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods, and the aforementioned storage media include: ROM, RAM, disk or optical disk, and other media that can store program codes.

[0108] Compared with the prior art, the test method, device, and storage medium disclosed in the present invention have the following beneficial effects:

[0109] 1) By using a selector to bypass the device under test, a bypass circuit is formed between the data input interface and the data output interface of the device under test, so that the data of the input interface of the data of the device under test can be intercepted through the bypass circuit for subsequent measurement, thereby obtaining the fault condition of the logic circuit of the device under test, and using the control circuit input control stimulus to enable the logic circuit after the data output interface to output the corresponding value to the observation circuit for observation. Through the bypass circuit, the fault detection of the functional path of the device under test can be covered, thereby improving the fault detection coverage of the functional path.

[0110] 2) The observation circuit and the control circuit are arranged in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain. By setting the control circuit and the observation circuit independently and inserting a clock buffer on the common clock path of the control circuit and the observation circuit, since the observation circuit does not have a next-level high-frequency clock path and the previous-level high-frequency clock path of the control circuit is simple, it is easy to meet the timing convergence of the register. When a timing violation occurs, the timing violation problem of the register and the device under test can be solved by adjusting the clock tree of the clock buffer arranged in the control circuit and the observation circuit.

[0111] 3) Due to timing convergence, there is no need to abandon the path to the register, which can improve the transition test fault coverage and reduce the number of vectors, thereby reducing the chance of escape during chip testing, improving the yield of chip testing, and reducing unnecessary economic losses caused by escaped faulty chips.

[0112] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A testing device, characterized in that: It includes an observation circuit, a control circuit, a selector, and clock buffers respectively arranged in the observation circuit and the control circuit; wherein, The selector is provided at the data input interface and the data output interface of the device under test, and the selector is used to bypass the device under test to form a bypass circuit between the data input interface and the data output interface; the observation circuit and the control circuit are provided in the bypass circuit, the data input path and the data output path of the device under test in the form of a scan chain, and the output of the observation circuit serves as one of the inputs of the control circuit; The clock buffer is used to adjust the timing of registers in the observation circuit and the control circuit; The control circuit is used to output control excitation to the logic circuits in the data input path and the data output path, so that the logic circuits output corresponding operation result values; The observation circuit is used to output the operation result value of the logic circuit, so as to obtain the test result of the corresponding logic circuit by comparing the operation result value with the expected value corresponding to the control stimulus.

2. The test device according to claim 1, characterized in that The test device includes a first control circuit arranged in the bypass circuit and at least one second control circuit arranged before the logic circuit; the test device includes a first observation circuit arranged in the bypass circuit and at least one second observation circuit arranged after the logic circuit.

3. The testing device according to claim 1 or 2, characterized in that Each observation circuit includes at least one observation register, and a clock buffer is provided on a common clock path of the observation registers.

4. The testing device according to claim 1 or 2, characterized in that: Each control circuit includes at least one control register, and a clock buffer is arranged on the common clock path of the control registers.

5. The testing device according to claim 1 or 2, characterized in that: In the bypass circuit, the number of observation registers in each observation circuit is equal to the number of control registers in the control circuit.

6. The testing device according to claim 1 or 2, characterized in that: The observation register in each observation circuit includes a first observation input terminal, a second observation input terminal and an observation output terminal; wherein the first observation input terminal is used to input the calculation result value, and the second observation input terminal is used to input the control stimulus; when the observation register works in the first state, the observation register is used to capture the input data of the first observation input terminal; when the observation register works in the second state, the observation output terminal is used to output the input data of the first observation input terminal and the second observation input terminal.

7. The testing device according to claim 1 or 2, characterized in that: The control register in each control circuit includes a first control input terminal, a second control input terminal and a control output terminal; wherein the second control input terminal is connected to the observation output terminal of the observation register in the corresponding observation circuit; when the control register operates in a first state, the control register is used to capture the input data of the first control input terminal; when the control register operates in a second state, the control output terminal is used to output the input data of the first control input terminal and the second control input terminal.

8. The testing device according to claim 6, characterized in that The first state is a capture state, and the second state is a shift state.

9. The testing device according to claim 7, characterized in that An inverter is provided in the control register, and the control output end of the control register is connected to the first control input end through the inverter.

10. The testing device according to claim 2, characterized in that The test device also includes a compression circuit arranged in the bypass circuit, which is used to receive at least two operation result values, compress the at least two operation result values ​​and send them to the first observation circuit in the bypass circuit, so that the first observation circuit outputs corresponding compressed data.

11. The test device according to claim 10, characterized in that The compression level of the compression circuit is positively correlated with the number of interfaces of the data input interface of the device under test.

12. The testing device according to claim 1 or 2, characterized in that: The clock signals of each observation circuit, each control circuit and the device under test are synchronized.

13. The testing device according to claim 1, characterized in that The device under test is a memory.

14. A testing method, characterized in that: The test device applied to any one of claims 1 to 13, the method comprising: Adjust the working status of all observation circuits and all control circuits; When all observation circuits and all control circuits operate in a first state, each observation circuit captures a calculation result value of a corresponding logic circuit, and each control circuit captures input data of its input terminal; When all observation circuits and all control circuits operate in the second state, each observation circuit shifts the output of the captured calculation result value and compares it with the expected value corresponding to the control stimulus to obtain the test result of the corresponding logic circuit; and each control circuit shifts the output of the corresponding control stimulus to transmit the control stimulus to the corresponding logic circuit.

15. The testing method according to claim 14, characterized in that: The method further comprises: When it is detected that the device under test and the register meet a timing violation condition, a clock tree of the clock buffer is adjusted.

16. A computer-readable storage medium, characterized in that: A program is stored thereon, and when the program is called, the program enables the computer to execute the testing method according to any one of claims 14-15.

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