Display device

Abstract

A display device includes: a display panel; a plurality of flexible circuit boards connected to the display panel, and the plurality of flexible circuit boards are bent and disposed below the display panel; a main circuit board connected to the plurality of flexible circuit boards and disposed below the display panel; a first cover member disposed on the display panel, in which the first cover member is bent at a curvature and disposed on a rear surface of the display panel, the first cover member covering a portion of the plurality of flexible circuit boards and a portion of the main circuit board; and a second cover covering other portions of the plurality of flexible circuit boards.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0082443 filed in the Korean Intellectual Property Office on June 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device including a flexible circuit board. Background Art

[0004] Display devices such as televisions, monitors, smartphones, and tablet personal computers (PCs) that provide images to users include display panels that display images. There are many types of display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0005] The display device may include a flexible circuit board connected to the display panel and a main circuit board connected to the display panel through the flexible circuit board. Summary of the invention

[0006] According to an embodiment, a display device includes: a display panel; a plurality of flexible circuit boards connected to the display panel, and the plurality of flexible circuit boards are bent and arranged below the display panel; a main circuit board connected to the plurality of flexible circuit boards and arranged below the display panel; a first cover member arranged on the display panel, wherein the first cover member is bent with a curvature and arranged on a rear surface of the display panel, the first cover member covers portions of the plurality of flexible circuit boards and a portion of the main circuit board; and a second cover member covering other portions of the flexible circuit boards exposed from the first cover member.

[0007] According to an embodiment, a display device includes: a display panel; a first flexible circuit board connected to the center of an edge of the display panel and bent from the center of the edge of the display panel; a second flexible circuit board connected to the edge of the display panel and bent from the edge of the display panel, the second flexible circuit board being spaced apart from the first flexible circuit board, and the second flexible circuit board being adjacent to one side of the edge of the display panel; a main circuit board disposed on a lower surface of the display panel and connected to the first flexible circuit board and the second flexible circuit board; a first cover covering the first flexible circuit board and the main circuit board; and a second cover covering the second flexible circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0009] Figure 1is a perspective view of a display device according to an embodiment of the present disclosure.

[0010] Figure 2 is included in Figure 1 A cross-sectional view of a display module in a display device.

[0011] Figure 3 yes Figure 2 A cross-sectional view of a display panel is shown in FIG.

[0012] Figure 4A , Figure 4B and Figure 4C yes Figure 3 A plan view of a display panel is shown in FIG.

[0013] Figure 5 is an example showing Figure 4A An arbitrary pixel shown in the figure corresponds to a cross-sectional view of a display module.

[0014] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G is a view for describing the first cover.

[0015] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E is a view for describing the second cover.

[0016] Fig. 8A It is a view for describing the structure of the first cover.

[0017] Figure 8B It is a view for describing that the first cover is grounded via the main circuit board.

[0018] Figure 8C It is a view for describing that the first cover is grounded via the cover panel.

[0019] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D is a view for describing a first cover according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The advantages and features of the present disclosure and methods for achieving the advantages and features will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not necessarily limited to the embodiments described below, but will be implemented in various forms, and the embodiments presented are merely for the purpose of making the disclosure of the present disclosure complete, and the embodiments presented are provided to fully inform the technical personnel of the technical field to which the present disclosure belongs of the scope of the present disclosure, and the scope of the present disclosure is limited only by the scope of the attached claims. Throughout the specification, the same reference numerals refer to the same components.

[0021] When a first element or a first layer is referred to as being disposed “on” or “over” a second element or a second layer, this includes both the first element or the first layer being directly “on” or “over” the second element or the second layer and the third element or the third layer being between the first element or the first layer and the second element or the second layer. On the other hand, when a first element is referred to as being directly disposed “on” or “over” a second element, this means that there is no third element or the third layer between the first element and the second element. The term “and / or” includes each of a plurality of the referenced items and all combinations of one or more of the plurality of the referenced items.

[0022] As shown in the drawings, spatially relative terms such as "below", "under", "lower", "above", and "on" may be used to simply describe the relationship between a first element or a first component and a second element or a second component. Spatially relative terms should be understood as terms that include different orientations of elements during use or operation in addition to the orientation shown in the drawings. Throughout the specification, the same reference numerals may refer to the same elements.

[0023] Although the terms of first and second, etc. are used to describe various elements, various components and / or various parts, it is clear that these elements, these components and / or these parts are not necessarily limited by these terms. These terms are used to distinguish an element, a component or a part from another element, another component or another part. Therefore, it is obvious that within the technical spirit of the present disclosure, the first element, the first component or the first part mentioned below can be the second element, the second component or the second part.

[0024] The embodiments described herein will be described with reference to the plan views and cross-sectional views as ideal schematic diagrams of the present disclosure. Therefore, the shapes of the illustrative drawings may be modified due to manufacturing techniques and / or tolerances. Therefore, although each of the drawings may represent one or more specific embodiments of the present disclosure drawn to scale, so that relative lengths, thicknesses, and angles can be inferred from the drawings, it should be understood that the present invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be modified within the spirit and scope of the present disclosure, for example, to allow for manufacturing limitations, etc.

[0025] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

[0026] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is included in Figure 1 A cross-sectional view of a display module in a display device. Figure 3 yes Figure 2 A cross-sectional view of a display panel is shown in FIG.

[0027] refer to Figure 1 , the display device DD according to an embodiment of the present disclosure may have a rectangular shape in a plan view, the rectangular shape having a shorter side extending in a first direction DR1 and a longer side extending in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not necessarily limited thereto, and the display device DD may have various shapes such as a circular shape and other polygonal shapes.

[0028] Hereinafter, the third direction DR3 is defined as being substantially perpendicular to a plane formed by the first direction DR1 and the second direction DR2. In addition, in this specification, the wording "when viewed on a plane" or "in a plan view" may be a state viewed from the third direction DR3.

[0029] An upper surface of the display device DD may be defined as a display surface DS. The display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0030] The display surface DS may include a display area DA and a non-display area NDA adjacent to the display area DA. The display area DA displays an image, and the non-display area NDA does not display an image. The non-display area NDA may at least partially surround the display area DA and define an edge of the display device DD printed in a predetermined color.

[0031] refer to Figure 2, the display device DD may include a display module DM. The display module DM may include a display panel DP, an input sensing unit ISP disposed on the display panel DP, an anti-reflection layer RPL disposed on the input sensing unit ISP, and a panel protection layer PPL disposed under the display panel DP. The display panel DP may be a flexible panel. For example, the display panel DP may include a flexible substrate and a plurality of elements arranged on the flexible substrate.

[0032] The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel, but the present disclosure is not necessarily limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0033] The input sensing unit ISP may include a plurality of sensor components for detecting an external input in a capacitive manner. The input sensing unit ISP may be directly formed on the display panel DP when manufacturing the display module DM.

[0034] The anti-reflection layer RPL may be provided on the input sensing unit ISP. When manufacturing the display module DM, the anti-reflection layer RPL may be directly formed on the input sensing unit ISP. The anti-reflection layer RPL may be an external light reflection prevention film. The anti-reflection layer RPL may reduce the reflectivity of external light input from the upper side of the display device DD toward the display panel DP.

[0035] The input sensing unit ISP may be formed directly on the display panel DP, and the anti-reflection layer RPL may be formed directly on the input sensing unit ISP, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the input sensing unit ISP may be manufactured separately and attached to the display panel DP through an adhesive layer, and the anti-reflection layer RPL may be manufactured separately and attached to the input sensing unit ISP through an adhesive layer. Therefore, the adhesive layer may be provided between the input sensing unit ISP and the display panel DP, and may also be provided between the anti-reflection layer RPL and the input sensing unit ISP.

[0036] The panel protection layer PPL may be disposed under the display panel DP and protect a lower portion of the display panel DP. The panel protection layer PPL may include a flexible plastic material such as polyethylene terephthalate (PET).

[0037] refer to Figure 3The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0038] The substrate SUB may include a display area DA and a non-display area NDA adjacent to the display area DA. For example, the display area DA may be disposed between the non-display areas NDA. The display element layer DP-OLED may be disposed in the display area DA. The substrate SUB may include a flexible plastic material such as polyimide (PI) or glass.

[0039] A plurality of pixels PX (see Figure 5 ) may be arranged in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels PX may include a transistor TR (see Figure 5 ) and a light emitting element disposed in the display element layer DP-OLED, the light emitting element being connected to the transistor TR. Figure 5 The configuration of the pixel PX will be described in detail in .

[0040] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL, and the thin film encapsulation layer TFE covers the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixel PX from moisture, oxygen, and foreign substances.

[0041] Figure 4A , Figure 4B and Figure 4C yes Figure 3 A plan view of a display panel is shown in FIG.

[0042] Figure 4A is a view of a state before the flexible circuit board FPC and the main circuit board MCB connected to the display panel DP are bent, and Figure 4B 1 is a view of a state in which a flexible circuit board FPC and a main circuit board MCB connected to a display panel DP are bent. Figure 4C is along Figure 4B A cross-sectional view taken along line II' shown in FIG.

[0043] refer to Figure 4A The display device DD may include a flexible circuit board FPC, a main circuit board MCB and a display module DM. The display module DM may include a display panel DP, a scan driver GDC, a plurality of signal lines SGL, a plurality of data drivers DDV and a plurality of pixels PX.

[0044] The display panel DP may include a display area DA and a non-display area NDA adjacent to the display area DA. The non-display area NDA may at least partially surround the display area DA. The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where an image is not displayed.

[0045] The data driver DDV may be arranged in the non-display area NDA of the display panel DP. The data driver DDV may be arranged adjacent to an edge of the display panel DP. The data driver DDV may be arranged in the second direction DR2.

[0046] The data driver DDV may include a first data driver DDV1, a second data driver DDV2, and a third data driver DDV3. In a plan view, the first data driver DDV1 may overlap a central area of ​​the display panel DP.

[0047] The second data driver DDV2 may be spaced apart from the first data driver DDV1 in the second direction DR2. The second data driver DDV2 may be disposed on the left side of the first data driver DDV1 in a plan view.

[0048] The third data driver DDV3 may be spaced apart from the first data driver DDV1 in the second direction DR2. The third data driver DDV3 may be disposed on the right side of the first data driver DDV1 in a plan view. For example, the first data driver DDV1 may be disposed between the second data driver DDV2 and the third data driver DDV3.

[0049] The first, second, and third data drivers DDV1, DDV2, and DDV3 may be mounted on the display panel DP. Each of the first, second, and third data drivers DDV1, DDV2, and DDV3 may be electrically connected to the display panel DP and provide an electrical signal to the display panel DP.

[0050] The flexible circuit board FPC may be connected to the display panel DP. One end of the flexible circuit board FPC may be arranged in a peripheral area of ​​the display panel DP. For example, the flexible circuit board FPC may be arranged adjacent to an edge of the display panel DP.

[0051] The flexible circuit board FPC may be arranged on the pads arranged on the display panel DP. The flexible circuit board FPC may be electrically connected to the pads through the anisotropic conductive adhesive layer. Therefore, the flexible circuit board FPC may be electrically connected to the display panel DP through the pads.

[0052] The flexible circuit board FPC may include a first flexible circuit board FPC1, a second flexible circuit board FPC2, and a third flexible circuit board FPC3. In a plan view, the first flexible circuit board FPC1 may overlap a central area of ​​the display panel DP.

[0053] The second flexible circuit board FPC2 may be spaced apart from the first flexible circuit board FPC1 in the second direction DR2. In a plan view, the second flexible circuit board FPC2 may be disposed on the left side of the first flexible circuit board FPC1.

[0054] The third flexible circuit board FPC3 may be spaced apart from the first flexible circuit board FPC1 in the second direction DR2. In a plan view, the third flexible circuit board FPC3 may be disposed on the right side of the first flexible circuit board FPC1. For example, the first flexible circuit board FPC1 may be disposed between the second flexible circuit board FPC2 and the third flexible circuit board FPC3.

[0055] The first flexible circuit board FPC1 may be spaced apart from the first data driver DDV1 in the first direction DR1. The second flexible circuit board FPC2 may be spaced apart from the second data driver DDV2 in the first direction DR1. The third flexible circuit board FPC3 may be spaced apart from the third data driver DDV3 in the first direction DR1. For example, the data drivers DDV1, DDV2, and DDV3 may be vertically disposed above the flexible circuit boards FPC1, FPC2, and FPC3, respectively.

[0056] Each of the flexible circuit boards FPC may be connected to a corresponding data driver DDV through a data line DL, which will be described later.

[0057] Although Figure 4A 3 and 4. Although three flexible circuit boards FPC and three data drivers DDV are shown in FIG. 3 , the number of the flexible circuit boards FPC and the number of the data drivers DDV are not necessarily limited thereto.

[0058] The main circuit board MCB may be connected to the flexible circuit board FPC. One side of the flexible circuit board FPC located in a direction opposite to the first direction DR1 may be connected to the main circuit board MCB. For example, the side of the flexible circuit board FPC connected to the main circuit board MCB is opposite to the side of the flexible circuit board FPC connected to the display panel DP. The main circuit board MCB may be electrically connected to the display panel DP through the flexible circuit board FPC.

[0059] The main circuit board MCB may include a first board MCB1 and a second board MCB2. A flexible circuit board FPC may be connected to an edge of the first board MCB1 facing the display panel DP.

[0060] The second board MCB2 may extend from the first board MCB1 in a direction opposite to the first direction DR1. The first board MCB1 and the second board MCB2 may be integrally formed.

[0061] In a plan view, the main circuit board MCB may have a “T” shape. A width of the main circuit board MCB in the second direction DR2 may vary.

[0062] The length of the first board MCB1 in the second direction DR2 may be greater than the length of the second board MCB2 in the second direction DR2. The length of the first board MCB1 in the first direction DR1 may be shorter than the length of the second board MCB2 in the first direction DR1. However, this is exemplary, and the lengths of the first board MCB1 and the second board MCB2 in the first direction DR1 and the second direction DR2 may vary.

[0063] The voltage generating unit may be provided on the main circuit board MCB. The main circuit board MCB may generate voltages for operation of the display panel DP.

[0064] The scan driver GDC may generate a plurality of scan signals and output the scan signals to a plurality of scan lines GL, which will be described later. The scan driver GDC may also output another control signal to a driving circuit of the pixel PX.

[0065] The scan driver GDC may include a plurality of transistors TR (see Figure 5 ), the plurality of transistors TR and the data driver DDV for the pixel PX are formed by the same process (such as a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0066] The signal line SGL may include a scan line GL, a data line DL, a power line PL, and a control signal line CSL. The scan line GL may extend in a direction opposite to the second direction DR2 and be connected to the scan driver GDC. Each of the scan line GL, the data line DL, and the power line PL may be connected to a corresponding pixel PX. The control signal line CSL may be connected to the scan driver GDC and provide a control signal.

[0067] The data line DL may be connected to the data driver DDV and the flexible circuit board FPC as it extends in a direction opposite to the first direction DR1. The data line DL may be electrically connected to the data driver DDV and the flexible circuit board FPC through a pad.

[0068] The power lines PL may be electrically connected to the third flexible circuit board FPC3 and the main circuit board MCB. In addition, the power lines PL may be electrically connected to a voltage generating unit in the main circuit board MCB, and the power lines PL may provide a reference voltage to the pixels PX.

[0069] The control signal line CSL may be connected to the scan driver GDC. In addition, the control signal line CSL may be electrically connected to the second flexible circuit board FPC2 and the main circuit board MCB through the pads.

[0070] The main circuit board MCB may include a timing controller T-CON. The timing controller T-CON may be disposed on the second board MCB2, and the timing controller T-CON may be spaced apart from the first flexible circuit board FPC1 in the first direction DR1.

[0071] The timing controller T-CON may control operations of the scan driver GDC and the data driver DDV. The timing controller T-CON may generate a scan control signal and a data control signal in response to a control signal received from an external unit.

[0072] The scan control signal may be provided to the scan driver GDC through the control signal line CSL. The data control signal may be provided to the data driver DDV. The timing controller T-CON may receive an image signal from an external unit, convert the data format of the image signal to meet the interface specification with the data driver DDV, and provide the converted image signal to the data driver DDV.

[0073] The scan driver GDC may generate a plurality of scan signals in response to the scan control signal. The scan signals may be applied to the pixels PX through the scan lines GL. The plurality of scan signals may be sequentially applied to the pixels PX.

[0074] The data driver DDV may generate a plurality of data voltages corresponding to the image signal in response to the data control signal. The data voltages may be applied to the pixels PX through the data lines DL.

[0075] The pixel PX may receive a data voltage in response to the scan signal, and the pixel PX may display an image by emitting light having brightness corresponding to the data voltage.

[0076] refer to Figure 4B and Figure 4C , the display module DM may further include a cover panel CP. The cover panel CP may be disposed under the panel protection layer PPL. The cover panel CP may be bonded to the panel protection layer PPL by an adhesive layer. The cover panel CP may support a rear surface of the display panel DP. The rear surface of the display panel DP may be defined as a surface opposite to an upper surface on which the input sensing unit ISP is disposed.

[0077] The input sensing unit ISP, the anti-reflection layer RPL, and the edges of the cover panel CP may be arranged within the edges of the display panel DP and the panel protection layer PPL. The display panel DP and the panel protection layer PPL may have the same width.

[0078] According to an embodiment of the present disclosure, the flexible circuit board FPC may be bent with respect to an imaginary axis parallel to the second direction DR2 so that the main circuit board MCB is disposed under the display panel DP.

[0079] For example, Figure 4C As shown in FIG. 1 , the first flexible circuit board FPC1 may be bent twice with respect to the first bending axis RX1 and the second bending axis RX2. For example, the first flexible circuit board FPC1 may have an inverted "S" shape in the left-right direction. However, this is exemplary, and the number of bending axes may be one or three or more.

[0080] The second flexible circuit board FPC2 and the third flexible circuit board FPC3 may have substantially the same shape and may also be bent.

[0081] When the flexible circuit board FPC is bent, a portion of the flexible circuit board FPC may be disposed under the cover panel CP. Figure 4C As shown in FIG. 1 , an adhesive layer AL may be provided between the first flexible circuit board FPC1 and the cover panel CP. The first flexible circuit board FPC1 and the cover panel CP may be bonded to each other through the adhesive layer AL. The second and third flexible circuit boards FPC2 and FPC3 and the cover panel CP may be bonded to each other through the adhesive layer AL.

[0082] When the flexible circuit board FPC is bent, the main circuit board MCB may be disposed under the display panel DP. The top surface of the first board MCB1 may face the bottom surface of the cover panel CP. In a plan view, a portion of the second board MCB2 may be exposed to the outside of the display panel DP. Hereinafter, the portion of the second board MCB2 exposed to the outside of the display panel DP in a plan view may be defined as an exposed board OMC.

[0083] Figure 5 is an example showing Figure 4A An arbitrary pixel shown in the figure corresponds to a cross-sectional view of a display module.

[0084] refer to Figure 5 , the pixel PX may include a transistor TR and a light emitting element OLED. The light emitting element OLED may include a first electrode (or anode) AE, a second electrode (or cathode) CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EML. The transistor TR and the light emitting element OLED may be arranged on a substrate SUB. Although one transistor TR is exemplarily shown, the pixel PX may include a plurality of transistors TR and one or more capacitors for driving the light emitting element OLED.

[0085] The display area DA may include a light emitting area PA corresponding to each of the pixels PX and a non-light emitting area NPA next to the light emitting area PA. For example, the light emitting area PA may be disposed between the non-light emitting areas NPA. The light emitting element OLED may be disposed in the light emitting area PA.

[0086] The buffer layer BFL may be disposed on the substrate SUB, and the buffer layer BFL may be an inorganic layer. The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon, amorphous silicon, or metal oxide.

[0087] The semiconductor pattern may be doped with an N-type dopant or a P-type dopant. The semiconductor pattern may include a high-doped region (e.g., a region doped with a high concentration) and a low-doped region (e.g., a region doped with a low concentration). The conductivity of the high-doped region is higher than that of the low-doped region, and the high-doped region may be used as a source electrode and a drain electrode of the transistor TR. The low-doped region may correspond to an active region (or channel region) A of the transistor TR.

[0088] The source region S, the active region A, and the drain region D of the transistor TR may be formed by a semiconductor pattern. The first insulating layer INS1 may be disposed on the semiconductor pattern. The gate G of the transistor TR may be disposed on the first insulating layer INS1. The second insulating layer INS2 may be disposed on the gate G. For example, the second insulating layer INS2 may at least partially surround the gate G. The third insulating layer INS3 may be disposed on the second insulating layer INS2.

[0089] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 to connect the transistor TR and the light emitting element OLED. The first connection electrode CNE1 may be disposed on the third insulating layer INS3 and may be vertically connected to the drain region D through a first contact hole CH1 defined by the first insulating layer INS1 to the third insulating layer INS3. For example, the first connection electrode CNE1 may extend from the top surface of the third insulating layer INS3 and penetrate the first insulating layer INS1 to the third insulating layer INS3 through the first contact hole CH1.

[0090] The fourth insulating layer INS4 may be disposed on the first connection electrode CNE1. For example, the fourth insulating layer INS4 may at least partially cover the first connection electrode CNE1. The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5. The second connection electrode CNE2 may be vertically connected to the first connection electrode CNE1 through a second contact hole CH2 defined by the fourth insulating layer INS4 and the fifth insulating layer INS5. For example, the second connection electrode CNE2 may extend from the upper surface of the fifth insulating layer INS5 and penetrate the fourth insulating layer INS4 and the fifth insulating layer INS5 through the second contact hole CH2.

[0091] The sixth insulating layer INS6 may be disposed on the second connection electrode CNE2. For example, the sixth insulating layer INS6 may at least partially surround the second connection electrode CNE2. The circuit element layer DP-CL may include layers from the buffer layer BFL to the sixth insulating layer INS6. The first to sixth insulating layers INS1 to INS6 may be inorganic layers or organic layers.

[0092] The first electrode AE ​​may be disposed on the sixth insulating layer INS6. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined by the sixth insulating layer INS6. For example, the first electrode AE ​​may extend from the top surface of the sixth insulating layer INS6 and penetrate the sixth insulating layer INS6 through the third contact hole CH3. A pixel defining film PDL in which an opening PX_OP for exposing a predetermined portion of the first electrode AE ​​is defined may be disposed on the first electrode AE ​​and the sixth insulating layer INS6. For example, the pixel defining film PDL may at least partially surround the first electrode AE ​​and the sixth insulating layer INS6.

[0093] The hole control layer HCL may be disposed on the first electrode AE ​​and the pixel definition layer PDL. The hole control layer HCL may contact the opening PX_OP. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0094] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening PX_OP. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate any one of red light, green light, and blue light.

[0095] The electron control layer ECL may be disposed on the light emitting layer EML and the hole control layer HCL. The electron control layer ECL may include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly arranged in the light emitting area PA and the non-light emitting area NPA.

[0096] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed in the pixel PX. A layer in which the light emitting element OLED is disposed may be defined as a display element layer DP-OLED.

[0097] The thin film encapsulation layer TFE may include a first encapsulation layer EN1 disposed on the second electrode CE, a second encapsulation layer EN2 disposed on the first encapsulation layer EN1, and a third encapsulation layer EN3 disposed on the second encapsulation layer EN2. The thin film encapsulation layer TFE may be disposed on the second electrode CE to cover the pixel PX.

[0098] The first encapsulation layer EN1 and the third encapsulation layer EN3 may include an inorganic insulating layer and protect the pixel PX from moisture / oxygen. The second encapsulation layer EN2 may include an organic insulating layer and protect the pixel PX from foreign substances such as dust particles.

[0099] A first voltage may be applied to the first electrode AE ​​through the transistor TR, and a second voltage having a voltage level lower than that of the first voltage may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML are recombined with each other to form excitons, and as the excitons transition to the ground state, the light emitting element OLED may emit light.

[0100] The input sensing unit ISP may be disposed on the thin film encapsulation layer TFE. The input sensing unit ISP may be directly manufactured on the upper surface of the thin film encapsulation layer TFE.

[0101] The base layer BS may be disposed on the thin film encapsulation layer TFE. The base layer BS may include an inorganic insulating layer. At least one inorganic insulating layer of the base layer BS may be provided on the thin film encapsulation layer TFE.

[0102] The input sensing unit ISP may include a first conductive pattern CTL1 and a second conductive pattern CTL2 disposed on the first conductive pattern CTL1. The first conductive pattern CTL1 may be disposed on the base layer BS. The insulating layer TINS ​​may be disposed on the base layer BS to at least partially cover the first conductive pattern CTL1. The insulating layer TINS ​​may include an inorganic insulating layer or an organic insulating layer. The second conductive pattern CTL2 may be disposed on the insulating layer TINS. For example, the second conductive pattern CTL2 may extend from the upper surface of the insulating layer TINS ​​and extend vertically to be connected to the first conductive pattern CTL1.

[0103] The first conductive pattern CTL1 and the second conductive pattern CTL2 may overlap at the non-light emitting area NPA. The first conductive pattern CTL1 and the second conductive pattern CTL2 may be arranged in the non-light emitting area NPA between the plurality of light emitting areas PA and have a mesh shape.

[0104] The first conductive pattern CTL1 and the second conductive pattern CTL2 may form a sensor of the input sensing unit ISP. For example, the first conductive pattern CTL1 and the second conductive pattern CTL2 having a mesh shape may be separated from each other in a predetermined area to form a plurality of sensors. A portion of the second conductive pattern CTL2 may be connected to the first conductive pattern CTL1.

[0105] The anti-reflection layer RPL may include a black matrix BM and a plurality of color filters CF. The anti-reflection layer RPL may be disposed on the second conductive pattern CTL2. The black matrix BM may overlap the non-emission area NPA, and the color filter CF may overlap the emission area PA.

[0106] The black matrix BM may be disposed on the insulating layer TINS ​​and cover the second conductive pattern CTL2. An opening B_OP overlapping the light emitting area PA and the opening PX_OP may be defined in the black matrix BM. The black matrix BM may absorb and block light. The width of the opening B_OP may be greater than the width of the opening PX_OP.

[0107] The color filter CF may be arranged on the insulating layer TINS ​​and the black matrix BM. For example, the color filter CF may at least partially cover the insulating layer TINS ​​and the black matrix BM. The color filter CF may be arranged in the opening B_OP, respectively. The planarization insulating layer PINS may be provided on the color filter CF. The planarization insulating layer PINS may provide a flat upper surface.

[0108] When external light moving toward the display panel DP is reflected by the display panel DP and returned to the external user, the user may visually perceive the external light as a mirror effect. In order to prevent this phenomenon, the anti-reflection layer RPL may include a plurality of color filters CF, and the color filters CF display the same color as the color of the light emitted by the pixel PX of the display panel DP. The color filter CF may filter the external light into the same color as the color of the light emitted by the pixel PX. Therefore, the user may not perceive the external light.

[0109] However, the embodiments of the present disclosure are not necessarily limited thereto, and the anti-reflection layer RPL may include a polarizing film to reduce the reflectivity of external light. The polarizing film may be manufactured separately and attached to the input sensing unit ISP through an adhesive layer. The polarizing film may include a phase retarder and / or a polarizer.

[0110] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G is a view for describing the first cover.

[0111] FIG. 6A to FIG. 6EIt is a floor plan. Fig. 6F is along Figure 6C A cross-sectional view taken along line II-II' shown in FIG. Figure 6G is along Figure 6C A cross-sectional view taken along line III-III' is shown in FIG.

[0112] Fig. 6A and Figure 6B is a view showing the first cover CVP1 before bending, and Figures 6C to 6G is a view showing the first cover CVP1 being bent.

[0113] Fig. 6E It is a plan view viewed from the lower surface of the display panel DP.

[0114] Figure 6B yes Fig. 6A An enlarged plan view of the first enlarged area IN1 is shown in FIG. Fig.6D yes Figure 6C An enlarged plan view of the second expanded area IN2 is shown in FIG.

[0115] FIG. 6C to FIG. 6G The flexible circuit board FPC is shown in a bent state.

[0116] FIG. 6A to FIG. 6G The display module DM, flexible circuit board FPC and main circuit board MCB are Figure 4A and Figure 4B The display module DM, the flexible circuit board FPC and the main circuit board MCB are the same, and thus a description thereof will be omitted or simplified.

[0117] refer to Fig. 6A and Figure 6B , display device DD (see Figure 1 ) may further include a first cover CVP1. The first cover CVP1 may include a first part PT1, a second part PT2, and a third part PT3. The first part PT1 may be disposed on the data driver DDV and a portion of the first flexible circuit board FPC1, a portion of the second flexible circuit board FPC2, and a portion of the third flexible circuit board FPC3.

[0118] One side of the first component PT1 may overlap with a portion of the flexible circuit boards FPC1, FPC2, and FPC3. For example, the bottom surface of the first component PT1 may contact with the top surfaces of the flexible circuit boards FPC1, FPC2, and FPC3. The second component PT2 may extend from the first component PT1 in a direction opposite to the first direction DR1. The second component PT2 may be disposed on another portion of the first flexible circuit board FPC1 that does not overlap with the first component PT1 and the exposed board OMC of the main circuit board MCB. In a plan view, the second component PT2 may cover the exposed board OMC.

[0119] In the plan view, Figure 6B As shown in FIG. 1 , the first part PT1 and the second part PT2 may cover a portion of the third flexible circuit board FPC3 and a portion of the second flexible circuit board FPC2. In a plan view, the other portion of the second flexible circuit board FPC2 and the other portion of the third flexible circuit board FPC3 may be exposed to the outside of the first part PT1 and the second part PT2. Hereinafter, the portions of the second flexible circuit board FPC2 and the third flexible circuit board FPC3 exposed to the outside of the first part PT1 and the second part PT2 may be defined as a first exposed part OWP1.

[0120] The third portion PT3 may extend from the second portion PT2 in a direction opposite to the first direction DR1 .

[0121] In a plan view, the first cover CVP1 may have a dumbbell shape. The dumbbell shape may refer to a form including two parallel planes connected by a central portion between the two parallel planes. In detail, in a plan view, the length of the first component PT1 in the second direction DR2 may be greater than the length of the second component PT2 in the second direction DR2. The length of the first component PT1 in the second direction DR2 may be greater than the length of the third component PT3 in the second direction DR2. The length of the third component PT3 in the second direction DR2 may be greater than the length of the second component PT2 in the second direction DR2. That is, the length of the second component PT2 in the second direction DR2 may be the shortest, and the length of the first component PT1 in the second direction DR2 may be the longest.

[0122] The length of the second part PT2 in the second direction DR2 may be shorter than the length of the exposure board OMC of the main circuit board MCB in the second direction DR2. As shown in FIG6B, both ends of the exposure board OMC in the second direction DR2 opposite to each other may be exposed outside the second part PT2.

[0123] refer to Fig. 6F and Figure 6G, the first cover CVP1 may be disposed on the input sensing unit ISP. The first cover CVP1 may be disposed on an edge of the input sensing unit ISP adjacent to the data driver DDV. The first cover CVP1 may be coupled to the input sensing unit ISP through an adhesive layer. However, this is merely exemplary, and the first cover CVP1 may be disposed on the anti-reflection layer RPL.

[0124] refer to Figure 6C , Fig.6D , Fig. 6F and Figure 6G , the first cover member CVP1 may be bent and cover the first flexible circuit board FPC1, the data driver DDV, and the main circuit board MCB. The first cover member CVP1 may be bent with a predetermined curvature.

[0125] A portion of the first part PT1 and a portion of the second part PT2 may be arranged on the display panel DP. On the display panel DP, the first part PT1 may cover the data driver DDV and a portion of the first flexible circuit board FPC1, a portion of the second flexible circuit board FPC2, and a portion of the third flexible circuit board FPC3. On the display panel DP, a portion of the second part PT2 may cover the remaining portion of the first flexible circuit board FPC1 not covered by the first part PT1 and the exposed board OMC.

[0126] refer to Fig. 6E , Fig. 6F and Figure 6G , the remaining portion of the second part PT2 and the third part PT3 may be arranged below the display panel DP. Fig. 6E and Fig. 6F As shown in FIG. 1 , below the display panel DP, the second component PT2 may cover the main circuit board MCB and the first flexible circuit board FPC1. Fig. 6E and Figure 6G As shown in FIG. 1 , under the display panel DP, the second part PT2 and the third part PT3 may not cover a portion of the second flexible circuit board FPC2 and a portion of the third flexible circuit board FPC3.

[0127] In detail, the second part PT2 may cover the second board MCB2 of the main circuit board MCB. In this case, the length of the second part PT2 in the second direction DR2 is shorter than the length of the second board MCB2 in the second direction DR2. Fig. 6E As shown in FIG. 2 , both ends of the second board MCB2 that are opposite to each other in the second direction DR2 may be exposed outside the second part PT2 .

[0128] like Fig. 6EAs shown in FIG. 1 , the length of the second part PT2 in the second direction DR2 may be less than the length from one side of the second flexible circuit board FPC2 to one side of the third flexible circuit board FPC3. Therefore, a portion of the second flexible circuit board FPC2 and a portion of the third flexible circuit board FPC3 may be exposed to the outside of the first cover CVP1. Portions of the second flexible circuit board FPC2 and the third flexible circuit board FPC3 that are arranged under the display panel DP and exposed to the outside of the first cover CVP1 may be defined as a second exposed part OWP2.

[0129] The length of the third part PT3 in the first direction DR1 and the length of the third part PT3 in the second direction DR2 may be respectively greater than the length of the first board MCB1 in the first direction DR1 and the length of the first board MCB1 in the second direction DR2. That is, the area of ​​the third part PT3 may be greater than the area of ​​the first board MCB1. Therefore, the third part PT3 may completely cover the first board MCB1 disposed under the display panel DP.

[0130] like Fig. 6F and Figure 6G As shown in FIG. 1 , the second part PT2 may be in contact with the lower surface of the main circuit board MCB. The third part PT3 may be in contact with the lower surface of the cover panel CP.

[0131] The second component PT2 can be grounded via the main circuit board MCB, and the third component PT3 can be grounded via the cover panel CP. The grounding of the second component PT2 and the third component PT3 will refer to Figure 8B and Figure 8C Describe in detail.

[0132] The first cover CVP1 may cover a portion of the flexible circuit board FPC, the data driver DDV, and a portion of the main circuit board MCB to shield static electricity. In addition, the first cover CVP1 may block noise generated near the data driver DDV, the flexible circuit board FPC, and the main circuit board MCB.

[0133] refer to Fig. 6A and Figure 6C , a connection opening OP may be defined in the first cover CVP1. The connection opening OP may overlap with a portion of the main circuit board MCB exposed to the outside of the display panel DP. A connector provided on the main circuit board MCB may be exposed to the outside of the first cover CVP1 through the connection opening OP. The connector exposed to the outside may be connected to a main processor of a notebook computer or a mobile phone, etc.

[0134] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7Eis a view for describing the second cover.

[0135] Fig. 7A and Fig.7D is a plan view, and Fig. 7E is along Figure 7B A cross-sectional view taken along line IV-IV' is shown.

[0136] Figure 7C yes Figure 7B An enlarged plan view of the third enlarged area IN3.

[0137] Fig. 7A is a view showing the second cover CVP2 before bending, and Figure 7B and Fig. 7E is a view showing the bent second cover CVP2.

[0138] Fig.7D It is a plan view viewed from the lower surface of the display panel DP.

[0139] 7A to 7D The flexible circuit board FPC is shown in a bent state.

[0140] 7A to 7E The display module DM, the flexible circuit board FPC, the main circuit board MCB and the first cover CVP1 are Figure 4A and FIG. 6A to FIG. 6C The display module DM, the flexible circuit board FPC, the main circuit board MCB, and the first cover CVP1 in FIG. 1 are the same, and thus a description thereof will be omitted or simplified.

[0141] refer to Fig. 7A , display device DD (see Figure 1 ) may further include a second cover CVP2. In a plan view, the second cover CVP2 may be arranged on the first cover CVP1 (see Fig. 6A ) on the first component PT1.

[0142] The second cover pieces CVP2 may be spaced apart from each other in the second direction DR2. In a plan view, the second cover piece CVP2 may be disposed adjacent to both ends of the second part PT2 that are opposite to each other in the second direction DR2. The second part PT2 may be disposed between the second cover pieces CVP2.

[0143] In a plan view, the second cover CVP2 may overlap the second and third data drivers DDV2 and DDV3. The second cover CVP2 may overlap the second and third flexible circuit boards FPC2 and FPC3. The second cover CVP2 may overlap the first exposed part OWP1.

[0144] In a plan view, the second cover CVP2 may be in a rectangular shape. However, the present disclosure is not necessarily limited thereto, and the second cover CVP2 may be in various shapes.

[0145] refer to Figure 7B and Fig. 7E , the second cover CVP2 can be bent to cover the second flexible circuit board FPC2 and the third flexible circuit board FPC3. Fig. 7E As shown in FIG. 1 , the second cover CVP2 may be curved at a predetermined curvature. For example, the curvature of the second cover CVP2 may be greater than Figure 6G However, the present disclosure is not necessarily limited thereto, and the curvature of the first cover CVP1 may be greater than the curvature of the second cover CVP2.

[0146] refer to Figures 7B to 7E When the second cover member CVP2 is bent, some of the second cover members CVP2 may be disposed on and / or under the display panel DP. The second cover member CVP2 disposed under the display panel DP may extend from an edge of the display panel DP to an edge of the third part PT3.

[0147] like Figure 7B and 7C As shown in FIG. 1 , the second cover CVP2 is arranged on the display panel DP (see Fig. 7E ) may at least partially cover the first exposed part OWP1. Fig.7D As shown in FIG. 1 , some of the second cover pieces CVP2 disposed under the display panel DP may at least partially cover the second exposed part OWP2.

[0148] Since the second cover CVP2 covers the first exposed part OWP1 and the second exposed part OWP2 , the areas of the second flexible circuit board FPC2 and the third flexible circuit board FPC3 exposed to the outside may be reduced.

[0149] refer to Figure 6C , Figure 6G , Figure 7B and Fig. 7E , when the first cover CVP1 covers the data driver DDV, the flexible circuit board FPC, and the main circuit board MCB, the first and second exposed parts OWP1 and OWP2 of the second and third flexible circuit boards FPC2 and FPC3 may be exposed outside the first cover CVP1 .

[0150] In this case, static electricity may be generated in the first exposed part OWP1 and the second exposed part OWP2 exposed to the outside. Figure 4A) may be damaged due to static electricity. In addition, noise may be generated near the second flexible circuit board FPC2 and the third flexible circuit board FPC3 exposed to the outside, thereby reducing the reliability of the display module DM.

[0151] However, covering the first exposed part OWP1 and the second exposed part OWP2 with the second cover CVP2 can reduce the exposed area. Therefore, static electricity can be prevented from being generated in the second flexible circuit board FPC2 and the third flexible circuit board FPC3, and noise can be prevented from being generated near the second flexible circuit board FPC2 and the third flexible circuit board FPC3. Therefore, damage to the display module DM can be prevented.

[0152] Fig. 8A It is a view for describing the structure of the first cover. Figure 8B It is a view for describing that the first cover is grounded via the main circuit board. Figure 8C It is a view for describing that the first cover is grounded via the cover panel.

[0153] Fig. 8A yes Fig. 6F An enlarged view of the first area AA1 is shown in FIG. Figure 8B yes Fig. 6F An enlarged view of the second area AA2 is shown in FIG. Figure 8C yes Fig. 6F An enlarged view of the third area AA3 is shown in FIG.

[0154] Figure 8B The main circuit board MCB in Figure 4A The main circuit board MCB is the same as shown in Figure 8C The cover panel CP shown in Fig. 6F Therefore, the description thereof will be omitted or simplified.

[0155] refer to Fig. 8A The first cover member CVP1 may include a first cover insulating layer ISL1, an intermediate layer CDL, and a second cover insulating layer ISL2. The first cover insulating layer ISL1 may include an insulating material such as a polymer material. For example, the polymer material may be polyethylene terephthalate (PET).

[0156] The intermediate layer CDL may be disposed on the first cover insulating layer ISL1. The intermediate layer CDL may be coupled to the first cover insulating layer ISL1 through an adhesive layer.

[0157] The intermediate layer CDL may include a conductive material such as metal. However, the present disclosure is not necessarily limited thereto, and the intermediate layer CDL may include conductive fibers.

[0158] The first cover CVP1 may include an intermediate layer CDL to shield static electricity. Figure 8B and 8C Described in detail in.

[0159] The second cover insulating layer ISL2 may be disposed on the intermediate layer CDL. The second cover insulating layer ISL2 may be coupled to the intermediate layer CDL through an adhesive layer.

[0160] The second cover insulating layer ISL2 may include an insulating material such as an organic material. For example, the organic material may be polyethylene terephthalate (PET). According to an embodiment, the second cover insulating layer ISL2 may be black and shield light.

[0161] Although the structure of the first cover CVP1 is already Fig. 8A However, the second cover CVP2 (see Fig. 7A ) may also have substantially the same configuration as the first cover CVP1.

[0162] refer to Fig. 6F and Figure 8B , a first grounding groove CGG1 may be defined on the lower surface of the main circuit board MCB through the first cover insulating layer ISL1. The intermediate layer CDL may be exposed from the first cover insulating layer ISL1 through the first grounding groove CGG1. The exposed intermediate layer CDL may contact the main circuit board MCB. The intermediate layer CDL may be connected to a wiring provided on the main circuit board MCB and grounded. Therefore, the first cover CVP1 may electrostatically shield the main circuit board MCB from the outside.

[0163] refer to Fig. 6F and Figure 8C , a second grounding groove CGG2 may be defined on the lower surface of the cover panel CP through the first cover insulating layer ISL1. The intermediate layer CDL may be exposed from the first cover insulating layer ISL1 through the second grounding groove CGG2. The exposed intermediate layer CDL may contact the cover panel CP. The intermediate layer CDL may be connected to a wiring disposed on the cover panel CP and grounded. Therefore, the first cover CVP1 may electrostatically shield the cover panel CP from the outside.

[0164] The intermediate layer CDL can be grounded via the main circuit board MCB and the cover panel CP to shield external static electricity, thereby preventing the display module DM (see Figure 4A ) damage.

[0165] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D 2 is a view describing a first cover according to an embodiment of the present disclosure.

[0166] 9A to 9C It is a floor plan.

[0167] Fig. 9B yes Fig.9A An enlarged plan view of a fourth enlarged area IN4 is shown in FIG. Fig.9D yes Fig. 9C An enlarged plan view of the fifth enlarged area IN5 is shown in FIG.

[0168] Fig. 9C and Fig.9D 1 and 2 are views showing the first cover CVP1a and the second cover CVP2 in a bent state.

[0169] Fig.9A and Fig. 9B The display module DM, the flexible circuit board FPC, the main circuit board MCB and the second cover CVP2 in the Fig. 6A and Fig. 7A The display module DM, the flexible circuit board FPC, the main circuit board MCB and the second cover CVP2 are the same, and thus a description thereof will be omitted or simplified.

[0170] refer to Fig.9A and Fig. 9B , the first cover CVP1a may further include a plurality of sub-covers SCP. The sub-covers SCP may be arranged at both ends of the second part PT2 that are opposite to each other in the second direction DR2. The sub-covers SCP may be arranged adjacent to one side of the two sides of the second part PT2 that are opposite to each other in the first direction DR1. One side of the two sides of the second part PT2 that are opposite to each other in the first direction DR1 may be defined as a side adjacent to the first part PT1.

[0171] The sub-cover SCP may extend in the second direction DR2 from both sides of the second part PT2 that are opposite to each other in the second direction DR2. Basically, the second part PT2 and the sub-cover SCP may be integrally formed.

[0172] refer to Fig. 9C and Fig.9D The sub-cover SCP may be bent with respect to a bending axis parallel to the first direction DR1. The sub-cover SCP may be bent and cover the portion exposed to the display panel DP (see Figure 4B ) a portion of the exposed board OMC outside. The sub-cover SCP may cover two sides of the exposed board OMC that are opposite to each other in the second direction DR2. Therefore, the area of ​​the main circuit board MCB exposed to the outside may be reduced. Therefore, the main circuit board MCB may be prevented from being damaged by external static electricity, and noise may be prevented from being generated near the main circuit board MCB.

[0173] According to an embodiment of the present disclosure, the first cover CVP1 and the second cover CVP2 can prevent static electricity from being generated on the flexible circuit board FPC and the main circuit board MCB, and can block noise. The first cover CVP1 covers the flexible circuit board FPC and the main circuit board MCB, and the second cover CVP2 covers the portion not covered by the first cover CVP1, and thus the area of ​​the flexible circuit board FPC and the main circuit board MCB exposed to the outside can be reduced. Therefore, the possibility of static electricity being generated on the flexible circuit board FPC and the main circuit board MCB can be reduced, and noise generated in the flexible circuit board FPC and the main circuit board MCB can be blocked.

[0174] Although the embodiments have been described above, it will be appreciated by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure described in the appended claims. In addition, it should be understood that the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, and all technical spirits within the appended claims and their equivalents are included within the scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: Display panel; a plurality of flexible circuit boards connected to the display panel, and the plurality of flexible circuit boards are bent and disposed under the display panel; A main circuit board connected to the plurality of flexible circuit boards and disposed below the display panel; A first cover is provided on the display panel. wherein the first covering member is bent with a curvature and is disposed on the rear surface of the display panel, and the first covering member covers a portion of the plurality of flexible circuit boards and a portion of the main circuit board; and The second cover covers other portions of the plurality of flexible circuit boards exposed from the first cover.

2. The display device according to claim 1, wherein: The second cover is bent with a curvature, Wherein, the curvature of the first cover member and the curvature of the second cover member are different from each other.

3. The display device according to claim 1, wherein: The plurality of flexible circuit boards include: a first flexible circuit board overlapping a center of an edge of the display panel in a plan view; and The second flexible circuit board is spaced apart from the first flexible circuit board.

4. The display device according to claim 3, wherein: The first covering member covers the first flexible circuit board and the main circuit board, Wherein, the second covering member covers the second flexible circuit board.

5. The display device according to claim 1, wherein: The main circuit board comprises: a first board connected to the plurality of flexible circuit boards; and A second plate extends from the first plate in a first direction.

6. The display device according to claim 5, wherein: A length of the first plate in a second direction intersecting the first direction is longer than a length of the second plate in the second direction.

7. The display device according to claim 5, wherein: The first covering member comprises: A first component covering the plurality of flexible circuit boards; a second member extending from the first member in the first direction and covering the second plate; and The third component extends from the second component in the first direction and covers the first plate.

8. The display device according to claim 7, wherein: In a plan view, a length of the third component in a second direction intersecting the first direction is longer than a length of the second component in the second direction, and the length of the third component in the second direction is shorter than a length of the first component in the second direction.

9. The display device according to claim 7, wherein: The second covering member is disposed on the first component and covers the second flexible circuit board.

10. The display device according to claim 9, wherein: The second cover is disposed between the first component and the third component in a plan view.

11. The display device according to claim 7, wherein: The first cover includes a plurality of sub-covers arranged on both sides of the second component that are opposite to each other in the second direction, The plurality of sub-covers cover portions of the second plate that are opposite to each other in the second direction.

12. The display device according to claim 1, wherein: Each of the first cover and the second cover comprises: a first covering insulating layer; an intermediate layer, disposed on the first covering insulating layer and comprising at least metal or conductive fibers; and The second cover insulating layer is disposed on the intermediate layer.

13. The display device according to claim 12, wherein: The middle layer is grounded via the main circuit board and the display panel.

14. The display device according to claim 1, wherein: The display device further includes: A data driver is provided on the display panel. Wherein, the first covering member covers the data driver.

15. A display device, wherein: The display device comprises: Display panel; a first flexible circuit board connected to a center of an edge of the display panel and bent from the center of the edge of the display panel; a second flexible circuit board connected to the edge of the display panel and bent from the edge of the display panel, the second flexible circuit board being spaced apart from the first flexible circuit board and adjacent to one side of the edge of the display panel; a main circuit board, disposed on a lower surface of the display panel and connected to the first flexible circuit board and the second flexible circuit board; a first covering member, covering the first flexible circuit board and the main circuit board; and The second covering member covers the second flexible circuit board.

16. The display device according to claim 15, wherein: The first covering member comprises: A first component, covering the first flexible circuit board; a second component extending from the first component in a first direction and covering the main circuit board; and The third component extends from the second component in the first direction and covers the main circuit board.

17. The display device according to claim 16, wherein: In a plan view, a length of the third component in a second direction intersecting the first direction is longer than a length of the second component in the second direction, and the length of the third component in the second direction is shorter than a length of the first component in the second direction.

18. The display device according to claim 16, wherein: The first cover includes a plurality of sub-covers disposed on both sides of the second member that are opposite to each other in a second direction intersecting the first direction, The plurality of sub-covers cover portions on two sides of the main circuit board that are opposite to each other in the second direction.

19. The display device according to claim 16, wherein: The second cover is disposed between the first component and the third component in a plan view.

20. The display device according to claim 15, wherein: Each of the first cover and the second cover comprises: a first covering insulating layer; an intermediate layer, disposed on the first cover insulating layer and comprising at least metal or conductive fibers; and The second cover insulating layer is disposed on the intermediate layer.

Images