Pixel driving circuit, display panel and display device

Abstract

The invention discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a data writing sub-circuit, a first capacitor and a driving sub-circuit. The data write-in sub-circuit is configured to control connection or disconnection of the data signal end and the first node. The transistor includes a first transistor and a second transistor. First poles of the first transistor and the second transistor are connected with a data signal end, second poles of the first transistor and the second transistor are connected with a first node, a control pole of the first transistor is connected with a high-brush scanning signal end, and a control pole of the second transistor is connected with a first scanning signal end. The data write-in sub-circuit is configured such that when the pixel is in a high brush mode, in a data write-in stage, the first transistor is turned on while the second transistor is turned on. One end of the first capacitor is connected with the first node and the other end is connected with the second node. The driving sub-circuit is connected with the second node, the third node and the fourth node and is configured to control connection or disconnection of the third node and the fourth node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) has the advantages of bright colors, higher refresh rate, higher contrast, lower power consumption, etc., which gradually replaces LCD (Liquid Crystal Display) in the small and medium-sized market. However, AMOLED (Active Matrix Organic Light Emitting Diode) has a more complex pixel driving circuit than LCD, which makes the TFT (Thin Film Transistor) process of AMOLED more complicated, so the design of AMOLED pixel driving circuit is particularly important. Summary of the invention

[0003] The purpose of the present application is to provide a pixel driving circuit, a display panel and a display device with excellent data signal writing capability.

[0004] The present application discloses a pixel driving circuit, which comprises:

[0005] A data writing subcircuit is connected to the data signal terminal and the first node, and is configured to control the connection or disconnection between the data signal terminal and the first node; the data writing subcircuit includes a first transistor and a second transistor; the first electrodes of the first transistor and the second transistor are both connected to the data signal terminal, and the second electrodes are both connected to the first node, the control electrode of the first transistor is connected to the high refresh scan signal terminal, and the control electrode of the second transistor is connected to the first scan signal terminal;

[0006] The data writing subcircuit is configured such that when the pixel is in the high refresh mode, in the data writing stage, the high refresh scan signal terminal controls the first transistor to be turned on, and the first scan signal terminal controls the second transistor to be turned on;

[0007] A first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node;

[0008] The driving subcircuit is connected to the second node, the third node and the fourth node, and is configured to control the connection or disconnection of the third node and the fourth node, wherein the third node is connected to the light-emitting unit, and the fourth node is connected to the first power signal terminal.

[0009] Optionally, the data writing sub-circuit is further configured that when the pixel is in the low refresh mode, during the data writing phase, the high refresh scan signal terminal controls the first transistor to be disconnected, and the first scan signal terminal controls the second transistor to be turned on.

[0010] Optionally, the pixel driving circuit further includes:

[0011] a compensation subcircuit, connected to the second node and the third node, and configured to compensate for the data signal;

[0012] The compensation sub-circuit comprises a fourth transistor, a first electrode of the fourth transistor is connected to the third node, a second electrode is connected to the second node, and a control electrode is connected to the second scanning signal terminal;

[0013] The fourth transistor is a metal oxide thin film transistor.

[0014] Optionally, the compensation sub-circuit further includes a tenth transistor;

[0015] The first electrode of the tenth transistor is connected to the second electrode of the fourth transistor, the second electrode is connected to the second node, and the control electrode is connected to the second gate signal terminal; or the first electrode of the tenth transistor is connected to the third node, the second electrode is connected to the first electrode of the fourth transistor, and the control electrode is connected to the second gate signal terminal;

[0016] The tenth transistor is a low temperature polysilicon transistor.

[0017] Optionally, the driving sub-circuit includes a third transistor and a ninth transistor;

[0018] The first electrode of the third transistor is connected to the fourth node, the second electrode is connected to the third node, and the control electrode is connected to the second electrode of the ninth transistor;

[0019] The first electrode of the ninth transistor is connected to the second node, and the control electrode is connected to the fourth scanning signal terminal; the ninth transistor is a metal oxide thin film transistor.

[0020] Optionally, the driving sub-circuit further includes a fifteenth transistor;

[0021] The first electrode of the fifteenth transistor is connected to the second electrode of the ninth transistor, the second electrode is connected to the control electrode of the third transistor, and the control electrode is connected to the fourth gate signal terminal; or the first electrode of the fifteenth transistor is connected to the second node, the second electrode is connected to the first electrode of the ninth transistor, and the control electrode is connected to the fourth gate signal terminal;

[0022] The fifteenth transistor is a low temperature polysilicon transistor.

[0023] Optionally, the pixel driving circuit further includes a first light emitting control subcircuit;

[0024] The first light emitting control subcircuit comprises a sixth transistor and an eleventh transistor, one of the sixth transistor and the eleventh transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0025] The first electrode of the sixth transistor is connected to the second electrode of the eleventh transistor, the second electrode is connected to the fourth node, and the control electrode is connected to the first light emitting control signal terminal;

[0026] The first electrode of the eleventh transistor is connected to the first power signal terminal, and the control electrode is connected to the first gate control signal terminal.

[0027] Optionally, the pixel driving circuit further includes a second light emitting control subcircuit;

[0028] The second light emitting control subcircuit comprises a fifth transistor and a twelfth transistor, one of the fifth transistor and the twelfth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0029] The first electrode of the fifth transistor is connected to the second electrode of the twelfth transistor, the second electrode is connected to the light-emitting unit, and the control electrode is connected to the second light-emitting control signal terminal;

[0030] The first electrode of the twelfth transistor is connected to the third node, and the control electrode is connected to the second gate control signal terminal.

[0031] Optionally, the pixel driving circuit further includes a first reset subcircuit;

[0032] The first reset subcircuit includes an eighth transistor and a thirteenth transistor, one of the eighth transistor and the thirteenth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0033] The first electrode of the eighth transistor is connected to the second electrode of the thirteenth transistor, the second electrode is connected to the light emitting unit, and the control electrode is connected to the third scanning signal terminal;

[0034] The first electrode of the thirteenth transistor is connected to the second reset signal terminal, and the control electrode is connected to the third gate signal terminal.

[0035] Optionally, the pixel driving circuit further includes a second reset subcircuit;

[0036] The second reset subcircuit comprises a seventh transistor and a fourteenth transistor, one of the seventh transistor and the fourteenth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor;

[0037] The first electrode of the seventh transistor is connected to the first reset signal terminal, the second electrode is connected to the first electrode of the fourteenth transistor, and the control electrode is connected to the third scan signal terminal;

[0038] The second electrode of the fourteenth transistor is connected to the first node, and the control electrode is connected to the third gate signal terminal.

[0039] Optionally, the pixel driving circuit further includes a pre-charging sub-circuit;

[0040] The pre-charging sub-circuit is connected to the data signal terminal, the data writing sub-circuit is connected to the data signal terminal through a conductor, and the pre-charging sub-circuit is configured to pre-charge the line between the data signal terminal and the data writing sub-circuit.

[0041] Optionally, the pixel driving circuit further includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein the first light-emitting control subcircuit is connected between the first power signal terminal and the fourth node, and is connected to the first light-emitting control signal terminal; the second light-emitting control subcircuit is connected between the third node and the fourth node, and is connected to the second light-emitting control signal terminal;

[0042] The pre-charge sub-circuit includes a seventeenth transistor;

[0043] The first electrode of the seventeenth transistor is connected to the pre-charge signal terminal, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to: control the seventeenth transistor to be turned on before the data writing stage.

[0044] Optionally, the pre-charging sub-circuit further includes a sixteenth transistor;

[0045] The first electrode of the sixteenth transistor is connected to the second electrode of the seventeenth transistor, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the control signal terminal.

[0046] Optionally, the control signal terminal is configured to: when the pixel is in a high refresh mode, control the sixteenth transistor to be turned on; when the pixel is in a low refresh mode, control the sixteenth transistor to be turned off.

[0047] The present application also provides a display panel, which includes the above-mentioned pixel driving circuit.

[0048] Optionally, the display panel includes a plurality of pixel driving circuits, a plurality of first light-emitting control signal lines, and a plurality of second light-emitting control signal lines, the plurality of pixel driving circuits are arranged in a plurality of rows, the first light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same first light-emitting control signal line, and the second light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same second light-emitting control signal line;

[0049] When the pre-charging sub-circuit includes the seventeenth transistor, in the pixel driving circuit, the control electrode of the seventeenth transistor is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal of the upper n rows of pixel driving circuits, where n is an integer greater than 0.

[0050] The present application also provides a display device, which includes the above-mentioned display panel.

[0051] Compared with the related art, the data writing subcircuit of the present application includes a first transistor and a second transistor arranged in parallel. When the pixel is in the high refresh mode, the first transistor and the second transistor are turned on at the same time during the data writing stage to improve the writing capability of the data signal.

[0052] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0054] Figure 1 FIG. 4 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0055] Figure 2 FIG. 4 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0056] Figure 3 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0057] Figure 4 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0058] Figure 5 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0059] Figure 6In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0060] Figure 7 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0061] Figure 8 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0062] Fig. 9 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0063] Fig.10 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0064] Fig.11 In one embodiment Figure 2 Circuit diagram of the pixel driving circuit.

[0065] Fig.12 In one embodiment Figure 4 A timing diagram of the pixel driving circuit shown.

[0066] Fig.13 FIG. 4 is a schematic block diagram of a pixel driving circuit in an embodiment of the present application.

[0067] Fig.14 In one embodiment, multiple Fig.13 The specific connection circuit diagram of the pixel driving circuit is shown.

[0068] Fig.15 In one embodiment, multiple Fig.13 The specific connection circuit diagram of the pixel driving circuit is shown. DETAILED DESCRIPTION

[0069] Here, the technical solutions in the embodiments (or "implementations") of the present application will be described clearly and completely in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0070] The terms "first" and "second" in the embodiments of the present application are only used for the purpose of convenience of description and should not be understood as indicating or implying relative importance.

[0071] The present application provides a pixel driving circuit for a display panel. Figures 1 to 3 As shown, the pixel driving circuit includes a data writing sub-circuit 10 , a first capacitor C1 and a driving sub-circuit 20 .

[0072] The data writing sub-circuit 10 is connected to the data signal terminal DATA and the first node N1, and is configured to control the connection or disconnection between the data signal terminal DATA and the first node N1. The data writing sub-circuit 10 includes a first transistor T1 and a second transistor T2. The first electrodes of the first transistor T1 and the second transistor T2 are both connected to the data signal terminal DATA, and the second electrodes are both connected to the first node N1. The control electrode of the first transistor T1 is connected to the high refresh scan signal terminal SC-HR, and the control electrode of the second transistor T2 is connected to the first scan signal terminal SC1.

[0073] The data writing sub-circuit DATA is configured as follows: when the display panel is in the high refresh mode, in the data writing stage, the high refresh scan signal terminal SC-HR controls the first transistor T1 to be turned on, and the first scan signal terminal SC1 controls the second transistor T2 to be turned on. The display panel may have a high refresh mode and a low refresh mode, and the number of images displayed per second by the display panel in the high refresh mode is greater than the number of images displayed per second in the low refresh mode.

[0074] One end of the first capacitor C1 is connected to the first node N1 , and the other end of the first capacitor C1 is connected to the second node N2 .

[0075] The driving subcircuit 20 is connected to the second node N2, the third node N3 and the fourth node N4, and is configured to control the connection or disconnection between the third node N3 and the fourth node N4. The third node N3 is connected to the light emitting unit 90, and the fourth node N4 is connected to the first power signal terminal VDD.

[0076] The data writing subcircuit of the present application includes a first transistor and a second transistor arranged in parallel. When the pixel is in the high refresh mode, the first transistor and the second transistor are turned on at the same time during the data writing stage to increase the conduction current between the data signal terminal DATA and the first node N1, thereby improving the writing capability of the data signal data.

[0077] The following will describe in detail various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0078] like Figure 3As shown, the signal terminals connected to the pixel circuit provided by the present application also include a first power signal terminal VDD, a second power signal terminal VSS, a first scan signal terminal SC1, a second scan signal terminal SC2, a third scan signal terminal SC3 and a fourth scan signal terminal SC4, a second gate signal terminal VC2, a third gate signal terminal VC3 and a fourth gate signal terminal VC4, a first light-emitting control signal terminal EM1, a second light-emitting control signal terminal EM2, a first gate control signal terminal VC-M1 and a second gate control signal terminal VC-M2, a first reset signal terminal VINIT1, a second reset signal terminal VINIT2, a control signal terminal CONTROL and a pre-charge signal terminal VRE-CHARGE.

[0079] Wherein, the first power signal terminal VDD and the second power signal terminal VSS are respectively configured to provide the first power signal vdd and the second power signal vss to the pixel circuit. The first scan signal terminal SC1, the second scan signal terminal SC2, the third scan signal terminal SC3 and the fourth scan signal terminal SC4 are respectively configured to provide the first scan signal sc1, the second scan signal sc2, the third scan signal sc3 and the fourth scan signal sc4 to the pixel circuit. The second gate signal terminal VC2, the third gate signal terminal VC3 and the fourth gate signal terminal VC4 are respectively configured to provide the second gate signal vc2, the third gate signal vc3 and the fourth gate signal vc4 to the pixel circuit. Wherein, the second gate signal vc2, the third gate signal vc3 and the fourth gate signal vc4 are respectively opposite in phase to the second scan signal sc2, the third scan signal sc3 and the fourth scan signal sc4. The high refresh scan signal terminal SC-HR is configured to output the high refresh scan signal sc-hr. The first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 are respectively configured to provide the first light-emitting control signal em1 and the second light-emitting control signal em2 to the pixel circuit. The first gate control signal terminal VC-M1 and the second gate control signal terminal VC-M2 are respectively configured to provide the first gate control signal vc-m1 and the second gate control signal vc-m2 to the pixel circuit, and the first gate control signal vc-m1 and the second gate control signal vc-m2 are respectively opposite in phase to the first light-emitting control signal em1 and the second light-emitting control signal em2. The first reset signal terminal VINIT1 and the second reset signal terminal VINIT2 are respectively configured to provide the first reset signal vinit1 and the second reset signal vinit2 to the pixel circuit. The data signal terminal DATA is configured to output the data signal data. The control signal terminal CONTROL is configured to provide the control signal control to the pixel circuit. The pre-charge signal terminal VRE-CHARGE is configured to provide the pre-charge signal terminal vre-charge to the pixel circuit.

[0080] Unless otherwise specified, the transistors used in this application can be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0081] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0083] like Figure 1 As shown, in an optional embodiment, the pixel driving circuit includes a data writing sub-circuit 10 , a first capacitor C1 and a driving sub-circuit 20 .

[0084] The data writing sub-circuit 10 is connected to the first scan signal terminal SC1, the data signal terminal DATA and the first node N1. The data writing sub-circuit 10 is configured to control whether the data signal data is written into the first node N1 under the control of the first scan signal sc1.

[0085] The first node N1 is coupled to the second node N2 via the first capacitor C1 , so that the potential of the second node N2 is adjusted by the potential change of the first node N1 .

[0086] The driving subcircuit 20 is connected to the second node N2, the third node N3 and the fourth node N4, and is configured to control the conduction of the third node N3 and the fourth node N4 under the control of the second node N2. The fourth node N4 is connected to the first power signal terminal VDD, and the third node N3 is connected to the light emitting unit 90.

[0087] like Figure 2 As shown, in an optional embodiment, the pixel driving circuit further includes a compensation subcircuit 30 and / or a first light-emitting control subcircuit 40 and / or a second light-emitting control subcircuit 50 and / or a first reset subcircuit 60 and / or a second reset subcircuit 70.

[0088] The compensation sub-circuit 30 is connected to the second scan signal terminal SC2, the second node N2 and the third node N3. The compensation sub-circuit 30 is configured to control the connection between the second node N2 and the third node N3 under the control of the second scan signal sc2.

[0089] The first light-emitting control subcircuit 40 is disposed between the driving subcircuit 20 and the first power signal terminal VDD. Specifically, the first light-emitting control subcircuit 40 is connected to the first power signal terminal VDD, the first light-emitting control signal terminal EM1 and the fourth node N4. The first light-emitting control subcircuit 40 is configured to control whether the first power signal vdd is written into the fourth node N4 under the control of the first light-emitting control signal em1.

[0090] The second light-emitting control subcircuit 50 is disposed between the driving subcircuit 20 and the light-emitting unit 90. Specifically, the second light-emitting control subcircuit 50 is connected to the second light-emitting control signal terminal EM2, the third node N3 and the fifth node N5, and the fifth node N5 is connected to the light-emitting unit 90. The second light-emitting control subcircuit 50 is configured to control the connection between the fifth node N5 and the third node N3 under the control of the second light-emitting control signal em2.

[0091] The first reset sub-circuit 60 is connected to the second reset signal terminal VINIT2, the third scan signal terminal SC3 and the fifth node N5. The first reset sub-circuit 60 is configured to control whether the second reset signal vinit2 is written into the fifth node N5 under the control of the third scan signal sc3.

[0092] The second reset sub-circuit 70 is connected to the first reset signal terminal VINIT1, the third scan signal terminal SC3 and the first node N1. The second reset sub-circuit 70 is configured to control whether the first reset signal vinit1 is written into the first node N1 under the control of the third scan signal sc3.

[0093] like Figure 3 As shown, in an optional embodiment, the data writing sub-circuit 10 includes a first transistor T1 and a second transistor T2. The first electrodes of the first transistor T1 and the second transistor T2 are both connected to the data signal terminal DATA, the second electrodes of the first transistor T1 and the second transistor T2 are both connected to the first node N1, the control electrode of the first transistor T1 is connected to the high refresh scan signal terminal SC-HR, and the control electrode of the second transistor T2 is connected to the first scan signal terminal SC1. The first transistor T1 and the second transistor T2 can both be low temperature polysilicon transistors.

[0094] The driving subcircuit 20 includes a third transistor T3. A first electrode of the third transistor T3 is connected to the fourth node N4, a second electrode of the third transistor T3 is connected to the third node N3, and a control electrode of the third transistor T3 is connected to the second node N2. The third transistor T3 may be a low temperature polysilicon transistor.

[0095] The compensation subcircuit 30 includes a fourth transistor T4. A first electrode of the fourth transistor T4 is connected to the third node N3, a second electrode of the fourth transistor T4 is connected to the second node N2, and a control electrode of the fourth transistor T4 is connected to the second scan signal terminal SC2. The fourth transistor T4 may be a metal oxide thin film transistor, specifically, the fourth transistor T4 may be an IGZO (Indium Gallium Zinc Oxide) transistor. When the refresh rate of the display panel is low, the fourth transistor T4 is an IGZO transistor, and its lower leakage current can make the potential of the second node N2 more stable, thereby making the signal of the control electrode of the third transistor T3 more stable, thereby bringing better optical performance.

[0096] The first light emission control subcircuit 40 includes a sixth transistor T6. A first electrode of the sixth transistor T6 is connected to the first power signal terminal VDD, a second electrode of the sixth transistor T6 is connected to the fourth node N4, and a control electrode of the sixth transistor T6 is connected to the first light emission control signal terminal EM1. The sixth transistor T6 may be a low temperature polysilicon transistor.

[0097] The second light emission control subcircuit 50 includes a fifth transistor T5. A first electrode of the fifth transistor T5 is connected to the third node N3, a second electrode of the fifth transistor T5 is connected to the light emitting unit 90, and a control electrode of the fifth transistor T5 is connected to the second light emission control signal terminal EM2. The fifth transistor T5 may be a low temperature polysilicon transistor.

[0098] The first reset subcircuit 60 includes an eighth transistor T8. A first electrode of the eighth transistor T8 is connected to the second reset signal terminal VINIT2, a second electrode of the eighth transistor T8 is connected to the fifth node N5, and a control electrode of the eighth transistor T8 is connected to the third scan signal terminal SC3. The eighth transistor T8 may be a low temperature polysilicon transistor.

[0099] The second reset subcircuit 70 includes a seventh transistor T7. A first electrode of the seventh transistor T7 is connected to the first reset signal terminal VINIT1, a second electrode of the seventh transistor T7 is connected to the first node N1, and a control electrode of the seventh transistor T7 is connected to the third scan signal terminal SC3. The seventh transistor T7 may be a low temperature polysilicon transistor.

[0100] like Figure 4 As shown, Figure 4 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 4The driving subcircuit 20 of the circuit shown also includes a ninth transistor T9. The ninth transistor T9 is arranged between the control electrode of the third transistor T3 and the second node N2. Specifically, the first electrode of the ninth transistor T9 is connected to the second node N2, the second electrode of the ninth transistor T9 is connected to the control electrode of the third transistor T3, and the control electrode of the ninth transistor T9 is connected to the fourth scanning signal terminal SC4. The ninth transistor T9 can be a metal oxide thin film transistor, specifically, the ninth transistor T9 can be an IGZO transistor. When the refresh rate of the pixel is low, the ninth transistor T9 is an IGZO transistor, and its lower leakage current can make the signal transmitted from the second node N2 to the control electrode of the third transistor T3 more stable, thereby bringing better optical performance.

[0101] like Figure 5 As shown, Figure 5 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 4 Compared with the circuit shown, Figure 5 The driving subcircuit 20 of the circuit shown also includes a fifteenth transistor T15. The first electrode of the fifteenth transistor T15 is connected to the second electrode of the ninth transistor T9, the second electrode of the fifteenth transistor T15 is connected to the control electrode of the third transistor T3, and the control electrode of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. Alternatively, the first electrode of the fifteenth transistor T15 is connected to the second node N2, the second electrode of the fifteenth transistor T15 is connected to the first electrode of the ninth transistor T9, and the control electrode of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. The fifteenth transistor T15 can be a low-temperature polysilicon transistor. Since the ninth transistor T9 is connected in series with the fifteenth transistor T15, and the ninth transistor T9 is a low-temperature polysilicon transistor, the fifteenth transistor T15 is an IGZO transistor, which can effectively prevent the leakage current of the second node N2 from affecting the control electrode of the third transistor T3.

[0102] like Figure 6 As shown, Figure 6 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 6The compensation subcircuit 30 of the circuit shown also includes a tenth transistor T10. The first electrode of the tenth transistor T10 is connected to the second electrode of the fourth transistor T4, the second electrode of the tenth transistor T10 is connected to the second node N2, and the control electrode of the tenth transistor T10 is connected to the second gate signal terminal VC2. Or the first electrode of the tenth transistor T10 is connected to the third node N3, the second electrode of the tenth transistor T10 is connected to the first electrode of the fourth transistor T4, and the control electrode of the tenth transistor T10 is connected to the second gate signal terminal VC2. The tenth transistor is a low-temperature polysilicon transistor. Since the tenth transistor T10 is connected in series with the fourth transistor T4, and the tenth transistor T10 is a low-temperature polysilicon transistor, and the fourth transistor T4 is an IGZO transistor, the leakage current of the third node N3 can be effectively prevented from affecting the second node N2.

[0103] like Figure 7 As shown, Figure 7 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 7 The first light-emitting control subcircuit 40 of the circuit shown also includes an eleventh transistor T11. The first electrode of the eleventh transistor T11 is connected to the first power signal terminal VDD, the second electrode of the eleventh transistor T11 is connected to the first electrode of the sixth transistor T6, and the control electrode of the eleventh transistor T11 is connected to the first gate control signal terminal VC-M1. One of the sixth transistor T6 and the eleventh transistor T11 is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor. In this embodiment, the sixth transistor T6 is a low-temperature polysilicon transistor and the eleventh transistor T11 is an IGZO transistor, which can effectively prevent the leakage current of the first power signal terminal VDD from affecting the fourth node N4.

[0104] like Figure 8 As shown, Figure 8 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Figure 8 The second light emitting control subcircuit 50 of the circuit shown also includes a twelfth transistor T12. The first electrode of the twelfth transistor T12 is connected to the third node N3, the second electrode of the twelfth transistor T12 is connected to the first electrode of the fifth transistor T5, and the control electrode of the twelfth transistor T12 is connected to the second gate control signal terminal VC-M2. One of the fifth transistor T5 and the twelfth transistor T12 is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor. In this embodiment, the fifth transistor T5 is a low-temperature polysilicon transistor, and the twelfth transistor T12 is an IGZO transistor, which can effectively prevent the leakage current of the third node N3 from affecting the fifth node N5.

[0105] like Fig. 9 As shown, Fig. 9 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Fig. 9 The first reset subcircuit 60 of the circuit shown also includes a thirteenth transistor T13. The first electrode of the thirteenth transistor T13 is connected to the second reset signal terminal VINIT2, the second electrode of the thirteenth transistor T13 is connected to the first electrode of the eighth transistor T8, and the control electrode of the thirteenth transistor T13 is connected to the third gate signal terminal VC3. One of the eighth transistor T8 and the thirteenth transistor T13 is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor. In this embodiment, the eighth transistor T8 is a low-temperature polysilicon transistor and the thirteenth transistor T13 is an IGZO transistor, which can effectively prevent the leakage current of the second reset signal terminal VINIT2 from affecting the fifth node N5.

[0106] like Fig.10 As shown, Fig.10 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Fig.10 The second reset subcircuit 70 of the circuit shown also includes a fourteenth transistor T14. The first electrode of the fourteenth transistor T14 is connected to the second electrode of the seventh transistor T7, the second electrode of the fourteenth transistor T14 is connected to the first node N1, and the control electrode of the fourteenth transistor T14 is connected to the third gate signal terminal VC3. One of the seventh transistor T7 and the fourteenth transistor T14 is a low-temperature polysilicon transistor and the other is a metal oxide thin film transistor. In this embodiment, the seventh transistor T7 is a low-temperature polysilicon transistor and the fourteenth transistor T14 is an IGZO transistor, which can effectively prevent the leakage current of the first reset signal terminal VINIT1 from affecting the first node N1.

[0107] like Fig.11 As shown, Fig.11 FIG. 1 is a circuit diagram of a pixel circuit in another optional embodiment. Figure 3 Compared with the circuit shown, Fig.11 The driving subcircuit 20 of the circuit shown further includes a ninth transistor T9 and a fifteenth transistor T15, the compensation subcircuit 30 further includes a tenth transistor T10, the first light-emitting control subcircuit 40 further includes an eleventh transistor T11, the second light-emitting control subcircuit 50 further includes a twelfth transistor T12, the first reset subcircuit 60 further includes a thirteenth transistor T13, and the second reset subcircuit 70 further includes a fourteenth transistor T14. The connection methods and types of the above transistors are similar to Figures 4 to 10 The embodiment shown is the same as that shown in the figure, and no further description will be given here. Of course, in some optional embodiments, the pixel circuit can be Figures 4 to 10 Combinations of the embodiments shown, for example, the pixel circuit may be configured Figure 5The ninth transistor T9 and the fifteenth transistor T15 are shown Fig.10 The fourteenth transistor T14 shown may also be set Figure 6 The tenth transistor T10 and Figure 7 The eleventh transistor T11 is shown and so on.

[0108] like Fig.12 As shown, Fig.12 In one embodiment Figure 4 The timing diagram of the circuit diagram shown. The driving period of a frame includes an initialization period S1, a compensation period S2, a data writing period S3 and a light emitting period S4. The data writing sub-circuit 10 is configured such that when the display panel is in the high refresh mode, in the S3 stage, the high refresh scan signal terminal SC-HR controls the first transistor T1 to be turned on; when the display panel is in the low refresh mode, in the S3 stage, the high refresh scan signal terminal SC-HR controls the first transistor to be turned off.

[0109] like Fig.12 As shown, in the S1 period, the first scanning signal sc1 is high, the second scanning signal sc2 is low, the third scanning signal sc3 is low, the fourth scanning signal sc4 is low, the first light-emitting control signal em1 is high, and the first light-emitting control signal em1 is changed to high. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off. The seventh transistor T7 and the eighth transistor T8 are turned on. The first reset signal vinit1 resets the first node N1 and the second node N2, and the second reset signal vinit2 resets the fifth node N5.

[0110] like Fig.12 As shown, in the S2 period, the second scanning signal sc2 is changed to a high potential, the fourth scanning signal sc4 is changed to a high potential, and the first light-emitting control signal em1 is changed to a low potential. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned into a conductive state. The first power signal vdd starts to charge the second node N2 until the second node N2 is charged to a potential of ELVDD+Vth, where ELVDD is the potential of the first power signal vdd, and Vth is the threshold voltage of the third transistor T3.

[0111] like Fig.12As shown, in the S3 period, the first scanning signal sc1 is changed to a low potential, the second scanning signal sc2 is changed to a low potential, the third scanning signal sc3 is changed to a high potential, and the first light-emitting control signal em1 is changed to a high potential. The first transistor T1 and the second transistor T2 are changed to an on state, and the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the sixth transistor T6 are changed to an off state. The data signal data is written into the first node N1 and written into the second node N2 through the first capacitor C1, and the potential of the second node N2 is changed to Vdata+ELVDD+Vth. In this way, when the third transistor T3 is driven, it can offset the influence of the ELVDD voltage drop and the influence of Vth.

[0112] like Fig.12 As shown, in the S4 period, the first scanning signal sc1 is changed to a high potential, the first light-emitting control signal em1 is changed to a low potential, and the second light-emitting control signal em2 is changed to a low potential. The first transistor T1 and the second transistor T2 are changed to an off state, and the fifth transistor T5 and the sixth transistor T6 are changed to an on state. The third transistor T3 is turned on under the control of the potential of the second node N2, and the first power supply signal vdd is connected to the light-emitting unit 90 through the sixth transistor T6, the third transistor T3 and the fifth transistor T5 to drive the light-emitting unit 90 to emit light.

[0113] Afterwards, the pixel circuit repeats the above driving sequence to control the light-emitting unit 90 to emit light.

[0114] For pixel circuits in other embodiments of the present application, the light-emitting unit 90 may also be driven to emit light according to the above-mentioned timing logic. Fig.11 The pixel circuit shown in FIG. 1 can also be operated according to the method described in detail, because the added transistor and the driving end do not affect the conduction of the original circuit. Fig.12 The driving is realized by referring to the timing diagram shown in the figure.

[0115] like Fig.13 As shown, in an optional embodiment, the pixel driving circuit further includes a pre-charging sub-circuit 80. The pre-charging sub-circuit 80 is connected to the data signal terminal DATA, and the data writing sub-circuit 10 is connected to the data signal terminal DATA through a wire. The pre-charging sub-circuit 80 is configured to pre-charge the line between the data signal terminal DATA and the data writing sub-circuit 10.

[0116] like Fig.14As shown, the pre-charge sub-circuit 80 further includes a seventeenth transistor T17. The first electrode of the seventeenth transistor T17 is connected to the pre-charge signal terminal VRE-CHARGE, the second electrode of the seventeenth transistor T17 is connected to the data signal terminal DATA and the wire between the data writing sub-circuit 10, and the control electrode of the seventeenth transistor T17 is connected to the first light-emitting control signal terminal EM1 or the second light-emitting control signal terminal EM2. The seventeenth transistor T17 can be a metal oxide thin film transistor, specifically, the seventeenth transistor T17 can be an IGZO transistor. According to Fig.12 As can be seen from the timing sequence shown, the seventeenth transistor T17 is turned on before the S3 period, ie, the data writing period, so that the precharge signal terminal VRE-CHARGE precharges the wire between the data signal terminal DATA and the data writing sub-circuit 10 .

[0117] like Fig.14 As shown, optionally, the pre-charge sub-circuit 80 also includes a sixteenth transistor T16. The first electrode of the sixteenth transistor T16 is connected to the second electrode of the seventeenth transistor T17, the second electrode of the sixteenth transistor T16 is connected to the wire between the data signal terminal DATA and the data writing sub-circuit 10, and the control electrode of the sixteenth transistor T16 is connected to the control signal terminal CONTRIL. The control signal terminal CONTRIL is configured to control the sixteenth transistor T16 to be turned on when the pixel is in the high refresh mode, and to control the sixteenth transistor T16 to be turned off when the pixel is in the low refresh mode. In this way, the writing ability of the data signal data can be improved when the pixel is in the high refresh mode, and power consumption can be saved when the pixel is in the low refresh mode. The sixteenth transistor T16 is a low-temperature polysilicon transistor, and because the seventeenth transistor T17 is a metal oxide thin film transistor, the leakage current of the pre-charge signal terminal VRE-CHARGE can be effectively prevented from affecting the wire between the data signal terminal DATA and the data writing sub-circuit 10.

[0118] The present application also provides a display panel, the display panel comprising the above-mentioned pixel driving circuit. The display panel also comprises a plurality of sub-pixels, the sub-pixels and the pixel driving circuits may correspond one to one, and each pixel driving circuit is electrically connected to a corresponding sub-pixel to drive the corresponding sub-pixel.

[0119] The display panel includes a plurality of pixel driving circuits, a plurality of first light emitting control signal lines, and a plurality of second light emitting control signal lines. The plurality of pixel driving circuits are arranged in a plurality of rows, a first light emitting control signal terminal EM1 of a row of pixel driving circuits is connected to the same first light emitting control signal line, and a second light emitting control signal terminal EM2 of a row of pixel driving circuits is connected to the same second light emitting control signal line.

[0120] like Fig.15As shown, when the pre-charging sub-circuit 80 includes the seventeenth transistor T17, in the pixel driving circuit, the control electrode of the seventeenth transistor T17 is connected to the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the upper n-row pixel driving circuit, where n is an integer greater than 0. In this way, when the light-emitting control signal provided to the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the upper n-row pixel driving circuit is at a high potential, the seventeenth transistor T17 is turned on, which can effectively ensure that the pre-charging signal terminal VRE-CHARGE pre-charges the wire between the data signal terminal DATA and the data writing sub-circuit 10 before the pixel circuit writes data.

[0121] The present application also provides a display device, which includes the above-mentioned display panel.

[0122] In one embodiment, the display device further includes a driver and a power supply circuit, wherein the driver is used to provide a driving signal for driving the sub-pixel to emit light, and the power supply circuit is used to supply power to the display substrate.

[0123] In one embodiment, the display device further includes a housing, and the display panel is disposed in the housing.

[0124] The display device provided in the embodiment of the present application may be, for example, a mobile phone, a tablet computer, a television, a laptop computer, a vehicle-mounted device, or any other device with a display function.

[0125] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without causing conflicts. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A pixel driving circuit, characterized in that: For display panels; The pixel driving circuit comprises: A data writing subcircuit is connected to the data signal terminal and the first node, and is configured to control the connection or disconnection between the data signal terminal and the first node; the data writing subcircuit includes a first transistor and a second transistor; the first electrodes of the first transistor and the second transistor are both connected to the data signal terminal, and the second electrodes are both connected to the first node, the control electrode of the first transistor is connected to the high refresh scan signal terminal, and the control electrode of the second transistor is connected to the first scan signal terminal; The data writing sub-circuit is configured as follows: when the display panel is in a high refresh mode, in a data writing stage, the high refresh scan signal terminal controls the first transistor to be turned on, and the first scan signal terminal controls the second transistor to be turned on; A first capacitor, one end of which is connected to the first node, and the other end of which is connected to the second node; The driving subcircuit is connected to the second node, the third node and the fourth node, and is configured to control the connection or disconnection of the third node and the fourth node, wherein the third node is connected to the light-emitting unit, and the fourth node is connected to the first power signal terminal.

2. The pixel driving circuit according to claim 1, characterized in that: The data writing sub-circuit is further configured such that: when the display panel is in a low refresh mode, during a data writing phase, the high refresh scan signal terminal controls the first transistor to be disconnected, and the first scan signal terminal controls the second transistor to be turned on.

3. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: a compensation subcircuit, connected to the second node and the third node, and configured to compensate for the data signal; The compensation sub-circuit comprises a fourth transistor, a first electrode of the fourth transistor is connected to the third node, a second electrode is connected to the second node, and a control electrode is connected to the second scanning signal terminal; The fourth transistor is a metal oxide thin film transistor.

4. The pixel driving circuit according to claim 3, characterized in that: The compensation sub-circuit further includes a tenth transistor; The first electrode of the tenth transistor is connected to the second electrode of the fourth transistor, the second electrode is connected to the second node, and the control electrode is connected to the second gate signal terminal; or the first electrode of the tenth transistor is connected to the third node, the second electrode is connected to the first electrode of the fourth transistor, and the control electrode is connected to the second gate signal terminal; The tenth transistor is a low temperature polysilicon transistor.

5. The pixel driving circuit according to claim 1, characterized in that: The driving sub-circuit includes a third transistor and a ninth transistor; The first electrode of the third transistor is connected to the fourth node, the second electrode is connected to the third node, and the control electrode is connected to the second electrode of the ninth transistor; The first electrode of the ninth transistor is connected to the second node, and the control electrode is connected to the fourth scanning signal terminal; the ninth transistor is a metal oxide thin film transistor.

6. The pixel driving circuit according to claim 5, characterized in that: The driving sub-circuit further includes a fifteenth transistor; The first electrode of the fifteenth transistor is connected to the second electrode of the ninth transistor, the second electrode is connected to the control electrode of the third transistor, and the control electrode is connected to the fourth gate signal terminal; or the first electrode of the fifteenth transistor is connected to the second node, the second electrode is connected to the first electrode of the ninth transistor, and the control electrode is connected to the fourth gate signal terminal; The fifteenth transistor is a low temperature polysilicon transistor.

7. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a first light emitting control subcircuit; The first light emitting control subcircuit comprises a sixth transistor and an eleventh transistor, one of the sixth transistor and the eleventh transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the sixth transistor is connected to the second electrode of the eleventh transistor, the second electrode is connected to the fourth node, and the control electrode is connected to the first light emitting control signal terminal; The first electrode of the eleventh transistor is connected to the first power signal terminal, and the control electrode is connected to the first gate control signal terminal.

8. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit also includes a second light emitting control subcircuit; The second light emitting control subcircuit comprises a fifth transistor and a twelfth transistor, one of the fifth transistor and the twelfth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the fifth transistor is connected to the second electrode of the twelfth transistor, the second electrode is connected to the light-emitting unit, and the control electrode is connected to the second light-emitting control signal terminal; The first electrode of the twelfth transistor is connected to the third node, and the control electrode is connected to the second gate control signal terminal.

9. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a first reset subcircuit; The first reset subcircuit includes an eighth transistor and a thirteenth transistor, one of the eighth transistor and the thirteenth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the eighth transistor is connected to the second electrode of the thirteenth transistor, the second electrode is connected to the light emitting unit, and the control electrode is connected to the third scanning signal terminal; The first electrode of the thirteenth transistor is connected to the second reset signal terminal, and the control electrode is connected to the third gate signal terminal.

10. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a second reset subcircuit; The second reset subcircuit comprises a seventh transistor and a fourteenth transistor, one of the seventh transistor and the fourteenth transistor is a low temperature polysilicon transistor and the other is a metal oxide thin film transistor; The first electrode of the seventh transistor is connected to the first reset signal terminal, the second electrode is connected to the first electrode of the fourteenth transistor, and the control electrode is connected to the third scan signal terminal; The second electrode of the fourteenth transistor is connected to the first node, and the control electrode is connected to the third gate signal terminal.

11. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit also includes a pre-charging sub-circuit; The pre-charging sub-circuit is connected to the data signal terminal, the data writing sub-circuit is connected to the data signal terminal through a conductor, and the pre-charging sub-circuit is configured to pre-charge the line between the data signal terminal and the data writing sub-circuit.

12. The pixel driving circuit according to claim 11, characterized in that: The pixel driving circuit further includes a first light emitting control subcircuit and a second light emitting control subcircuit, wherein the first light emitting control subcircuit is connected between the first power signal terminal and the fourth node, and is connected to the first light emitting control signal terminal; The second light emitting control subcircuit is connected between the third node and the fourth node, and is connected to the second light emitting control signal terminal; The pre-charge sub-circuit includes a seventeenth transistor; The first electrode of the seventeenth transistor is connected to the pre-charge signal terminal, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to: control the seventeenth transistor to be turned on before the data writing stage.

13. The pixel driving circuit according to claim 12, characterized in that: The pre-charge sub-circuit further includes a sixteenth transistor; The first electrode of the sixteenth transistor is connected to the second electrode of the seventeenth transistor, the second electrode is connected to the data signal terminal and the wire between the data writing sub-circuit, and the control electrode is connected to the control signal terminal.

14. The pixel driving circuit according to claim 13, characterized in that: The control signal terminal is configured to: when the display panel is in a high refresh mode, control the sixteenth transistor to be turned on; when the pixel is in a low refresh mode, control the sixteenth transistor to be turned off.

15. A display panel, characterized in that: The display panel comprises a pixel driving circuit as described in any one of claims 1-14.

16. The display panel according to claim 15, characterized in that: The display panel comprises a plurality of pixel driving circuits, a plurality of first light-emitting control signal lines and a plurality of second light-emitting control signal lines, wherein the plurality of pixel driving circuits are arranged in a plurality of rows, wherein the first light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same first light-emitting control signal line, and the second light-emitting control signal terminals of the pixel driving circuits in a row are connected to the same second light-emitting control signal line; When the pre-charging sub-circuit includes the seventeenth transistor, in the pixel driving circuit, the control electrode of the seventeenth transistor is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal of the upper n rows of pixel driving circuits, where n is an integer greater than 0.

17. A display device, characterized in that: The display device comprises the display panel according to claim 15 or 16.

Images