Semiconductor device and preparation method thereof
By forming a first inter-gate dielectric layer with a groove and an oxidized second inter-gate dielectric layer in the semiconductor device, the problems of insufficient thickness and holes in the high-deep aspect ratio trench structure are solved, and higher quality is achieved and reliable intergate dielectric layer reduces cost and process complexity.
Patent Information
- Application Number
- CN202411301870.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2024-12-27
AI Technical Summary
In the prior art, when forming the intergate dielectric layer of semiconductor devices, holes and insufficient thickness are prone to occur in the high-deep aspect ratio trench structure, resulting in increased leakage current and capacitance, complex process and poor reliability.
By forming a first intergate dielectric layer with a groove and a crystalline silicon layer located in the groove, and forming a second intergate dielectric layer by oxidation, combining a CVD process and an etching process, a shielded gate and Dielectric layer between gates.
The formation of a thicker thickness and better quality intergrid dielectric layer in a trench structure with a high aspect ratio reduces leakage current and capacitance, improves the reliability of semiconductor devices, and avoids the formation of additional mask layers, reducing the formation of cost.
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Figure CN119208138A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art
[0002] In a semiconductor device with a shielded gate, there is an inter-gate dielectric layer between the shielded gate and the gate. The inter-gate dielectric layer is usually composed of silicon oxide, etc. The thickness and density of the inter-gate dielectric layer determine the leakage current and inter-gate capacitance between the shielded gate and the gate.
[0003] For trench-type shielded gate devices, the inter-gate dielectric layer is usually formed by filling silicon oxide in the trench and etching back through the HDPCVD (High Density Plasma Chemical Vapor Deposition) process, or by a one-step molding process, that is, thermally oxidizing the polysilicon shielding gate to form the inter-gate dielectric layer.
[0004] The HDPCVD process has high requirements for the aspect ratio before filling. For trench structures with a high aspect ratio, holes are prone to appear in the inter-gate dielectric layer, which affects the stability of the quality of the inter-gate dielectric layer, resulting in increased inter-gate leakage current and inter-gate capacitance, and requires the formation of an additional mask layer, which makes the process complicated. The maximum thickness of the inter-gate dielectric layer formed by the one-step molding process is limited by the thermal oxidation thickness of the polysilicon shielding gate, and it is easy to have insufficient thickness, resulting in increased inter-gate leakage current and inter-gate capacitance, and poor reliability.
[0005] Therefore, improvements are needed to at least partially solve the above problems. Summary of the invention
[0006] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.
[0007] In order to at least partially solve the above problem, according to a first aspect of the present invention, a method for preparing a semiconductor device is provided, comprising:
[0008] Providing a substrate, forming a groove in the substrate, and forming a shielding gate structure in the lower space of the groove, wherein the shielding gate structure includes a shielding gate and a first gate dielectric layer located between the shielding gate and the inner surface of the groove;
[0009] forming a first inter-gate dielectric layer having a groove in the groove and a crystalline silicon layer located in the groove, wherein the first inter-gate dielectric layer covers the top of the shielding gate structure and a portion of the sidewall of the groove and surrounds the groove;
[0010] Oxidizing the crystalline silicon layer and the exposed inner surface of the trench to form a second inter-gate dielectric layer and a second gate dielectric layer;
[0011] A gate is formed in the trench.
[0012] Exemplarily, a shielding gate structure is formed in the lower space of the trench, including:
[0013] forming a first dielectric layer on the inner surface of the groove;
[0014] Filling the trench with a shielding grid material;
[0015] removing a portion of the shielding grid material in the groove;
[0016] Etching the first dielectric layer to form the first gate dielectric layer, wherein the upper surface of the first gate dielectric layer is lower than the upper surface of the remaining shielding gate material;
[0017] The remaining shielding gate material is etched to form the shielding gate, wherein the upper surface of the shielding gate is flush with the upper surface of the first gate dielectric layer.
[0018] Exemplarily, forming a first inter-gate dielectric layer having a groove in the trench and a crystalline silicon layer located in the groove includes:
[0019] Oxidizing the exposed inner surface of the trench to form a gate oxide layer;
[0020] Forming a second dielectric layer on the surface of the shielding gate structure and the surface of the gate oxide layer by a CVD process;
[0021] Filling the trench with crystalline silicon material, and partially removing the crystalline silicon material so that the upper surface of the remaining crystalline silicon material is lower than the opening of the trench;
[0022] Etching the gate oxide layer and the second dielectric layer so that the upper surface of the remaining gate oxide layer and the upper surface of the remaining second dielectric layer are lower than the upper surface of the remaining crystalline silicon material, wherein the remaining gate oxide layer and the remaining second dielectric layer together constitute the first inter-gate dielectric layer;
[0023] The upper surface of the remaining crystalline silicon material is etched to the upper surface of the first inter-gate dielectric layer to form the crystalline silicon layer.
[0024] Exemplarily, the thickness of the gate oxide layer is 3nm-30nm.
[0025] Exemplarily, forming a first inter-gate dielectric layer having a groove in the trench and a crystalline silicon layer located in the groove includes:
[0026] forming a third dielectric layer on the surface of the shielding gate structure and the exposed inner surface of the trench by a CVD process;
[0027] Filling the trench with crystalline silicon material, and partially removing the crystalline silicon material so that the upper surface of the remaining crystalline silicon material is lower than the opening of the trench;
[0028] Etching the third dielectric layer to form the first inter-gate dielectric layer, wherein an upper surface of the first inter-gate dielectric layer is lower than an upper surface of the remaining crystalline silicon material;
[0029] The upper surface of the remaining crystalline silicon material is etched to the upper surface of the first inter-gate dielectric layer to form the crystalline silicon layer.
[0030] Exemplarily, the thickness of the remaining crystalline silicon material is 100 nm-250 nm.
[0031] Exemplarily, the thickness of the crystalline silicon layer is 20nm-100nm.
[0032] Exemplarily, the crystalline silicon layer is an undoped polycrystalline silicon layer.
[0033] Exemplarily, the first gate dielectric layer is a silicon dioxide layer;
[0034] The first inter-gate dielectric layer is a silicon dioxide layer;
[0035] The second inter-gate dielectric layer is a silicon dioxide layer;
[0036] The second gate dielectric layer is a silicon dioxide layer. According to a second aspect of the present invention, a semiconductor device is provided, and the semiconductor device is manufactured by the manufacturing method as described above.
[0037] According to the semiconductor device and the preparation method thereof of the present invention, the inter-gate dielectric layer located between the shielding gate and the gate is composed of at least a first inter-gate dielectric layer and a second inter-gate dielectric layer formed by oxidizing the crystalline silicon layer. On the one hand, compared with the HDPCVD process, a thicker and better quality inter-gate dielectric layer can be formed in a trench structure with a high aspect ratio without forming an additional mask layer, which can effectively reduce costs. On the other hand, compared with the one-step molding process, the thickness of the inter-gate dielectric layer can be significantly increased, the inter-gate leakage current and the inter-gate capacitance can be reduced, and the reliability of the formed semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,
[0039] Figure 1 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present application;
[0040] Figures 2 to 14 FIG. 4 is a schematic cross-sectional view of a device structure in a method for preparing a semiconductor device according to an embodiment of the present invention.
[0041] Description of reference numerals:
[0042] 100-base, 110-substrate, 120-epitaxial layer, 121-groove, 200-first dielectric layer, 210-first gate dielectric layer, 300-shielding gate material, 310-shielding gate, 400-gate oxide layer, 500-second dielectric layer, 600-crystalline silicon material, 610-crystalline silicon layer, 700-second inter-gate dielectric layer, 800-second gate dielectric layer, 900-gate. DETAILED DESCRIPTION
[0043] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.
[0044] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.
[0045] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.
[0046] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.
[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0048] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.
[0049] See attached Figure 1 An exemplary method for preparing a semiconductor device according to an embodiment of the present application is described. The semiconductor device may be a trench-type shielded gate device, that is, a shielded gate trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The preparation method comprises the following steps:
[0050] S100: providing a substrate, forming a groove in the substrate, and forming a shielding gate structure in the lower space of the groove, wherein the shielding gate structure includes a shielding gate and a first gate dielectric layer located between the shielding gate and the inner surface of the groove.
[0051] S200: forming a first inter-gate dielectric layer having a groove in the trench and a crystalline silicon layer located in the groove, wherein the first inter-gate dielectric layer covers the top of the shielding gate structure and a portion of the trench sidewall and surrounds the groove.
[0052] S300: Oxidizing the crystalline silicon layer and the exposed inner surface of the trench to form a second inter-gate dielectric layer and a second gate dielectric layer.
[0053] S400: forming a gate in the trench.
[0054] According to the method for preparing a semiconductor device in an embodiment of the present application, the inter-gate dielectric layer located between the shielding gate and the gate is composed of at least a first inter-gate dielectric layer and a second inter-gate dielectric layer formed by oxidizing the crystalline silicon layer. On the one hand, compared with the HDPCVD process, a thicker and better-quality inter-gate dielectric layer can be formed in a trench structure with a high aspect ratio without forming an additional mask layer, which can effectively reduce costs. On the other hand, compared with the one-step molding process, the thickness of the inter-gate dielectric layer can be significantly increased, the inter-gate leakage current and the inter-gate capacitance can be reduced, and the reliability of the formed semiconductor device can be improved.
[0055] Please refer to the attached Figure 2 -Attached Fig.14 A method for preparing a semiconductor device according to an embodiment of the present application is described in detail. The semiconductor device is prepared through the above steps S100 - S400 .
[0056] In step S100, first, see the attached Figure 2, providing a substrate 100, forming a groove 121 in the substrate 100. Specifically, the substrate 100 includes a substrate 110 and an epitaxial layer 120. In this embodiment, the substrate 110 is a silicon substrate. In some other embodiments, the substrate 110 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors. The epitaxial layer 120 is formed on the substrate 110 by an epitaxial process, and the epitaxial process may be, for example, a CVD (Chemical Vapor Deposition) process or an MBE (Molecular Beam Epitaxy) process. In this embodiment, the material of the epitaxial layer 120 is silicon. In some other embodiments, the material of the epitaxial layer 120 may be silicon carbide or other suitable materials known to those skilled in the art. In some other embodiments, the substrate 100 may only include the substrate 110. Then, a patterned mask layer (not shown) can be formed on the epitaxial layer 120 by processes such as mask material deposition, photolithography, etching, and photoresist removal. Exemplarily, the mask layer can be a silicon dioxide layer. Afterwards, using the mask layer as a mask, a groove 121 is formed in the substrate 100 by a dry etching process and / or a wet etching process, that is, a groove 121 is formed in the epitaxial layer 120, and the depth of the groove 121 is less than the thickness of the epitaxial layer 120. After the groove 121 is formed, the mask layer can be removed by a CMP (Chemical Mechanical Polishing) process or an etching process.
[0057] Then, see Appendix Figure 3 , a first dielectric layer 200 is formed on the inner surface of the groove 121. Specifically, the first dielectric layer 200 can be formed on the inner surface of the groove 121 by a thermal oxidation process and / or a CVD process. In the present embodiment, the first dielectric layer 200 is a silicon dioxide layer, which is simultaneously formed on the upper surface of the epitaxial layer 120. In some other embodiments, the first dielectric layer 200 can be a multilayer structure, for example, it can be an ONO (Oxide-Nitride-Oxide, oxide layer-nitride layer-oxide layer) structure or an ON (Oxide-Nitride, oxide layer-nitride layer) structure. After the first dielectric layer 200 is formed, the shielding gate material 300 is filled in the groove 121. Exemplarily, the shielding gate material 300 can be filled in the groove 121 by a CVD process or other suitable deposition process. In the present embodiment, the shielding gate material 300 is polysilicon.
[0058] Then, see Appendix Figure 4, removing part of the shielding gate material 300 in the groove 121. Specifically, the shielding gate material 300 in the groove 121 can be etched by a plasma etching process, a reactive ion etching process or other suitable dry etching process, so that the upper surface of the remaining shielding gate material 300 is much lower than the opening of the groove 121. In some embodiments, the shielding gate material 300 can also be etched by a wet etching process to remove part of the shielding gate material 300 in the groove 121.
[0059] Then, see Appendix Figure 5 , the first dielectric layer 200 is etched to form a first gate dielectric layer 210, and the upper surface of the first gate dielectric layer 210 is lower than the upper surface of the shielding gate material 300. The first gate dielectric layer 210 is also the first dielectric layer 200 remaining after etching. Exemplarily, the first dielectric layer 200 can be etched by a wet etching process. Exemplarily, the first dielectric layer 200 can be etched using a hydrofluoric acid solution or other suitable wet etching solution to form the first gate dielectric layer 210. After the first dielectric layer 200 is etched, the inner surface of a portion of the groove 121 is exposed.
[0060] Then, see Appendix Figure 6 , the remaining shielding gate material 300 is etched to form a shielding gate 310, and the upper surface of the shielding gate 310 is flush with the upper surface of the first gate dielectric layer 210. Exemplarily, the shielding gate material 300 in the trench 121 can be etched by a plasma etching process, a reactive ion etching process or other suitable dry etching process to form the shielding gate 310. In this embodiment, the shielding gate 310 is a polysilicon gate.
[0061] Since the material of the first dielectric layer 200 is different from that of the shielding grid 310, a wet etching process and a dry etching process can be used for etching respectively. However, it is difficult to accurately control the etching depth in the wet etching process, and the dry etching process can relatively accurately control the etching depth. Therefore, in this embodiment, the first dielectric layer 200 is first etched to a depth lower than the remaining shielding grid material 300 by a wet etching process to form a first gate dielectric layer 210, and then the remaining shielding grid material 300 is etched to be flush with the upper surface of the first gate dielectric layer 210 by a dry etching process to form a shielding grid 310. The upper surface of the shielding grid 310 is flush with the upper surface of the first gate dielectric layer 210, which can effectively improve the quality of the inter-gate dielectric layer formed subsequently.
[0062] In step S200, first, see the attached Figure 7, the exposed inner surface of the trench 121 (that is, the inner surface of the upper space in the trench 121) is oxidized to form a gate oxide layer 400. In this embodiment, the gate oxide layer 400 is a silicon dioxide layer, and the gate oxide layer 400 is used to protect the inner surface of the trench 121 to prevent it from being damaged in the subsequent CVD process. Exemplarily, the exposed inner surface of the trench 121 can be oxidized by a thermal oxidation process or other suitable oxidation process. Exemplarily, the thickness of the gate oxide layer 400 (that is, Figure 7 The height of the gate oxide layer 400 in the left-right direction is 3nm-30nm. It should be noted that when the shielding gate 310 is a polysilicon gate, when the gate oxide layer 400 is formed on the inner surface exposed by the trench 121 through a thermal oxidation process, an oxide layer (not shown in the figure) will also be formed on the surface of the shielding gate 310. Exemplarily, the gate oxide layer 400 is also formed on the upper surface of the epitaxial layer 120.
[0063] Then, see Appendix Figure 8 , a second dielectric layer 500 is formed on the surface of the shield gate 310 structure and the surface of the gate oxide layer 400 by a CVD process. That is, a second dielectric layer 500 is formed on the sidewall and bottom of the current trench 121 as a whole. In this embodiment, the second dielectric layer 500 is a silicon dioxide layer. Exemplarily, the CVD process can be a SACVD (sub-atmospheric pressure chemical vapor deposition) process, a PECVD (plasma enhanced chemical vapor deposition) process, or other suitable CVD processes known to those skilled in the art.
[0064] Then, see Appendix Fig. 9 , the crystalline silicon material 600 is filled in the trench 121. In the present embodiment, the crystalline silicon material 600 is undoped polycrystalline silicon. In some other embodiments, the crystalline silicon material 600 may be doped polycrystalline silicon, undoped single crystal silicon or doped single crystal silicon. Exemplarily, the crystalline silicon material 600 may be filled in the trench 121 by a LPCVD (low pressure chemical vapor deposition) process, a PECVD (plasma enhanced chemical vapor deposition) process or a PVD (physical vapor deposition) process.
[0065] Then, see Appendix Fig.10 , remove part of the crystalline silicon material 600 in the groove 121, so that the upper surface of the remaining crystalline silicon material 600 is lower than the opening of the groove 121. Exemplarily, the crystalline silicon material 600 in the groove 121 can be etched by a plasma etching process, a reactive ion etching process or other suitable dry etching process, so that the upper surface of the remaining crystalline silicon material 600 is much lower than the opening of the groove 121. In some embodiments, the crystalline silicon material 600 can also be etched by a wet etching process to remove part of the crystalline silicon material 600 in the groove 121. In this embodiment, the thickness of the remaining crystalline silicon material 600 (i.e. Fig.10The height of the mesocrystalline silicon material 600 in the vertical direction is controlled to be between 100 nm and 250 nm.
[0066] Then, see Appendix Fig.11 , the gate oxide layer 400 and the second dielectric layer 500 are etched so that the upper surface of the remaining gate oxide layer 400 and the upper surface of the remaining second dielectric layer 500 are lower than the upper surface of the remaining crystalline silicon material 600. In the present embodiment, the gate oxide layer 400 and the second dielectric layer 500 are both silicon dioxide layers. For example, the gate oxide layer 400 and the second dielectric layer 500 can be etched simultaneously by a wet etching process, for example, a hydrofluoric acid solution or other suitable wet etching solution can be used to etch the gate oxide layer 400 and the second dielectric layer 500 so that the upper surface of the remaining gate oxide layer 400 and the upper surface of the remaining second dielectric layer 500 are lower than the upper surface of the remaining crystalline silicon material 600. The remaining gate oxide layer 400 and the remaining second dielectric layer 500 together constitute a first inter-gate dielectric layer. The first inter-gate dielectric layer covers the top of the shielding gate structure and part of the sidewalls of the trench 121, and surrounds a groove, and the crystalline silicon material 600 is located in the groove. After the gate oxide layer 400 and the second dielectric layer 500 are etched, a portion of the inner surface of the trench 121 is exposed (ie, the epitaxial layer 120 is exposed). In other embodiments, when the gate oxide layer 400 and the second dielectric layer 500 are made of different materials, they can be etched separately.
[0067] Then, see Appendix Fig.12 , the upper surface of the remaining crystalline silicon material 600 is etched to the upper surface of the first inter-gate dielectric layer to form a crystalline silicon layer 610. Exemplarily, the remaining crystalline silicon material 600 may be etched by a dry etching process, for example, by a plasma etching process, a reactive ion etching process or other suitable dry etching process to form the crystalline silicon layer 610. In this embodiment, the thickness of the crystalline silicon layer 610 (i.e. Fig.12 The height of the mesocrystalline silicon layer 610 in the vertical direction is 20 nm-100 nm.
[0068] It should be noted that, the etching of the upper surface of the remaining crystalline silicon material 600 to the upper surface of the first inter-gate dielectric layer (that is, the upper surface of the remaining gate oxide layer 400 and the upper surface of the remaining second dielectric layer 500) mentioned here may refer to etching the upper surface of the remaining crystalline silicon material 600 to a position flush with the upper surface of the first inter-gate dielectric layer, or may refer to etching the upper surface of the remaining crystalline silicon material 600 to a position close to the upper surface of the first inter-gate dielectric layer. That is, the upper surface of the formed crystalline silicon layer 610 is flush with or close in height to the upper surface of the first inter-gate dielectric layer, that is, the upper surface of the crystalline silicon layer 610 is flush with the upper surface of the first inter-gate dielectric layer, or the upper surface of the crystalline silicon layer 610 is slightly lower than the upper surface of the first inter-gate dielectric layer, or the upper surface of the crystalline silicon layer 610 is slightly higher than the upper surface of the first inter-gate dielectric layer. When the upper surface of the crystalline silicon layer 610 is slightly lower than the upper surface of the first inter-gate dielectric layer, the height difference between the upper surface of the crystalline silicon layer 610 and the upper surface of the first inter-gate dielectric layer (ie Fig.12 The height difference between the upper surface of the crystalline silicon layer 610 and the upper surface of the first inter-gate dielectric layer is less than or equal to 100 nm, preferably, the height difference is less than or equal to 50 nm; when the upper surface of the crystalline silicon layer 610 is slightly higher than the upper surface of the first inter-gate dielectric layer, the height difference between the upper surface of the crystalline silicon layer 610 and the upper surface of the first inter-gate dielectric layer (i.e. Fig.12 The height difference (the distance in the up and down directions) is less than or equal to the thickness of the crystalline silicon layer 610. Preferably, the height difference is less than or equal to 20 nm.
[0069] Since the material of the first inter-gate dielectric layer is different from that of the crystalline silicon material 600, it is necessary to use a wet etching process and a dry etching process for etching respectively. However, it is difficult to accurately control the etching depth by a wet etching process, and the etching depth can be relatively accurately controlled by a dry etching process. Therefore, in this embodiment, the first inter-gate dielectric layer is first etched to a depth lower than the remaining crystalline silicon material 600 by a wet etching process, and then the remaining crystalline silicon material 600 is etched to be flush with or close in height to the upper surface of the first inter-gate dielectric layer by a dry etching process. The upper surface of the crystalline silicon layer 610 is flush with or close in height to the upper surface of the first inter-gate dielectric layer, which can effectively ensure the quality of the second inter-gate dielectric layer 700 and the second gate dielectric layer 800 formed in subsequent steps.
[0070] In some other embodiments, in step S200, a third dielectric layer may be formed on the surface of the shield gate structure and the exposed inner surface of the trench 121 (i.e., the inner surface of the upper space in the trench 121) by a CVD process, and the third dielectric layer may be a silicon dioxide layer. Then, a crystalline silicon material is filled in the trench 121, and the crystalline silicon material is partially removed so that the upper surface of the remaining crystalline silicon material is lower than the opening of the trench. Exemplarily, the thickness of the remaining crystalline silicon material is controlled to be 100nm-250nm. Then, the third dielectric layer is etched to form a first inter-gate dielectric layer, wherein the upper surface of the first inter-gate dielectric layer is lower than the upper surface of the remaining crystalline silicon material. The first inter-gate dielectric layer is also the third dielectric layer remaining after etching. The first inter-gate dielectric layer covers the top of the shield gate structure and part of the sidewall of the trench 121, and surrounds a groove, in which the crystalline silicon material is located. Afterwards, the upper surface of the remaining crystalline silicon material is etched to the upper surface of the first inter-gate dielectric layer to form a crystalline silicon layer. Exemplarily, the thickness of the crystalline silicon layer is 20 nm-100 nm.
[0071] In step S300, see the attached Fig.13 The crystalline silicon layer 610 and the exposed inner surface of the trench 121 (i.e., the exposed surface of the epitaxial layer 120) are oxidized by a thermal oxidation process or other suitable oxidation process to form a second inter-gate dielectric layer 700 and a second gate dielectric layer 800, wherein the second inter-gate dielectric layer 700 and the second gate dielectric layer 800 are both silicon dioxide layers, the second inter-gate dielectric layer 700 is formed by oxidizing the crystalline silicon layer 610, and the second gate dielectric layer 800 is formed by oxidizing the exposed inner surface of the trench 121.
[0072] The second gate dielectric layer 800 is formed by etching the gate oxide layer 400 and the second dielectric layer 500 and oxidizing the exposed inner surface of the trench 121 . The thickness of the second gate dielectric layer 800 can be accurately defined, and a second gate dielectric layer 800 with a thickness that meets requirements and good quality can be formed.
[0073] In step S400, see the attached Fig.14 , a gate material is deposited in the trench 121 by a CVD process or other suitable deposition process to form a gate 900. The gate material may be polysilicon or a metal, such as aluminum, tungsten, etc. The inter-gate dielectric layer between the gate 900 and the shielding gate 310 is composed of the first inter-gate dielectric layer and the second inter-gate dielectric layer 700, and a second gate dielectric layer 800 is provided between the gate 900 and the epitaxial layer 120.
[0074] So far, the introduction of the relevant steps of the method for preparing the semiconductor device of the embodiment of the present application has been completed. After the above steps, other conventional steps for making the trench-type shielding gate may also be included, which will not be repeated here. In addition, in addition to the above steps, the preparation method of this embodiment may also include other steps in the above steps or between different steps, and these steps can be implemented by various processes in the prior art, which will not be repeated here.
[0075] The preparation method of this embodiment is mainly implemented through a thermal oxidation process, a CVD process, and an etching process. The process route is simple and can effectively reduce the semiconductor production manufacturing cost. In addition, the preparation method of this application forms a first inter-gate dielectric layer and a second inter-gate dielectric layer 700 through a CVD process and a thermal oxidation process to jointly constitute an inter-gate dielectric layer between the gate 900 and the shielding gate 310. A thicker and better-quality inter-gate dielectric layer can be formed in a trench with a high aspect ratio, which can effectively reduce inter-gate leakage current and inter-gate capacitance, and improve the reliability of the formed semiconductor device.
[0076] The present application also provides a semiconductor device, which is prepared by the above-mentioned preparation method, and the semiconductor device can be a trench-type shielded gate device, that is, a shielded gate trench MOSFET. The semiconductor device prepared by the above steps has lower inter-gate leakage current and inter-gate capacitance.
[0077] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.
[0078] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0079] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.
[0080] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.
[0081] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.
[0082] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.
[0083] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.
[0084] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, forming a groove in the substrate, and forming a shielding gate structure in the lower space of the groove, wherein the shielding gate structure includes a shielding gate and a first gate dielectric layer located between the shielding gate and the inner surface of the groove; forming a first inter-gate dielectric layer having a groove in the groove and a crystalline silicon layer located in the groove, wherein the first inter-gate dielectric layer covers the top of the shielding gate structure and a portion of the sidewall of the groove and surrounds the groove; Oxidizing the crystalline silicon layer and the exposed inner surface of the trench to form a second inter-gate dielectric layer and a second gate dielectric layer; A gate is formed in the trench.
2. The preparation method according to claim 1, characterized in that: A shielding grid structure is formed in the lower space of the trench, comprising: forming a first dielectric layer on the inner surface of the groove; Filling the trench with a shielding grid material; removing a portion of the shielding grid material in the groove; Etching the first dielectric layer to form the first gate dielectric layer, wherein the upper surface of the first gate dielectric layer is lower than the upper surface of the remaining shielding gate material; The remaining shielding gate material is etched to form the shielding gate, wherein the upper surface of the shielding gate is flush with the upper surface of the first gate dielectric layer.
3. The preparation method according to claim 1, characterized in that: A first inter-gate dielectric layer having a groove and a crystalline silicon layer located in the groove are formed in the trench, comprising: Oxidizing the exposed inner surface of the trench to form a gate oxide layer; Forming a second dielectric layer on the surface of the shielding gate structure and the surface of the gate oxide layer by a CVD process; Filling the trench with crystalline silicon material, and partially removing the crystalline silicon material so that the upper surface of the remaining crystalline silicon material is lower than the opening of the trench; Etching the gate oxide layer and the second dielectric layer so that the upper surface of the remaining gate oxide layer and the upper surface of the remaining second dielectric layer are lower than the upper surface of the remaining crystalline silicon material, wherein the remaining gate oxide layer and the remaining second dielectric layer together constitute the first inter-gate dielectric layer; The upper surface of the remaining crystalline silicon material is etched to the upper surface of the first inter-gate dielectric layer to form the crystalline silicon layer.
4. The preparation method according to claim 3, characterized in that: The thickness of the gate oxide layer is 3nm-30nm.
5. The preparation method according to claim 1, characterized in that: A first inter-gate dielectric layer having a groove and a crystalline silicon layer located in the groove are formed in the trench, comprising: forming a third dielectric layer on the surface of the shielding gate structure and the exposed inner surface of the trench by a CVD process; Filling the trench with crystalline silicon material, and partially removing the crystalline silicon material so that the upper surface of the remaining crystalline silicon material is lower than the opening of the trench; Etching the third dielectric layer to form the first inter-gate dielectric layer, wherein an upper surface of the first inter-gate dielectric layer is lower than an upper surface of the remaining crystalline silicon material; The upper surface of the remaining crystalline silicon material is etched to the upper surface of the first inter-gate dielectric layer to form the crystalline silicon layer.
6. The preparation method according to any one of claims 3 to 5, characterized in that: The thickness of the remaining crystalline silicon material is 100nm-250nm.
7. The preparation method according to any one of claims 3 to 5, characterized in that: The thickness of the crystalline silicon layer is 20nm-100nm.
8. The preparation method according to claim 1, characterized in that: The crystalline silicon layer is an undoped polycrystalline silicon layer.
9. The preparation method according to claim 1, characterized in that: The first gate dielectric layer is a silicon dioxide layer; The first inter-gate dielectric layer is a silicon dioxide layer; The second inter-gate dielectric layer is a silicon dioxide layer; The second gate dielectric layer is a silicon dioxide layer.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9.