An SGT transistor and method of fabrication

Abstract

The application discloses an SGT transistor and a manufacturing method. A second oxide layer is formed on the surface of the gate oxide layer in the groove and is flush with the surface of the substrate, silicon nitride on both sides of the second oxide layer is removed, and second polysilicon lower than the surface of the substrate is filled on both sides of the second oxide layer, so that the second polysilicon presents a relatively narrow strip-shaped structure, the parasitic capacitance between the gate and the source is obviously reduced, the switching frequency of the device is effectively improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design, and in particular to an SGT transistor and a manufacturing method thereof. Background Art

[0002] In the existing shielded gate trench transistor cell structure, the gate polysilicon is located in the upper half of the trench, basically filling the trench opening, making the gate area relatively large, and thus the parasitic capacitance between the gate and the source is also relatively large, which limits the further increase of the switching frequency and makes the device unsuitable for operation under higher frequency conditions. Summary of the Invention

[0003] The purpose of the present invention is to provide an SGT transistor in response to the technical problems existing in the background technology.

[0004] In order to achieve the above technical objectives, the technical solutions adopted by the present invention are as follows:

[0005] In a first aspect, the present invention provides a method for manufacturing an SGT transistor, comprising:

[0006] S100, providing a substrate, and forming a plurality of grooves on the substrate;

[0007] S200, forming a first oxide layer and a first polysilicon layer in sequence in the trench and on the surface of the substrate;

[0008] S300, etching the first oxide layer and the first polysilicon, and sequentially forming a gate oxide layer and silicon nitride on the surface of the oxide layer and the surface of the first polysilicon;

[0009] S400, forming a second oxide layer flush with the surface of the substrate on the surface of the gate oxide layer in the trench, and removing silicon nitride on both sides of the second oxide layer;

[0010] S500, filling both sides of the second oxide layer with second polysilicon below the surface height of the substrate;

[0011] S600, forming a plurality of stacked P-type well regions and N-type source regions on adjacent sides of the plurality of trenches;

[0012] S700, covering the surface of the first oxide layer, the surface of the second polysilicon, and the surface of the second oxide layer with a dielectric layer, and opening a plurality of contact holes on the dielectric layer that penetrate into the P-type well region;

[0013] S800 , covering the plurality of contact holes and the surface of the dielectric layer with a metal layer.

[0014] Optionally, step S100 includes:

[0015] Provide a substrate, and cover the surface of the substrate Thickness of the third oxide layer;

[0016] A photolithography process is used to expose a preset groove pattern, and a dry etching process is used to form a plurality of grooves with intervals and a depth of 5 to 6 μm on the substrate according to the groove pattern.

[0017] Optionally, step S200 includes:

[0018] The thickness is formed by the deposition process a first oxide layer covering a surface inside the trench and extending onto a surface of the third oxide layer;

[0019] The thickness is formed by thin film process The first polysilicon fills the interior of the trench and covers the second oxide layer.

[0020] Optionally, step S300 includes:

[0021] A preset first polysilicon pattern is exposed by a photolithography process, and the first polysilicon is etched to a depth of 1.0 to 1.4 μm below the surface height of the substrate according to the first polysilicon pattern by a dry etching process;

[0022] A photolithography process is used to expose a preset active area pattern, and a wet etching process is used to etch the first oxide layer according to the active area pattern;

[0023] The thickness is formed by diffusion process a gate oxide layer covering a surface of the first polysilicon and extending to a surface of the third oxide layer;

[0024] A thin film process is used to form a of silicon nitride.

[0025] Optionally, the surface height of the second polysilicon is 0.1 to 0.18 um lower than the surface height of the substrate.

[0026] Optionally, step S600 includes:

[0027] An ion implantation process is used to form a plurality of P-type well regions on the surface of the substrate, wherein the plurality of P-type well regions are respectively arranged on adjacent sides of the plurality of trenches;

[0028] By adopting ion implantation process and according to the active area pattern, a plurality of N-type source regions are formed on the surface of the substrate, and the plurality of N-type source regions are respectively stacked on the plurality of P-type well regions.

[0029] Optionally, step S700 includes:

[0030] The thickness is formed by thin film process a dielectric layer covering a surface of the second oxide layer, a surface of the second polysilicon, and a surface of the third oxide layer;

[0031] A photolithography process is used to expose a preset contact hole pattern, a dry etching process is used to form multiple contact holes according to the contact hole pattern, the contact holes are inserted into the P-type well area, and an ion implantation process is used to form a P-type contact area in the contact holes.

[0032] Optionally, step S800 includes:

[0033] Using a thin film process to cover the metal layer in the plurality of contact holes and on the surface of the dielectric layer;

[0034] A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer according to the gate pattern and the source pattern to form a gate and a source.

[0035] Optionally, the metal layer includes titanium, titanium nitride, tungsten and aluminum.

[0036] In a second aspect, the present invention provides an SGT transistor, which is manufactured by the manufacturing method of the SGT transistor as described in any of the above schemes. The SGT transistor includes a substrate, a dielectric layer and a metal layer, wherein a plurality of grooves and a plurality of contact holes are provided on the substrate, the plurality of contact holes and the plurality of trenches are cross-arranged, the dielectric layer covers the plurality of trenches, the metal layer covers the dielectric layer and penetrates the plurality of contact holes; the trenches are filled with a first oxide layer, a first polysilicon, a gate oxide layer, silicon nitride, a second polysilicon and a second oxide layer, wherein the first oxide layer, the first polysilicon, the gate oxide layer, the silicon nitride and the second oxide layer are stacked in sequence, the second polysilicon is arranged on both sides of the second oxide layer, the surface height of the second oxide layer is flush with the surface height of the substrate, and the surface height of the second polysilicon is lower than the surface height of the substrate.

[0037] Compared with the prior art, the present invention has the following beneficial technical effects: by forming a second oxide layer flush with the surface height of the substrate on the surface of the gate oxide layer in the trench, removing the silicon nitride on both sides of the second oxide layer, and filling the second polysilicon on both sides of the second oxide layer with a surface height lower than the substrate, the second polysilicon presents a relatively narrow and long strip structure, thereby significantly reducing the parasitic capacitance between the gate and the source, thereby effectively improving the switching frequency of the device and reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a flow chart of an embodiment of the first aspect of the present invention;

[0039] Figure 2 The process steps of the first embodiment of the present invention are Figure 1 ;

[0040] Figure 3 The process steps of the first embodiment of the present invention are Figure 2 ;

[0041] Figure 4 The process steps of the first embodiment of the present invention are Figure 3 ;

[0042] Figure 5 The process steps of the first embodiment of the present invention are Figure 4 ;

[0043] Figure 6 The process steps of the first embodiment of the present invention are Figure 5 ;

[0044] Figure 7 The process steps of the first embodiment of the present invention are Figure 6 ;

[0045] Figure 8 The process steps of the first embodiment of the present invention are Figure 7 ;

[0046] Figure 9 The process steps of the first embodiment of the present invention are Figure 8 ;

[0047] Figure 10 The process steps of the first embodiment of the present invention are Figure 9 ;

[0048] Figure 11 The process steps of the first embodiment of the present invention are Figure 10 ;

[0049] Figure 12 The process steps of the first embodiment of the present invention are Figure 10 one;

[0050] Figure 13 The process steps of the first embodiment of the present invention are Figure 10 two;

[0051] Figure 14 The process steps of the first embodiment of the present invention are Figure 10 three;

[0052] Figure 15 The process steps of the first embodiment of the present invention are Figure 10 Four.

[0053] Reference numerals: 100 substrate, 101 third oxide layer, 200 trench, 201 first oxide layer, 202 first polysilicon, 203 gate oxide layer, 204 silicon nitride, 205 second oxide layer, 206 second polysilicon, 300 P-type well region, 400 N-type source region, 500 dielectric layer, 600 contact hole, 700 metal layer. DETAILED DESCRIPTION

[0054] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0055] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second" and the like may explicitly or implicitly include one or more features. In the description of the present invention, unless otherwise specified, "" means two or more.

[0056] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed or detachable connections, or specific connections; they may refer to mechanical or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0057] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] For ease of understanding, the specific process of the embodiment of the first aspect of the present invention is described below. Figures 1-15 , the manufacturing method of the SGT transistor includes:

[0059] S100, providing a substrate 100, and forming a plurality of trenches 200 on the substrate 100;

[0060] Step S100 includes:

[0061] A substrate 100 is provided, and a surface of the substrate 100 is covered with A third oxide layer 101 having a thickness of 100 nm;

[0062] A photolithography process is used to expose a pattern of the preset grooves 200 , and a dry etching process is used to form a plurality of grooves 200 spaced apart and having a depth of 5 to 6 μm on the substrate 100 according to the pattern of the grooves 200 .

[0063] See attached Figure 2 And attached Figure 3 The substrate 100 is made of N-type silicon, the third oxide layer 101 is made of silicon dioxide, and Thickness deposited on N-type silicon.

[0064] S200 , sequentially forming a first oxide layer 201 and a first polysilicon layer 202 in the trench 200 and on the surface of the substrate 100 ;

[0065] Step S200 includes:

[0066] The thickness is formed by the deposition process a first oxide layer 201 covering the surface inside the trench 200 and extending to the surface of the third oxide layer 101;

[0067] The thickness is formed by thin film process The first polysilicon 202 fills the interior of the trench 200 and covers the second oxide layer 205 .

[0068] See attached Figure 4 And attached Figure 5 The first oxide layer 201 is also made of silicon dioxide, and its deposition thickness is higher than that of the third oxide layer 101. The first oxide layer 201 can also be grown using a diffusion process.

[0069] S300, etching the first oxide layer 201 and the first polysilicon 202, and sequentially forming a gate oxide layer 203 and a silicon nitride layer 204 on the surface of the oxide layer and the surface of the first polysilicon 202;

[0070] Step S300 includes:

[0071] A photolithography process is used to expose a preset first polysilicon 202 pattern, and a dry etching process is used to etch the first polysilicon 202 to a height of 1.0 to 1.4 μm below the surface height of the substrate 100 according to the first polysilicon 202 pattern.

[0072] A photolithography process is used to expose a preset active area pattern, and a wet etching process is used to etch the first oxide layer 201 according to the active area pattern;

[0073] The thickness is formed by diffusion process A gate oxide layer 203, the gate oxide layer 203 covers the surface of the first polysilicon 202 and extends to the surface of the third oxide layer 101;

[0074] A thin film process is used to form a Silicon nitride 204.

[0075] See attached Figure 6 -Attached Figure 9 , the side of the first oxide layer 201 etched in the trench 200 close to the first polysilicon 202 is lower than the surface height of the first polysilicon 202. As can be seen from the figure, the surface of the first oxide layer 201 is concave toward the first polysilicon 202. Through the corresponding process, the gate oxide layer 203 and the silicon nitride 204 are sequentially covered on the surface of the oxide layer 201 and the surface of the first polysilicon 202. Figure 8 shown.

[0076] S400+, forming a second oxide layer 205 flush with the surface of the substrate 100 on the surface of the gate oxide layer 203 in the trench 200, and removing the silicon nitride 204 on both sides of the second oxide layer 205;

[0077] S500 , filling the second polysilicon 206 on both sides of the second oxide layer 205 with a height lower than the surface of the substrate 100 ;

[0078] See attached Figure 10 -Attached Figure 12 The surface height of the second polysilicon 206 is 0.1 to 0.18 μm lower than the surface height of the substrate 100, and the width of the second polysilicon 206 is less than 0.5 μm. That is, the total width of the two second polysilicon layers 206 on both sides of the second oxide layer 205 is less than 1 μm. In contrast, the height of the gate polysilicon in a conventional SGT transistor is designed to be 1.8 to 1.9 μm. Under controlled variables, the SGT transistor fabricated by this SGT transistor fabrication method has a smaller volume occupied by the second polysilicon 206 than a conventional SGT transistor, so that theoretically the gate-source capacitance will decrease proportionally, thereby greatly improving the operating frequency of the device.

[0079] S600 , forming a plurality of stacked P-type well regions 300 and N-type source regions 400 on adjacent sides of the plurality of trenches 200 ;

[0080] Step S600 includes:

[0081] A plurality of P-type well regions 300 are formed on the surface of the substrate 100 by an ion implantation process. The plurality of P-type well regions 300 are respectively disposed on adjacent sides of the plurality of trenches 200 .

[0082] By adopting an ion implantation process and according to the active region pattern, a plurality of N-type source regions 400 are formed on the surface of the substrate 100 . The plurality of N-type source regions 400 are respectively overlapped with the plurality of P-type well regions 300 .

[0083] See attached Figure 13 , an ion implantation process is used to implant P-type impurities (boron) into the surface of the substrate 100, and after furnace annealing, a P-type well region 300 is formed; then a photolithography process is used to expose the active area, and an N-type impurity (arsenic) is implanted into the surface of the substrate 100, and after furnace annealing, an N-type source region 400 is formed.

[0084] S700 , covering the surface of the first oxide layer 201 , the surface of the second polysilicon 206 , and the surface of the second oxide layer 205 with a dielectric layer 500 , and opening a plurality of contact holes 600 penetrating to the P-type well region 300 on the dielectric layer 500 ;

[0085] Step S700 includes:

[0086] The thickness is formed by thin film process The dielectric layer 500 covers the surface of the second oxide layer 205, the surface of the second polysilicon 206 and the surface of the third oxide layer 101;

[0087] A photolithography process is used to expose a preset contact hole 600 pattern, a dry etching process is used to form multiple contact holes 600 according to the contact hole 600 pattern, the contact holes 600 are inserted into the P-type well region 300, and an ion implantation process is used to form a P-type contact region in the contact hole 600.

[0088] S800 , covering the contact holes 600 and the surface of the dielectric layer 500 with a metal layer 700 .

[0089] Step S800 includes:

[0090] A metal layer 700 is formed in the plurality of contact holes 600 and on the surface of the dielectric layer 500 using a thin film process;

[0091] A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer 700 according to the gate pattern and the source pattern to form a gate and a source.

[0092] Specifically, the metal layer 700 includes titanium, titanium nitride, tungsten, and aluminum. Titanium, titanium nitride, tungsten, and aluminum are deposited sequentially using CVD (chemical vapor deposition) or PVD (physical vapor deposition) thin-film processes. Photolithography is then used to expose the gate and source regions. The metal is then etched using a dry or wet process (or a combination of both) to form the gate and source. Finally, the backside is thinned and metallized to form the drain.

[0093] In a second aspect, the present invention provides an SGT transistor, which is manufactured by the method for manufacturing an SGT transistor according to any of the above solutions. The SGT transistor includes a substrate 100, a dielectric layer 500, and a metal layer 700. The substrate 100 is provided with a plurality of trenches 200 and a plurality of contact holes 600. The plurality of contact holes 600 and the plurality of trenches 200 are intersectingly arranged. The dielectric layer 500 covers the plurality of trenches 200. The metal layer 700 covers the dielectric layer 500 and penetrates the plurality of contact holes 600.

[0094] The trench 200 is filled with a first oxide layer 201, a first polysilicon 202, a gate oxide layer 203, a silicon nitride 204, a second polysilicon 206 and a second oxide layer 205, wherein the first oxide layer 201, the first polysilicon 202, the gate oxide layer 203, the silicon nitride 204 and the second oxide layer 205 are stacked in sequence, and the second polysilicon 206 is arranged on both sides of the second oxide layer 205. The surface height of the second oxide layer 205 is flush with the surface height of the substrate 100, and the surface height of the second polysilicon 206 is lower than the surface height of the substrate 100.

[0095] The above description provides one or more implementations of an SGT transistor in conjunction with specific content, and does not limit the specific implementation of the present invention to these descriptions. Any similarity or similarity to the methods and structures of the present invention, or any technical deduction or substitution based on the concepts of the present invention, shall be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing an SGT transistor, characterized in that: include: S100, providing a substrate (100), and forming a plurality of grooves (200) on the substrate (100); S200, forming a first oxide layer (201) and a first polysilicon (202) in sequence in the trench (200) and on the surface of the substrate (100); S300, etching the first oxide layer (201) and the first polysilicon (202), and sequentially forming a gate oxide layer (203) and silicon nitride (204) on the surface of the oxide layer and the surface of the first polysilicon (202); S400, forming a second oxide layer (205) flush with the surface of the substrate (100) on the surface of the gate oxide layer (203) in the trench (200), and removing silicon nitride (204) on both sides of the second oxide layer (205); S500, filling second polysilicon (206) below the surface height of the substrate (100) on both sides of the second oxide layer (205); S600, forming a plurality of stacked P-type well regions (300) and N-type source regions (400) on adjacent sides of the plurality of trenches (200); S700, covering the surface of the first oxide layer (201), the surface of the second polysilicon (206), and the surface of the second oxide layer (205) with a dielectric layer (500), and opening a plurality of contact holes (600) on the dielectric layer (500) that penetrate the P-type well region (300); S800 , covering the inside of the plurality of contact holes ( 600 ) and the surface of the dielectric layer ( 500 ) with a metal layer ( 700 ).

2. The method for manufacturing an SGT transistor according to claim 1, wherein: The step S100 includes: A substrate (100) is provided, and a surface of the substrate (100) is covered a third oxide layer (101) having a thickness of A photolithography process is used to expose a preset groove (200) pattern, and a dry etching process is used to form a plurality of grooves (200) spaced apart and having a depth of 5 to 6 μm on the substrate (100) according to the groove (200) pattern.

3. The method for manufacturing an SGT transistor according to claim 2, wherein: The S200 includes: The thickness is formed by the deposition process a first oxide layer (201), the first oxide layer (201) covering the surface inside the groove (200) and extending to the surface of the third oxide layer (101); The thickness is formed by thin film process The first polysilicon (202) is filled in the interior of the trench (200) and covers the second oxide layer (205).

4. The method for manufacturing an SGT transistor according to claim 3, wherein: The S300 includes: A photolithography process is used to expose a preset first polysilicon (202) pattern, and a dry etching process is used to etch the first polysilicon (202) to a height of 1.0 to 1.4 μm below the surface height of the substrate (100) according to the first polysilicon (202) pattern; Using a photolithography process to expose a preset active area pattern, and using a wet etching process to etch the first oxide layer (201) according to the active area pattern; The thickness is formed by diffusion process a gate oxide layer (203), the gate oxide layer (203) covering the surface of the first polysilicon (202) and extending to the surface of the third oxide layer (101); A thin film process is used to form a gate oxide layer (203) on the surface of the gate oxide layer (203). of silicon nitride (204).

5. The method for manufacturing an SGT transistor according to claim 4, wherein: The surface height of the second polysilicon (206) is 0.1 to 0.18 μm lower than the surface height of the substrate (100).

6. The method for manufacturing an SGT transistor according to claim 5, wherein: The S600 includes: An ion implantation process is used to form a plurality of P-type well regions (300) on the surface of the substrate (100), wherein the plurality of P-type well regions (300) are respectively and correspondingly arranged on adjacent sides of the plurality of trenches (200); A plurality of N-type source regions (400) are formed on the surface of the substrate (100) by adopting an ion implantation process and according to the active region pattern. The plurality of N-type source regions (400) are respectively and correspondingly stacked on the plurality of P-type well regions (300).

7. The method for manufacturing an SGT transistor according to claim 6, wherein: The S700 includes: The thickness is formed by thin film process a dielectric layer (500), the dielectric layer (500) covering the surface of the second oxide layer (205), the surface of the second polysilicon (206), and the surface of the third oxide layer (101); A photolithography process is used to expose a preset contact hole (600) pattern, a dry etching process is used to form a plurality of contact holes (600) according to the contact hole (600) pattern, the contact holes (600) are inserted into the P-type well region (300), and an ion implantation process is used to form a P-type contact region in the contact holes (600).

8. The method for manufacturing an SGT transistor according to claim 7, wherein: The S800 includes: Using a thin film process to cover the metal layer (700) in the plurality of contact holes (600) and on the surface of the dielectric layer (500); A photolithography process is used to expose a preset gate pattern and a preset source pattern, and an etching process is used to etch the metal layer (700) according to the gate pattern and the source pattern to form a gate and a source.

9. The method for manufacturing an SGT transistor according to claim 8, wherein: The metal layer (700) includes titanium, titanium nitride, tungsten and aluminum.

10. An SGT transistor, characterized in that: The SGT transistor is manufactured by the method for manufacturing the SGT transistor according to any one of claims 1 to 9, wherein the SGT transistor comprises: A substrate (100) is provided with a plurality of grooves (200) and a plurality of contact holes (600), wherein the plurality of contact holes (600) and the plurality of grooves (200) are arranged crosswise; a dielectric layer (500), covering the plurality of grooves (200); a metal layer (700), covering the dielectric layer (500) and penetrating into the plurality of contact holes (600); The trench (200) is filled with a first oxide layer (201), a first polysilicon (202), a gate oxide layer (203), silicon nitride (204), a second polysilicon (206) and a second oxide layer (205), wherein the first oxide layer (201), the first polysilicon (202), the gate oxide layer (203), the silicon nitride (204) and the second oxide layer (205) are stacked in sequence, the second polysilicon (206) is arranged on both sides of the second oxide layer (205), the surface height of the second oxide layer (205) is flush with the surface height of the substrate (100), and the surface height of the second polysilicon (206) is lower than the surface height of the substrate (100).

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