Manufacturing method of SONOS memory

Abstract

The present invention provides a method for manufacturing a SONOS memory device. The method includes first performing a first etching on a second hard mask layer, then performing a second etching on a select gate polysilicon layer to remove a portion of the select gate polysilicon layer on the first hard mask layer, wherein the etching rate of the second hard mask layer is lower than the etching rate of the select gate polysilicon layer. The method then performs a third etching on the second hard mask layer and the remaining select gate polysilicon layer to remove a portion of the second hard mask layer and a portion of the select gate polysilicon layer on the first hard mask layer, wherein the etching rate of the second hard mask layer is equal to the etching rate of the select gate polysilicon layer. The method then performs a fourth etching on the remaining select gate polysilicon layer using the remaining second hard mask layer as a mask, and forms a select gate using the select gate polysilicon layer between the second hard mask layer and the control gate. In this manner, the morphology of the select gate can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a SONOS memory. Background Art

[0002] As an essential storage device in computers, non-volatile memory plays an important role in storing the information being processed. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory has the characteristics of small cell size, good memory retention, low operating voltage, and compatibility with CMOS technology. Currently, the manufacturing methods of SONOS memory include: Figure 1 As shown, first, a substrate 10 is provided, on which at least two control gates 11 spaced apart are formed, and a first hard mask layer 12 is formed on each of the control gates 11. The first hard mask layer includes a silicon nitride layer 12a and a silicon oxide layer 12b, and the silicon nitride layer 12a covers the silicon oxide layer 12b; then, a select gate polysilicon layer (SG A select gate polysilicon layer (POLY) is used to form the select gate. The select gate polysilicon layer covers the first hard mask layer 12 and the substrate 10. Next, a second hard mask layer 13 made of silicon nitride is formed on the sidewalls and top surface of the select gate polysilicon layer. The second hard mask layer 13 is then broken through to remove the second hard mask layer 13 from the top surface of the first hard mask layer. The select gate polysilicon layer on the first hard mask layer 12 is then removed using a high-selectivity etching step. However, due to the significant etch rate difference between the select gate polysilicon layer and the second hard mask layer 13 during the etching process, portions of the second hard mask layer 13 that were not completely etched remain after the select gate polysilicon layer is etched, forming a structure resembling "horns" with relatively high protrusions. Furthermore, in the areas of the select gate (SG) 14 near these "horns," recessed regions appear due to uneven etching. Subsequently, film layers such as spacers are likely to remain in the recessed region of the select gate 14. The remaining film layers such as spacers may further affect the formation of metal silicide in subsequent processes, thereby potentially causing problems such as CT (contact hole) over-etching. Summary of the Invention

[0003] The object of the present invention is to provide a method for manufacturing a SONOS memory to improve the morphology of a select gate polysilicon layer.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a SONOS memory, comprising:

[0005] Providing a substrate, on which at least two control gates spaced apart are formed, and a first hard mask layer is formed on each of the control gates;

[0006] forming a select gate polysilicon layer, wherein the select gate polysilicon layer covers the first hard mask layer and the substrate;

[0007] forming a second hard mask layer, wherein the second hard mask layer covers a top surface and sidewalls of the select gate polysilicon layer;

[0008] performing a first etching process on the second hard mask layer to remove the second hard mask layer on the top surface of the select gate polysilicon layer;

[0009] performing a second etching process on the select gate polysilicon layer using the second hard mask layer as a mask to remove a portion of the thickness of the select gate polysilicon layer on the first hard mask layer, wherein during the second etching process, an etching rate of the second hard mask layer is lower than an etching rate of the select gate polysilicon layer, and a top surface of a second portion of the second hard mask layer is higher than a top surface of the remaining select gate polysilicon layer;

[0010] performing a third etching process on the second hard mask layer and the remaining select gate polysilicon layer to remove a portion of the second portion of the second hard mask layer and a portion of the select gate polysilicon layer on the first hard mask layer, wherein during the third etching process, an etching rate of the second hard mask layer is equal to an etching rate of the select gate polysilicon layer to reduce a height difference between a top surface of the second portion of the second hard mask layer and a top surface of the remaining select gate polysilicon layer;

[0011] Using the remaining second hard mask layer as a mask, the remaining selection gate polysilicon layer is subjected to a fourth etching process, and the etching stops at the top surface of the first hard mask layer, and the selection gate polysilicon layer between the second hard mask layer and the control gate is used to form a selection gate.

[0012] Optionally, in the method for manufacturing the SONOS memory, during the second etching process, a ratio of an etching rate of the select gate polysilicon layer to an etching rate of the second hard mask layer is greater than or equal to 30:1.

[0013] Optionally, in the method for manufacturing the SONOS memory, both the first etching process and the third etching process adopt a push etching process, and the process gases of both the first etching process and the third etching process include carbon tetrafluoride.

[0014] Optionally, in the method for manufacturing the SONOS memory, the second etching process adopts a high selectivity etching process, and the process gas of the second etching process includes hydrogen bromide and oxygen.

[0015] Optionally, in the method for manufacturing the SONOS memory, during the fourth etching process, a ratio of an etching rate of the select gate polysilicon layer to an etching rate of the second hard mask layer is greater than or equal to 30:1.

[0016] Optionally, in the method for manufacturing the SONOS memory, the fourth etching process adopts a high selectivity etching process, and the process gas of the fourth etching process includes hydrogen bromide and oxygen.

[0017] Optionally, in the manufacturing method of the SONOS memory, the material of the selection gate polysilicon layer is polysilicon, and is formed by deposition using a furnace tube process.

[0018] Optionally, in the manufacturing method of the SONOS memory, the first hard mask layer includes a silicon oxide layer and a silicon nitride layer, and the silicon nitride layer covers the silicon oxide layer; and the second hard mask layer is made of silicon nitride.

[0019] Optionally, in the manufacturing method of the SONOS memory, after performing the fourth etching process on the remaining select gate polysilicon layer, the method further includes:

[0020] removing the second hard mask layer by a wet etching process;

[0021] removing the select gate polysilicon layer between adjacent control gates;

[0022] removing the first hard mask layer to expose the top surface of the control gate;

[0023] forming a metal silicide layer, wherein the metal silicide layer covers a top surface of the select gate, a top surface of the control gate, and the substrate;

[0024] An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the metal silicide layer.

[0025] Optionally, in the method for manufacturing the SONOS memory, sidewalls of the control gate and the first hard mask layer are both formed with sidewall spacers, and a gate dielectric layer is formed between the control gate and the substrate.

[0026] In the manufacturing method of the SONOS memory provided by the present invention, the second hard mask layer is first etched to remove the second hard mask layer on the top surface of the select gate polysilicon layer, and then, the select gate polysilicon layer is subjected to a second etching process using the remaining second hard mask layer as a mask to remove a portion of the thickness of the select gate polysilicon layer on the first hard mask layer. During the second etching process, the etching rate of the second hard mask layer is lower than the etching rate of the select gate polysilicon layer, and the top surface of the second hard mask layer is higher than the top surface of the remaining select gate polysilicon layer; then, the second hard mask layer and the remaining select gate polysilicon layer are subjected to a third etching process to remove the arc portion. The second hard mask layer is separated (the second portion) and a portion of the select gate polysilicon layer on the first hard mask layer is removed. During a third etching process, the etching rate of the second hard mask layer is equal to the etching rate of the select gate polysilicon layer, thereby reducing the height difference between the top surface of the second hard mask layer and the top surface of the remaining select gate polysilicon layer. Then, a fourth etching process is performed on the remaining select gate polysilicon layer using the remaining second hard mask layer as a mask, and the etching is stopped at the top surface of the first hard mask layer. The morphology of the sidewalls of the second hard mask layer, i.e., the "bull horn" morphology and height, are significantly improved. The select gate polysilicon layer is formed by the select gate polysilicon layer between the second hard mask layer and the control gate. In this way, the height of the top surface of the second hard mask layer can be reduced, thereby improving the morphology of the select gate polysilicon layer, and further improving the morphology of the subsequently formed select gate, and reducing or avoiding the occurrence of a recess in the top surface of the subsequently formed select gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a SEM schematic diagram of a SONOS memory device in the prior art;

[0028] Figure 2 1 is a flow chart of a method for manufacturing a SONOS memory according to an embodiment of the present invention;

[0029] Figures 3 to 10 1 is a schematic diagram of a structure formed in a method for manufacturing a SONOS memory according to an embodiment of the present invention;

[0030] Figure 11 is a SEM schematic diagram after forming contact holes in the manufacturing method of the SONOS memory according to an embodiment of the present invention;

[0031] In the figure,

[0032] 10-substrate; 11-control gate; 12-first hard mask layer; 12a-silicon nitride layer; 12b-silicon oxide layer; 13-second hard mask layer; 14-select gate;

[0033] 100 - substrate; 101 - gate dielectric layer; 102 - select gate oxide layer; 110 - control gate; 111 - sidewall; 120 - first hard mask layer; 121 - silicon oxide layer; 122 - silicon nitride layer; 130 - select gate polysilicon layer; 130a - select gate; 140 - second hard mask layer; 150 - metal silicide layer; 160 - interlayer dielectric layer; 170 - contact hole. DETAILED DESCRIPTION

[0034] The following is a further detailed description of the SONOS memory manufacturing method proposed in the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0035] Figure 2 FIG is a flow chart of a method for manufacturing a SONOS memory according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for manufacturing a SONOS memory, including:

[0036] Step S1: providing a substrate, on which at least two control gates spaced apart are formed, and a first hard mask layer is formed on each of the control gates;

[0037] Step S2: forming a select gate polysilicon layer, wherein the select gate polysilicon layer covers the first hard mask layer and the substrate, wherein the second hard mask layer includes a first portion covering the top surface of the select gate polysilicon layer and a second portion covering the sidewall of the select gate polysilicon layer, and the cross-section of the second portion is an arc shape;

[0038] Step S3: forming a second hard mask layer, wherein the second hard mask layer covers the top surface and sidewalls of the select gate polysilicon layer;

[0039] Step S4: performing a first etching process on the second hard mask layer to remove the second hard mask layer on the top surface of the select gate polysilicon layer;

[0040] Step S5: using the remaining second hard mask layer as a mask, performing a second etching process on the select gate polysilicon layer to remove a portion of the thickness of the select gate polysilicon layer on the first hard mask layer, wherein during the second etching process, an etching rate of the second hard mask layer is lower than an etching rate of the select gate polysilicon layer, and a top surface of the second hard mask layer is higher than a top surface of the remaining select gate polysilicon layer;

[0041] Step S6: performing a third etching process on the second hard mask layer and the remaining select gate polysilicon layer to remove a portion of the second portion of the second hard mask layer and a portion of the select gate polysilicon layer on the first hard mask layer. During the third etching process, an etching rate of the second hard mask layer is equal to an etching rate of the select gate polysilicon layer to reduce a height difference between a top surface of the second portion of the second hard mask layer and a top surface of the remaining select gate polysilicon layer.

[0042] Step S7: Using the remaining second hard mask layer as a mask, perform a fourth etching process on the remaining selection gate polysilicon layer, and stop the etching at the top surface of the first hard mask layer, and use the selection gate polysilicon layer between the second hard mask layer and the control gate to form a selection gate.

[0043] Figures 3 to 10 1 is a schematic diagram of a structure formed in a method for manufacturing a SONOS memory according to an embodiment of the present invention; Figure 11 1 is a SEM diagram of a SONOS memory after forming a contact hole in a manufacturing method of the embodiment of the present invention; Figures 3 to 11 The manufacturing method of the SONOS memory provided in this embodiment is described in more detail.

[0044] First, if Figure 3 As shown, step S1 is performed to provide a substrate 100, on which at least two control gates 110 spaced apart are formed, and a first hard mask layer 120 is formed on each of the control gates 110, wherein the first hard mask layer 120 includes a silicon oxide layer 121 and a silicon nitride layer 122 stacked in sequence from bottom to top; the material of the substrate 100 may include but is not limited to single crystal or polycrystalline semiconductor materials, and the substrate 100 may also include an intrinsic single crystal silicon substrate or a doped silicon substrate.

[0045] A gate dielectric layer 101 is formed on the substrate 100 to isolate the substrate 100 from the control gate 110 . The gate dielectric layer 101 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially from bottom to top, that is, the gate dielectric layer 101 is an ONO stack structure.

[0046] Next, refer to Figure 3 As shown, a control gate material layer (not shown) and a first hard mask layer 120 are sequentially formed on the gate dielectric layer 101, with the control gate material layer covering the gate dielectric layer 101. The control gate material layer can be made of polysilicon and can be formed using a furnace tube process. The first hard mask layer 120 includes a silicon oxide layer 121 and a silicon nitride layer 122, with the silicon nitride layer 122 covering the silicon oxide layer 121.

[0047] Next, a patterned photoresist layer (not shown) is formed on the first hard mask layer 120, wherein the patterned photoresist layer exposes a portion of the first hard mask layer 120, and the first hard mask layer 120 and the control gate material layer are sequentially etched using the patterned photoresist layer as a mask to form the control gate 110, and the remaining first hard mask layer 120 covers the top surface of the control gate 110.

[0048] Afterwards, if Figure 3 As shown, a spacer 111 is formed, and the spacer 111 covers the sidewall of the control gate 110 and the sidewall of the first hard mask layer 120 . The material of the spacer 111 includes silicon oxide and / or silicon nitride.

[0049] Afterwards, a select gate oxide layer 102 is formed, and the select gate oxide layer 102 covers the sidewall spacer 111 , the first hard mask layer, and the exposed substrate 100 . The select gate oxide layer 102 is made of silicon oxide.

[0050] Then, execute step S2, as Figure 4 As shown, a select gate polysilicon layer 130 is formed, and the select gate polysilicon layer 130 covers the first hard mask layer 120 and the substrate 100. The select gate polysilicon layer 130 is made of polysilicon and can be formed by a furnace process at a process temperature of 600°C to 620°C. The thickness of the select gate polysilicon layer 130 can be 750 angstroms to 850 angstroms.

[0051] Since the top surface of the first hard mask layer 120 is higher than the surface of the substrate 100 , the top surface of the select gate polysilicon layer 130 on the first hard mask layer 120 is higher than the top surface of the select gate polysilicon layer 130 on the substrate 100 .

[0052] Then, execute step S3, as Figure 5 and Figure 6 As shown, a second hard mask layer 140 is formed. The second hard mask layer 140 covers the top surface and sidewalls of the select gate polysilicon layer 130. The second hard mask layer 140 is conformal. The second hard mask material layer 140 is made of silicon nitride and can be formed using an atomic layer deposition (ALD) process. The second hard mask layer 140 includes a first portion covering the top surface of the select gate polysilicon layer 130 and a second portion covering the sidewalls of the select gate polysilicon layer 130. The cross-section of the second portion is an arc.

[0053] Next, step S4 is performed to perform a first etching process on the second hard mask layer 140 to remove the second hard mask layer 140 on the top surface of the select gate polysilicon layer 130. In other words, the second hard mask layer 140 on the sidewalls of the select gate polysilicon layer 130 is retained. Here, the sidewalls of the select gate polysilicon layer 130 refer to the sidewalls between the top surface of the select gate polysilicon layer 130 on the substrate 100 and the top surface of the select gate polysilicon layer 130 on the first hard mask layer 120.

[0054] like Figure 6 As shown, the second hard mask layer 140 is etched to remove the second hard mask layer 140 on the top surface of the select gate polysilicon layer 130, that is, the second hard mask layer 140 is pushed downward (breakthrough), that is, the first etching process adopts a push-through etching process.

[0055] Furthermore, the shape of the second hard mask layer 140 on the sidewall of the retained select gate polysilicon layer 130 is similar to a “horn”, or in other words, is an arc shape.

[0056] Then, if Figure 7 As shown, step S5 is executed, and the selection gate polysilicon layer 130 is subjected to a second etching process using the remaining second hard mask layer 140 as a mask to remove a portion of the thickness of the selection gate polysilicon layer 130 on the first hard mask layer 120. During the second etching process, the etching rate of the second hard mask layer 140 is less than the etching rate of the selection gate polysilicon layer 130, and the top surface of the second hard mask layer 140 is higher than the top surface of the remaining selection gate polysilicon layer 130.

[0057] Preferably, the second etching process uses a high selectivity etching process, which has a high etching rate for the select gate polysilicon layer 130, that is, the etching rate of the select gate polysilicon layer 130 is higher than the etching rate of the second hard mask layer. During the second etching process, the ratio of the etching rate of the select gate polysilicon layer 130 to the etching rate of the second hard mask layer 140 is greater than or equal to 30:1. Furthermore, the second etching process is a dry etching process, and the process gas for the second etching process includes hydrogen bromide and oxygen.

[0058] Then, if Figure 8As shown, step S6 is performed to perform a third etching process on the second hard mask layer 140 and the remaining select gate polysilicon layer 130 to remove a portion of the second hard mask layer 140 and a portion of the select gate polysilicon layer 130 on the first hard mask layer 120. During the third etching process, the etching rate of the second hard mask layer 140 is equal to the etching rate of the select gate polysilicon layer 130, thereby reducing the height difference between the top surface of the second hard mask layer 140 and the top surface of the remaining select gate polysilicon layer 130, thereby reducing the height of the second hard mask layer 140. That is, by using a push etching process in the third etching process, the second hard mask layer 140 can be etched, and the morphology of the second hard mask layer 140 can be improved and optimized, thereby reducing the height of the top surface of the second hard mask layer 140, and further reducing the height difference between the top surface of the second hard mask layer 140 and the top surface of the remaining select gate polysilicon layer 130.

[0059] Furthermore, after the third etching process, a partial thickness of the selection gate polysilicon layer 130 is still retained on the top surface of the first hard mask layer. In this way, damage to the selection gate polysilicon layer 130 can be avoided during the etching process of the second hard mask layer 140, thereby avoiding damage to the active area (AA) of the device.

[0060] Preferably, the third etching process adopts a dry etching process, and the process gas of the third etching process includes carbon tetrafluoride. In this way, the etching rate of the second hard mask layer 140 can be equal to the etching rate of the select gate polysilicon layer 130, so that the third etching process is a non-selective etching.

[0061] Then, if Figure 9 As shown, step S7 is performed, using the remaining second hard mask layer 140 as a mask, performing a fourth etching process on the remaining select gate polysilicon layer 130, and the etching stops at the top surface of the first hard mask layer 120, and using the select gate polysilicon layer 130 between the second hard mask layer 140 and the control gate 110 to form a select gate 130a, wherein the top surface of the select gate 130a can be lower than the top surface of the second hard mask layer 140. Figure 9 As shown, the morphology of the second hard mask layer at the sidewall (the morphology of the second portion), ie, the morphology and height of the "horns" are significantly improved.

[0062] During the fourth etching process, a ratio of an etching rate of the select gate polysilicon layer 130 to an etching rate of the second hard mask layer 140 is greater than or equal to 30:1, and the process gases used in the fourth etching process include hydrogen bromide and oxygen. In other words, the fourth etching process is a high-selectivity etching process having a high etching selectivity for the select gate polysilicon layer 130, and the etching rate of the select gate polysilicon layer 130 is greater than the etching rate of the second hard mask layer 140. Since the morphology of the second hard mask layer 140 is improved and optimized in the aforementioned steps, the height of the top surface of the second hard mask layer 140 is reduced, that is, the height difference between the top surface of the second hard mask layer 140 and the selection gate polysilicon layer 130 is reduced, and the top surface of the second hard mask layer 140 is nearly flush with the top surface of the selection gate polysilicon layer 130, therefore, in the process of etching the selection gate polysilicon layer 130, the etching of the selection gate polysilicon layer 130 can be made more uniform, thereby improving the morphology of the selection gate polysilicon layer 130, and further improving the surface morphology of the subsequently formed selection gate 130a, reducing or avoiding the occurrence of depressions on the top surface of the selection gate 130a, and further avoiding the presence of film residues in the depressions, etc.

[0063] After the fourth etching process is performed on the remaining selection gate polysilicon layer 130, the method further includes: Figure 10 As shown, a wet etching process is used to remove the second hard mask layer 140. The etchant used in the wet etching process may be phosphoric acid to improve the etching selectivity of the second hard mask layer 140. In addition, the select gate polysilicon layer 130 between the adjacent control gates 110 is removed. Furthermore, the select gate oxide layer 102 between the adjacent control gates 110 is removed.

[0064] Next, the first hard mask layer 120 is removed to expose the top surface of the control gate 110. Furthermore, the first hard mask layer 120 may be removed by a wet etching process.

[0065] Then, if Figure 11 As shown, a metal silicide layer 150 is formed, and the metal silicide layer 150 covers the top surface of the select gate 130a and the substrate 100. Since the morphology of the select gate 130a is improved, the surface morphology of the metal silicide layer 150 can be improved during the formation of the metal silicide layer 150, so that the metal silicide layer 150 can be formed more evenly on the top surface of the select gate 130a, and the surface morphology of the metal silicide layer 150 is relatively flat, thereby avoiding the problem of over-etching of the contact hole (CT) 170 formed subsequently.

[0066] Next, an interlayer dielectric layer 160 is formed, the interlayer dielectric layer 160 covers the metal silicide layer 150, and the interlayer dielectric layer 160 is etched to form a contact hole 170 on the selection gate 130a and the substrate 100. The contact hole 170 on the selection gate 130a passes through the interlayer dielectric layer 160 and is aligned with the selection gate 130a.

[0067] In addition, the manufacturing method of the SONOS memory provided in this embodiment can be used to form a 1.5T SONOS memory.

[0068] In summary, in the manufacturing method of the SONOS memory provided by the embodiment of the present invention, the second etching process is first performed on the select gate polysilicon layer to remove a portion of the thickness of the select gate polysilicon layer on the first hard mask layer. During the second etching process, the etching rate of the second hard mask layer is less than the etching rate of the select gate polysilicon layer, and the top surface of the second hard mask layer is higher than the top surface of the remaining select gate polysilicon layer; then, the second hard mask layer and the remaining select gate polysilicon layer are subjected to a third etching process to remove a portion of the second hard mask layer. and removing a portion of the select gate polysilicon layer on the first hard mask layer. During the third etching process, the etching rate of the second hard mask layer is equal to the etching rate of the select gate polysilicon layer, thereby reducing the height difference between the top surface of the second hard mask layer and the top surface of the remaining select gate polysilicon layer. Thereafter, using the remaining second hard mask layer as a mask, a fourth etching process is performed on the remaining select gate polysilicon layer, and the etching stops at the top surface of the first hard mask layer. The select gate polysilicon layer between the second hard mask layer and the control gate is used to form a select gate. In this way, the height of the top surface of the second hard mask layer can be reduced, thereby improving the morphology of the select gate polysilicon layer, and further improving the morphology of the subsequently formed select gate, and reducing or avoiding the occurrence of a recess in the top surface of the subsequently formed select gate.

[0069] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a SONOS memory, characterized in that: include: Providing a substrate, on which at least two control gates spaced apart are formed, and a first hard mask layer is formed on each of the control gates; forming a select gate polysilicon layer, wherein the select gate polysilicon layer covers the first hard mask layer and the substrate; forming a second hard mask layer, wherein the second hard mask layer covers the top surface and sidewalls of the select gate polysilicon layer, wherein the second hard mask layer includes a first portion covering the top surface of the select gate polysilicon layer and a second portion covering the sidewalls of the select gate polysilicon layer, and the cross-section of the second portion is an arc shape; performing a first etching process on the second hard mask layer to remove the second hard mask layer on the top surface of the select gate polysilicon layer; performing a second etching process on the select gate polysilicon layer using the remaining second hard mask layer as a mask to remove a portion of the thickness of the select gate polysilicon layer on the first hard mask layer, wherein during the second etching process, an etching rate of the second hard mask layer is lower than an etching rate of the select gate polysilicon layer, and a top surface of a second portion of the second hard mask layer is higher than a top surface of the remaining select gate polysilicon layer; performing a third etching process on the second hard mask layer and the remaining select gate polysilicon layer to remove a second portion of the second hard mask layer and a portion of the select gate polysilicon layer on the first hard mask layer, wherein during the third etching process, an etching rate of the second hard mask layer is equal to an etching rate of the select gate polysilicon layer to reduce a height difference between a top surface of the second hard mask layer and a top surface of the remaining select gate polysilicon layer; Using the remaining second hard mask layer as a mask, the remaining selection gate polysilicon layer is subjected to a fourth etching process, and the etching stops at the top surface of the first hard mask layer, and the selection gate polysilicon layer between the second hard mask layer and the control gate is used to form a selection gate.

2. The method for manufacturing a SONOS memory according to claim 1, wherein: During the second etching process, a ratio of an etching rate of the select gate polysilicon layer to an etching rate of the second hard mask layer is greater than or equal to 30:

1.

3. The method for manufacturing a SONOS memory according to claim 1 or 2, wherein: The first etching process and the third etching process both adopt a push etching process, and the process gases of the first etching process and the third etching process both include carbon tetrafluoride.

4. The method for manufacturing a SONOS memory according to claim 1, wherein: The second etching process adopts a high selectivity etching process, and the process gas of the second etching process includes hydrogen bromide and oxygen.

5. The method for manufacturing a SONOS memory according to claim 1, wherein: During the fourth etching process, a ratio of an etching rate of the select gate polysilicon layer to an etching rate of the second hard mask layer is greater than or equal to 30:

1.

6. The method for manufacturing a SONOS memory according to claim 1 or 5, wherein: The fourth etching process adopts a high selectivity etching process, and the process gas of the fourth etching process includes hydrogen bromide and oxygen.

7. The method for manufacturing a SONOS memory according to claim 1, wherein: The selection gate polysilicon layer is made of polysilicon and is formed using a furnace tube process.

8. The method for manufacturing a SONOS memory according to claim 1, wherein: The first hard mask layer includes a silicon oxide layer and a silicon nitride layer, and the silicon nitride layer covers the silicon oxide layer; the second hard mask layer is made of silicon nitride.

9. The method for manufacturing a SONOS memory according to claim 1, wherein: After performing the fourth etching process on the remaining select gate polysilicon layer, the method further includes: removing the second hard mask layer by a wet etching process; removing the select gate polysilicon layer between adjacent control gates; removing the first hard mask layer to expose the top surface of the control gate; forming a metal silicide layer, wherein the metal silicide layer covers a top surface of the select gate, a top surface of the control gate, and the substrate; An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the metal silicide layer.

10. The method for manufacturing a SONOS memory according to claim 1, wherein: Sidewalls of the control gate and the first hard mask layer are both formed with sidewall spacers, and a gate dielectric layer is formed between the control gate and the substrate.

Images