Test method and system for improving wafer WAT test capacity
Through partition processing and AutoRetest judgment, the problem of excessive number of chips and frequent abnormal alarms in traditional WAT tests is solved, and the production capacity and efficiency of wafer WAT tests are improved, ensuring the accuracy of test data and the improvement of production capacity.
Patent Information
- Application Number
- CN202411313661.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-27
AI Technical Summary
The traditional wafer WAT test method leads to an increase in the number of test core particles, affecting production capacity, and frequent abnormal alarms lead to retesting of the entire batch, reducing machine utilization and production capacity.
The target core particles are selected by partitioning processing, WAT test, and AutoRetest judgment is performed after the test. If the specifications are not met, retest will be retested. The HOLD process is avoided through SPC judgment, and the testing efficiency and production capacity will be improved.
Effectively control abnormal output, improve automation efficiency and production capacity, improve product direct rate, ensure that the test data represents the entire wafer capacity, reduce the number of retests, and improve machine utilization.
Smart Images
Figure CN119208177A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of LED technology, and in particular to a testing method and system for improving wafer WAT testing capacity. Background Art
[0002] In recent years, semiconductor technology has developed rapidly. In the production process of semiconductor chips, wafer acceptance test (WAT) plays an important role as a chip quality detection process. It is located after the wafer production process is completed and before wafer testing (CP). It is used to measure the electrical parameters of specific structures to verify whether the quality and stability of the manufacturing process and the electrical specifications of the process platform meet the requirements, and to accurately control and evaluate the production and manufacturing of wafers throughout the entire process of wafer production.
[0003] like Figure 1 As shown in the figure, the traditional WAT test adopts the test method of setting the step distance in the X and Y directions for jump test. To test the required number of core particles, the probe is inserted into the N and P pads of the corresponding chip, and the photoelectric parameter value of the corresponding core particle is measured by applying voltage / current. Among them, the step distance in the X and Y directions needs to be calculated based on the total number of particles scanned on the entire wafer and the aspect ratio of a single core particle. When the number of particles required for the test is calculated, how much X and Y should be set respectively. The specific calculation formula is:
[0004]
[0005] Y = X × aspect ratio
[0006] However, since the wafer is circular, when calculating the X and Y setting step distances according to the above formula, the actual number of test cores will be greater than the required number of point tests, and the increase in the number of test cores will inevitably increase the test time, which in turn affects the WAT machine capacity. At the same time, during the WAT test, the entire batch of wafers is tested, and the system determines and triggers the hold process, but some resistance or leakage parameters are easily affected by poor probe contact or accumulation of particle impurities, causing the test value to exceed the card control specification, thereby triggering an abnormal alarm and requiring re-loading and testing. The wafer batch re-testing requires waiting for an empty machine to test, which will also occupy the WAT machine utilization rate, thereby reducing the WAT machine utilization rate and capacity.
[0007] In view of the above problems, how to improve the production capacity of chips is an urgent problem that technical personnel in this field need to solve. Summary of the invention
[0008] The technical problem to be solved by the present invention is to provide a testing method and system for improving the wafer WAT testing capacity, which can effectively control abnormal output and improve product pass rate.
[0009] In order to solve the above technical problems, the present invention provides a testing method for improving the WAT test capacity of wafers, including: partitioning the wafers in the current batch according to the number of target point tests to select target core particles; performing WAT tests on the target core particles in the current wafer in turn; if the target core particles in the current wafer have completed the WAT test, then performing AutoRetest judgment on the target core particles in the current wafer and then continuing to perform WAT testing on the target core particles in the next wafer in the current batch, otherwise, continuing to perform WAT testing on the target core particles in the current wafer that have not undergone WAT testing; if the target core particles in the current batch have completed the AutoRetest processing, then performing SPC judgment on the target core particles in the current batch.
[0010] As an improvement of the above scheme, the step of performing WAT test on the target core grain in the next wafer in the current batch after performing AutoRetest judgment on the target core grain in the current wafer includes: performing AutoRetest judgment on the target core grain in the current wafer to determine whether the target core grain in the current wafer meets the preset parameter specifications; if the target core grain in the current wafer meets the preset parameter specifications, performing WAT test on the target core grain in the next wafer in the current batch; if the target core grain in the current wafer does not meet the preset parameter specifications, re-performing WAT test on the target core grain in the current wafer, and then performing WAT test on the target core grain in the next wafer in the current batch.
[0011] As an improvement of the above scheme, when the WAT test is re-performed on the target core grain in the current wafer: the original target core grain in the sub-region of the current wafer is retained, and the WAT test is performed on the original target core grain in the current wafer; or a new target core grain is re-selected in the sub-region of the current wafer, and the WAT test is performed on the new target core grain in the current wafer.
[0012] As an improvement of the above solution, when the WAT test is performed again on the target die in the current wafer, the previous WAT test result is overwritten by the new WAT test result.
[0013] As an improvement on the above scheme, the steps of partitioning the wafers in the current batch according to the target point measurement number to select the target core particles include: scanning the wafer; partitioning the wafers in the current batch according to the target point measurement number to divide the wafer into at least one sub-area, wherein the target point measurement number is the same as the number of sub-areas; and randomly selecting the target core particles in the sub-areas.
[0014] As an improvement of the above solution, the areas of the sub-regions are equal.
[0015] As an improvement of the above-mentioned scheme, the testing method for improving the wafer WAT testing capacity also includes: performing SPC judgment on the target core particles in the current batch to determine whether the target core particles in the current batch meet the SPC rules; if the target core particles in the current batch meet the SPC rules, testing the next batch; if the target core particles in the current batch do not meet the SPC rules, executing the HOLD process, and then retesting the target core particles in the current batch.
[0016] Accordingly, the present invention also provides a test system for improving the wafer WAT test capacity, including: a core extraction module, used to partition the wafers in the current batch according to the number of target point test particles, so as to select the target core; a WAT test module, used to perform WAT test on the target cores in the current wafer in turn; an AutoRetest judgment module, used to perform AutoRetest judgment on the target cores in the current wafer; an SPC judgment module, used to perform SPC judgment on the target cores in the current batch to determine whether the target cores in the current wafer meet the preset parameter specifications; a first judgment module, used to judge the target cores in the current wafer Whether all the core particles have completed the WAT test, when it is judged as yes, the AutoRetest judgment module is driven to perform AutoRetest judgment on the target core particles in the current wafer, and the WAT test module is driven to continue to perform WAT test on the target core particles in the next wafer in the current batch; when it is judged as no, the WAT test module is driven to continue to perform WAT test on the target core particles in the current wafer that have not undergone WAT test; the second judgment module is used to judge whether all the target core particles in the current batch have completed the AutoRetest processing, and when it is judged as yes, the SPC judgment module is driven to perform SPC judgment on the target core particles in the current batch.
[0017] As an improvement of the above-mentioned scheme, the test system for improving the wafer WAT test capacity also includes a third judgment module, which is used to drive the WAT test module to re-perform WAT test on the target core grain in the current wafer when the SPC judgment module determines that the target core grain in the current wafer does not meet the preset parameter specifications.
[0018] As an improvement of the above scheme, the core particle extraction module includes: a scanning unit, used to scan the wafer; a partitioning unit, partitioning the wafers in the current batch according to the target point measurement number, so as to divide the wafer into at least one sub-area, wherein the target point measurement number is the same as the number of sub-areas; an extraction unit, used to randomly select target core particles in the sub-areas respectively.
[0019] The implementation of the present invention can effectively control abnormal output, improve automation efficiency, increase production capacity, increase product pass rate, and ensure quality and quantity; it has the following beneficial effects:
[0020] The present invention adopts a partitioning method to extract the target core particles, which can achieve the same number of core particles actually tested as the required number of core particles, improve the WAT test capacity, and the test data can also represent the capacity of the entire wafer;
[0021] At the same time, after all the target cores in the current wafer have completed the WAT test, the present invention immediately performs an AutoRetest judgment, thereby quickly discovering that the test value exceeds the card control specification, avoiding subsequent re-loading test of the entire batch;
[0022] Furthermore, the present invention performs parameter origin re-measurement and re-assignment for problematic parameters during the WAT process; and after the WAT test of all wafers in the same batch is completed, if the SPC system determines that the SPC rules are violated, there is no need to perform WAT re-measurement on the batch of wafers before executing the HOLD process, thereby effectively improving the WAT test capacity. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a flow chart of the existing WAT test;
[0024] Figure 2 It is a flow chart of a first embodiment of a test method for improving wafer WAT test capacity of the present invention;
[0025] Figure 3 It is a flow chart of a second embodiment of a test method for improving wafer WAT test capacity of the present invention;
[0026] Figure 4 is a flow chart of a third embodiment of a test method for improving wafer WAT test capacity of the present invention;
[0027] Figure 5 It is a schematic diagram of the structure of an embodiment of a test system for improving wafer WAT test capacity of the present invention. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. It is hereby stated that the directional terms such as up, down, left, right, front, back, inside, outside, etc. that appear or will appear in the text of the present invention are only based on the accompanying drawings of the present invention, and are not specific limitations of the present invention.
[0029] See also Figure 2 , Figure 2 The flowchart of the first embodiment of the test method for improving wafer WAT test capacity of the present invention is shown, which includes:
[0030] S101, partitioning the wafers in the current batch according to the number of target point measurements to select target chips;
[0031] The existing WAT test system defines the number of test cores by calculating the step size in the X and Y directions, so that the estimated number of cores is greater than the required number of cores, wasting WAT test capacity. Different from the prior art, the present invention adopts a partitioning method and flexibly sets the number and area of partitions to select target cores, which can effectively ensure that the number of selected target cores is consistent with the number of target point test particles, avoiding waste of WAT test capacity.
[0032] Further, the steps of partitioning the wafers in the current batch according to the number of target point measurements to select target core particles include:
[0033] (1) Scanning the wafer;
[0034] (2) performing partition processing on the wafers in the current batch according to the number of wafers measured at the target point, so as to divide the wafers into at least one sub-region;
[0035] It should be noted that the number of particles measured at the target point is the same as the number of sub-regions, thereby ensuring that the number of target core particles selected is consistent with the number of particles measured at the target point.
[0036] For example, if the number of cores to be tested in the WAT test (i.e., the number of target point test cores) is 100, then after scanning, the wafer needs to be divided into 100 sub-areas according to the coordinates.
[0037] Preferably, the areas of the sub-regions are equal, which can further ensure the uniformity of the subsequent target core particles, so as to ensure that the WAT test results can represent the capabilities of the entire wafer.
[0038] Optionally, the partitioning method can be rectangular, triangular, or other special shapes, but is not limited thereto and can be set according to actual conditions.
[0039] (3) Randomly select target core particles in each sub-region.
[0040] Therefore, before implementing WAT testing on the wafer, when scanning and partitioning the wafer, the partitioning principle can be to divide the wafer into equal areas according to the number of target point measurements, and then randomly / regularly measure a target core particle in the divided sub-area, which can represent the photoelectric parameters of the core particles within this area.
[0041] S102, performing WAT test on the target chips in the current wafer in sequence;
[0042] S103, if all target chips in the current wafer have completed the WAT test, then after AutoRetest judgment is performed on the target chips in the current wafer, the WAT test is continued on the target chips in the next wafer in the current batch; otherwise, the WAT test is continued on the target chips in the current wafer that have not undergone the WAT test;
[0043] AutoRetest means that during the wafer testing process, if the wafer yield, mean or the result of a certain test item is not within the preset qualified range, the system will automatically trigger a retest function.
[0044] In the prior art, there is no need to perform AutoRetest judgment, but some resistance or leakage parameters are easily affected by poor probe contact or accumulation of particle impurities, which will cause the test value to exceed the card control specification. Therefore, after the entire batch of wafers has completed the WAT test, if it is found during the SPC judgment that the batch of wafers violates the SPC rules, the entire batch needs to be re-tested.
[0045] Different from the prior art, the present invention performs AutoRetest judgment immediately after the target core particles in the current wafer have completed the WAT test, so as to quickly discover the situation where the test value exceeds the card control specification and avoid subsequent re-loading test of the entire batch.
[0046] S104: If all target core particles in the current batch have completed the AutoRetest process, a SPC (Statistical Process Control) judgment is performed on the target core particles in the current batch.
[0047] Therefore, the present invention can effectively control abnormal output, improve automation efficiency, increase production capacity, increase product pass rate, and ensure quality and quantity.
[0048] See also Figure 3 , Figure 3 A flow chart of a second embodiment of a test method for improving wafer WAT test capacity according to the present invention is shown, which includes:
[0049] S201, partitioning the wafers in the current batch according to the number of target point measurements to select target chips;
[0050] S202, performing WAT test on the target chips in the current wafer in sequence;
[0051] S203, if the target chip in the current wafer has not completed the WAT test, continue to perform the WAT test on the target chip in the current wafer that has not undergone the WAT test;
[0052] S204, if all target chips in the current wafer have completed the WAT test, AutoRetest is performed on the target chips in the current wafer to determine whether the target chips in the current wafer meet the preset parameter specifications;
[0053] S205, if the target chip in the current wafer meets the preset parameter specifications, then perform a WAT test on the target chip in the next wafer in the current batch;
[0054] S206 , if the target chip in the current wafer does not meet the preset parameter specifications, re-perform WAT test on the target chip in the current wafer, and then perform WAT test on the target chip in the next wafer in the current batch.
[0055] Accordingly, when the WAT test is performed again on the target die in the current wafer, the previous WAT test result is overwritten by the new WAT test result.
[0056] Furthermore, when the WAT test is performed again on the target core grain in the current wafer, the original target core grain in the sub-region of the current wafer can be retained and the WAT test can be performed on the original target core grain in the current wafer; or a new target core grain can be reselected in the sub-region of the current wafer, and the WAT test can be performed on the new target core grain in the current wafer.
[0057] It should be noted that, if the target core particle in the current wafer does not meet the control setting of the machine end (i.e. the preset parameter specifications), the origin (i.e. the original target core particle) or the core particle moved to the side of the origin (it can be next to, above, below, or around the origin) can be re-measured. If the second re-measurement still does not meet the AutoRenst judgment, it is assumed that the abnormal point measurement data is caused by the process abnormality of the wafer itself, and the AutoRenst judgment is abandoned and the next wafer is tested. This step mainly controls the abnormal point measurement data caused by hardware-related abnormalities such as probe abnormalities and the integrating sphere not reaching the specified position.
[0058] Therefore, through steps S204 to S206, it can be effectively determined whether the test results of the WAT test meet the parameter specifications. If not, the parameter that does not meet the parameter control specifications is retested, and then the WAT test is performed on the next wafer in the same batch. If yes, the WAT test can be performed on the next wafer in the same batch.
[0059] S207: If all target core particles in the current batch have completed the AutoRetest process, then SPC judgment is performed on the target core particles in the current batch.
[0060] See also Figure 4 , Figure 4 A flow chart of a third embodiment of a test method for improving wafer WAT test capacity according to the present invention is shown, which includes:
[0061] S301, partitioning the wafers in the current batch according to the number of target point measurements to select target cores;
[0062] S302, performing WAT test on the target chips in the current wafer in sequence;
[0063] S303, if the target chip in the current wafer has not completed the WAT test, continue to perform the WAT test on the target chip in the current wafer that has not undergone the WAT test;
[0064] S304, if all target chips in the current wafer have completed the WAT test, AutoRetest is performed on the target chips in the current wafer to determine whether the target chips in the current wafer meet the preset parameter specifications;
[0065] S305, if the target chip in the current wafer meets the preset parameter specifications, then perform a WAT test on the target chip in the next wafer in the current batch;
[0066] S306 , if the target chip in the current wafer does not meet the preset parameter specifications, re-perform WAT test on the target chip in the current wafer, and then perform WAT test on the target chip in the next wafer in the current batch.
[0067] S307, if all target core particles in the current batch have completed the AutoRetest process, then perform SPC judgment on the target core particles in the current batch to determine whether the target core particles in the current batch meet the SPC rules;
[0068] S308, if the target core particles in the current batch meet the SPC rules, the next batch is tested.
[0069] S309, if the target core particles in the current batch do not meet the SPC rules, the HOLD process is executed, and the target core particles in the current batch are tested again.
[0070] After the WAT test of all wafers in the current batch is completed, the test results need to be further judged by SPC. If the SPC rules are violated, the abnormal HOLD process is executed according to the test results, and the WAT test is re-implemented on the batch of wafers; if the SPC rules are not violated, the WAT test is not re-implemented on the batch of wafers, and the batch of wafers enters the next site for subsequent processing.
[0071] It should be noted that after the whole batch of wafers are tested and the machine is unloaded, if the SPC judges that it is abnormal, the system will perform a HOLD action. Among them, the wafers held are generally divided into two types: one is caused by machine hardware abnormalities, and the other is caused by process abnormalities; however, abnormal wafers held need to be retested after personnel judgment (the personnel will observe the actual appearance of the wafers, as well as the pictures generated by the point measurement data, etc.); if it is a process abnormality, it will be directly reworked, and if it is caused by machine hardware abnormalities, it needs to be retested.
[0072] The present invention can give priority to judging the abnormality of the machine hardware by adding the AutoRetest judgment on the machine side, and then retest on the machine at the first time, thereby reducing the generation of HOLD, thereby reducing the pressure of personnel to judge the hold and saving the time and cumbersome process of the second retest on the machine (the second retest on the machine requires the personnel to release the HOLD, the personnel to re-enter the station, the personnel to swipe the AutoRecre, the personnel to go on the machine, and the machine to scan), thereby shortening the production time and improving the production capacity.
[0073] Therefore, the testing method of the present invention for improving the wafer WAT test capacity is to re-measure the parameter origin and re-assign the problematic parameters during the WAT process. After the WAT test of all wafers in the same batch is completed, if the SPC system determines that the SPC rules are violated, there is no need to re-measure the WAT of the batch of wafers before executing the HOLD process, thereby effectively improving the WAT test capacity.
[0074] See also Figure 5 , Figure 5 The specific structure of the test system 100 for improving the wafer WAT test capacity of the present invention is shown, which includes a core particle extraction module 1, a WAT test module 2, an AutoRetest judgment module 3, an SPC judgment module 4, a first judgment module 5 and a second judgment module 6. Specifically:
[0075] The core particle extraction module 1 is used to partition the wafers in the current batch according to the target point measurement number to select the target core particles; the existing WAT test system defines the number of test core particles by calculating the step size in the X and Y directions, so that the estimated number of core particles is greater than the required number of core particles, wasting the WAT test capacity; different from the prior art, the core particle extraction module 1 adopts a partitioning method and flexibly sets the number and area of partitions to select the target core particles, which can effectively ensure that the selected target core particle number is consistent with the target point measurement number, avoiding the waste of WAT test capacity.
[0076] The WAT test module 2 is used to perform WAT tests on the target chips in the current wafer in sequence;
[0077] The AutoRetest judgment module 3 is used to perform AutoRetest judgment on the target core grain in the current wafer; AutoRetest (automatic retest) means that during the wafer testing process, if the yield, mean or result of a certain test item of the wafer is not within the preset qualified range, the system will automatically trigger the retest function.
[0078] The SPC judgment module 4 is used to perform SPC judgment on the target core particles in the current batch to determine whether the target core particles in the current wafer meet the preset parameter specifications;
[0079] The first judgment module 5 is used to judge whether all the target core grains in the current wafer have completed the WAT test. When the judgment is yes, the AutoRetest judgment module is driven to perform the AutoRetest judgment on the target core grains in the current wafer, and the WAT test module is driven to continue to perform the WAT test on the target core grains in the next wafer in the current batch. When the judgment is no, the WAT test module is driven to continue to perform the WAT test on the target core grains in the current wafer that have not undergone the WAT test.
[0080] The second judgment module 6 is used to judge whether all target core particles in the current batch have completed the AutoRetest process. If the judgment is yes, the SPC judgment module is driven to perform SPC judgment on the target core particles in the current batch.
[0081] Unlike the prior art, the present invention performs AutoRetest judgment immediately after all the target cores in the current wafer complete the WAT test, thereby quickly discovering the situation where the test value exceeds the card control specification, avoiding the subsequent re-testing of the entire batch. Therefore, the present invention can effectively control abnormal output, improve automation efficiency, increase production capacity, improve product pass rate, and ensure quality and quantity.
[0082] Accordingly, the core particle extraction module 1 includes:
[0083] A scanning unit, used for scanning the wafer;
[0084] A partitioning unit performs partitioning processing on the wafers in the current batch according to the number of target point measurement wafers, so as to divide the wafers into at least one sub-area;
[0085] The extraction unit is used to randomly select target core particles in the sub-regions respectively.
[0086] It should be noted that in the present invention, the number of target point test particles is the same as the number of sub-areas, so as to ensure that the number of selected target core particles is consistent with the number of target point test particles. For example, if the number of core particles required to be tested by the WAT test (i.e., the number of target point test particles) is 100, then after scanning, the wafer needs to be divided into 100 sub-areas according to the coordinates.
[0087] Preferably, the areas of each sub-region are equal, which can further ensure the uniformity of the subsequent target core particles, so as to ensure that the WAT test results can represent the capabilities of the entire wafer. At the same time, the partitioning method can be rectangular, triangular, or other special shapes, but it is not limited to this and can be set according to actual conditions.
[0088] Therefore, before implementing WAT testing on the wafer, when scanning and partitioning the wafer, the partitioning principle can be to divide the wafer into equal areas according to the number of target point measurements, and then randomly / regularly measure a target core particle in the divided sub-area, which can represent the photoelectric parameters of the core particles within this area.
[0089] Furthermore, the test system 100 for improving wafer WAT test capacity also includes a third judgment module, which is used to drive the WAT test module to re-perform WAT test on the target chip in the current wafer when the SPC judgment module determines that the target chip in the current wafer does not meet the preset parameter specifications.
[0090] Accordingly, when the WAT test is performed again on the target die in the current wafer, the previous WAT test result is overwritten by the new WAT test result.
[0091] At the same time, when the WAT test is performed again on the target core grain in the current wafer, the original target core grain in the sub-region of the current wafer can be retained, and the WAT test can be performed on the original target core grain in the current wafer; or a new target core grain can be reselected in the sub-region of the current wafer, and the WAT test can be performed on the new target core grain in the current wafer.
[0092] It should be noted that, if the target core particle in the current wafer does not meet the control setting of the machine end (that is, the preset parameter specifications), the origin (that is, the original target core particle) or the core particle moved to the side of the origin (it can be next to, above, below, or around the origin) can be re-measured. If the second re-measurement still does not meet the AutoRenst judgment, it is assumed that the point measurement data abnormality is caused by the process abnormality of the wafer itself. The AutoRenst judgment is abandoned and the test of the next wafer is continued. This step mainly controls the point measurement data abnormality caused by hardware-related abnormalities such as probe abnormalities and the integrating sphere not reaching the specified position.
[0093] Therefore, the testing method of the present invention for improving the wafer WAT test capacity is to re-measure the parameter origin and re-assign the problematic parameters during the WAT process. After the WAT test of all wafers in the same batch is completed, if the SPC system determines that the SPC rules are violated, there is no need to re-measure the WAT of the batch of wafers before executing the HOLD process, which can effectively improve the WAT test capacity.
[0094] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A test method for improving wafer WAT test capacity, characterized in that: include: According to the number of target points, the wafers in the current batch are partitioned to select the target core particles; Perform WAT test on the target chips in the current wafer in turn; If all target chips in the current wafer have completed the WAT test, then the target chips in the current wafer are subjected to the AutoRetest judgment and then the WAT test is continued on the target chips in the next wafer in the current batch; otherwise, the WAT test is continued on the target chips in the current wafer that have not undergone the WAT test; If all target core particles in the current batch have completed the AutoRetest process, then the SPC judgment is performed on the target core particles in the current batch.
2. The test method for improving wafer WAT test capacity as claimed in claim 1, characterized in that: The step of performing the WAT test on the target die in the next wafer in the current batch after performing the AutoRetest judgment on the target die in the current wafer comprises: Performing AutoRetest on the target chip in the current wafer to determine whether the target chip in the current wafer meets the preset parameter specifications; If the target die in the current wafer meets the preset parameter specifications, the WAT test is performed on the target die in the next wafer in the current batch; If the target die in the current wafer does not meet the preset parameter specifications, the WAT test is performed again on the target die in the current wafer, and then the WAT test is performed on the target die in the next wafer in the current batch.
3. The test method for improving wafer WAT test capacity as claimed in claim 2, characterized in that: When re-performing WAT test on the target chip in the current wafer: retaining the original target chips in the sub-region of the current wafer and performing WAT test on the original target chips in the current wafer; or A new target die is reselected in the sub-area of the current wafer, and a WAT test is performed on the new target die in the current wafer.
4. The test method for improving wafer WAT test capacity as claimed in claim 2, characterized in that: When the WAT test is performed again on the target die in the current wafer, the previous WAT test result is overwritten by the new WAT test result.
5. The test method for improving wafer WAT test capacity as claimed in claim 1, characterized in that: The step of partitioning the wafers in the current batch according to the number of target point measurements to select target core particles includes: Scanning wafers; Partitioning the wafers in the current batch according to the target point measurement number to divide the wafers into at least one sub-region, wherein the target point measurement number is the same as the number of sub-regions; Target core particles are randomly selected in the sub-regions respectively.
6. The test method for improving wafer WAT test capacity as claimed in claim 5, characterized in that: The areas of each sub-region are equal.
7. The test method for improving wafer WAT test capacity as claimed in claim 1, characterized in that: Also includes: When performing SPC judgment on the target core particles in the current batch to determine whether the target core particles in the current batch meet the SPC rules, If the target core particles in the current batch meet the SPC rules, the next batch is tested; If the target core particles in the current batch do not meet the SPC rules, the HOLD process is executed, and the target core particles in the current batch are tested again.
8. A test system for improving wafer WAT test capacity, characterized in that: include: The core particle extraction module is used to partition the wafers in the current batch according to the number of target point measurements to select the target core particles; A WAT test module is used to perform WAT tests on target chips in the current wafer in sequence; The AutoRetest judgment module is used to perform AutoRetest judgment on the target core in the current wafer; An SPC judgment module is used to perform SPC judgment on the target core particles in the current batch to determine whether the target core particles in the current wafer meet the preset parameter specifications; The first judgment module is used to judge whether all target core grains in the current wafer have completed the WAT test. When the judgment is yes, the AutoRetest judgment module is driven to perform the AutoRetest judgment on the target core grains in the current wafer, and the WAT test module is driven to continue to perform the WAT test on the target core grains in the next wafer in the current batch. When the judgment is no, the WAT test module is driven to continue to perform the WAT test on the target core grains in the current wafer that have not undergone the WAT test; The second judgment module is used to judge whether all target core particles in the current batch have completed the AutoRetest process, and if the judgment is yes, drive the SPC judgment module to perform SPC judgment on the target core particles in the current batch.
9. The test system for improving wafer WAT test productivity as claimed in claim 8, characterized in that: It also includes a third judgment module, which is used to drive the WAT test module to re-perform the WAT test on the target chip in the current wafer when the SPC judgment module determines that the target chip in the current wafer does not meet the preset parameter specifications.
10. The test system for improving wafer WAT test productivity as claimed in claim 8, characterized in that: The core particle extraction module comprises: A scanning unit, used for scanning the wafer; A partitioning unit, which performs partitioning processing on the wafers in the current batch according to the number of target point measurement particles, so as to divide the wafers into at least one sub-region, wherein the number of target point measurement particles is the same as the number of sub-regions; The extraction unit is used to randomly select target core particles in the sub-areas respectively.