Manufacturing method of semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps: providing a first substrate and a second substrate; a bonding process is carried out to bond the first substrate and the second substrate with each other and form a bonding structure, the bonding process comprises a plurality of process steps carried out by using a plurality of independent machines in a plurality of work stations, and the bonding process comprises the following steps: forming a bonding layer on the first substrate by using a film layer forming device, forming a first substrate structure comprising a first substrate base plate and a bonding layer; performing a planarization process on the bonding layer of the first substrate structure by using planarization equipment; performing a cleaning process on the first substrate structure by using cleaning equipment; performing surface activation treatment on the bonding layer of the first substrate structure by using plasma generation equipment; performing a pre-bonding process in a bonding machine so as to pre-bond the first substrate structure to the second substrate base plate and form a pre-bonded structure; and performing an annealing process on the pre-bonding structure by using annealing equipment, and forming a bonding structure.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor structure. Background Art

[0002] In semiconductor technology, bonding processes can be used for product pattern transfer or special reinforcement processes, etc. In the bonding process, dielectric surfaces or semiconductor surfaces are mostly used as bonding surfaces, such as bonding silicon dioxide surfaces to silicon surfaces. For example, for the first structure and the second structure to be bonded, in the traditional process, a high-temperature (e.g., 800°C to 1000°C) thermal oxidation process is usually performed on the first structure (e.g., a silicon wafer or other material sheet) to form a silicon dioxide layer, and then the first structure formed with the silicon dioxide layer is pre-bonded to the second structure (e.g., another silicon wafer); then an annealing process is performed at a temperature of, for example, 800°C to 1000°C to complete the bonding of the first structure and the second structure.

[0003] However, in actual applications, many products (for example, filters with cavities, products including cantilever beam structures, etc.) cannot undergo high-temperature processes. In order to avoid bonding under high-temperature process conditions, some high-end process machines have been developed on the market, such as the EVG 850LT / EVG Gemini machine with a market share of more than 80%. This machine is a fully automatic bonding system that can achieve effective pre-bonding without undergoing a high-temperature annealing process. When using this machine for the bonding process, the surface treatment steps for the structure to be bonded (for example, silicon wafers) and the bonding steps are all completed in the same machine. However, such machines are expensive, which significantly increases manufacturing costs. Summary of the invention

[0004] According to at least one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a first substrate substrate and a second substrate substrate; performing a bonding process to bond the first substrate substrate and the second substrate substrate to each other and form a bonding structure, wherein the bonding process comprises a plurality of process steps performed in a plurality of workstations using a plurality of independent machines, the bonding process comprising: at a first workstation, forming a bonding layer on the first substrate substrate using a film layer forming device, thereby forming a first substrate structure comprising the first substrate substrate and the bonding layer; at a second workstation, performing a flattening process on the bonding layer of the first substrate structure using a flattening device; at a third workstation, performing a cleaning process on the first substrate structure using a cleaning device; at a fourth workstation, performing a surface activation treatment on the bonding layer of the first substrate structure using a plasma generating device; at a fifth workstation, performing a pre-bonding process in a bonding machine to pre-bond the first substrate structure to the second substrate substrate and form a pre-bonded structure; and at a sixth workstation, performing an annealing process on the pre-bonded structure using an annealing device and forming the bonding structure.

[0005] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the film layer forming equipment includes a deposition machine.

[0006] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the deposition machine is a chemical vapor deposition machine, and using the film layer forming equipment to form the bonding layer on the first substrate includes using the chemical vapor deposition machine to deposit silicon dioxide material on the first substrate under a temperature condition of 250°C to 450°C.

[0007] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the planarization equipment includes a chemical mechanical polishing machine.

[0008] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, after the planarization process is performed on the bonding layer, the surface roughness of the bonding layer is less than 0.7 nm.

[0009] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the cleaning equipment includes a wet acid bath, and the cleaning process cleans and removes impurity particles on the surface of the bonding layer in the wet acid bath; and introduces hydrogen bonds on the surface of the bonding layer away from the first substrate.

[0010] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the cleaning liquid used in the cleaning process includes at least one of chemical solution No. 1, chemical solution No. 2, hydrofluoric acid, sulfuric acid, and deionized water.

[0011] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, using the plasma generating equipment to perform surface activation treatment on the bonding layer of the first substrate structure includes introducing one or more of oxygen, argon, nitrogen, and helium into the plasma generating equipment to generate corresponding plasma, and performing surface activation treatment on the bonding layer by using the plasma.

[0012] In the method for manufacturing a semiconductor structure provided by at least one embodiment of the present disclosure, the bonding layer includes a silicon oxide material, and performing the surface activation treatment on the bonding layer includes performing a surface silicon-oxygen bond activation treatment.

[0013] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, performing a pre-bonding process in the bonding machine includes bringing the first substrate structure and the second substrate substrate into contact with each other under vacuum or normal pressure and temperature conditions, and placing the bonding layer of the first substrate structure facing the second substrate substrate, and applying a pressure of 10KN to 100KN to the first substrate structure and the second substrate substrate.

[0014] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the annealing process is performed at a temperature of 300° C. to 400° C.

[0015] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, the annealing equipment includes an oven or an annealing machine.

[0016] In the method for manufacturing a semiconductor structure provided according to at least one embodiment of the present disclosure, in the multiple process steps, the transfer time of the first substrate structure from the previous station to the next station in the first station to the sixth station is controlled within 1 hour. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0018] Figure 1A and Figure 1B A schematic cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figure 3A schematic block diagram showing multiple workstations in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0021] Figure 4 A schematic diagram showing a bonding strength test of a bonding structure according to some embodiments of the present disclosure.

[0022] Figure 5 A picture showing a detection structure for performing ultrasonic flaw detection on a bonding structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0025] The present embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a first substrate substrate and a second substrate substrate; and performing a bonding process to bond the first substrate substrate and the second substrate substrate to each other and form a bonding structure, wherein the bonding process includes a plurality of process steps performed in a plurality of workstations using a plurality of independent machines; wherein the bonding process includes: at a first workstation, using a film layer forming device to form a bonding layer on the first substrate substrate, thereby forming a first substrate structure including the first substrate substrate and the bonding layer; at a second workstation, using a flattening device to perform a flattening process on the bonding layer of the first substrate structure; at a third workstation, using a cleaning device to perform a cleaning process on the first substrate structure; at a fourth workstation, using a plasma generating device to perform a surface activation treatment on the bonding layer of the first substrate structure; at a fifth workstation, performing a pre-bonding process in a bonding machine to pre-bond the first substrate structure to the second substrate substrate; and at a sixth workstation, using an annealing device to perform an annealing process on the first substrate structure and the second substrate substrate pre-bonded to each other.

[0026] In the embodiments of the present disclosure, by using multiple devices to perform related processes in multiple process steps of the bonding process, the expected bonding requirements can be achieved, and the present disclosure can use common machines / equipment, and can achieve effective bonding with a bonding machine with simple functions (for example, domestic laminating machines, EVG510, 620, etc.), and there is no need to perform an annealing process under high temperature conditions after pre-bonding is completed. In this way, the method can be applied to product needs that cannot undergo high-temperature processes while reducing dependence on expensive high-end machines. Compared with the cost of using high-end machines, the cost of using conventional machines in the present disclosure can be effectively reduced, for example, about 1 / 4 of the cost of high-end machines.

[0027] Figure 1A and Figure 1B A schematic cross-sectional view illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 3 A schematic block diagram showing multiple workstations through which multiple process steps are performed in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0028] refer to Figure 1A , Figure 2 and Figure 3In some embodiments, in step S1, a first substrate substrate is provided, and a bonding layer is formed on the first substrate substrate to form a first substrate structure including the first substrate substrate and the bonding layer. For example, a first substrate substrate 100 is provided, and a bonding layer 101 is formed on the first substrate substrate 100 to form a first substrate structure 105 including the first substrate substrate 100 and the bonding layer 101. The first substrate substrate 100 may be or include a semiconductor wafer, such as a silicon wafer (or silicon chip). The first substrate substrate 100 may include a semiconductor substrate such as a silicon substrate.

[0029] In some embodiments, the first substrate 100 may include only the semiconductor substrate, and the bonding layer 101 may be directly formed on the semiconductor substrate and in direct contact with the semiconductor substrate. In other embodiments, the first substrate 100 may also include one or more material layers located on the semiconductor substrate, such as one or more of a dielectric layer, a conductive layer, and a semiconductor layer, and the present disclosure does not limit the number and type of the material layers. For example, in the first substrate 100, one or more devices may be provided on the semiconductor substrate, such as one or more active devices such as transistors, and passive devices such as capacitors, and the present disclosure does not limit the number and type of the devices. That is, one or more material layers and / or one or more devices may also be provided between the semiconductor substrate and the bonding layer 101.

[0030] In some embodiments, step S1 of forming a bonding layer 101 on the first substrate 100 is performed in a film forming device E1 at the workstation WS1; for example, the film forming device E1 may be a deposition machine, such as a chemical vapor deposition (CVD) machine, and may achieve low-temperature deposition below 600°C. For example, step S1 includes using a CVD machine to deposit a bonding layer 101 on the first substrate 100 through a CVD process, wherein the CVD process is performed at a temperature of 250°C to 450°C, for example. The bonding layer 101 may include a dielectric material such as silicon dioxide. For example, the CVD process may be a plasma-enhanced CVD process, and may include heating and decomposing tetraethyl orthosilicate (TEOS) under high-density plasma conditions at a temperature of 250°C to 450°C to form a silicon dioxide material on the surface of the first substrate 100. However, the present disclosure is not limited thereto. The bonding layer 101 may also be formed using other types of deposition machines and deposition processes to select suitable source materials.

[0031] refer to Figure 1A , Figure 2 and Figure 3Then, in step S2, a planarization process is performed on the first substrate structure 105; for example, a planarization process is performed on the surface of the bonding layer 101 on the side away from the first substrate substrate 100, so that the bonding layer 101 has a flat surface on the side away from the first substrate substrate 100, which is convenient for the subsequent bonding process. For example, the step S2 of performing a planarization process on the first substrate structure 105 is performed at the workstation WS2 using a planarization device E2. For example, the planarization process may include a grinding process such as chemical mechanical polishing (CMP), and the planarization device E2 may be or include a grinding machine such as a CMP machine.

[0032] In some embodiments, after the first substrate structure 105 is planarized in step S2 , the roughness of the surface of the bonding layer 101 away from the first substrate 100 may be less than 0.7 nm, so as to facilitate the subsequent bonding process.

[0033] refer to Figure 1A , Figure 2 and Figure 3 Then, in step S3, a cleaning process is performed on the first substrate structure. For example, a cleaning process is performed on the surface of the bonding layer 101 of the first substrate structure 105 that is away from the first substrate substrate 100 to remove impurities (e.g., particle impurities) on the surface of the bonding layer 101; in some embodiments, the cleaning process also introduces hydrogen bonds on the surface of the bonding layer 101 that is away from the first substrate substrate 100 to facilitate subsequent bonding processes.

[0034] For example, the cleaning process of step S3 is performed at station WS3 using cleaning equipment E3; cleaning equipment E3 may be or include a wet acid tank, and the cleaning liquid used in the cleaning process may include one or more of chemical liquid No. 1, chemical liquid No. 2, hydrofluoric acid (e.g., diluted hydrofluoric acid), sulfuric acid (e.g., diluted sulfuric acid), etc., and deionized water; the deionized water may be deionized water with ultrasound or deionized water doped with N2 or CO2. In this article, liquid No. 1 refers to a mixed cleaning liquid obtained by mixing ammonia water, hydrogen peroxide (i.e., hydrogen peroxide) and water (e.g., deionized water) in a certain proportion; liquid No. 2 refers to a mixed cleaning liquid obtained by mixing hydrochloric acid, hydrogen peroxide and water (e.g., deionized water) in a certain proportion.

[0035] refer to Figure 1A , Figure 2 and Figure 3, in step S4, the bonding layer of the first substrate structure is subjected to surface activation treatment. For example, step S4 is performed at workstation WS4 using plasma generating equipment E4. For example, the plasma generating equipment E4 may be or include any machine with an electric arc starting function and capable of generating plasma, such as P5000, ENDURA, CENTURA, SPTS, Northern Micro, etc., but the present disclosure is not limited thereto. In some embodiments, the bonding layer 101 includes a silicon dioxide material, and the surface activation treatment includes performing a silicon oxygen bond (Si-O) activation treatment on the surface of the bonding layer 101 away from the first substrate substrate 100. For example, the activation treatment may include introducing one or more of an inert gas such as oxidation, argon, nitrogen, helium, etc. into the plasma generating equipment E1, and then ionizing the gas by electric arc starting to form a corresponding plasma, and using the plasma to activate the surface of the bonding layer 101.

[0036] refer to Figure 1A , Figure 1B , Figure 2 and Figure 3 In step S5, a pre-bonding process is performed to pre-bond the first substrate structure 105 having the bonding layer 101 to the second substrate 200, and form a pre-bonded structure including the first substrate structure 105 and the second substrate 200. For example, the pre-bonding process can be performed at station WS5 by a bonding machine E5; for example, after the first substrate structure 105 is subjected to a surface activation treatment at station WS4, the first substrate structure 105 subjected to a series of surface processing such as steps S1 to S4 is removed from the plasma generating device E4 at station WS4, and the first substrate structure 105 is transferred to the bonding machine E5 at station WS5.

[0037] Step 5 also includes providing a second substrate substrate 200, and placing the second substrate substrate 200 in the bonding machine E5; it should be understood that the first substrate structure 105 and the second substrate substrate 200 can be placed in the bonding machine E5 one after another or simultaneously to perform a subsequent pre-bonding process. The second substrate substrate 200 may include a semiconductor substrate such as a silicon substrate. For example, the second substrate substrate 200 may be a semiconductor wafer such as a silicon wafer, such as a bare wafer, that is, the second substrate substrate 200 may only include a semiconductor substrate, and no other device layers are formed on the semiconductor substrate, but the present disclosure is not limited to this. The second substrate substrate 200 may also include a substrate and a device layer formed on the substrate. In an embodiment where the second substrate substrate 200 is a bare wafer, the surface of the bare wafer has good bonding conditions, and the second substrate substrate 200 may not need to be surface treated before the pre-bonding process, but the present disclosure is not limited to this. In other embodiments, the second substrate substrate 200 may also be subjected to one or more of a flattening process, a cleaning process, a surface activation process, etc. similar to the surface processing of the first substrate structure.

[0038] For example, in the pre-bonding process, the first substrate structure 105 and the second substrate substrate 200 are aligned with each other, so that the first substrate structure 105 and the second substrate substrate 200 are in contact, and the bonding layer 101 in the first substrate structure 105 faces the second substrate substrate 200, that is, the bonding layer 101 is located between the first substrate substrate 100 and the second substrate substrate 200. Then, for example, under vacuum or normal pressure and normal temperature conditions, a pressure of 10 kilonewtons (KN) to 100 KN is applied to the first substrate structure 105 and the second substrate substrate 200 for pre-bonding. It should be understood that the pressure applied to the first substrate structure 105 and the second substrate substrate 200 includes pressure applied to the first substrate structure 105 and the second substrate substrate 200 toward each other, respectively, so as to pre-bond the two together.

[0039] Continue to refer Figure 1B , Figure 2 and Figure 3 In some embodiments, in step S6, an annealing process is performed on the pre-bonded structure formed in step S5 to complete the bonding process and form a bonding structure 500. The annealing process is, for example, completed at station WS6 by an annealing device E6. In some embodiments, the annealing device E6 may include an oven or an annealing machine.

[0040] In some embodiments, the annealing process can be performed under low temperature conditions; for example, the annealing process is performed at a temperature of 300°C to 400°C. In the embodiments of the present disclosure, since a series of surface processing treatments have been performed on the bonding layer before pre-bonding, the surface of the bonding layer has good bonding conditions and meets the expected pre-bonding requirements, so that the subsequent annealing process can be performed under low temperature conditions to complete the bonding and achieve a good bonding effect. In this way, the bonding process of the present disclosure can meet the needs of products that cannot undergo high temperature processes, and can be applied to the manufacturing processes of these products. It can ensure the bonding quality while avoiding the reliability of these products from being affected by high temperature processes.

[0041] In some embodiments, multiple process steps of the bonding process (i.e., including surface treatment steps, pre-bonding steps, annealing steps, etc.) are completed at multiple stations using multiple devices, and the multiple devices are independent of each other, and the first substrate structure needs to be removed from the device used in the previous step after completing the previous step, and transferred to the device of the next step to perform the next step. In some embodiments, when transferring the structure to be bonded between each station, the transfer time needs to be controlled to avoid environmental pollution or other adverse effects on the structure to be bonded during the transfer process, thereby avoiding affecting the subsequent bonding effect.

[0042] For example, after completing step S1 at station WS1, the first substrate structure 105 is taken out of the film forming equipment E1 and transferred to the flattening machine E2 of station WS2 to perform step S2. In some embodiments, during the process of transferring the first substrate structure 105 from station WS1 to station WS2, the transfer time is controlled within 1 hour, for example, within about 30 minutes to 1 hour or 30 minutes, so as to avoid the first substrate structure 105 from being contaminated by the external environment during the transfer process. In this article, "transfer time" refers to the interval time between the moment when the structure is removed from the equipment of the previous station and the moment when it enters the equipment of the next station, and may include the time for transfer and / or waiting between stations.

[0043] For example, after completing step S2 at station WS2, the first substrate structure 105 is taken out of the planarization equipment E2 and transferred to the cleaning equipment E3 of station WS3 to perform step S3. In some embodiments, during the process of transferring the first substrate structure 105 from station WS2 to station WS3, the transfer time is controlled within 1 hour, for example, from about 30 minutes to 1 hour or within 30 minutes, so as to avoid the first substrate structure 105 being contaminated or otherwise adversely affected by the external environment during the transfer between stations.

[0044] For example, after completing step S3 at station WS3, the first substrate structure 105 is taken out of the cleaning equipment E3 and transferred to the plasma generating equipment E4 of station WS4 to perform step S4. In some embodiments, during the process of transferring the first substrate structure 105 from station WS3 to station WS4, the transfer time is controlled within 1 hour, for example, from about 30 minutes to 1 hour or within 30 minutes, so as to avoid the first substrate structure 105 being contaminated or otherwise adversely affected by the external environment during the transfer process.

[0045] For example, after completing step S4 at station WS4, the first substrate structure 105 is removed from the plasma generating device E4 at station WS4, and the first substrate structure 105 is transferred to the bonding machine E5 at station WS5 to perform step S5. In some embodiments, during the process of transferring the first substrate structure 105 from station WS4 to station WS5, the transfer time is controlled within 1 hour, for example, within about 30 minutes to 1 hour or 30 minutes, so as to avoid the first substrate structure 105 being contaminated or otherwise adversely affected by the external environment during the transfer process.

[0046] For example, after completing step S5 at station WS5, the pre-bonded structure including the first substrate structure 105 and the second substrate substrate 200 is removed from the bonding machine E5, and the pre-bonded structure is transferred to the annealing equipment E6 of station WS6. In some embodiments, during the process of transferring the first substrate structure 105 from station WS5 to station WS6, the transfer time is controlled within 1 hour, for example, within about 30 minutes to 1 hour or 30 minutes, so as to avoid the pre-bonded structure from being contaminated by the external environment. In some embodiments, station WS1, station WS2, station WS3, station WS4, station WS5 and station WS6 can also be referred to as the first station, the second station, the third station, the fourth station, the fifth station and the sixth station, respectively.

[0047] refer to Figure 1B, the bonding structure 500 includes a first substrate structure 105 and a second substrate substrate 200, that is, includes a first substrate substrate 100, a second substrate substrate 200 and a bonding layer 101 located between the first substrate substrate 100 and the second substrate substrate 200. The bonding structure 500 includes a bonding interface located between the bonding layer 101 and the second substrate substrate 200, and the bonding interface may be a semiconductor-to-dielectric bonding interface, such as a silicon dioxide-to-silicon bonding interface, but the present disclosure is not limited thereto. In other embodiments, a bonding layer (e.g., a silicon oxide layer) may be formed on the first substrate substrate 100 and the second substrate substrate 200, respectively, and the resulting bonding structure may include a dielectric-to-dielectric bonding interface. In some embodiments, the first substrate substrate 100 and the second substrate substrate 200 may be respectively referred to as sub-bonding structures of the bonding structure 500.

[0048] In some embodiments, after the bonding process is completed, ultrasonic flaw detection and bonding strength test may be performed to detect the performance of the formed bonding structure. Ultrasonic flaw detection is used to check whether there are cavities, bubbles, etc. at the bonding interface of the bonding structure. The bonding strength test may, for example, include inserting a fixed thickness blade between two substrates and calculating the bonding strength of the bonding structure according to the following formula:

[0049] BE(mJ / m 2 )=(3×h 2 ×E×t 3 ) / (32×L 4 )

[0050] For example, refer to Figure 4 For the bonding structure BS including the sub-bonding structure W1 and the sub-bonding structure W2, when performing a bonding strength test on the bonding structure BS, a blade 60 is inserted between the two sub-bonding structures W1 and W2 to generate a gap between the two sub-bonding structures, and then the bonding strength is calculated using the above formula.

[0051] For example, in the above formula, BE represents the bonding strength of the bonding structure BS, h represents the thickness of the blade 60 (in mm), E represents the Young's modulus (in Pa) of the sub-bonding structure material (for example, silicon); t is the thickness of the sub-bonding structure, and L is the length of the gap generated between the two sub-bonding structures after the blade is inserted.

[0052] It should be understood that in the above formula, it is assumed that the thickness of the sub-bonding structure W1 is t w1 and the thickness t of the sub-bonding structure W2 w2 are equal to each other, then t=t in the above formula w1 =t w2Assuming that the two sub-bonding structures W1 and W2 have approximately the same or similar Young's modulus, E in the above formula is equal to the Young's modulus of any one of the two sub-bonding structures. If the sub-bonding structures W1 and W2 have different thicknesses and / or different Young's moduli, other corresponding calculation formulas can be used to calculate the bonding strength of the bonding structure.

[0053] In some embodiments, the above method is used to test the bonding strength of the bonding structure 500 formed by the method of the embodiment of the present disclosure, that is, the bonding structure BS is Figure 1B The bonding structure 500 shown is a first substrate 100 and a second substrate 200. In some examples, the bonding strength of the bonding structure 500 can reach 1.8 J / m 2 Up to 2.2 J / m 2 .

[0054] Figure 5 FIG. 5 is a picture showing the results of ultrasonic flaw detection on the bonding structure 500. Figure 5 As shown, from the detection results of ultrasonic flaw detection, there are no defects such as voids and bubbles on the bonding interface of the bonding structure 500.

[0055] That is to say, the bonding method according to the embodiment of the present disclosure can make the bonding strength between the first substrate and the second substrate higher, and there are substantially no defects such as voids and bubbles at the bonding interface of the formed bonding structure, that is, it has a better bonding effect.

[0056] In the bonding process of the embodiment of the present disclosure, the surface of the structure to be bonded (for example, the surface of the bonding layer) is subjected to multiple steps of surface treatment processes (for example, planarization process, cleaning process, surface activation treatment, etc.) before pre-bonding, so that the surface of the structure to be bonded meets the expected pre-bonding requirements, and then the bonding can be completed by performing an annealing process at a relatively low temperature (for example, 300°C to 400°C) after the pre-bonding is completed; moreover, in the bonding process, the bonding layer is formed on the first substrate by a low-temperature deposition process rather than a high-temperature thermal oxidation process; in this way, in the entire bonding process, damage to the bonding structure that may be caused by a high-temperature process can be avoided.

[0057] On the other hand, in the embodiments of the present disclosure, the multiple steps of the bonding process are completed in different workstations by multiple independent devices, rather than in multiple chambers of the same bonding machine. Compared with the expensive fully automatic bonding machine, the devices used in the embodiments of the present disclosure are easily available on the market, with low cost, and can meet the needs of products that cannot withstand high temperature processes while achieving substantially the same bonding effect as the expensive machines.

[0058] In addition, in the manufacturing method of the semiconductor structure disclosed in the present invention, each process step is performed in multiple independent devices, so the process flexibility can be greatly improved; the devices in each workstation do not affect each other, so as to avoid the situation where the entire process flow cannot be carried out due to a failure of a device in a certain workstation. That is, the failed device can be repaired separately without affecting the process steps of other workstations.

[0059] The bonding process in the semiconductor structure manufacturing method disclosed in the present invention can be applied to the manufacturing processes of various semiconductor devices or other electronic devices, for example, it can be applied to the manufacturing of resonator devices, semiconductor packaging and other devices, and the present invention is not limited thereto.

[0060] There are a few points to note:

[0061] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0062] (2) In the absence of conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0063] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a first substrate substrate and a second substrate substrate; A bonding process is performed to bond the first substrate substrate and the second substrate substrate to each other and form a bonding structure, wherein the bonding process includes a plurality of process steps performed in a plurality of workstations using a plurality of independent machines, and the bonding process includes: At a first workstation, a bonding layer is formed on the first substrate substrate using a film forming device, thereby forming a first substrate structure including the first substrate substrate and the bonding layer; At the second workstation, using a planarization device to perform a planarization process on the bonding layer of the first substrate structure; At a third workstation, using a cleaning device to perform a cleaning process on the first substrate structure; At a fourth station, using a plasma generating device to perform surface activation treatment on the bonding layer of the first substrate structure; At a fifth station, performing a pre-bonding process in a bonding machine to pre-bond the first substrate structure to the second substrate substrate and form a pre-bonded structure; and At the sixth station, an annealing device is used to perform an annealing process on the pre-bonded structure to form the bonding structure. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the film forming equipment comprises a deposition machine.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein the deposition machine is a chemical vapor deposition machine, and using the film layer forming equipment to form the bonding layer on the first substrate includes using the chemical vapor deposition machine to deposit silicon dioxide material on the first substrate under a temperature condition of 250°C to 450°C. The method for manufacturing a semiconductor structure according to claim 1 , wherein the planarization equipment comprises a chemical mechanical polishing machine. 5 . The method for manufacturing a semiconductor structure according to claim 1 , wherein after the planarization process is performed on the bonding layer, the surface roughness of the bonding layer is less than 0.7 nm.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein the cleaning equipment comprises a wet acid bath, and the cleaning process cleans and removes impurity particles on the surface of the bonding layer in the wet acid bath; and introduces hydrogen bonds on the surface of the bonding layer away from the first substrate. 7 . The method for manufacturing a semiconductor structure according to claim 6 , wherein the cleaning solution used in the cleaning process comprises at least one of chemical solution No. 1, chemical solution No. 2, hydrofluoric acid, sulfuric acid, and deionized water.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein using the plasma generating equipment to perform surface activation treatment on the bonding layer of the first substrate structure comprises introducing one or more of oxygen, argon, nitrogen, and helium into the plasma generating equipment to generate corresponding plasma, and performing surface activation treatment on the bonding layer by using the plasma. 9 . The method for manufacturing a semiconductor structure according to claim 8 , wherein the bonding layer comprises a silicon oxide material, and performing the surface activation treatment on the bonding layer comprises performing a surface silicon-oxygen bond activation treatment.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein the pre-bonding process performed in the bonding machine includes bringing the first substrate structure and the second substrate substrate into contact with each other under vacuum or normal pressure and temperature conditions, and placing the bonding layer of the first substrate structure facing the second substrate substrate, and applying a pressure of 10KN to 100KN to the first substrate structure and the second substrate substrate. 11 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the annealing process is performed at a temperature of 300° C. to 400° C. 12 . The method for manufacturing a semiconductor structure according to claim 11 , wherein the annealing equipment comprises an oven or an annealing machine.

13. The method for manufacturing a semiconductor structure according to any one of claims 1 to 12, wherein in the multiple process steps, the transfer time of the first substrate structure from the previous station to the next station in the first station to the sixth station is controlled within 1 hour.

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