Multi-layer semiconductor packaging assembly, stress adjusting device and manufacturing method thereof

Abstract

The invention discloses a multilayer semiconductor packaging assembly, a stress adjusting device and a manufacturing method thereof. The stress adjusting device includes a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation into the package-on-package assembly to reduce stress, strain, and / or warpage on the active elements within the package assembly.

Description

Technical Field

[0001] The present disclosure relates to a multi-layer semiconductor package component, a stress regulating device and a manufacturing method of the stress regulating device. Background Art

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor components are manufactured by sequentially depositing dielectric layers, conductive layers, and semiconductor layers of insulation or materials on a substrate, and patterning the various material layers using lithography to form circuit components and components thereon. As the semiconductor industry enters nanotechnology process nodes in pursuit of higher component density, higher performance, and lower cost, challenges in manufacturing and design issues have led to the development of three-dimensional designs, including, for example, Metal-Oxide-Silicon Field Effect Transistors (MOS-FET), Field Effect Transistors (FET), Fin Field Effect Transistors (FinFET), Gate-All-Around (GAA) devices (nanowires / nanosheets), GAA devices configured as Complementary Field Effect Transistors (CFET) devices, and Multi-Bridge Channel Field Effect Transistors (MBCFET) devices (nanosheets).

[0003] In some cases, the integrated circuit (IC) manufacturing process is divided into front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing. FEOL processes generally cover those processes associated with manufacturing functional elements (such as transistors and resistors) in or on a semiconductor substrate. For example, FEOL processes generally include forming isolation features, gates and dielectrics, and source and drain features (also called source / drain or S / D features). BEOL processes generally cover processes associated with manufacturing multilayer interconnect (MLI) features that interconnect functional IC elements and structures manufactured during FEOL processing to provide connections to the resulting IC device and enable it to operate.

[0004] With the continued reduction in size and the increased use of wafer-attached wafers and wafer-attached wafer assemblies, stress analysis and control at the wafer and package level is gaining importance. Reduction of stress and warpage between and across semiconductor elements will tend to improve the performance and reliability of the resulting semiconductor elements. Wafers, packages and / or boards in a stacked package are all potential sources of structural and thermal stresses, which tend to increase with increasing levels of integration and complexity. Process and / or structural modifications that reduce and / or compensate for some of the mechanical and thermal stresses that arise from the selection and configuration of material layers, bonding structures, semiconductor devices, complex assemblies and / or operations of such devices are helpful in reducing defects, improving performance and / or extending the useful life of the final device. Summary of the invention

[0005] According to some embodiments of the present disclosure, a stress adjustment device includes a semiconductor substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is located above a first side of the semiconductor substrate. The second insulating layer is located above the first insulating layer. The third insulating layer is located above a second side of the semiconductor substrate. The fourth insulating layer is located above the third insulating layer. The fifth insulating layer is located above the fourth insulating layer, wherein the stress adjustment device substantially does not include a conductive material.

[0006] According to some embodiments of the present disclosure, a method of manufacturing a stress regulating device includes the following operations: forming a first insulating material over a first side and a second side of a semiconductor substrate; forming a second insulating material over the first insulating material on the first side and the second side of the semiconductor substrate; forming a third insulating material over the second insulating material on the second side of the semiconductor substrate; forming a fourth insulating material over the second insulating material on the first side of the semiconductor substrate and over the third insulating material on the second side of the semiconductor substrate.

[0007] According to some embodiments of the present disclosure, a multilayer semiconductor package assembly includes a first semiconductor device, a second semiconductor device, and a first stress adjustment device. The second semiconductor device is mounted on the first semiconductor device. The first semiconductor device is electrically connected to the second semiconductor device. The combination of the first semiconductor device and the second semiconductor device has an initial stress load. The first stress adjustment device is configured to reduce the initial stress load. The first stress adjustment device includes a semiconductor substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is located on a first side of the semiconductor substrate. The second insulating layer is located on the first insulating layer. The third insulating layer is located on a second side of the semiconductor substrate. The fourth insulating layer is located on the third insulating layer. The fifth insulating layer is located on the fourth insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard practices in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figures 1A to 1C is a cross-sectional view of a stress and warpage modulating (SWM) structure during a manufacturing process according to some embodiments of the present disclosure;

[0010] Figure 1D is based on Figures 1A to 1C A flow chart of a portion of a manufacturing process for producing a SWM structure of some embodiments of the structure;

[0011] FIG. 2A to FIG. 2C is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments of the present disclosure;

[0012] Figure 2D The figure is based on FIG. 2A to FIG. 2C A flow chart of a portion of a manufacturing process for producing a SWM structure of some embodiments of the structure;

[0013] FIG. 3A to FIG. 3D is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments of the present disclosure;

[0014] Figure 3E is based on FIG. 3A to FIG. 3D A flow chart of a portion of a manufacturing process for producing a SWM structure of some embodiments of the structure;

[0015] FIG. 4A to FIG. 4D is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing flow according to some embodiments;

[0016] Figure 4E is based on FIG. 4A to FIG. 4D A flow chart of a portion of a manufacturing process for producing a SWM structure of some embodiments of the structure;

[0017] FIG. 5A to FIG. 5E is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments of the present disclosure;

[0018] Fig. 5F is based on FIG. 5A to FIG. 5E A flow chart of a portion of a manufacturing process for producing a SWM structure of some embodiments of the structure;

[0019] 6A to 6His a cross-sectional view of a multi-stacked wafer / wafer-level package incorporating a SWM structure during a manufacturing flow according to some embodiments;

[0020] 7A to 7D is a cross-sectional view of an embodiment of a multi-stacked wafer / wafer-level package incorporating a SWM structure;

[0021] FIG. 8A to FIG. 8H is a cross-sectional view of a multi-stacked wafer / wafer-level package incorporating a SWM structure during a manufacturing flow according to some embodiments;

[0022] Fig. 9 is a cross-sectional view of a multi-stacked wafer / die system of integrated chips (SOIC) during a manufacturing process incorporating a SWM structure according to some embodiments;

[0023] Fig.10 is a block diagram of an electronic process control (EPC) system that may be used to produce CFET devices according to some embodiments;

[0024] Fig.11 is a block diagram of a system for manufacturing a CFET element according to some embodiments;

[0025] Fig.12 is a block diagram of fabrication facility operations for fabricating IC devices, according to some embodiments.

[0026]

Explanation of symbols

[0027] 100A: Zero layer structure

[0028] 100B: First layer structure

[0029] 100C: SWM structure

[0030] 100D: Manufacturing Process

[0031] 102:Semiconductor substrate

[0032] 104 b0 :Backside pad oxide layer

[0033] 104 b1 :First rear side additional oxide layer

[0034] 104 bN : Additional oxide layer behind N layer

[0035] 104 f0 :Front side pad oxide layer

[0036] 104 f1:First front side additional oxide layer

[0037] 106 b0 : Backside silicon nitride layer

[0038] 106 b1 :First back side silicon nitride layer

[0039] 106 bN :N layer back side silicon nitride layer

[0040] 106 f0 : Front side silicon nitride layer

[0041] 106 f1 :First front side silicon nitride layer

[0042] 109: Interface

[0043] 112 b0 : Back side SiN:OX layer

[0044] 120: Predetermined deviation angle

[0045] 200A: Zero layer structure

[0046] 200B: First layer structure

[0047] 200C:SWM structure

[0048] 200D: Manufacturing Process

[0049] 202A: First semiconductor device

[0050] 202B: Second semiconductor device

[0051] 202C: Carrier

[0052] 202M: Multilayer Interconnection Structure

[0053] 204:Through Silicon Via

[0054] 206A: Copper bump

[0055] 206B: Copper bump

[0056] 208:Semiconductor wafer

[0057] 210: Bottom filling material

[0058] 214A: Silicon oxide layer

[0059] 214B: Silicon oxide and silicon nitride

[0060] 215: passivation layer

[0061] 216: SWM structure

[0062] 216A: First SWM structure

[0063] 216B: Second SWM structure

[0064] 217: Contact bump

[0065] 218A: First chip

[0066] 218B: Second chip

[0067] 222: Cutting frame

[0068] 300A: Zero layer structure

[0069] 300B: First layer structure

[0070] 300C: Intermediate SWM structure

[0071] 300D:SWM structure

[0072] 300E: Manufacturing Process

[0073] 400A: Zero layer structure

[0074] 400B: Intermediate SWM structure

[0075] 400C: First layer structure

[0076] 400D: SWM structure

[0077] 400E: Manufacturing Process

[0078] 500A: Zero layer structure

[0079] 500B: Modified zero-layer structure

[0080] 500C: First layer structure

[0081] 500D: Intermediate SWM structure

[0082] 500E:SWM structure

[0083] 500F: Manufacturing Process

[0084] 1000:EPC system

[0085] 1002:Hardware processor

[0086] 1004: Computer readable storage medium

[0087] 1006: Computer program code

[0088] 1008: Control Data

[0089] 1010: User interface

[0090] 1012:I / O interface

[0091] 1014: Network interface

[0092] 1016: Network

[0093] 1018: Bus

[0094] 1020: Manufacturing Equipment

[0095] 1100:Using the Manufacturing System

[0096] 1120: Design Company

[0097] 1122: IC Design Layout

[0098] 1130:Mask Company

[0099] 1132: Data Preparation

[0100] 1144:Mask Manufacturing

[0101] 1145: Mask

[0102] 1150:Manufacturer

[0103] 1152: Wafer Manufacturing

[0104] 1153:Semiconductor Wafer

[0105] 1155: IC Factory

[0106] 1157: Wafer Manufacturing

[0107] 1159: Wafer

[0108] 1160:IC device

[0109] 1180: Back-end production line

[0110] 1202: Wafer transport operations

[0111] 1204: Photolithography operation

[0112] 1206: Etching operation

[0113] 1208: Ion implantation operation

[0114] 1210: Cleaning / stripping operations

[0115] 1212: Chemical Mechanical Polishing Operation

[0116] 1214: Epitaxial growth operation

[0117] 1216: Deposition operation

[0118] 1218: Heat Treatment

[0119] 1220: Wafer Assembly

[0120] S102: Operation

[0121] S104: Operation

[0122] S106: Operation

[0123] S108: Operation

[0124] S110: Operation

[0125] S112: Operation

[0126] S114: Operation

[0127] S116: Operation

[0128] S118: Operation

[0129] S202: Operation

[0130] S204: Operation

[0131] S206: Operation

[0132] S208: Operation

[0133] S210: Operation

[0134] S212: Operation

[0135] S214: Operation

[0136] S216: Operation

[0137] S218: Operation

[0138] S302: Operation

[0139] S304: Operation

[0140] S306: Operation

[0141] S308: Operation

[0142] S310: Operation

[0143] S312: Operation

[0144] S314: Operation

[0145] S316: Operation

[0146] S318: Operation

[0147] S402: Operation

[0148] S404: Operation

[0149] S406: Operation

[0150] S408: Operation

[0151] S410: Operation

[0152] S412: Operation

[0153] S414: Operation

[0154] S416: Operation

[0155] S418: Operation

[0156] S420: Operation

[0157] S502: Operation

[0158] S504: Operation

[0159] S506: Operation

[0160] S508: Operation

[0161] S510: Operation

[0162] S512: Operation

[0163] S514: Operation

[0164] S516: Operation

[0165] S518: Operation

[0166] S520: Operation DETAILED DESCRIPTION

[0167] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and configurations will be described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, a first feature formed above or on a second feature in the subsequent description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not directly contactable. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0168] Additionally, to facilitate description of the relationship of one element or feature to another element or feature(s) as illustrated in the figures, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "top," "bottom," and the like, may be used herein. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0169] Figures 1A to 1C is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments. Figure 1A In the process, a semiconductor substrate 102 is prepared, and a front side pad oxide layer 104 is formed on the opposite side of the semiconductor substrate. f0 and the back side pad oxide layer 104 b0 The pad oxide layer is typically formed using a method selected from atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM), and / or one or more other suitable methods, and in some embodiments, will include a suitable material other than silicon dioxide. In some embodiments, the front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 With about In some embodiments, a pad oxide layer is formed using a thermal oxidation process to obtain a thickness of Oxide layer. Oxide layers larger than 100 nm tend to degrade dielectric properties and / or create undesirable thickness variations across the wafer. Oxide layers often increase processing time without a corresponding improvement in the properties of the resulting layer and / or cause problems during back-end processing.

[0170] Then, the corresponding front side pad oxide layer 104 f0and the back side pad oxide layer 104 b0 A front silicon nitride layer 106 is formed on the f0 and the back side silicon nitride layer 106 b0 In some embodiments, the silicon nitride layer has a thickness of about The silicon nitride layer is typically formed using a process selected from atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM) deposition, and / or one or more other suitable methods, and, in some embodiments, includes other suitable materials in addition to silicon nitride. Semiconductor substrate 102 and front side pad oxide layer 104 f0 , rear side pad oxide layer 104 b0 , front side silicon nitride layer 106 f0 and the back side silicon nitride layer 106 b0 The combination includes a zero layer structure 100A. In some embodiments, a silicon nitride layer is formed by a thermal nitridation process to obtain a thickness of In some embodiments, the relative thicknesses of the pad oxide layer and the silicon nitride layer are selected to provide an oxide:nitride thickness ratio of 1:9 to 1:10. Nitride layers with a thickness greater than 100 nm tend to degrade dielectric properties and / or produce undesirable thickness variations across the wafer. The relative thicknesses of the pad oxide and silicon nitride layers that result in oxide:nitride thickness ratios greater than 1:9 or less than 1:10 tend to have reduced dielectric and / or mechanical properties when compared to those combinations having relative thicknesses within the range of 1:9 and 1:10.

[0171] exist Figure 1B By adding a first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the zero layer structure 100A. In some embodiments, the first front side additional oxide layer 104 f1 With about The thickness of the back side silicon nitride layer 106 may be 100 mm, but in some embodiments, layers with other thicknesses are used. b1 To further modify the zero layer structure, the first back side silicon nitride layer 106 b1 A silicon nitride layer 106 is formed on the back side b0 without an intervening oxide layer having an interface 109, and providing a double nitride layer 106 on the back side of the first layer structure 100B b0 +106 b1 In some embodiments, the first front side silicon nitride layer 106 f1 and a first backside silicon nitride layer 106 b1 With about , although in some embodiments one or both of the first silicon nitride layers having other thicknesses are used. In some embodiments, the zero layer structure 100A is rotated to a predetermined offset angle 120 that is offset by θ degrees from the orientation used during formation of the underlying layer. In some embodiments, the offset angle is between 0° and 90°. In some embodiments, continuous deposition is performed at an offset angle of 15°, 30°, 45°, 60°, 75°, or 90°. In some embodiments, a specific device for rotating the substrate to produce a predetermined θ degree offset angle will have an inherent mechanical interference position that defines a prohibited rotation angle for the specific device. Using machine-specific messages, the range of acceptable values ​​for the predetermined θ degree offset angle for a process utilizing such a machine will be adjusted accordingly to exclude the prohibited angle. In some embodiments, a narrow range of values ​​on both sides of the prohibited angle will also be excluded to ensure proper operation of the machine.

[0172] exist Figure 1C By removing the first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1The first layer structure 100B is modified to form the SWM structure 100C. In some embodiments, the pad oxide layer and the silicon nitride layer are removed using a dry etching or plasma etching process. In some embodiments, plasma etching (PE) or reactive ion etching (RIE) of the substrate material is performed using a halogen-containing reactive gas excited by an electromagnetic field to dissociate into ions. The reactive gas or etchant gas includes, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2 or a combination thereof, but other semiconductor material etchant gases are also contemplated within the scope of the present disclosure. In some embodiments, wet etching is used to completely or partially remove at least one substrate material, wherein the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or a combination thereof to remove the target material.

[0173] Figure 1D is based on Figures 1A to 1CA flow chart of a portion of a manufacturing process 100D for producing a SWM structure of some embodiments of the structure of the present invention includes preparing a semiconductor substrate for deposition of a pad oxide during operation S102, forming a zero-layer pad oxide layer on the frontside (FS) and backside (BS) surfaces of the semiconductor substrate 102 during operation S104, and forming a zero-layer silicon nitride layer 102 on the FS and BS surfaces of the semiconductor substrate to complete the zero-layer structure 100A during operation S106. The zero-layer structure 100A is then further modified in operation S108, during which a first layer of additional oxide is formed on the FS of the zero-layer structure 100A, followed by an optional operation S110, during which the zero-layer structure 100A is rotated to an offset angle θ°, such as 45°, and an operation S112, during which a first layer of silicon nitride is deposited on the FS and BS of the zero-layer structure 100A to complete the first-layer structure 100B. In operation S114, the first silicon nitride layer and the first additional oxide layer are removed from the FS of the first layer structure 100B to complete an embodiment of the SWM structure 100C. The SWM structure 100C can then be used in multiple stacked wafers / wafers and wafers / wafers including systems of integrated chip (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

[0174] FIG. 2A to FIG. 2C is a cross-sectional view of a stress and warpage moderating structure (SWM) during a manufacturing flow according to some embodiments. Figure 2A In the process, a semiconductor substrate 102 is prepared, and a front side pad oxide layer 104 is formed on the opposite side of the semiconductor substrate. f0 and the back side pad oxide layer 104 b0 . Usually the above combination is used Figure 1A The pad oxide layer may be formed by one or more of the processes discussed above, and in some embodiments, may include materials other than silicon dioxide or other suitable materials. In some embodiments, the front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 With about A thickness of , however, in some embodiments, a pad oxide layer having other thicknesses may be used.

[0175] Then, the corresponding front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 A front silicon nitride layer 106 is formed on the f0 and the back side silicon nitride layer 106 b0 In some embodiments, the silicon nitride layer has a thickness of about The silicon nitride layer will typically be used in combination with the above Figure 1A The semiconductor substrate 102 and the front side pad oxide layer 104 are formed by one or more of the processes discussed above and, in some embodiments, will include other suitable materials besides silicon nitride. f0 , rear side pad oxide layer 104 b0 , front side silicon nitride layer 106 f0 and the back side silicon nitride layer 106 b0 The combination includes a zero-layer structure 200A.

[0176] exist Figure 2B By adding a first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the zero layer structure 200A. In some embodiments, the first front side additional oxide layer 104 f1 With about By adding the first backside silicon nitride layer 106 b1 To further modify the zero layer structure, the first back side silicon layer 106 b1 A silicon nitride layer 106 is formed on the back side b without an intermediate oxide layer having an interface 109, and providing a double nitride layer 106 on the back side of the first layer structure 100B b0 +106 b1 In some embodiments, the first front side silicon nitride layer 106 f1 and a first backside silicon nitride layer 106 b1 With about The thickness, for example However, in some embodiments, one or both of the first silicon nitride layers having other thicknesses may be used. In some embodiments, the zero layer structure 200A is rotated to a predetermined offset angle 120 that is offset by θ degrees from the orientation used during formation of the underlying layer. In some embodiments, the offset angle is between 0° and 90°. In some embodiments, sequential depositions are performed at an offset angle of 15°, 30°, 45°, 60°, 75°, or 90°.

[0177] exist Figure 2C By removing the first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the first layer structure 200B to form a SWM structure 200C. In some embodiments, the above reference Figure 1CThe dry etch, plasma etch and / or wet etch processes described in detail remove the additional oxide and silicon nitride layers.

[0178] Figure 2D is based on FIG. 2A to FIG. 2C Flowchart of a portion of a manufacturing process 200D for producing a SWM structure of some embodiments of the structure of the present invention, including operation S202, during which a semiconductor substrate is prepared for pad oxide deposition; operation S204, during which a zero-layer pad oxide layer is formed on the front side (FS) and back side (BS) surfaces of the semiconductor substrate 102, and during operation S206, a zero-layer silicon nitride layer 102 is formed on the FS and BS surfaces of the semiconductor substrate to complete the zero-layer structure 200A. The zero-layer structure 200A is then further modified in operation S208, during which a first layer of additional oxide is formed on the FS of the zero-layer structure 200A, followed by an optional operation S210, during which the zero-layer structure 200A is rotated to an offset angle of θ°, such as 45°; and operation S212, during which a thicker first layer of silicon nitride is deposited on the FS and BS of the zero-layer structure 200A to complete the first layer structure 200B. In operation S214, the first layer of silicon nitride and the first layer of additional oxide are removed from the FS of the first layer structure 200B to complete an embodiment of the SWM structure 200C. The SWM structure 200C can then be used in multiple stacked wafers / wafers and wafers / wafers including systems of integrated chip (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

[0179] FIG. 3A to FIG. 3D is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments. Figure 3A In the process, a semiconductor substrate 102 is prepared, and a front side pad oxide layer 104 is formed on the opposite side of the semiconductor substrate. f0 and the back side pad oxide layer 104 b0 . Usually the above combination is used Figure 1A The pad oxide layer may be formed by one or more of the processes discussed above, and in some embodiments, may include materials other than silicon dioxide or other suitable materials. In some embodiments, the front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 With about A thickness of , however, in some embodiments, a pad oxide layer having other thicknesses may be used.

[0180] Then, the corresponding front side pad oxide layer 104 f0and the back side pad oxide layer 104 b0 A front silicon nitride layer 106 is formed on the f0 and the back side silicon nitride layer 106 b0 In some embodiments, the silicon nitride layer has a thickness of about The silicon nitride layer will typically be used in conjunction with the above Figure 1A The semiconductor substrate 102 and the front side pad oxide layer 104 are formed by one or more of the processes discussed above, and in some embodiments, will include other suitable materials in addition to silicon nitride. f0 , rear side pad oxide layer 104 b0 , front side silicon nitride layer 106 f0 and the back side silicon nitride layer 106 b0 The combination includes a zero layer structure 300A.

[0181] exist Figure 3B By adding a first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the zero layer structure 300A. In some embodiments, the first front side additional oxide layer 104 f1 With about By adding the first back side additional oxide layer 104 b1 and a backside silicon nitride layer 106 formed on the backside of the first layer structure 300B b0 The first back side silicon nitride layer 106 b1 To further modify the zero layer structure. In some embodiments, the first back side additional oxide layer 104 b1 With about In some embodiments, the first front side silicon nitride layer 106 may have a thickness of 100,0 ... f1 and a first backside silicon nitride layer 106 b1 With about The thickness, for example However, in some embodiments, one or both of the first silicon nitride layers having other thicknesses may be used. In some embodiments, the zero layer structure 300A is rotated to a predetermined offset angle 120 that is offset by θ degrees from the orientation used during formation of the underlying layer. In some embodiments, the offset angle is between 0° and 90°. In some embodiments, sequential deposition is performed at an offset angle of 15°, 30°, 45°, 60°, 75°, or 90°.

[0182] exist Figure 3C By removing the first front side additional oxide layer 104f1 and the first front side silicon nitride layer 106 f1 To modify the first layer structure 300B to form the intermediate SWM structure 300C. In some embodiments, the above reference Figure 1C The additional oxide and silicon nitride layers are removed by dry etching, plasma etching and / or wet etching processes as described in detail.

[0183] exist Figure 3D In the middle SWM structure 300C, an additional N-1 (“N is a positive integer”) front-side additional oxide layer 104 is repeatedly formed. fN-1 , rear side additional oxide layer 104 bN-1 , front side silicon nitride layer 106 fN-1 and the back side silicon nitride layer 106 bN-1 To modify, as mentioned above Figure 3B Detailed description. Then, after the additional deposition, the additional N-1 front side additional oxide layers 104 are removed. fN-1 and the front side silicon nitride layer 106 fN-1 to form a SWM structure 300D, wherein the back side of the SWM structure 300D includes an N-layer back side additional oxide layer 104 bN and N-layer rear side silicon nitride layer 106 bN In some embodiments, the above-referenced Figure 1C The additional oxide and silicon nitride layers are removed by dry etching, plasma etching and / or wet etching processes as described in detail.

[0184] Figure 3E is based on FIG. 3A to FIG. 3DA flow chart of a portion of a manufacturing process 300E for producing a SWM structure of some embodiments of the structure of the present invention includes operation S302, during which a semiconductor substrate is prepared for pad oxide deposition, a zero-layer pad oxide layer is formed on the front side (FS) and back side (BS) surfaces of the semiconductor substrate 102 during operation S304, and a zero-layer silicon nitride layer 102 is formed on the FS and BS surfaces of the semiconductor substrate to complete the zero-layer structure 300A during operation S306. The zero-layer structure 300A then enters optional operation S308, during which the zero-layer structure 300A is rotated to an offset angle of θ°, such as 45°, and during operation S310, a first layer of additional oxide is formed on the FS of the zero-layer structure 300A, and during operation S312, a thicker first layer of silicon nitride is deposited on the FS and BS of the zero-layer structure 200A to complete the first layer structure 200B. In operation S214, the first layer of silicon nitride and the first layer of additional oxide are removed from the FS of the first layer structure 200B to complete an embodiment of the SWM structure 200C. The SWM structure 200C can then be used in multiple stacked wafers / wafers and wafers / wafers including systems of integrated chip (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

[0185] FIG. 4A to FIG. 4D is a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments. Figure 4A In the embodiment, a semiconductor substrate 102 is prepared, and a front side pad oxide layer 104 is formed on the opposite side of the semiconductor substrate. f0 and the back side pad oxide layer 104 b0 . Usually the above combination is used Figure 1A The pad oxide layer may be formed by one or more of the processes discussed above, and in some embodiments, will include a suitable material other than silicon dioxide. In some embodiments, the front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 With about A thickness of , however, in some embodiments, a pad oxide layer having other thicknesses may be used.

[0186] Then, the corresponding front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 A front silicon nitride layer 106 is formed on the f0 and the back side silicon nitride layer 106 b0 In some embodiments, the silicon nitride layer has a thickness of about The silicon nitride layer will typically be formed using the above combined Figure 1A The semiconductor substrate 102 and the front side pad oxide layer 104 are formed by one or more of the processes discussed above, and in some embodiments, will include other suitable materials in addition to silicon nitride. f0 , rear side pad oxide layer 104 b0 , front side silicon nitride layer 106 f0 and the back side silicon nitride layer 106 b0 The combination includes a zero layer structure 400A.

[0187] exist Figure 4B By implanting oxygen into the back side silicon nitride layer 106 b0 The zero layer structure 400A is modified to obtain a SiON composition (or SiN:OX) to form a rear side SiN:OX layer 112 b0 Instead of the initially formed backside silicon nitride layer 106 b0 To form the intermediate SWM structure 400B. In some embodiments, the backside SiN:OX layer 112 b0 will have a thickness similar to that of the initial deposition The thickness of the layer may be as described above, however in some embodiments, layers having other thicknesses may be used.

[0188] exist Figure 4C Then by adding a first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the intermediate SWM structure 400B to form a first layer structure 400C. In some embodiments, the first front side additional oxide layer 104 f1 With about The thickness, for example However, in some embodiments, layers having other thicknesses may be used. By adding a backside SiN:OX layer 112 formed on the backside of the intermediate SWM structure 400B b0 The first back side silicon nitride layer 106 b1 To further modify the intermediate SWM structure 400B. In some embodiments, the first front side silicon nitride layer 106 f1 and a first backside silicon nitride layer 106 b1 With about The thickness, for example However, in some embodiments, one or both of the first silicon nitride layers having other thicknesses may be used. In some embodiments, the intermediate SWM structure 400B is rotated to a predetermined offset angle that is offset by θ degrees from the orientation used during the formation of the underlying layer between the formation of the successive layers. In some embodiments, the offset angle is between 0° and 90°. In some embodiments, the successive depositions are performed at an offset angle of 15°, 30°, 45°, 60°, 75°, or 90°.

[0189] exist Figure 4D By removing the first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the first layer structure 400C to form a SWM structure 400D. In some embodiments, the above reference Figure 1C The additional oxide and silicon nitride layers are removed by dry etching, plasma etching and / or wet etching processes as described in detail.

[0190] Figure 4E is based on Figure 4A Figure 4D Flowchart of a portion of a manufacturing process 400E for producing a SWM structure of some embodiments of the structure of the present invention, including operation S402, during which a semiconductor substrate is prepared for pad oxide deposition; operation S404, during which a zero-layer pad oxide layer is formed on the front side (FS) and back side (BS) surfaces of the semiconductor substrate 102; and operation S406, during which a zero-layer silicon nitride layer is formed on the FS and BS surfaces of the semiconductor substrate 102 to complete the zero-layer structure 400A. In operation S408, the BS silicon nitride layer of the zero-layer structure 400A is implanted with oxygen to convert the initially deposited silicon nitride into SiN:OX material. In operation S410, a first layer of additional oxide is formed on the FS of the intermediate SWM structure 400B, and then enters optional operation S412 and operation S414, during which the intermediate SWM structure 400B is rotated to an offset angle of θ°, such as 45°, and during which a first silicon nitride layer is formed on the FS and BS of the intermediate SWM structure 400B. In operation S416, the first layer of silicon nitride and the first layer of additional oxide are removed from the FS of the first layer structure 400C to complete an embodiment of the SWM structure 400D. The SWM structure 400D is then ready for use as a multi-stacked wafer / wafer and wafer / wafer including systems of integrated chip (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

[0191] FIG. 5A to FIG. 5Eis a cross-sectional view of a stress and warpage modulating structure (SWM structure) during a manufacturing process according to some embodiments. Figure 5A In the process, a semiconductor substrate 102 is prepared, and a front side pad oxide layer 104 is formed on the opposite side of the semiconductor substrate. f0 and the back side pad oxide layer 104 b0 . Usually the above combination is used Figure 1A The pad oxide layer may be formed by one or more of the processes discussed above, and in some embodiments, may include materials other than silicon dioxide or other suitable materials. In some embodiments, the front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 With about A thickness of , however, in some embodiments, a pad oxide layer having other thicknesses may be used.

[0192] Then, the corresponding front side pad oxide layer 104 f0 and the back side pad oxide layer 104 b0 A front silicon nitride layer 106 is formed on the f0 and the back side silicon nitride layer 106 b0 In some embodiments, the silicon nitride layer has a thickness of about The silicon nitride layer will typically be formed using the above combined Figure 1A The semiconductor substrate 102 and the front side pad oxide layer 104 are formed by one or more of the processes discussed above, and in some embodiments, will include other suitable materials in addition to silicon nitride. f0 , rear side pad oxide layer 104 b0 , front side silicon nitride layer 106 f0 and the back side silicon nitride layer 106 b0 The combination includes a zero layer structure 500A.

[0193] exist Figure 5B By implanting oxygen into the back side silicon nitride layer 106 b0 The zero layer structure 500A is modified to obtain a SiON composition (or SiN:OX) to form a rear side SiN:OX layer 112 b0 Instead of the initially formed backside silicon nitride layer 106 b0 To form a modified zero layer structure 500B. In some embodiments, the backside SiN:OX layer 112 b0 will have a thickness similar to that of the initial deposition The thickness of the layer may be as described above, however in some embodiments, layers having other thicknesses may be used.

[0194] exist Figure 5CThen, by adding a first front side additional oxide layer 104 f1 , first back side additional oxide layer 104 b1 and the first front side silicon nitride layer 106 f1 The modified zero layer structure 500B is formed into a first layer structure 500C. In some embodiments, the first front side additional oxide layer 104 f1 With about The thickness, for example However, in some embodiments, layers with other thicknesses may be used. By adding a first backside additional oxide layer 104 formed on the backside of the intermediate SWM structure 500B b1 The first back side silicon nitride layer 106 b1 To further modify the intermediate SWM structure 500B to obtain the first layer structure 500C. In some embodiments, the first front side silicon nitride layer 106 f1 and a first backside silicon nitride layer 106 b1 With about The thickness, for example However, in some embodiments, one or both of the first silicon nitride layers having other thicknesses may be used. In some embodiments, the intermediate SWM structure 500B is rotated to a predetermined offset angle that is offset by θ degrees from the orientation used during the formation of the underlying layer between the formation of the successive layers. In some embodiments, the offset angle is between 0° and 90°. In some embodiments, the successive depositions are performed at an offset angle of 15°, 30°, 45°, 60°, 75°, or 90°.

[0195] exist Figure 5D By removing the first front side additional oxide layer 104 f1 and the first front side silicon nitride layer 106 f1 To modify the first layer structure 500C to form an intermediate SWM structure 500D. In some embodiments, the above reference Figure 1C The additional oxide and silicon nitride layers are removed by dry etching, plasma etching and / or wet etching processes as described in detail.

[0196] exist Figure 5E In the embodiment, by repeatedly forming additional N-1 front side additional oxide layers 104 fN-1 , rear side additional oxide layer 104 bN-1 , front side silicon nitride layer 106 fN-1 and the back side silicon nitride layer 106 bN-1 To further modify the intermediate SWM structure 500D as referenced above Figure 5D Then, after the additional deposition, the additional N-1 front side additional oxide layers 104 are removed. fN-1 and the front side silicon nitride layer 106fN-1 to form a SWM structure 500E, wherein the back side of the SWM structure 500E includes an N-layer back side additional oxide layer 104 bN and the back side silicon nitride layer 106 bN In some embodiments, the back side additional oxide layer 104 bN and the back side silicon nitride layer 106 bN The thickness of the alternating layers is constant, while in other embodiments, the rear side additional oxide layer 104 bN and the back side silicon nitride layer 106 bN One or both of the alternating layers have varying thicknesses, for example, the thickness of the back side silicon nitride layer increases from the first back side silicon nitride layer 106 to the thickness of the back side silicon nitride layer 106. b1 Added to the first rear side 106 bN In some embodiments, the silicon nitride layer is used as described above. Figure 5D The additional oxide and silicon nitride layers are removed by dry etching, plasma etching and / or wet etching processes as described in detail.

[0197] Fig. 5F According to the figure FIG. 5A to FIG. 5EFlowchart of a portion of a manufacturing process 500F for producing a SWM structure of some embodiments of the structure of the present invention, including operation S502, during which a semiconductor substrate is prepared for pad oxide deposition; operation S504, during which a zero-layer pad oxide layer is formed on the front side (FS) and back side (BS) surfaces of the semiconductor substrate 102; and operation S506, during which a zero-layer silicon nitride layer is formed on the FS and BS surfaces of the semiconductor substrate 102 to complete the zero-layer structure 500A. In operation S508, the BS silicon nitride layer of the zero-layer structure 500A is implanted with oxygen to convert the initially deposited silicon nitride into SiN:OX material and form a modified zero-layer structure 500B. In optional operation S510, the modified zero-layer structure 500B is rotated to an offset angle of θ°, such as 45°, and then a first layer of additional oxide is formed on the FS of the intermediate SWM structure 500B in operation S512. In operation S514, a first silicon nitride layer is formed on the FS and BS of the modified zero layer structure 500B to form a first layer structure 500C. In operation S516, the first layer of silicon nitride and the first layer of additional oxide are removed from the FS of the first layer structure 500C to form an intermediate SWM structure 500D. Then, the intermediate SWM structure 500D is further modified by repeatedly applying operations S512 to S516 (and optionally, operation S510) to form a series of alternating layers of silicon oxide and silicon nitride on the back side of the intermediate SWM structure 500D. After forming a predetermined number (N-1) of additional alternating layers, the SWM structure 500E is completed and can be used for multi-layer stacked wafer / wafer and wafer / wafer packaging assemblies, including systems of integrated chip (SOIC) and chip on wafer on substrate (CoWoS) packaging configurations.

[0198] The performance of the SWM structure within a multi-layer stacked die / wafer and wafer / wafer package assembly is a function of the specific SWM structure configuration, including, for example, the thickness of the semiconductor substrate, the thickness and amount of silicon dioxide layers remaining on the front and back sides of the semiconductor substrate, the thickness and amount of silicon nitride layers remaining on the front and back sides of the semiconductor substrate. Other factors will include the configuration of the layers present, the angle offset used between adjacent deposited layers, the presence of one or more modified deposited layers (e.g., SiN:OX layers), and the methods and materials used to attach the SWM structure to the structure within the multi-layer stacked die / wafer or wafer / wafer package assembly. When properly utilized, some embodiments of the SWM structure will improve the uniformity of the deposited layers and avoid stress cracking, which provides access to underlying layers and impairs the etching process.

[0199] 6A to 6His a cross-sectional view of a multi-stacked wafer / wafer-level package incorporating a SWM structure during a manufacturing flow, according to some embodiments. Fig. 6A is a cross-sectional view of the first semiconductor device 202A after adding an interposer and forming through silicon vias 204 (TSVs). Figure 6B is a cross-sectional view reflecting the results of subsequent operations during which a μ-bump structure (eg, copper bump 206A) has been formed on the front side of the first semiconductor device 202A. Figure 6C 2 is a cross-sectional view of an assembly including a second semiconductor device 202B, the second semiconductor device 202B including one or more semiconductor wafers 208 and a corresponding plurality of copper bumps 206B, in some embodiments, the copper bumps 206B are inverted and mounted from frontside to frontside to the first semiconductor device 202A using a die-to-wafer (D2W) bonding process, in some embodiments. In some embodiments, an underfill material 210 is used to fill spaces between components or elements configured as the second semiconductor device 202B, such as Figure 6C shown.

[0200] In some embodiments, Fig. 6E As shown, the assembly including the first semiconductor device 202A and the second semiconductor device 202B is inverted, and the carrier 202C is mounted on the rear side of the second semiconductor device. Fig. 6F As shown, a portion of the back side of the first semiconductor device 202A is removed to thin the assembly and expose the lower surface of the TSV (relative to the first semiconductor device). Fig. 6F and Figure 6G In some of the embodiments shown, a portion of the back side of the semiconductor wafer 208 is removed and replaced with, for example, a silicon oxide layer 214A or a combination of silicon oxide and silicon nitride 214B. Figure 6H As shown, in some embodiments, a stress and warpage mitigation (SWM) structure 216 is then mounted on the backside of the first semiconductor device 202A to reduce deleterious effects associated with stress, strain, and warpage on the performance and / or lifetime of the resulting multi-stack package.

[0201] 7A to 7D is a cross-sectional view of an embodiment of a multi-stacked wafer / wafer-level package incorporating a SWM structure. Fig. 7A The embodiment of the multi-stack wafer / wafer level package is configured to incorporate the SWM structure 216 by mounting the SWM structure on the backside carrier 202C. Fig. 7A The embodiment of the multi-stack wafer / wafer level package is configured to incorporate the SWM structure 216 by mounting the SWM structure on the backside carrier 202C. Figure 7BAn embodiment of a multi-stack wafer / wafer level package is configured to incorporate a SWM structure 216 by mounting the SWM structure 216 on the backside surface of a first wafer 218A and mounting the SWM structure 216 on the backside surface of a second wafer in a multi-stack configuration. Figure 7C Embodiments of the multi-stack wafer / wafer level package are configured to incorporate the SWM structure 216 by mounting the SWM structure 216 on a backside surface of the first semiconductor device 202A opposite to the included carrier. Fig.7D Embodiments of the multi-stack wafer / wafer level package are configured to incorporate a SWM structure 216 by mounting a first SWM structure 216A on a backside surface of the first semiconductor device 202A opposite to an included carrier and mounting a second SWM structure 216B on the carrier 202C.

[0202] FIG. 8A to FIG. 8H is a cross-sectional view of a multi-stacked wafer / wafer-level package incorporating a SWM structure during a manufacturing flow, according to some embodiments. Fig. 8A is a cross-sectional view of the first semiconductor device 202A after adding an interposer and forming a through silicon via (TSV) 204 . Figure 8B is a cross-sectional view reflecting the result of a subsequent operation during which a μ-bump structure, such as a copper bump 206A, has been formed on the front side of the first semiconductor device 202A. Figure 8C 2 is a cross-sectional view of an assembly including a second semiconductor device 202B, the second semiconductor device 202B including one or more semiconductor wafers 208 and a corresponding plurality of copper bumps 206B, which in some embodiments are inverted and mounted from frontside-to-frontside to the first semiconductor device 202A using a die-to-wafer (D2W) bonding process. In some embodiments, an underfill material 210 is used to fill spaces between assemblies or components including a semiconductor wafer 208 configured as the second semiconductor device 202B, such as Fig.8D shown.

[0203] In some embodiments, Fig. 8E As shown, the assembly including the first semiconductor device 202A and the second semiconductor device 202B is inverted, and the carrier 202C is mounted on the rear side of the second semiconductor device. Fig.8F As shown, a portion of the back side of the first semiconductor device 202A is removed to thin the assembly and expose the lower surface of the TSV (relative to the first semiconductor device). Fig.8FIn some of the illustrated embodiments, a backside portion of the semiconductor wafer 208 is removed and replaced with, for example, a silicon oxide layer 214A or a combination of silicon oxide and silicon nitride 214B (not shown) that provides a local SWM structure. Figure 8G As shown, in some embodiments, a passivation layer 215 is added to the back side of the first semiconductor device 202A and then patterned and etched so that contact bumps 217 can be formed on the TSVs 214. Figure 8H As shown, in some embodiments, the carrier 202C is removed and the composite package is counted on a dicing frame 222. Then, a stress and warpage mitigation (SWM) structure 216 is mounted on the back side of the first semiconductor device 202A to reduce deleterious effects associated with stress, strain, and warpage on the performance and / or life of the resulting multi-stack package.

[0204] Fig. 9 is a cross-sectional view of multiple stacked wafers / dies of a system of integrated chip (SOIC) package during a manufacturing flow incorporating a SWM structure according to some embodiments. Fig. 9 The composite multi-stack package includes a first semiconductor device 202A, a multi-layer interconnect structure 202M, a second semiconductor device 202B, the multi-layer interconnect structure 202M including a series of metal patterns separated by an interlayer dielectric layer (not shown) and a through hole 219 added to the first semiconductor device during back-end of line (BEOF) processing, a carrier 202C and a SWM structure 216 mounted on the back side of the carrier, the SWM structure 216 will reduce the mechanical and thermal stress experienced by the active components and improve the performance and / or life of the multi-stack assembly. In some embodiments, the through hole 219 extending through the carrier 202C and the second semiconductor device 202B provides an electrical connection between the front side and the back side circuits.

[0205] Fig.10 is a block diagram of an electronic process control (EPC) system 1000 according to some embodiments. Methods for generating cell layouts corresponding to some embodiments of the FET element structures detailed above, particularly with respect to the addition and placement of electrical contacts, thermal contacts, active metal patterns, dummy metal patterns, and other heat dissipation structures, may be implemented using the EPC system 1000, for example, according to some embodiments of such a system.

[0206] In some embodiments, the EPC system 1000 is a general-purpose computing device, including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. The computer-readable storage medium 1004 is encoded with, i.e., stores, computer program code (or instructions) 1006 (i.e., a set of executable instructions). The execution of the computer program code 1006 by the hardware processor 1002 (at least in part) represents an EPC tool, such as a part or all of one or more of the methods described herein (hereinafter referred to as processes and / or methods).

[0207] The hardware processor 1002 is electrically coupled to the computer readable storage medium 1004 via a bus 1018. The hardware processor 1002 is also electrically coupled to the I / O interface 1012 via the bus 1018. The network interface 1014 is also electrically connected to the hardware processor 1002 via the bus 1018. The network interface 1014 is connected to the network 1016, so that the hardware processor 1002 and the computer readable storage medium 1004 can be connected to external elements via the network 1016. The hardware processor 1002 is configured to execute the computer program code 1006 encoded in the computer readable storage medium 1004 so that the EPC system 1000 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the hardware processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or an appropriate processing unit.

[0208] In one or more embodiments, the computer readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk drive, random access memory (RAM), read only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer readable storage medium 1004 includes compact disk read only memory (CD ROM), compact disk read / write (CD R / W), and / or digital video disc (DVD).

[0209] In one or more embodiments, the computer readable storage medium 1004 stores computer program code 1006 configured to enable the EPC system 1000 (where such execution represents (at least in part) an EPC tool) to perform a portion or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 1004 also stores information that facilitates the execution of a portion or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 1004 stores process control data 1008, which in some embodiments includes control algorithms, process variables and constants, target ranges, set points, process control data, and program code for enabling statistical process control (SPC) and / or model based predictive control (MPC) control of various processes.

[0210] The EPC system 1000 includes an I / O interface 1012. The I / O interface 1012 is coupled to external circuits. In one or more embodiments, the I / O interface 1012 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and instructions to the hardware processor 1002.

[0211] The EPC system 1000 also includes a network interface 1014 coupled to the hardware processor 1002. The network interface 1014 allows the EPC system 1000 to communicate with a network 1016 to which one or more other computer systems are connected. The network interface 1014 includes wireless network interfaces such as Bluetooth, WiFi, WIMAX, GPRS, WCDMA, etc.; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more EPC systems 1000.

[0212] The EPC system 1000 is configured to send and receive messages to and from manufacturing equipment 1020, which includes one or more of an ion implantation tool, an etching tool, a deposition tool, a coating tool, a rinsing tool, a cleaning tool, a chemical-mechanical planarizing (CMP) tool, a testing tool, an inspection tool, a transport system tool, and a thermal processing tool, which will perform a series of predetermined manufacturing operations to produce the desired integrated circuit components. The information includes one or more of operational data, parameter data, test data, and functional data used to control, monitor, and / or evaluate the execution, progress, and / or completion of a particular manufacturing process. The processing tool information is stored in and / or retrieved from the computer-readable storage medium 1004.

[0213] The EPC system 1000 is configured to receive messages through the I / O interface 1012. The information received through the I / O interface 1012 includes one or more of instructions, data, program data, design rules that specify, for example, layer thickness, spacing distances, structure and layer resistivity and feature size, process performance history, target ranges, set points, and / or other parameters processed by the hardware processor 1002. This information is transmitted to the hardware processor 1002 via the bus 1018. The EPC system 1000 is configured to receive information related to a user interface (UI) through the I / O interface 1012. This information is stored in the computer readable medium 1004 as a user interface (UI) 1010.

[0214] In some embodiments, part or all of the processes and / or methods mentioned are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EPC tool. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a software application used by the EPC system 1000.

[0215] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical disks (e.g., DVDs), one or more of magnetic disks such as hard disks, semiconductor memories (e.g., ROM, RAM), memory cards, etc.

[0216] Fig.11 1 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing flow associated therewith for manufacturing an IC device incorporating improved control of SSD and EPI configuration profiles according to some embodiments. In some embodiments, the manufacturing system 1100 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit based on a layout diagram.

[0217] exist Fig.11 , the IC manufacturing system 1100 includes entities such as a design company 1120, a mask company 1130, and an IC manufacturer / fabricator ("IC Fab") 1150 that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1160. Once the manufacturing process of forming multiple IC components on a wafer is completed, the wafer is optionally sent to a back-end or back-end production line (BEOL) 1180 for programming, electrical testing, and packaging according to the sequence of the device to obtain the final IC device product. The entities in the manufacturing system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network, the Internet, etc.

[0218] The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design company 1120, the mask company 1130, and the IC Fab 1150 are owned by a larger company. In some embodiments, two or more design companies 1120, the mask company 1130, and the IC Fab 1150 coexist in a common facility and use common resources.

[0219] The design company (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for the IC device 1160. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that constitute the various parts of the IC device 1160 to be manufactured. The layers are combined to form various IC functions.

[0220] For example, a portion of the IC design layout diagram 1122 includes various material layers to be disposed on a semiconductor substrate (e.g., a silicon wafer) and on the semiconductor substrate. The design company 1120 implements an appropriate design process to form the IC design layout diagram 1122. The design process includes one or more of a logic design, a physical design, or a layout and wiring. The IC design layout diagram 1122 is presented in one or more data files having geometric pattern information. For example, the IC design layout diagram 1122 will be expressed in a GDSII file format or a DFII file format in some operations.

[0221] Although the pattern of the modified IC design layout drawing is adjusted by appropriate methods so as to, for example, reduce the parasitic capacitance of the integrated circuit compared to the unmodified IC design layout drawing, the modified IC design layout drawing reflects the following results: the position of the wires in the layout drawing is changed, and in some embodiments, features related to the capacitor isolation structure are inserted into the IC design layout drawing to further reduce the parasitic capacitance compared to the IC structure with the modified IC design layout drawing. Features that are not used to form the capacitor isolation structure located therein.

[0222] The mask company 1130 includes mask data preparation 1132 and mask manufacturing 1144. The mask company 1130 uses the IC design layout drawing 1122 to manufacture one or more masks 1145, which are used to manufacture various layers of the IC device 1160 according to the IC design layout drawing 1122. The mask company 1130 performs mask data preparation 1132, wherein the IC design layout drawing 1122 is converted into a representative data file ("RDF"). The mask data preparation 1132 provides the RDF to the mask manufacturing 1144. The mask manufacturing device 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate such as a mask (mask plate) 1145 or a semiconductor wafer 1153. The IC design layout drawing 1122 is manipulated by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC factory 1150. In Fig.11 , mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 are collectively referred to as mask data preparation.

[0223] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those known to be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0224] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks an IC design layout 1122 that has undergone processing in OPC using a set of mask creation rules that contain certain geometry and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the constraints during mask fabrication 1144, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0225] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the process to be performed by IC manufacturing plant 1150 to manufacture IC element 1160. LPC simulates this process based on IC design layout 1122 to establish a simulated manufactured device, such as IC device 1160. In some embodiments, the process parameters in the LPC simulation will include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus ("depth of focus, DOF"), mask error enhancement factor ("mask error enhancement factor, MEEF"), other appropriate factors, etc. or combinations thereof. In some embodiments, after creating a simulated manufactured device through LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0226] It should be understood that the above description of mask data preparation 1132 has been simplified for the purpose of clarity. In some embodiments, mask data preparation 1132 includes additional features such as logic operations (LOPs) to modify IC design layout diagram 1122 according to manufacturing rules. In addition, the processing applied to IC design layout diagram 1122 during mask data preparation 1132 can be performed in a variety of different orders.

[0227] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 are manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more photolithography exposures based on the IC design layout 1122. In some embodiments, based on the modified IC design layout 1122, a pattern is formed on a mask (photomask or mask plate) 1145 using an electron beam (e-beam) or a multi-electron beam mechanism. The mask 1145 will be formed using a process selected from a variety of available technologies. In some embodiments, the mask 1145 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and passes through the transparent area. In one example, a binary mask version of mask 1145 includes a transparent substrate (eg, fused silica) and an opaque material (eg, chrome) coated in the opaque regions of the binary mask.

[0228] In another example, a phase shift technique is used to form the mask 1145. In a phase shift mask (PSM) version of the mask 1145, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask will be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 1144 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1153, in an etching process to form various etching regions in the semiconductor wafer 1153, and / or in other suitable processes.

[0229] IC factory 1150 includes wafer manufacturing 1152. IC Fab 1150 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 1150 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front end of line (FEOL) manufacturing), while a second manufacturing facility can provide back-end manufacturing products for interconnection and packaging of ICs (backend (backend of line, BEOL) manufacturing), and a third manufacturing facility can provide other services for the foundry business.

[0230] Wafer fabrication 1152 includes forming a patterned layer of mask material formed on a semiconductor substrate, the mask material layer being made of a mask material comprising one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4, SiON, SiC, SiOC), or a combination thereof. In some embodiments, mask 1145 comprises a single layer of mask material. In some embodiments, mask 1145 comprises multiple layers of mask material.

[0231] In some embodiments, IC factory 1155 includes wafer fabrication 1157. IC Fab 1155 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 1155 is a manufacturing facility that provides back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products to add one or more metallization layers to wafer 1159, and a third manufacturing facility (not shown) may provide other services for the foundry business, such as packaging and labeling.

[0232] In some embodiments, the mask material is patterned by exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a lamp that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (ultraviolet, visible and / or infrared) light.

[0233] In some embodiments, the etching process includes placing the exposed structure in the functional area in an oxygen-containing atmosphere to oxidize the exterior of the exposed structure, followed by a chemical trimming process, such as plasma etching or liquid chemical etching, as described above, to remove the oxidized material and leave the modified structure. In some embodiments, the oxidation is followed by chemical trimming to provide greater size selectivity for the exposed material and reduce the possibility of accidental material removal during the manufacturing process. In some embodiments, the exposed structure may include a fin structure of a Fin Field Effect Transistor (FinFET), wherein the fin is embedded in a dielectric support medium covering the sides of the fin. In some embodiments, the exposed portion of the fin of the functional area is the top and sides of the fin located above the top of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level below the top surface of the fin, but still covers the lower portion of the side of the fin.

[0234] After the mask patterning operation, the areas not covered by the mask are etched to modify the dimensions of one or more structures within the exposed areas. In some embodiments, the etching is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etching solution, according to some embodiments. The chemical composition of the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), sulfuric acid (H2SO4), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), ethylenediaminepyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or a combination thereof.

[0235] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of substrate materials is performed using a halogen-containing reactive gas that is dissociated into ions by electromagnetic field excitation. Reactive gases or etchant gases include, for example, CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2 or a combination thereof, but other semiconductor material etchant gases are also contemplated within the scope of the present disclosure. According to plasma etching methods known in the art, ions are accelerated to impact exposed materials by an alternating electromagnetic field or by a fixed bias.

[0236] In some embodiments, molecular-level processing techniques, sharing the self-limiting surface reaction properties used in ALD, include Molecular Layer Deposition (MLD) and Self-Assembled Monolayer (SAM). MLD utilizes a continuous precursor surface reaction in which a precursor is introduced into a reaction zone above the wafer surface. The precursor adsorbs to the wafer surface and is limited by physical adsorption. The precursor then undergoes a rapid chemical adsorption reaction with many active surface sites, resulting in the self-limiting formation of molecular attachments in specific components or regularly repeating structures. These MLD structures will be successfully formed using lower process temperatures than some traditional deposition techniques.

[0237] SAM is a deposition technique that involves the spontaneous adhesion of organized organic structures on the surface of a wafer. This adhesion involves the adsorption of organic structures from a gas phase or a liquid phase using relatively weak interactions with the wafer surface. Initially, the structure is physically adsorbed on the surface by, for example, van der Waals forces or polar interactions. The self-assembled monolayer will then be confined to the surface by a chemical adsorption process. In some embodiments, the ability of SAM to grow layers as thin as a single molecule through chemical adsorption-driven interactions with the wafer surface will be particularly useful for forming thin films, including, for example, "near-zero thickness" activation or barrier layers. SAM is also particularly useful for area selective deposition (ASD) (or specific area deposition), which uses molecules that exhibit preferential reactions with specific portions of the wafer surface below to promote or hinder subsequent material growth in the destination area. In some embodiments, SAM is used to form a base or blueprint area for subsequent area selective ALD (AS-ALD) or area selective CVD (AS-CVD).

[0238] ALD, MLD and SAM processes represent viable options for fabricating thin layers (in some embodiments, layers fabricated are only a few atoms thick) that exhibit sufficient uniformity, conformality and / or purity for intended IC device applications. By individually and sequentially delivering the components of the material system being fabricated to a processing environment, these processes and precise control of the resulting surface chemistry allow for fine control over processing parameters and the target composition and properties of the resulting thin films.

[0239] Fig.12 12 is a schematic diagram of various process departments defined within a fab / front end / foundry for manufacturing IC devices according to some embodiments. The process departments used in front end of line (FEOL) and back end of line (BEOL) IC device manufacturing typically include a wafer transport operation 1202 for moving wafers between the various process departments. In some embodiments, the wafer transport operation will be associated with the wafer transport operation according to Fig.10The integration of an Electronic Process Control (EPC) system is used to provide process control operations to ensure that wafers are processed in a timely manner and delivered to the appropriate processing departments in the process flow sequence. In some embodiments, the EPC system will also provide control and / or quality assurance and parameter data for the correct operation of defined processing equipment. Interconnected by the wafer transport operation 1202 will be various processing departments providing, for example, a lithography operation 1204, an etching operation 1206, an ion implantation operation 1208, a cleaning / stripping operation 1210, a Chemical Mechanical Polishing (CMP) operation 1212, an epitaxial growth operation 1214, a deposition operation 1216, and a heat treatment 1218; and, in some embodiments, wafer assembly 1220, during which two or more substrates are joined to form a final device substrate structure.

[0240] In some embodiments, the stress adjustment device includes a semiconductor substrate, a first insulating layer formed above the first side of the semiconductor substrate, a second insulating layer formed above the first insulating layer, a third insulating layer formed above the second side of the semiconductor substrate, a fourth insulating layer formed above the third insulating layer, and a fifth insulating layer formed above the fourth insulating layer, wherein the stress adjustment device substantially does not contain conductive materials.

[0241] Some embodiments of the stress adjustment element further include one or more additional elements selected from the group consisting of: a first insulating layer and a third insulating layer having a first composition and a second insulating layer and a fourth insulating layer having a second composition different from the first composition; a fifth insulating layer having a second composition; a first insulating layer and a third insulating layer including silicon dioxide and a second insulating layer, a fourth insulating layer, and a fifth insulating layer including silicon nitride; a first insulating layer and a third insulating layer containing silicon dioxide, a second insulating layer and a fifth insulating layer containing silicon nitride, and a fourth insulating layer containing Si x O y N z composition, where 1 ≤ x ≤ 3, 0 < y ≤ 2, and 0 < z ≤ 4; a series of N - 1 alternating layers of the first composition and the second composition; and a series of N - 1 alternating layers of silicon dioxide and silicon nitride formed above the fifth insulating layer.

[0242] In some embodiments of the method of manufacturing a stress adjustment device, it includes preparing a semiconductor substrate, forming a first insulating layer and a second insulating layer above the first side of the semiconductor substrate, forming a second insulating layer above the first insulating layer, and forming a third insulating layer, a fourth insulating layer, and a fifth insulating layer above the second side of the semiconductor substrate.

[0243] Some embodiments of the method of manufacturing a stress regulating device further include one or more additional elements selected from the group consisting of: forming a first insulating layer by depositing a thin film including silicon dioxide, forming a second insulating layer by depositing a thin film including silicon nitride, forming a third insulating layer by depositing a thin film including silicon dioxide, forming a fourth insulating layer by depositing a thin film including silicon nitride, and forming a fifth insulating layer by depositing a film including silicon nitride; depositing a silicon dioxide thin film between the fourth insulating layer and the fifth insulating layer; before forming the fifth insulating layer, modifying the fourth insulating layer with oxygen to form a SiON composition; after forming the third insulating layer and before forming the fifth insulating layer, Before depositing the fourth insulating layer, the semiconductor substrate is rotated by θ°; rotating the semiconductor substrate by θ° includes rotating the semiconductor substrate by 45°; and / or depositing a series of N-1 alternating layers above the fifth insulating layer, the first layer including silicon dioxide and the second layer including silicon nitride; forming a series of N-1 alternating layers of silicon dioxide and silicon nitride above the first side of the semiconductor substrate, forming a series of N-1 alternating layers of silicon dioxide and silicon nitride above the second side of the semiconductor substrate, and before depositing additional layers in the series of N-1 alternating layers of silicon dioxide and silicon nitride, removing each layer in the series of N-1 alternating layers of silicon dioxide and silicon nitride formed on the first side of the semiconductor substrate.

[0244] In some embodiments of the method of manufacturing a stress adjustment device, a first insulating material is formed over a first side and a second side of a semiconductor substrate. A second insulating material is formed over the first insulating material on the first side and the second side of the semiconductor substrate. A third insulating material is formed over the second insulating material on the second side of the semiconductor substrate. A fourth insulating material is formed over the second insulating material on the first side of the semiconductor substrate and over the third insulating material on the second side of the semiconductor substrate.

[0245] In some embodiments, forming a first insulating material comprises depositing a film containing silicon dioxide; forming a second insulating material comprises depositing a film containing silicon nitride; forming a third insulating material comprises depositing a film containing silicon dioxide; and forming a fourth insulating material comprises depositing a film containing silicon nitride. In some embodiments, the second insulating material is deposited to form a first layer having a first thickness T1; and the fourth insulating material is deposited to form a second layer having a second thickness T2, wherein the first thickness and the second thickness satisfy the expression T2>T1. In some embodiments, the method of manufacturing a stress adjustment device further comprises, before forming the fourth insulating material, modifying the third insulating material with oxygen to form a SiON composition. In some embodiments, the method of manufacturing a stress adjustment device further comprises, after forming the third insulating material and before forming the fourth insulating material, rotating the semiconductor substrate by θ°. In some embodiments, rotating the semiconductor substrate by θ° comprises rotating the semiconductor substrate by 45°. In some embodiments, the method of manufacturing a stress adjustment device further comprises depositing a series of N-1 alternating layers over the fourth insulating material, the series of N-1 alternating layers consisting of a first material including silicon dioxide and a second material including silicon nitride. In some embodiments, the method of manufacturing a stress regulating device further includes forming a series of N-1 alternating silicon dioxide and silicon nitride layers over a first side of a semiconductor substrate; forming a series of N-1 alternating silicon dioxide and silicon nitride layers over a second side of the semiconductor substrate; removing each of the series of N-1 alternating silicon dioxide and silicon nitride layers formed over the first side of the semiconductor substrate; and depositing a last layer in the series of N-1 alternating silicon dioxide and silicon nitride layers.

[0246] Some embodiments of a multilayer semiconductor package assembly include a first semiconductor device, a second semiconductor device mounted on the first semiconductor device, which is used to establish an electrical connection between the first semiconductor device and the second semiconductor device, wherein the combination of the first semiconductor device and the second semiconductor device has an initial stress load, and a first stress adjustment device configured to reduce the initial stress load, the first stress adjustment device including a semiconductor substrate, a first insulating layer on a first side of the semiconductor substrate, a second insulating layer on the first insulating layer, a third insulating layer on a second side of the semiconductor substrate, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer.

[0247] Some embodiments of the multilayer semiconductor package assembly also include one or more additional elements or configurations selected from the following groups: a carrier mounted on the second semiconductor device, wherein the first stress regulating device is mounted on the carrier and reduces the initial stress load; the first stress regulating device is mounted on the first semiconductor device; a second stress regulating device mounted on the first semiconductor device, wherein the combination of the first stress regulating device and the second stress regulating device further reduces the initial stress load; and / or the first semiconductor device and the second semiconductor device are independently selected from semiconductor wafers and semiconductor chips.

[0248] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A stress adjustment device, characterized in that: Include: a semiconductor substrate; a first insulating layer located above a first side of the semiconductor substrate; a second insulating layer, located above the first insulating layer; a third insulating layer located above a second side of the semiconductor substrate; a fourth insulating layer, located above the third insulating layer; as well as A fifth insulating layer is located above the fourth insulating layer, wherein the stress adjustment device substantially does not include conductive material.

2. The stress adjustment device according to claim 1, characterized in that: in: The first insulating layer and the third insulating layer include silicon dioxide; The second insulating layer and the fifth insulating layer include silicon nitride; and The fourth insulating layer contains a Si x O y N z composition, where 1 ≤ x ≤ 3, 0 < y ≤ 2, and 0 < z ≤ 4.

3. A method for manufacturing a stress regulating device, characterized in that: Include: forming a first insulating material over a first side and a second side of a semiconductor substrate; forming a second insulating material over the first insulating material on the first side and the second side of the semiconductor substrate; forming a third insulating material over the second insulating material on the second side of the semiconductor substrate; as well as A fourth insulating material is formed over the second insulating material on the first side of the semiconductor substrate and over the third insulating material on the second side of the semiconductor substrate.

4. The method for manufacturing the stress adjustment device according to claim 3, characterized in that: Also includes: depositing the second insulating material to form a first layer having a first thickness T1; and The fourth insulating material is deposited to form a second layer having a second thickness T2, wherein the first thickness and the second thickness satisfy an expression T2>T1.

5. The method for manufacturing the stress adjustment device according to claim 3, characterized in that: Also includes: Before forming the fourth insulating material, the third insulating material is modified with oxygen to form a SiON composition.

6. The method for manufacturing the stress adjustment device according to claim 3, characterized in that: Also includes: After forming the third insulating material and before forming the fourth insulating material, the semiconductor substrate is rotated by θ°.

7. The method for manufacturing the stress adjustment device according to claim 3, characterized in that: Also includes: A series of N-1 alternating layers consisting of a first material including silicon dioxide and a second material including silicon nitride are deposited over the fourth insulating material.

8. The method for manufacturing the stress adjustment device according to claim 3, characterized in that: Also includes: forming a series of N-1 alternating silicon dioxide and silicon nitride layers over the first side of the semiconductor substrate; forming a series of N-1 alternating silicon dioxide and silicon nitride layers over the second side of the semiconductor substrate; removing each of the series of N-1 alternating silicon dioxide and silicon nitride layers formed over the first side of the semiconductor substrate; and A final layer in the series of N-1 alternating silicon dioxide and silicon nitride layers is deposited.

9. A multi-layer semiconductor package assembly, characterized in that: Include: a first semiconductor device; a second semiconductor device mounted on the first semiconductor device, wherein the first semiconductor device is electrically connected to the second semiconductor device, wherein a combination of the first semiconductor device and the second semiconductor device has an initial stress load; and a first stress adjustment device configured to reduce the initial stress load, wherein the first stress adjustment device comprises: a semiconductor substrate; a first insulating layer located on a first side of the semiconductor substrate; a second insulating layer, located on the first insulating layer; a third insulating layer, located on a second side of the semiconductor substrate; a fourth insulating layer, located on the third insulating layer; and A fifth insulating layer is located on the fourth insulating layer.

10. The multi-layer semiconductor package assembly according to claim 9, wherein: Also includes: A second stress regulating device is mounted on the first semiconductor device, wherein the second stress regulating device is configured to reduce the initial stress load.

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