A package substrate structure and a manufacturing method thereof

Abstract

This application discloses a packaging substrate structure and its manufacturing method. The packaging substrate structure provided by this application includes a core board, a first seed layer, a core board circuit layer, via pads, a first resin layer, a second seed layer, an inner circuit layer, a multilayer composite structure, a solder mask layer, and solder balls. The inner circuit layer adopts a buried circuit process. First, circuit grooves are etched in the first resin layer to form circuit grooves, and then the inner circuit layer is formed. This allows control over the spacing and width of the circuit grooves. By reducing the spacing and width of the circuit grooves, fine circuits with smaller spacing can be obtained, specifically achieving micron-level circuits. This solves the problem in the prior art where etching the metal layer makes it impossible to obtain fine circuits with smaller spacing. Furthermore, while achieving resin-filled vias and fine circuits, it also realizes a novel vertical stacked via structure for core board through-holes and outer layer circuit holes.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate structure and its manufacturing method. Background Technology

[0002] Packaging substrates are important materials used for device packaging. In advanced packaging technologies, the cost of substrates is much higher than that of conventional packaging, and packaging substrates play an increasingly important role in semiconductor packaging.

[0003] In high-speed signal transmission, due to the high requirements for signal transmission quality, it is necessary to minimize right-angle bends and corners in the signal transmission line. For multilayer interconnect package substrate structures, high-speed signal transmission requires the core board 01 vias and interlayer blind vias of the package substrate to be vertically stacked. For example... Figure 1-6 As shown, in the existing technology for manufacturing packaging substrate structures, such as Figure 1 As shown, a first copper layer 02 is first formed on the surface of the core board 01; as Figure 2 As shown, a resin layer 03 is then laminated onto the surface of the first copper layer 02, and the resin fills the through holes of the core board 01; as shown Figure 3 As shown, the resin layer 03 is further thinned to retain the resin inside the through-hole while exposing the first copper layer 02; as Figure 4 As shown, a second copper layer 04 is processed on the surface of the first copper layer 02; as Figure 5 As shown, a mask 05 is fabricated on the surface of the second copper layer 04; as... Figure 6 As shown, etching is performed using the cutout structure of mask 05 to partially etch the first copper layer 02 and the second copper layer to form a circuit layer with a line spacing of L. In the above scheme, after the resin fills the vias, a PCB-standard grinding device is used to brush the surface resin, removing the surface resin and exposing the resin in the holes. Then, the surface is metallized and patterned to form the circuit of the core layer. In the above scheme, a relatively thick first copper layer 02 needs to be formed on the surface of the core board 01 to ensure that the copper layer on the surface of the core board 01 is not torn during the brushing process. Furthermore, a second copper layer 04 is required after brushing to prevent stress formation under high temperature conditions. However, the combined thickness of the first copper layer 02 and the second copper layer 04 generally exceeds 25μm. During the etching process, due to the excessive thickness of the copper layer, the line spacing L generally exceeds 70μm, making it impossible to manufacture fine circuits with small line spacing. Summary of the Invention

[0004] The purpose of this application is to provide a packaging substrate structure and its manufacturing method to realize the manufacturing of fine circuits with small line spacing, and to realize a new structure of core board through holes and outer layer line holes with vertical stacked holes while realizing resin plug holes and fine circuits.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A packaging substrate structure, comprising:

[0007] A core board having a plurality of through holes, the core board including a first surface and a second surface opposite to each other along its thickness direction;

[0008] A first seed layer covers the inner wall of the through hole, the area around the opening of the through hole, and local areas of the first and second surfaces.

[0009] The core board circuit layer, the via pad, and the metal conductive layer, wherein the via pad covers the first seed layer in the area surrounding the via opening, the metal conductive layer covers the first seed layer on the inner wall of the via, and the core board circuit layer covers the first seed layer in the remaining areas.

[0010] The first resin layer fills the gap between the through holes and the circuit layer of the core board. The first resin layer has multiple circuit grooves on the side away from the core board, and the circuit grooves opposite to the hole pads are through grooves, while the other circuit grooves are blind grooves.

[0011] A second seed layer and an inner circuit layer are stacked together. The second seed layer covers the inner wall of the circuit groove of the first resin layer, and the inner circuit layer covers the side surface of the second seed layer away from the core board. The inner circuit layer is embedded in the circuit groove.

[0012] At least one multilayer composite structure is disposed on the side of the inner circuit layer away from the core board. The multilayer composite structure includes a second resin layer, a third seed layer and a circuit layer disposed sequentially in the direction away from the core board. The second resin layer has a through hole. The third seed layer and the circuit layer are stacked on the side of the second resin layer away from the core board.

[0013] A solder resist layer is disposed on the side of the multilayer composite structure opposite to the core board;

[0014] Solder ball, wherein the solder ball is disposed on the solder resist layer, and the bottom of the solder ball penetrates the solder resist layer and contacts the outermost circuit layer.

[0015] In one implementation, the first resin layer and / or the second resin layer comprise ABF resin and / or RCC.

[0016] In one implementation, the first seed layer, the second seed layer, and / or the third seed layer include at least one sub-metal layer; or,

[0017] The first seed layer, the second seed layer, and / or the third seed layer include multiple sub-metal layers, and the materials of the multiple sub-metal layers are different.

[0018] In one implementation, the sub-metal layer is made of titanium, copper, or tungsten.

[0019] In one implementation, the solder balls include chip solder balls and substrate solder balls. The chip solder balls are disposed on a solder resist layer on one side of the core board, and the substrate solder balls are disposed on a solder resist layer on the other side of the core board. The chip solder balls are used for bonding with a chip, and the substrate solder balls are used for bonding with a printed circuit board.

[0020] The chip solder ball has a flat surface on the side away from the core board; and / or, the substrate solder ball has a spherical surface on the side away from the core board.

[0021] In the aforementioned packaging substrate structure, buried circuit manufacturing technology is employed during the formation of the inner circuit layer. This involves forming circuit trenches within the first resin layer, with deep holes formed opposite the via openings. The depth of these deep holes reaches the via pads, covering the entire surface of the pads and the via-filling resin. During the inner circuit layer manufacturing, the inner circuit layer and via pads are vertically stacked. All subsequent circuit layers are also stacked vertically at the via locations. Because the inner circuit layer utilizes a buried circuit process, the circuit trenches are first etched into the first resin layer before the inner circuit layer is formed. This allows for control over the spacing and width of the circuit trenches. By reducing the spacing and width of the trenches, finer circuits with smaller spacing can be obtained, specifically achieving micron-level circuitry. This solves the problem in existing technologies where etching the metal layer prevents the formation of finer circuits with smaller spacing. In addition, during the manufacturing process of the inner layer circuit, only resin plugging and core board circuit layers were made. The resin surface of the core board through holes did not have the metal coverage of conventional resin plugging. The inner circuit layers covered the hole pads, and the through holes corresponding to multiple circuit layers were stacked perpendicularly to the through holes of the core board. All circuit layers were stacked perpendicularly to the hole pads. While realizing resin plugging and fine circuits, a new structure of vertical stacking of core board through holes and outer layer circuit holes was also realized.

[0022] A method for manufacturing a packaging substrate structure, comprising:

[0023] The core board has openings, with multiple through holes formed on it, and the core board has opposing first and second surfaces;

[0024] A first seed layer is formed on the surface of the core plate with through holes;

[0025] A first mask is formed on the surface of the structure formed in the previous step. The first mask has a hollow structure. The hollow structure of the first mask is at least opposite to the through hole of the structure formed in the previous step and the area around the opening of the through hole.

[0026] A core board circuit layer, via pads, and a conductive metal layer are formed. A first metal layer is formed within the cutout structure of the first mask, and the first metal layer covers the inner wall of the via and the area around the via opening. The first metal layer in the area around the via opening forms the via pads. The first metal layer covering the inner wall of the via forms the conductive metal layer. The first metal layer at the remaining locations, except for the inner wall of the via and the area around the via opening, forms the core board circuit layer.

[0027] Remove the first mask and the first seed layer covered by the first mask;

[0028] The through holes are plugged and resin is pressed in, and resin is pressed in on both the first and second surfaces of the core board so that the resin fills the gap between the through holes and the circuit layer of the core board, and a first resin layer is formed on the first and second surfaces of the structure formed in the previous step.

[0029] A circuit groove is formed on the first resin layer, and the circuit groove opposite to the through hole extends from the first resin layer to the hole pad.

[0030] A second seed layer is formed on the surface of the structure formed in the previous step;

[0031] A second metal layer is formed on the surface of the second seed layer;

[0032] An inner circuit layer is formed by removing the portion of the second metal layer that is not embedded in the circuit groove, and retaining the portion of the second metal layer embedded in the circuit groove to form the inner circuit layer.

[0033] A second resin layer is formed by pressing resin onto both the first and second surfaces of the structure formed in the previous step to form the second resin layer.

[0034] Drill holes to create through holes in the second resin layer;

[0035] A third seed layer is formed on the surface of the structure formed in the previous step;

[0036] A fourth mask is formed on the surface of the structure formed in the previous step;

[0037] A circuit layer is formed within the cutout structure of the fourth mask;

[0038] Remove the fourth mask and the third seed layer that is covered by the fourth mask;

[0039] Repeat the steps at least once to form the second resin layer until the fourth mask and the third seed layer covered by the fourth mask are removed, in order to form at least one circuit layer;

[0040] Solder resist layers are formed on the first and second surfaces of the structure formed in the previous step, and the solder resist layers have connection holes corresponding to the circuit layers;

[0041] Ball placement involves soldering balls onto the first and / or second surfaces of the structure formed in the previous step.

[0042] In one implementation, the plugging and pressing resin comprises:

[0043] The through holes are plugged by pressing resin onto both the first and second surfaces of the core board to fill the gaps between the through holes and the circuit layers of the core board.

[0044] The resin layer of the lamination is thinned so that the resin does not cover the core board circuit layer and the hole pads. The thinned resin layer is flush with the hole pads and the core board circuit layer, or the core board circuit layer and the hole pads are higher than the resin layer.

[0045] The resin is pressed again to form the first resin layer.

[0046] In one implementation, the thinning and laminating of the resin layer includes: thinning the laminated resin by chemical mechanical polishing so that the resin does not cover the core board circuit layer and via pads; and / or, the resin used in the via plugging and laminating resin step includes ABF resin and / or RCC.

[0047] In one implementation, the step of forming the line groove includes:

[0048] A metal protective layer is formed on both the first and second surfaces of the structure formed in the previous step.

[0049] A second mask is formed on the surface of the structure formed in the previous step, and the second mask has a hollow structure.

[0050] Remove the metal protective layer that is not covered by the second mask;

[0051] The first and second surfaces of the structure formed in the previous step are etched to form a circuit groove, the depth of which extends from the metal protective layer to the first resin layer, and the second mask is removed.

[0052] A third mask is formed on the surface of the structure formed in the previous step, and the hollow structure of the third mask is opposite to the opening of the through hole and the surrounding area.

[0053] The first and second surfaces of the structure formed in the previous step are etched to deepen the circuit grooves opposite to the orifice and surrounding area of ​​the via. The circuit grooves opposite to the via extend from the metal protective layer to the orifice pad, and the third mask is removed.

[0054] Remove the metal protective layer.

[0055] In one implementation, the step of forming the inner circuit layer involves removing the portion of the second metal layer that is not embedded in the circuit groove, specifically by using chemical mechanical polishing to remove the portion of the second metal layer that is not embedded in the circuit groove.

[0056] Compared with the prior art, the beneficial effects of the manufacturing method of the packaging substrate structure provided in this application are the same as those of the above-mentioned packaging substrate structure, and will not be repeated here. Attached Figure Description

[0057] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0058] Figure 1 This is a schematic diagram of the formation of the first copper layer during the fabrication of a packaging substrate structure in the prior art.

[0059] Figure 2 This is a schematic diagram of the resin layer formed during the fabrication of a packaging substrate structure in the prior art.

[0060] Figure 3 This is a schematic diagram of the resin layer after thinning during the fabrication of the packaging substrate structure in the prior art.

[0061] Figure 4 This is a schematic diagram showing the metal layer after deposition during the fabrication of a packaging substrate structure in the prior art.

[0062] Figure 5 This is a schematic diagram of the etching mask during the fabrication of a packaging substrate structure in the prior art.

[0063] Figure 6 This is a schematic diagram showing the circuit layer after it has been formed during the fabrication of a packaging substrate structure in the prior art.

[0064] Figure 7 A flowchart illustrating a method for manufacturing a packaging substrate structure provided in an embodiment of this application;

[0065] Figure 8 A cross-sectional view of the core board after through holes are opened in the embodiments of this application;

[0066] Figure 9 This is a cross-sectional view of the core board after the copper layer has been removed, as provided in an embodiment of this application.

[0067] Figure 10 This is a top view of the core board after the copper layer has been removed, as provided in an embodiment of this application.

[0068] Figure 11This is a cross-sectional view provided in an embodiment of this application after the formation of the first seed layer;

[0069] Figure 12 This is a cross-sectional view provided in an embodiment of this application after the formation of the first mask;

[0070] Figure 13 This is a cross-sectional view provided in an embodiment of the present application after the core board circuit layer and via pads have been formed;

[0071] Figure 14 This is a cross-sectional view provided in an embodiment of this application after removing the first mask;

[0072] Figure 15 This is a cross-sectional view provided in an embodiment of the present application after removing the first seed layer covered by a mask;

[0073] Figure 16 A structural diagram of the hole-plugging and first resin-pressing step provided in the embodiments of this application;

[0074] Figure 17 A cross-sectional view of the resin after thinning in the plugging and first pressing resin step provided in the embodiments of this application;

[0075] Figure 18 This is a cross-sectional view provided in an embodiment of this application after the formation of the first resin layer;

[0076] Figure 19 This is a cross-sectional view provided in an embodiment of this application after the formation of a metal protective layer;

[0077] Figure 20 This is a cross-sectional view provided in an embodiment of this application after the formation of the second mask;

[0078] Figure 21 A cross-sectional view provided for an embodiment of this application, showing the removal of the metal protective layer not covered by the second mask;

[0079] Figure 22 This is a cross-sectional view of the structure formed during the formation of the line groove, as provided in the embodiments of this application.

[0080] Figure 23 This is a cross-sectional view provided in an embodiment of this application after the formation of the third mask;

[0081] Figure 24 A cross-sectional view provided for an embodiment of this application, showing the wiring groove opposite to the through hole extending from the metal protective layer to the hole opening pad;

[0082] Figure 25 This is a cross-sectional view provided in an embodiment of this application after the metal protective layer has been removed;

[0083] Figure 26This is a cross-sectional view provided in an embodiment of this application after the formation of the second seed layer;

[0084] Figure 27 This is a cross-sectional view provided in an embodiment of this application after the formation of the second metal layer;

[0085] Figure 28 This is a cross-sectional view provided in an embodiment of this application after the formation of the internal circuit layer;

[0086] Figure 29 This is a cross-sectional view provided in an embodiment of this application after the formation of the second resin layer;

[0087] Figure 30 This is a cross-sectional view after drilling provided in an embodiment of this application;

[0088] Figure 31 This is a cross-sectional view provided in an embodiment of this application after the formation of the third seed layer;

[0089] Figure 32 This is a cross-sectional view of the fourth mask formed according to an embodiment of this application;

[0090] Figure 33 This is a cross-sectional view of the circuit layer after it has been formed, provided in an embodiment of this application.

[0091] Figure 34 This is a cross-sectional view provided in an embodiment of this application after removing the fourth mask;

[0092] Figure 35 A cross-sectional view provided for an embodiment of this application after removing the third seed layer covered by the fourth mask;

[0093] Figure 36 A cross-sectional view provided for embodiments of this application after repeating the third pressing resin step at least once – removing the fourth mask and the third seed layer covered by the fourth mask;

[0094] Figure 37 This is a cross-sectional view of the solder mask layer after fabrication, provided in an embodiment of this application.

[0095] Figure 38 This is a cross-sectional view of the planted balls provided in an embodiment of this application.

[0096] Figure label:

[0097] 01-Core board, 02-First copper layer, 03-Resin layer, 04-Second copper layer, 05-Mask;

[0098] 1-Core board, 1a-Through hole, 2-First seed layer, 3-First mask, 4-Core board circuit layer, 5-Hole pad, 5a-Metal conductive layer, 6-First resin layer, 6a-Circuit groove, 7-Metal protective layer, 8-Second mask, 9-Third mask, 10-Second seed layer, 11-Second metal layer, 12-Inner circuit layer, 13-Second resin layer, 13a-Through hole, 14-Third seed layer, 15-Fourth mask, 16-Circuit layer, 17-Solder resist layer, 18-Chip solder ball, 19-Substrate solder ball. Detailed Implementation

[0099] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0100] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0102] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0103] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0104] like Figure 37 As shown, this application provides a packaging substrate structure, which can be fabricated using any of the following packaging substrate manufacturing methods. The packaging substrate structure provided in this application includes a core board 1, a first seed layer 2, a core board circuit layer 4, via pads 5, a conductive metal layer 5a, a first resin layer 6, a second seed layer 10, an inner circuit layer 12, a multilayer composite structure, a solder mask layer 17, and solder balls. The first seed layer 2, core board circuit layer 4, first resin layer 6, second seed layer 10, inner circuit layer 12, multilayer composite structure, and solder mask layer 17 are symmetrically arranged on both sides of the core board 1.

[0105] The core board 1 has multiple through holes 1a and includes a first surface and a second surface opposite to each other along its thickness direction. The first surface can be the upper surface, and the second surface can be the lower surface. The through holes 1a penetrate the thickness of the core board 1, with one opening of the through hole 1a located on the first surface and the other opening of the through hole 1a located on the second surface. A first seed layer 2 covers the inner wall of the through holes 1a of the core board 1 and the area around the openings of the through holes 1a, that is, the areas around the openings located on the first surface and the areas around the openings located on the second surface are both covered by the first seed layer 2. The first seed layer 2 also covers a partial area of ​​the first surface and the second surface of the core board 1, which refers to the area used to form the core board circuit layer 4.

[0106] The via pad 5 covers the first seed layer 2 around the via opening 1a, the conductive metal layer 5a covers the first seed layer 2 on the inner wall of the via 1a, and the core board circuit layer 4 covers the remaining first seed layer 2. The via pad 5 is used for electrical connection with the inner circuit layer 12. Both the via pad 5 and the core board circuit layer 4 are metal layers. The metal layer can be a single layer of metal, such as copper, tungsten, or titanium. Alternatively, the metal layer can include multiple sub-metal layers, which can be made of the same or different materials; for example, the sub-metal layers can be made of copper, tungsten, or titanium. The thicknesses of the multiple sub-metal layers can be the same or different.

[0107] The first resin layer 6 fills the gap between the through-hole 1a of the core board 1 and the core board circuit layer 4, and also fills the gap between the hole pad 5 and the core board circuit layer 4. Multiple circuit grooves 6a are formed on the side of the first resin layer 6 away from the core board 1, with the circuit groove 6a opposite to the hole pad 5 being a through groove, and the remaining circuit grooves 6a being blind grooves. That is, the circuit groove 6a opposite to the hole pad 5 extends through the thickness direction of the first resin layer 6. The openings of the remaining circuit grooves 6a, except those opposite to the hole pad 5, are located on the surface of the first resin layer 6 away from the core board 1, and the bottoms of the remaining circuit grooves 6a are located within the first resin layer 6. Furthermore, the material filling the through-hole 1a of the core board 1 is a plugging material. The plugging material and the material filling the gaps between the core board circuit layers 4 can be of the same material, so as to fill the gaps between the core board circuit layers 4 simultaneously, simplifying the processing technology.

[0108] The second seed layer 10 and the inner circuit layer 12 are stacked. Specifically, the second seed layer 10 covers the inner wall of the circuit groove 6a, and the inner circuit layer 12 covers the side of the second seed layer 10 facing away from the first resin layer 6. The inner circuit layer 12 is embedded in the circuit groove 6a. That is, both the second seed layer 10 and the inner circuit layer 12 are embedded in the circuit groove 6a, with the second seed layer 10 located between the inner circuit layer 12 and the inner wall of the circuit groove 6a. The portion of the inner circuit layer 12 located in the circuit groove 6a opposite to the via pad 5 is electrically connected to the via pad 5. The surface of the inner circuit layer 12 can be flush with the first resin layer 6, or the surface of the inner circuit layer 12 can be higher than the surface of the first resin layer 6.

[0109] At least one multilayer composite structure is disposed on the side of the inner circuit layer 12 away from the core board 1. The multilayer composite structure includes a second resin layer 13, a third seed layer 14, and a circuit layer 16 arranged sequentially along the direction away from the core board 1. The second resin layer 13 has a through hole 13a, and the third seed layer 14 and the circuit layer 16 are stacked on the side of the second resin layer 13 away from the core board 1. When multiple multilayer composite structures are disposed on the upper or lower side of the core board 1, the multiple multilayer composite structures are stacked sequentially. Alternatively, a single multilayer composite structure can also be disposed on the upper or lower side of the core board 1. The multilayer composite structure includes a second resin layer 13, a third seed layer 14, and a circuit layer 16 arranged sequentially along the direction away from the core board 1. The second resin layer 13 has a through hole 13a, and the third seed layer 14 and the circuit layer 16 are stacked on the side of the second resin layer 13 away from the core board 1. Multiple through holes 13a can be respectively opposite to multiple hole pads 5, so as to facilitate the connection of the inner circuit layer 12 to the circuit layer through the through holes 13a.

[0110] The materials of the first resin layer 6 and the second resin layer 13 can be the same or different. When the materials of the first resin layer 6 and the second resin layer 13 are the same, the boundary line between the first resin layer 6 and the second resin layer 13 may not be obvious, and the first resin layer 6 and the second resin layer 13 form an integral resin layer.

[0111] A solder mask layer 17 is disposed on the side of the multilayer composite structure facing away from the core board 1. The solder mask layer 17 has connection holes corresponding to the circuit layers 16, which are used for connection with solder balls. Solder balls are disposed on the solder mask layer 17, with the bottom of the solder balls passing through the solder mask layer 17 and contacting the outermost circuit layer. The solder balls may include chip solder balls 18 and substrate solder balls 19, wherein the chip solder balls 18 are disposed on the solder mask layer 17 on one side of the core board, and the substrate solder balls 19 are disposed on the solder mask layer 17 on the other side of the core board 1. The chip solder balls 18 are used for bonding with chips, and the substrate solder balls 19 are used for bonding with printed circuit boards.

[0112] In the aforementioned packaging substrate structure, buried circuit manufacturing technology is employed during the formation of the inner circuit layer 12. Specifically, circuit trenches 6a are formed within the first resin layer 6, and deep holes are formed at the portion of the circuit trenches 6a opposite to the openings of vias 1a. The depth of the deep holes reaches the opening pads 5, and the deep holes cover the entire surface of the pads and the via-filling resin. During the fabrication of the inner circuit layer 12, the inner circuit layer 12 and the opening pads 5 are vertically stacked. All subsequent circuit layers 16 are also stacked vertically at the vias 1a. Because the inner circuit layer 12 uses a buried circuit process, the circuit trenches 6a are first etched into the first resin layer 6 before the inner circuit layer 12 is formed. This allows control over the spacing and width of the circuit trenches 6a. By reducing the spacing and width of the circuit trenches 6a, finer circuits with smaller spacing can be obtained, specifically achieving micron-level circuits. This solves the problem in existing technologies where etching the metal layer makes it impossible to obtain finer circuits with smaller spacing. In addition, during the manufacturing process of the inner layer circuit, only resin plugging and core board circuit layers were made. The resin surface of the core board through holes did not have the metal coverage of conventional resin plugging. The inner circuit layer 12 covered the hole pads 5, and the through holes corresponding to multiple circuit layers were all stacked perpendicularly to the through holes 1a of the core board. All circuit layers 16 were stacked perpendicularly to the hole pads 5. While realizing resin plugging and fine circuits, a new structure of vertical stacking of core board through holes and outer layer circuit holes was also realized.

[0113] In one specific embodiment, the first resin layer 6 may include an overlay film such as ABF (ABF Jinomoto Build-up Film) resin and / or RCC (Resin Coated Copper) material. And / or the second resin layer 13 may include an overlay film such as ABF resin and / or RCC (Resin Coated Copper) material. Of course, the first resin layer 6 and the second resin layer 13 may also be made of other materials, such as RCC and / or photosensitive dry film insulating layer material.

[0114] The first seed layer 2, the second seed layer 10, and / or the third seed layer 14 each include at least one sub-metal layer. That is, the first seed layer 2, the second seed layer 10, and / or the third seed layer 14 can be a single-layer metal, and the material of the single-layer metal can be copper, tungsten, or titanium, etc. Of course, the first seed layer 2, the second seed layer 10, and / or the third seed layer 14 can also include multiple sub-metal layers. The materials of the multiple sub-metal layers can be the same or different; for example, the materials of the sub-metal layers can be copper, tungsten, or titanium. The thicknesses of the multiple sub-metal layers can be the same or different.

[0115] The chip solder ball 18 is used to bond with the chip. The side of the chip solder ball 18 facing away from the core board 1 has a flat surface to facilitate bonding with the chip.

[0116] The substrate solder ball 19 is used to bond with the printed circuit board. The side of the substrate solder ball 19 facing away from the core board 1 is spherical to facilitate bonding with the printed circuit board.

[0117] Please see Figure 7 This application also provides a method for manufacturing a packaging substrate structure, including the following steps:

[0118] S1: The core board 1 has openings, and multiple through holes 1a are opened on the core board 1. The core board 1 has a first surface and a second surface with opposite sides.

[0119] like Figures 8-10 As shown, specifically, along the thickness direction, the core plate 1 has opposing first and second surfaces, both of which are perpendicular to the thickness direction of the core plate 1. Multiple through holes 1a penetrating the thickness of the core plate 1 are formed on the core plate 1, with one opening of each through hole 1a located on the first surface and the other opening located on the second surface.

[0120] In this step, such as Figure 8 As shown, the core board 1 can be a double-sided copper-clad laminate, and the copper layers on both sides of the double-sided copper-clad laminate are removed before the through hole 1a is made. Furthermore, the through hole 1a can be made using a laser in this step.

[0121] S2: Forming a first seed layer 2, forming a first seed layer 2 on the surface of the core plate 1 with through hole 1a;

[0122] like Figure 11 As shown, a first seed layer 2 is formed on the surface of the core board 1 after the hole is opened in step S1. The first seed layer 2 covers the first surface, the second surface, and the inner wall of the through hole 1a of the core board 1. Optionally, the first seed layer 2 can be formed by deposition, electroplating, or other methods.

[0123] In this way, a regular, dense and smooth first seed layer 2 is formed on the surface of the core plate 1. Its good brightness and level distribution enhance the adhesion between the electrolyte and the metal and promote the surface uniformity of the deposit.

[0124] S3: A first mask 3 is formed on the surface of the structure formed in the previous step. The first mask 3 has a hollow structure. The hollow structure of the first mask 3 is at least opposite to the through hole 1a of the structure formed in the previous step and the area around the opening of the through hole 1a.

[0125] like Figure 12 As shown, a first mask 3 is formed on the surface of the structure formed in step S2. Specifically, the first mask 3 is formed on both the first and second surfaces of the structure formed in step S2. The first surface can be the upper surface, and the second surface can be the lower surface. The first mask 3 has a perforated structure, which is at least opposite to the through-hole 1a and the area surrounding the opening of the through-hole 1a in the structure formed in the previous step. That is, at least the inner wall of the through-hole 1a and the area surrounding the opening of the through-hole 1a are not covered by the first mask 3, and the remaining local areas of the first and second surfaces are also not covered by the first mask 3. The inner wall of the through-hole 1a and the area surrounding the opening of the through-hole 1a are used to form the hole pad 5, and the remaining areas of the first and second surfaces not covered by the first mask 3 are used to form the core board circuit layer 4.

[0126] In this step, a first mask 3 can be formed on the surface of the structure formed in the previous step using photolithography to create an electroplating mask. Specifically, a dry film is first pressed onto the first and second surfaces of the structure formed in the previous step, and then exposure and development are performed sequentially to finally form the first mask 3. The dry film is made of a photosensitive polymer material. Of course, other methods can also be used to form the first mask 3, and this is not limited here.

[0127] S4: Form core board circuit layer 4, via pad 5 and metal conductive layer 5a. Form a first metal layer in the hollow structure of the first mask 3. The first metal layer covers the inner wall of the through hole 1a and the area around the opening of the through hole 1a. The first metal layer in the area around the opening of the through hole 1a forms the via pad 5. The first metal layer covering the inner wall of the through hole 1a forms the metal conductive layer. The first metal layer in the remaining positions except the inner wall of the through hole 1a and the area around the opening of the through hole 1a forms the core board circuit layer 4.

[0128] like Figure 13As shown, in this step, a first metal layer is formed on the inner wall of the through-hole 1a of the core board 1, around the opening of the through-hole 1a, and on the remaining areas of the first and second surfaces not covered by the first mask 3. Specifically, the first metal layer can be formed on the inner wall of the through-hole 1a and around the opening of the through-hole 1a by electroplating, deposition, or other methods. The portion of the first metal layer located around the opening of the through-hole 1a is the opening pad 5, used to connect the inner circuit layer 12. The portion of the first metal layer covering the inner wall of the through-hole 1a forms a conductive metal layer, and the portion of the first metal layer located on the remaining areas of the first and second surfaces not covered by the first mask 3 is the core board circuit layer 4.

[0129] In this step, the first metal layer can be a single metal layer, and the material of the single metal layer can be copper, tungsten, or titanium, etc. Of course, the first metal layer can also include multiple sub-metal layers, and the materials of the multiple sub-metal layers can be the same or different; for example, the materials of the sub-metal layers can be copper, tungsten, or titanium. The thickness of the multiple sub-metal layers can be the same or different.

[0130] S5: Remove the first mask 3 and the first seed layer 2 covered by the first mask 3;

[0131] like Figures 14-15 As shown, the first mask 3 and the first seed layer 2 covered by the first mask 3 are removed, leaving the first metal layer and the first seed layer 2 covered by the first metal layer.

[0132] This step can be divided into two steps: removing the first mask 3 and the first seed layer 2 covered by the first mask 3. Specifically, the first mask 3 can be removed first, followed by the removal of the first seed layer 2 covered by the first mask 3. Alternatively, the first mask 3 can be peeled off directly by a stripping method, and then the first seed layer 2 covered by the first mask 3 can be removed by wet etching or laser etching.

[0133] S6: Plug the holes and press the resin. Press the resin on both the first and second surfaces of the core board 1 so that the resin fills the gap between the through hole 1a of the core board 1 and the core board circuit layer 4, and form a first resin layer 6 on the first and second surfaces of the structure formed in the previous step.

[0134] In this step, the resin is pressed to fill the through holes 1a of the core board 1, the gaps between the core board circuit layers 4, and the gaps between the hole pads 5 and the core board circuit layers 4, and a first resin layer 6 is formed on the first and second surfaces of the structure formed in the previous step.

[0135] Further S6 plugging and resin lamination includes the following steps:

[0136] S6a: Plug the hole. Resin is pressed onto both the first and second surfaces of the core board 1 so that the resin fills the gap between the through hole 1a of the core board 1 and the core board circuit layer 4.

[0137] like Figure 16 As shown, in this step, resin is used to fill the through-hole 1a, that is, to fill the through-hole 1a with resin. Resin is then pressed onto both the first and second surfaces of the core board 1 to form a resin layer on both surfaces. The resin used for plugging the holes in this step includes ABF resin, PP prepreg, and / or PI material, etc., as a reinforcing film.

[0138] S6b: Thin the resin layer after lamination so that the resin does not cover the core board circuit layer 4 and the via pad 5. The thinned resin layer is flush with the via pad 5 and the core board circuit layer 4.

[0139] like Figure 17 As shown, the resin layer can be thinned using a grinding wheel or by chemical mechanical polishing. Further thinning can be followed by CMP (Chemical Mechanical Polishing) to remove minor surface scratches. Specifically, the resin does not cover the core board circuit layer 4 and the via pads 5; that is, the resin layer is thinned until the core board circuit layer 4 and the via pads 5 are exposed. The resin layer can be flush with the core board circuit layer 4 and the via pads 5, or the core board circuit layer 4 and the via pads 5 can be higher than the resin layer, to make the first and second surfaces of the structure smoother.

[0140] S6c: Press the resin again to form the first resin layer 6.

[0141] like Figure 18 As shown, resin is pressed again onto the side of the core board circuit layer 4, the hole pad 5, and the resin layer formed in the previous step away from the core board 1 to form the first resin layer 6.

[0142] In steps S6a-S6c above, the first resin layer 6 is formed by two resin lamination processes. In step S6a, the first resin lamination ensures that the resin density within the through-hole 1a is sufficiently high to prevent interlayer short circuits and ensure signal transmission. In step S6c, the second resin lamination ensures the density of the first resin layer 6 and guarantees interlayer insulation.

[0143] S7: Forming a circuit groove 6a, forming a plurality of circuit grooves 6a on the first resin layer 6, the circuit grooves 6a opposite to the through hole 1a extending from the first resin layer 6 to the hole pad 5.

[0144] Specifically, the wiring groove 6a opposite to the hole pad 5 is a through groove, while the other wiring grooves 6a are blind grooves. That is, the wiring groove 6a opposite to the hole pad 5 is through along the thickness direction of the first resin layer 6. The groove openings of the other wiring grooves 6a, except for the wiring grooves 6a opposite to the hole pad 5, are located on the side surface of the first resin layer 6 away from the core board 1, and the bottoms of the other wiring grooves 6a are located within the first resin layer 6.

[0145] Furthermore, step S7, which involves forming the wiring groove 6a, specifically includes:

[0146] S7a: Forming a metal protective layer 7, forming a metal protective layer 7 on both the first and second surfaces of the structure formed in the previous step;

[0147] like Figure 19 As shown, a metal protective layer 7 is formed on the surface of the first resin layer 6 facing away from the core board 1. The metal protective layer 7 can be formed by magnetron sputtering or chemical plating. The metal protective layer 7 can be a single layer of metal, in which case the metal protective layer 7 can be a copper layer. Alternatively, the metal protective layer 7 can also include a copper layer and a titanium layer stacked sequentially, with the titanium layer located between the first resin layer 6 and the copper layer.

[0148] The thickness of the metal protective layer 7 is 0.1-1 μm. When the metal protective layer 7 consists only of a copper layer, its thickness is 0.3-1 μm; when the metal protective layer 7 consists only of a copper layer and a titanium layer, its thickness is 0.1-1 μm. Exemplarily, the thickness of the metal protective layer 7 is 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm.

[0149] S7b: Form a second mask 8. A second mask 8 is formed on the surface of the structure formed in the previous step. The second mask 8 has a hollow structure.

[0150] like Figure 20 As shown, a second mask 8 is formed on the surface of the structure formed in step S7a. Specifically, the second mask 8 is formed on both the first and second surfaces of the structure formed in step S7a. The first surface can be the upper surface, and the second surface can be the lower surface. The second mask 8 covers the first and second surfaces of the structure formed in the previous step, and the second mask 8 has a perforated structure.

[0151] In this step, a second mask 8 can be formed on the surface of the structure formed in the previous step using photolithography to create an electroplating mask. Specifically, a dry film is first pressed onto the first and second surfaces of the structure formed in the previous step, and then exposed and developed sequentially to finally form the second mask 8. The dry film is made of a photosensitive polymer material. Of course, other methods can also be used to form the second mask 8, which are not limited here.

[0152] S7c: Remove the metal protective layer 7 that is not covered by the second mask 8;

[0153] like Figure 21As shown, the metal protective layer 7 not covered by the second mask 8 can be removed by dry etching or laser etching processes, while the metal protective layer 7 covered by the second mask 8 is retained.

[0154] S7d: Etch the first and second surfaces of the structure formed in the previous step to form a circuit groove 6a, so that the depth of the circuit groove 6a extends from the metal protective layer 7 to the first resin layer 6, and remove the second mask 8.

[0155] like Figure 22 As shown, the circuit trench 6a can be formed by dry etching or laser etching. Specifically, the circuit trench 6a on the first surface can be etched first, and then the circuit trench 6a on the second surface can be etched. In this step S7d, the depth of the circuit trench 6a formed opposite to the area around the via 1a does not reach the hole pad 5. The depth of the circuit trench 6a extends from the metal protective layer 7 to the first resin layer 6, that is, all the circuit trenches 6a formed in this step are blind trenches.

[0156] In step S7d, the second mask 8 is also removed. The second mask 8 and the line groove 6a can be formed simultaneously, or the line groove 6a can be formed first and then the second mask 8 is removed.

[0157] S7e: Form a third mask 9. A third mask 9 is formed on the surface of the structure formed in the previous step. The hollow structure of the third mask 9 is opposite to the opening and surrounding area of ​​the through hole 1a.

[0158] like Figure 23 As shown, a third mask 9 is formed on the surface of the structure formed in step S7d. Specifically, the third mask 9 is formed on both the first and second surfaces of the structure formed in step S7d. The first surface can be the upper surface, and the second surface can be the lower surface. The third mask 9 covers the first and second surfaces of the structure formed in the previous step. The third mask 9 has a hollow structure, and the hollow structure of the third mask 9 is opposite to the opening of the through hole 1a and the surrounding area.

[0159] In this step, a third mask 9 can be formed on the surface of the structure formed in the previous step using photolithography to create an electroplating mask. Specifically, a dry film is first pressed onto the first and second surfaces of the structure formed in the previous step, and then exposure and development are performed sequentially to finally form the third mask 9. The dry film is made of a photosensitive polymer material. Of course, other methods can also be used to form the third mask 9, which are not limited here.

[0160] S7f: Etch the first and second surfaces of the structure formed in the previous step, deepen the circuit groove 6a opposite to the orifice and surrounding area of ​​the through hole 1a. The circuit groove 6a opposite to the through hole 1a extends from the metal protective layer 7 to the hole pad 5, and remove the third mask 9.

[0161] like Figure 24 As shown, dry etching or laser etching is used to etch the area not covered by the third mask 9, that is, to etch the area within the hollow structure of the third mask 9, in order to deepen the circuit groove 6a opposite to the opening and surrounding area of ​​the via 1a, so that the circuit groove 6a opposite to the via 1a extends from the metal protective layer 7 to the hole pad 5. Specifically, in step S7d, the third mask 9 does not cover the circuit groove 6a opposite to the opening and surrounding area. This circuit groove 6a is opposite to the hollow structure of the third mask 9. In step S7f, the circuit groove 6a opposite to the opening and surrounding area of ​​the via 1a is etched to deepen the depth of the circuit groove 6a opposite to the opening and surrounding area of ​​the via 1a until it becomes a through groove, so that the hole pad 5 is exposed in the circuit groove 6a opposite to the opening and surrounding area of ​​the via 1a, which is beneficial to the connection between the hole pad 5 and the inner circuit layer 12.

[0162] S7g: Remove the metal protective layer 7.

[0163] like Figure 25 As shown, the metal protective layer 7 can be removed by etching, at which point a complete circuit groove 6a is formed on the surface of the first resin layer 6.

[0164] In the above steps S7a-S7g, two etching processes are used to form line trenches 6a of different depths. This makes the line trenches 6a opposite to the opening and surrounding area of ​​the through hole 1a through trenches, and the depth extends to the hole opening pad 5. At the same time, the other line trenches 6a that are not opposite to the opening and surrounding area of ​​the through hole 1a are blind trenches, and the depth is shallower.

[0165] S8: Form a second seed layer 10, forming a second seed layer 10 on the surface of the structure formed in the previous step;

[0166] like Figure 26 As shown, a second seed layer 10 is formed on the surface of the structure formed in step S7. Specifically, the second seed layer 10 is formed on the surface of the first resin layer 6 of the structure formed in the previous step that is away from the core board 1. The second seed layer 10 covers the surface of the first resin layer 6 away from the core board 1 and the inner wall of the circuit groove 6a. Optionally, the second seed layer 10 can be formed by deposition, electroplating, or other methods.

[0167] S9: Form a second metal layer 11, and form a second metal layer 11 on the surface of the second seed layer 10;

[0168] like Figure 27 As shown, in this step, a second metal layer 11 is formed on the side of the second seed layer 10 away from the core board 1. The second metal layer 11 is partially embedded in the circuit groove 6a, and at the same time, a metal layer is formed on the side of the first resin layer 6 away from the core board 1. Specifically, the second metal layer 11 can be formed by electroplating, deposition, or other methods.

[0169] In this step, the second metal layer 11 can be a single-layer metal, and the material of the single-layer metal can be copper, tungsten, or titanium, etc. Of course, the second metal layer 11 can also include multiple sub-metal layers, and the materials of the multiple sub-metal layers can be the same or different. For example, the materials of the sub-metal layers can be copper, tungsten, or titanium. The thickness of the multiple sub-metal layers can be the same or different.

[0170] S10: Form an inner circuit layer 12 by removing the portion of the second metal layer 11 that is not embedded in the circuit groove 6a, and retaining the portion of the second metal layer 11 embedded in the circuit groove 6a to form the inner circuit layer 12.

[0171] like Figure 28 As shown, in this step, the second metal layer 11 outside the circuit groove 6a can be removed by chemical mechanical polishing or etching. That is, the portion of the second metal layer 11 not embedded in the circuit groove 6a is removed by chemical mechanical polishing, leaving the portion of the second metal layer 11 embedded in the circuit groove 6a to form the inner circuit layer 12. In this step, the inner circuit layer 12 is embedded into the circuit groove 6a and connected to the hole opening pad 5 in the circuit groove 6a and surrounding area.

[0172] S11: Forming a second resin layer 13 by pressing resin onto both the first and second surfaces of the structure formed in the previous step to form the second resin layer 13.

[0173] like Figure 29 As shown, resin is pressed and filled onto the side of the inner circuit layer 12 of the structure formed in the previous step that is away from the core board 1 to form a second resin layer 13. That is, resin is pressed onto the first surface and the second surface of the structure formed in the previous step to form the second resin layer 13. The second resin layer 13 can be made of the same material as the first resin layer 6 or a different material.

[0174] S12: Drilling, machining a through hole 13a on the second resin layer 13;

[0175] like Figure 30 As shown, multiple through holes 13a extending through the thickness of the second resin layer 13 are formed. The multiple through holes 13a can be respectively opposite to multiple hole pads 5, so as to facilitate the connection between the inner circuit layer 12 and the circuit layer through the through holes 13a. Preferably, the through holes 13a can be formed on the second resin layer 13 using a laser process.

[0176] S13: Form a third seed layer 14, forming a third seed layer 14 on the surface of the structure formed in the previous step;

[0177] like Figure 31As shown, a third seed layer 14 is formed on the surface of the structure formed in step S12. Specifically, the third seed layer 14 is formed on the surface of the second resin layer 13 of the structure formed in the previous step that is away from the core plate 1. The third seed layer 14 is required on both the upper and lower sides of the structure formed in the previous step, and the third seed layer 14 covers the surface of the second resin layer 13 that is away from the core plate 1. Optionally, the third seed layer 14 can be formed by deposition, electroplating, or other methods.

[0178] S14: Form the fourth mask 15, forming the fourth mask 15 on the surface of the structure formed in the previous step;

[0179] like Figure 32 As shown, a fourth mask 15 is formed on the surface of the structure formed in step S13. Specifically, the fourth mask 15 is formed on both the first and second surfaces of the structure formed in step S13. The first surface can be the upper surface, and the second surface can be the lower surface. The fourth mask 15 covers the first and second surfaces of the structure formed in the previous step. The fourth mask 15 has a cutout structure, and the cutout structure of the fourth mask 15 is used to form the circuit layer 16.

[0180] In this step, a fourth mask 15 can be formed on the surface of the structure formed in the previous step using photolithography to create an electroplating mask. Specifically, a dry film is first pressed onto the first and second surfaces of the structure formed in the previous step, and then exposure and development are performed sequentially to finally form the fourth mask 15. The dry film is made of a photosensitive polymer material. Of course, other methods can also be used to form the fourth mask 15, and this is not limited here.

[0181] S15: Forming circuit layer 16, forming circuit layer 16 within the hollow structure of the fourth mask 15;

[0182] like Figure 33 As shown, in this step, a circuit layer 16 is formed within the hollow structure of the fourth mask 15. Specifically, the circuit layer 16 can be formed within the hollow structure of the fourth mask 15 by electroplating, deposition, or other methods.

[0183] In this step, the material of the circuit layer 16 can be copper, tungsten, or titanium.

[0184] S16: Remove the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15;

[0185] like Figures 34-35 As shown, the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15 are removed, leaving the circuit layer 16 and the third seed layer 14 covered by the circuit layer 16.

[0186] This step can be divided into two steps to remove the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15. That is, first remove the fourth mask 15, and then remove the third seed layer 14 covered by the fourth mask 15. Specifically, the fourth mask 15 can be directly peeled off by a stripping method, and then the third seed layer 14 covered by the fourth mask 15 can be removed by wet etching or laser etching.

[0187] S17: Repeat the steps at least once to form the second resin layer 13 until the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15 are removed to form at least one circuit layer 16.

[0188] like Figure 36 As shown, steps S11-S16 are repeated at least once to fabricate the multilayer circuit layer 16.

[0189] S18: A solder resist layer 17 is formed on the first and second surfaces of the structure formed in the previous step, and the solder resist layer 17 has connection holes corresponding to the circuit layer 16.

[0190] like Figure 37 As shown, in this step, a solder mask layer 17 is made on the first and second surfaces of the structure formed in the previous step. That is, a solder mask layer 17 is made on the outermost circuit layer 16 on the upper and lower sides of the structure formed in the previous step, and the solder mask layer 17 has a connection hole corresponding to the circuit layer 16. The connection hole is used to connect with solder balls.

[0191] S19: Ball placement, soldering balls onto the first and / or second surfaces of the structure formed in the previous step.

[0192] Specifically, chip solder balls 18 and substrate solder balls 19 can be respectively provided on the first and second surfaces of the structure formed in the previous step. The chip solder balls 18 are used to bond with the chip, and the substrate solder balls 19 are used to bond with the printed circuit board.

[0193] like Figure 38 As shown, chip solder balls 18 are disposed on the first surface of the structure formed in the previous step, and substrate solder balls 19 are disposed on the second surface of the structure formed in the previous step. The bottom of the solder balls corresponds to the connection holes. The chip solder balls 18 are used for bonding to the chip, and the side of the chip solder balls 18 facing away from the core board 1 has a flat surface to facilitate bonding with the chip. The substrate solder balls 19 are used for bonding to the printed circuit board, and the side of the substrate solder balls 19 facing away from the core board 1 has a spherical surface to facilitate bonding with the printed circuit board.

[0194] In the packaging substrate structure formed by the above-described manufacturing method, the via pads 5 and the inner circuit layer 12 are stacked perpendicularly. After resin plugging, the inner circuit layer 12 is fabricated using a buried circuit process. First, circuit grooves 6a are etched in the first resin layer 6, and then the inner circuit layer 12 is formed. This allows control over the spacing and width of the circuit grooves 6a. By reducing the spacing and width of the circuit grooves 6a, finer circuits with smaller spacing can be obtained, specifically achieving micron-level circuits. This solves the problem in the prior art where etching the metal layer makes it impossible to obtain finer circuits with smaller spacing.

[0195] In the above-mentioned manufacturing method of the package substrate structure, the hole pad 5 and the inner circuit layer 12 are stacked vertically, and four circuit layers can be formed by two metal layer depositions. Compared with the conventional vertical stacked hole substrate manufacturing process in the prior art, which requires two metallizations to manufacture two metal circuit layers, this method improves processing efficiency, shortens the process flow, increases wiring density, and reduces the number of wiring layers.

[0196] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0197] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A packaging substrate structure, characterized in that, include: A core board having a plurality of through holes, the core board including a first surface and a second surface opposite to each other along its thickness direction; A first seed layer covers the inner wall of the through hole, the area around the opening of the through hole, and local areas of the first and second surfaces. The core board circuit layer, the via pad, and the metal conductive layer, wherein the via pad covers the first seed layer in the area surrounding the via opening, the metal conductive layer covers the first seed layer on the inner wall of the via, and the core board circuit layer covers the first seed layer in the remaining areas. A first resin layer fills the gap between the through-holes and the circuit layer of the core board. Multiple circuit grooves are formed on the side of the first resin layer away from the core board, with the grooves opposite the via pads being through grooves and the remaining grooves being blind grooves. The first resin layer includes a resin layer that fills the through-holes of the core board, is formed on the first and second surfaces, and is flush with the circuit layer and the via pads, and another resin layer formed on the surfaces of the resin layer, the circuit layer, and the via pads. The circuit grooves are formed using dry etching. The resin layer that fills the through-holes of the core board, is formed on the first and second surfaces, and is flush with the circuit layer and the via pads, is formed using chemical mechanical polishing. A second seed layer and an inner circuit layer are stacked together. The second seed layer covers the inner wall of the circuit groove of the first resin layer, and the inner circuit layer covers the side surface of the second seed layer away from the core board. The inner circuit layer is embedded in the circuit groove. The surface of the inner circuit layer is flush with the first resin layer. At least one multilayer composite structure is disposed on the side of the inner circuit layer away from the core board. The multilayer composite structure includes a second resin layer, a third seed layer and a circuit layer disposed sequentially in the direction away from the core board. The second resin layer has a through hole. The third seed layer and the circuit layer are stacked on the side of the second resin layer away from the core board. A solder resist layer is disposed on the side of the multilayer composite structure opposite to the core board; Solder ball, wherein the solder ball is disposed on the solder resist layer, and the bottom of the solder ball penetrates the solder resist layer and contacts the outermost circuit layer.

2. The packaging substrate structure according to claim 1, characterized in that, The first resin layer and / or the second resin layer comprise ABF resin and / or RCC.

3. The packaging substrate structure according to claim 1, characterized in that, The first seed layer, the second seed layer, and / or the third seed layer each include at least one sub-metal layer; or, The first seed layer, the second seed layer, and / or the third seed layer include multiple sub-metal layers, and the materials of the multiple sub-metal layers are different.

4. The packaging substrate structure according to claim 3, characterized in that, The sub-metal layer is made of titanium, copper, or tungsten.

5. The packaging substrate structure according to claim 1, characterized in that, The solder balls include chip solder balls and substrate solder balls. The chip solder balls are disposed on the solder resist layer on one side of the core board, and the substrate solder balls are disposed on the solder resist layer on the other side of the core board. The chip solder balls are used for bonding with the chip, and the substrate solder balls are used for bonding with the printed circuit board.

6. A method for manufacturing a packaging substrate structure, characterized in that, include: The core board has openings, with multiple through holes formed on it, and the core board has opposing first and second surfaces; A first seed layer is formed on the surface of the core plate with through holes; A first mask is formed on the surface of the structure formed in the previous step. The first mask has a hollow structure. The hollow structure of the first mask is at least opposite to the through hole of the structure formed in the previous step and the area around the opening of the through hole. A core board circuit layer, via pads, and a conductive metal layer are formed. A first metal layer is formed within the cutout structure of the first mask, and the first metal layer covers the inner wall of the via and the area around the via opening. The first metal layer in the area around the via opening forms the via pads. The first metal layer covering the inner wall of the via forms the conductive metal layer. The first metal layer at the remaining locations, except for the inner wall of the via and the area around the via opening, forms the core board circuit layer. Remove the first mask and the first seed layer covered by the first mask; The through holes are plugged and resin is pressed in, and resin is pressed in on both the first and second surfaces of the core board so that the resin fills the gap between the through holes and the circuit layer of the core board, and a first resin layer is formed on the first and second surfaces of the structure formed in the previous step. The plugging and pressing resin comprises: The through holes are plugged by pressing resin onto both the first and second surfaces of the core board to fill the gaps between the through holes and the circuit layers of the core board. The resin layer is thinned so that it does not cover the core board circuit layer and the via pads. The thinned resin layer is flush with the via pads and the core board circuit layer, or the core board circuit layer and the via pads are higher than the resin layer. The thinned resin layer includes: thinning the resin layer by chemical mechanical polishing so that it does not cover the core board circuit layer and the via pads. The resin is pressed again to form the first resin layer; The circuit grooves are formed by dry etching, and multiple circuit grooves are formed on the first resin layer. The circuit grooves opposite to the through holes extend from the first resin layer to the hole pad. A second seed layer is formed on the surface of the structure formed in the previous step; A second metal layer is formed on the surface of the second seed layer; An inner circuit layer is formed by removing the portion of the second metal layer that is not embedded in the circuit groove, and retaining the portion of the second metal layer embedded in the circuit groove to form the inner circuit layer; the surface of the inner circuit layer is flush with the first resin layer. A second resin layer is formed by pressing resin onto both the first and second surfaces of the structure formed in the previous step to form the second resin layer. Drill holes to create through holes in the second resin layer; A third seed layer is formed on the surface of the structure formed in the previous step; A fourth mask is formed on the surface of the structure formed in the previous step; A circuit layer is formed within the cutout structure of the fourth mask; Remove the fourth mask and the third seed layer that is covered by the fourth mask; Repeat the steps at least once to form the second resin layer until the fourth mask and the third seed layer covered by the fourth mask are removed, in order to form at least one circuit layer; Solder resist layers are formed on the first and second surfaces of the structure formed in the previous step, and the solder resist layers have connection holes corresponding to the circuit layers; Ball placement involves soldering balls onto the first and / or second surfaces of the structure formed in the previous step.

7. The method for manufacturing the packaging substrate structure according to claim 6, characterized in that, The resin used in the plugging and pressing resin step includes ABF resin and / or RCC.

8. The method for manufacturing the packaging substrate structure according to claim 6, characterized in that, The step of forming the line groove includes: A metal protective layer is formed on both the first and second surfaces of the structure formed in the previous step. A second mask is formed on the surface of the structure formed in the previous step, and the second mask has a hollow structure. Remove the metal protective layer that is not covered by the second mask; The first and second surfaces of the structure formed in the previous step are etched to form a circuit groove, the depth of which extends from the metal protective layer to the first resin layer, and the second mask is removed. A third mask is formed on the surface of the structure formed in the previous step, and the hollow structure of the third mask is opposite to the opening of the through hole and the surrounding area. The first and second surfaces of the structure formed in the previous step are etched to deepen the circuit grooves opposite to the orifice and surrounding area of ​​the via. The circuit grooves opposite to the via extend from the metal protective layer to the orifice pad, and the third mask is removed. Remove the metal protective layer.

9. The method for manufacturing the packaging substrate structure according to claim 6, characterized in that, The step of forming the inner circuit layer involves removing the portion of the second metal layer that is not embedded in the circuit groove, specifically by using chemical mechanical polishing to remove the portion of the second metal layer that is not embedded in the circuit groove.

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