Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem that a semi-conductive structure is easy to short-circuit. The semiconductor structure comprises a substrate, a first dielectric layer and a second dielectric layer which are stacked, the at least two layers of conductive structures are arranged in the second dielectric layer at intervals; a plug connected between each conductive structure and the substrate; the at least two layers of conductive structures are sequentially arranged in the direction away from the substrate, and in every two adjacent layers of conductive structures, the top face of the layer of conductive structure close to the substrate is lower than the bottom face of the layer of conductive structure away from the substrate. The distance between the conductive structures on the same layer is increased, and the two adjacent conductive structures are separated, so that bridging of the conductive structures on the same layer and bridging of the conductive structures on different layers are reduced, and short circuit of the semiconductor structure is avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, semiconductor devices are increasingly used. In the fields of computers, communications, etc., semiconductor devices with different functions are needed. However, as the semiconductor structure process is miniaturized, the conductive structure in the semiconductor structure is also miniaturized, and the spacing between the conductive structures is also reduced. The conductive structures are easily bridged, causing the semiconductor structure to short-circuit and fail. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce short circuits in the semiconductor structure.

[0004] According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure comprising:

[0005] A substrate, a first dielectric layer, and a second dielectric layer are stacked;

[0006] At least two layers of conductive structures are arranged in the second dielectric layer and are spaced apart from each other;

[0007] a plug connected between each of the conductive structures and the substrate;

[0008] The at least two layers of conductive structures are arranged in sequence in a direction away from the substrate, and among two adjacent layers of conductive structures, a top surface of a layer of conductive structures close to the substrate is lower than a bottom surface of a layer of conductive structures away from the substrate.

[0009] In some possible embodiments, the second dielectric layer includes a plurality of layers stacked sequentially in a direction away from the substrate, and the number of the layers is greater than or equal to the number of layers of the conductive structure;

[0010] One layer of the conductive structure is correspondingly arranged in one of the layers and contacts the adjacent layers. Except for the outermost conductive structure located away from the substrate, the top surface of each of the other conductive structures is lower than the top surface of the corresponding layer.

[0011] In some possible embodiments, the conductive structures of different layers have a partially overlapping area in the orthographic projection of the substrate.

[0012] In some possible embodiments, each layer of the conductive structure includes at least one conductive element, and the ratio of an overlap area between the conductive elements of different layers on the orthographic projection of the substrate to an area of ​​the orthographic projection of the conductive element on the substrate is less than or equal to 0.2.

[0013] In some possible embodiments, the second dielectric layer includes a first layer and a second layer, the at least two layers of conductive structures include a first conductive structure and a second conductive structure, and the plug includes a first plug electrically connected to the first conductive structure and a second plug electrically connected to the second conductive structure;

[0014] The first conductive structure is arranged in the first layer, and the top surface of the first conductive structure is lower than the top surface of the first layer, the second layer is arranged on the first conductive structure and the first layer, the second conductive structure is arranged in the second layer, and the second conductive structure is located on the top surface of the first layer, the top surface of the first plug is lower than the top surface of the first layer and higher than the bottom surface of the first layer, and the top surface of the second plug is flush with the top surface of the first layer.

[0015] In some possible embodiments, the material of the second layer includes a low dielectric constant material, and a height difference between a top surface of the first conductive structure and a bottom surface of the second conductive structure is greater than or equal to 5 nm.

[0016] In some possible embodiments, a top surface of the plug contacts a bottom surface of the conductive structure, and a bottom surface of the plug is located in the substrate, and bottom surfaces of the plug connecting conductive structures of different layers are flush.

[0017] In some possible embodiments, the semiconductor structure further includes:

[0018] A gate structure located in the first dielectric layer, wherein a top surface of the gate structure is flush with a top surface of the first dielectric layer and is lower than a bottom surface of the conductive structure at the innermost layer close to the substrate;

[0019] The substrate includes a first source-drain region and a second source-drain region located at two sides of the gate structure, and the first source-drain region and the second source-drain region are respectively in contact with the plug.

[0020] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate, a first dielectric layer and a second dielectric layer, at least two layers of conductive structures arranged in the second dielectric layer and spaced apart from each other, and a plug connected between each conductive structure and the substrate. The at least two layers of conductive structures are arranged in sequence in a direction away from the substrate, so that the spacing between the conductive structures in the same layer increases, so as to reduce the bridging of the conductive structures in the same layer, and avoid the semiconductor structure from short-circuiting and failing. In the two adjacent layers of conductive structures, the top surface of the conductive structure close to the substrate is lower than the bottom surface of the conductive structure away from the substrate, so as to separate the two adjacent layers of conductive structures, avoid bridging of the conductive structures in different layers, and further avoid the semiconductor structure from short-circuiting and failing.

[0022] According to some embodiments, a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, which includes:

[0023] forming a first dielectric layer on a substrate, wherein the first dielectric layer covers the substrate;

[0024] A first layer, a first conductive structure located in the first layer, a first plug connecting the first conductive structure and the substrate, and a second layer located on the first layer and the first conductive structure, a second conductive structure located in the second layer, and a second plug connecting the second conductive structure and the substrate are formed on the first dielectric layer. The top surface of the first conductive structure is lower than the bottom surface of the second conductive structure. The first layer and the second layer form a second dielectric layer.

[0025] In some possible embodiments, forming a first layer on the first dielectric layer, a first conductive structure in the first layer, a first plug connecting the first conductive structure and the substrate, and a second layer on the first layer and the first conductive structure, a second conductive structure in the second layer, and a second plug connecting the second conductive structure and the substrate includes:

[0026] forming a first layer on the first dielectric layer, wherein the first layer covers the first dielectric layer;

[0027] Removing part of the first layer and part of the first dielectric layer to form a plurality of contact holes arranged at intervals, wherein the plurality of contact holes all expose the substrate;

[0028] Removing part of the first layer to form a first groove connected to part of the contact holes, the contact holes located at the bottom of the first groove form first plug holes, and the remaining contact holes form second plug holes;

[0029] forming a conductive layer filled in the first plug hole, the second plug hole, the first groove and located on the first layer, wherein the conductive layer located in the first plug hole forms the first plug, and the conductive layer located in the second plug hole forms the second plug;

[0030] removing part of the conductive layer, so that the remaining conductive layer in the first groove forms the first conductive structure, and the remaining conductive layer on the first layer forms the second conductive structure, wherein the top surface of the first conductive structure is lower than the top surface of the first layer, and the first conductive structure and the second conductive structure are spaced apart along a first direction;

[0031] A second layer is formed on the first layer and the first conductive structure, wherein the second layer exposes a top surface of the second conductive structure.

[0032] In some possible embodiments, forming a first layer on the first dielectric layer, a first conductive structure in the first layer, a first plug connecting the first conductive structure and the substrate, and a second layer on the first layer and the first conductive structure, a second conductive structure in the second layer, and a second plug connecting the second conductive structure and the substrate includes:

[0033] forming a first layer on the first dielectric layer, wherein the first layer covers the first dielectric layer;

[0034] Removing part of the first layer and part of the first dielectric layer to form a plurality of contact holes arranged at intervals, wherein the plurality of contact holes all expose the substrate;

[0035] Removing part of the first layer to form a first groove connected to part of the contact holes, the contact holes located at the bottom of the first groove form first plug holes, and the remaining contact holes form second plug holes;

[0036] Depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove, so that the conductive material in the first plug hole forms a first plug, and the conductive material in the first groove forms a first conductive structure, wherein a top surface of the first conductive structure is lower than a top surface of the first layer;

[0037] forming a second layer, wherein the second layer covers the first conductive structure, the second plug and the first layer;

[0038] removing a portion of the second layer to form a second groove, wherein the second groove exposes the second plug and at least exposes a portion of the first layer;

[0039] A conductive material is deposited at least in the second groove, the conductive material in the second groove forms the second conductive structure, and the conductive material in the second plug hole forms a second plug.

[0040] In some possible embodiments, depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove includes:

[0041] Depositing a conductive material in the first plug hole, in the second plug hole, in the first groove, and on the first layer;

[0042] removing the conductive material on the first layer to expose the first layer;

[0043] The conductive material in the first groove and the second plug hole is etched back, wherein the width of the first groove along the first direction is greater than the width of the second plug hole along the first direction, and the top surface of the conductive material remaining in the first groove is made lower than the top surface of the conductive material remaining in the second plug hole by utilizing the load effect of etching.

[0044] In some possible embodiments, depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove includes:

[0045] Depositing a conductive material in the first plug hole, in the second plug hole, in the first groove, and on the first layer;

[0046] removing the conductive material on the first layer to expose the first layer;

[0047] forming a protective layer on the conductive material in the second plug hole, wherein the protective layer is spaced apart from the first groove;

[0048] Etching a portion of the conductive material in the first groove so that a top surface of the remaining conductive material in the first groove is lower than a top surface of the first layer;

[0049] The protection layer is removed to expose the conductive material in the second plug hole.

[0050] In some possible embodiments, an orthographic projection of the first groove on the substrate and an orthographic projection of the second groove on the substrate have a partially overlapping area.

[0051] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0052] In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, a first dielectric layer is formed on a substrate, and a first layer is formed on the first dielectric layer, a first conductive structure is formed in the first layer, a first plug is formed to connect the first conductive structure and the substrate, a second layer is formed on the first layer and the first conductive structure, a second conductive structure is formed in the second layer, and a second plug is formed to connect the second conductive structure and the substrate. The first conductive structure and the second conductive structure are respectively arranged in the first layer and the second layer, so that the spacing between the internal structures of the first conductive structure increases, and the distance between the internal structures of the second conductive structure increases, thereby reducing the bridging in the first conductive structure and the bridging in the second conductive structure, and avoiding the semiconductor structure from short-circuiting and failing. The top surface of the first conductive structure is lower than the bottom surface of the second conductive structure, that is, the second conductive structure and the first conductive structure have a spacing in the direction away from the substrate, so as to separate the first conductive structure and the second conductive structure, avoid bridging between the first conductive structure and the second conductive structure, and further avoid the semiconductor structure from short-circuiting and failing. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a schematic diagram of a semiconductor structure in the related art;

[0054] Figure 2 is a schematic structural diagram of a semiconductor structure in an embodiment of the present disclosure;

[0055] Figure 3 is another structural schematic diagram of a semiconductor structure in an embodiment of the present disclosure;

[0056] Figure 4 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0057] Figure 5 It is a schematic diagram of the structure after the first layer is formed in one embodiment of the present disclosure;

[0058] Figure 6 is a schematic diagram of a structure after a contact hole is formed in an embodiment of the present disclosure;

[0059] Figure 7 It is a schematic diagram of the structure after the first groove is formed in one embodiment of the present disclosure;

[0060] Figure 8 is a schematic diagram of a structure after a conductive layer is formed in one embodiment of the present disclosure;

[0061] Fig. 9 is a schematic diagram of a structure after forming a first conductive structure and a second conductive structure in an embodiment of the present disclosure;

[0062] Fig.10 It is a schematic diagram of the structure after the second layer is formed in one embodiment of the present disclosure;

[0063] Fig.11 is a schematic diagram of a process of forming a contact hole in an embodiment of the present disclosure;

[0064] Fig.12 is a schematic diagram of a structure after a conductive material is formed in an embodiment of the present disclosure;

[0065] Fig.13 It is a schematic diagram of the structure after the second layer is formed in one embodiment of the present disclosure;

[0066] Fig.14 is a schematic diagram of a structure after a second groove is formed in an embodiment of the present disclosure;

[0067] Fig.15 is a schematic structural diagram after forming a second conductive structure in an embodiment of the present disclosure;

[0068] Fig.16 It is a schematic diagram of a structure after a portion of the conductive material is removed in one embodiment of the present disclosure;

[0069] Fig.17 It is a schematic diagram of the structure after forming a protective layer in one embodiment of the present disclosure.

[0070] Description of reference numerals:

[0071] 10-substrate; 20-first dielectric layer;

[0072] 30-second dielectric layer; 31-first layer;

[0073] 32-second layer; 33-first groove;

[0074] 34-second groove; 40-contact hole;

[0075] 41-first plug hole; 42-second plug hole;

[0076] 51-conductive layer; 52-conductive material;

[0077] 61-first plug; 62-second plug;

[0078] 70-conductive structure; 71-first conductive structure;

[0079] 72-second conductive structure; 80-protective layer;

[0080] 90-gate structure. DETAILED DESCRIPTION

[0081] There is a problem in the related art that the semiconductor structure is prone to short circuit. The inventor has found that the reason is: Figure 1The conductive structures 70 are usually arranged in the same layer. As the semiconductor structure is miniaturized and the integration level is improved, the distance between the conductive structures 70 is also reduced. It is easy for adjacent conductive structures 70 to be bridged or even burned out, making the semiconductor structure prone to short circuit and affecting the performance of the semiconductor structure.

[0082] To this end, the embodiment of the present disclosure provides a semiconductor structure, including a stacked substrate, a first dielectric layer, and a second dielectric layer, wherein the second dielectric layer has at least two layers of conductive structures, and the at least two layers of conductive structures are arranged in sequence in a direction away from the substrate. Among the at least two layers of conductive structures, the top surface of a layer of conductive structures close to the substrate is lower than the bottom surface of a layer of conductive structures away from the substrate, so as to separate the two adjacent layers of conductive structures and avoid bridging of the two adjacent layers of conductive structures. In addition, the layered arrangement of the conductive structures can also reduce the internal bridging of the conductive structures in the same layer to avoid short circuits in the semiconductor structure.

[0083] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0084] See also Figure 2 The present disclosure provides a semiconductor structure, which includes a substrate 10, a first dielectric layer 20, a second dielectric layer 30, at least two conductive structures, and a plug connected between each conductive structure and the substrate 10. The substrate 10 provides support and is used to form a device structure. The substrate 10 may include a base layer and a barrier layer disposed on the base layer, the base layer may be made of semiconductor materials such as silicon, germanium, and silicon germanium, and the barrier layer may be made of silicon nitride, silicon oxynitride, and the like.

[0085] The substrate 10, the first dielectric layer 20 and the second dielectric layer 30 are stacked in sequence, that is, the first dielectric layer 20 is disposed on the substrate 10, and the second dielectric layer 30 is disposed on the first dielectric layer 20. The first dielectric layer 20 and the second dielectric layer 30 are both insulated, and the first dielectric layer 20 and the second dielectric layer 30 are made of different materials, for example, the first dielectric layer 20 is an oxide layer, and the second dielectric layer 30 is a nitride layer.

[0086] At least two layers of conductive structures are arranged in the second dielectric layer 30, for example, two layers or three layers. The at least two layers of conductive structures are arranged in a direction away from the substrate 10 ( Figure 2In this way, the conductive structures are arranged in different layers, that is, the conductive structures are arranged in a staggered manner away from the substrate 10, so that the spacing between the conductive structures in the same layer is increased to reduce the bridging of the conductive structures in the same layer and avoid short circuit and failure of the semiconductor structure.

[0087] In two adjacent conductive structures, the top surface of a conductive structure close to the substrate 10 is lower than the bottom surface of a conductive structure away from the substrate 10. In this way, the two adjacent conductive structures have a gap in the direction away from the substrate 10 to separate the two adjacent conductive structures, thereby reducing the bridging of the two adjacent conductive structures and further preventing the semiconductor structure from short-circuiting and failing.

[0088] Wherein, each layer of the conductive structure may have one or more conductive members. When there are at least two conductive members in the same layer, at least two conductive members are arranged along the first direction ( Figure 2 The first direction is parallel to the substrate 10. The conductive member may be in block, column or strip shape. At least part of the conductive member may include a tungsten layer and a diffusion barrier layer covering the side and bottom of the tungsten layer.

[0089] In some examples, in two adjacent conductive structures, the top surface of the conductive structure of one layer close to the substrate 10 is flush with or slightly lower than the bottom surface of the conductive structure of one layer away from the substrate 10. The conductive structure of one layer away from the substrate 10 may include a first portion and a second portion stacked in a direction away from the substrate 10, and the size of the first portion along the first direction is smaller than the size of the second portion along the first direction, and the size of the first portion is smaller than the spacing between adjacent conductive members of the two adjacent conductive structures of one layer close to the substrate 10.

[0090] The number of conductive components in different layers of conductive structures may be different. For example, in a two-layer conductive structure, the number of conductive components in a layer of conductive structure (lower conductive structure) close to the substrate 10 is greater than the number of conductive components in another layer of conductive structure (upper conductive structure) away from the substrate 10.

[0091] In some examples, the orthographic projections of conductive structures of different layers on the substrate 10 may not overlap, that is, the orthographic projections of each conductive element on the substrate 10 are spaced apart to facilitate the production of each layer of conductive structures and avoid bridging of conductive elements in two adjacent layers of conductive structures.

[0092] In other examples, the conductive structures of different layers have a partially overlapping area in the orthographic projection on the substrate 10, that is, the conductive elements of different layers have a partially overlapping area in the orthographic projection on the substrate 10. In this way, at least part of the conductive elements in any layer of the conductive structure can extend to the top (or bottom) of at least one conductive element in the conductive structure of other layers, that is, at least part of the conductive elements of different layers are directly opposite to each other, so that the conductive elements of different layers can be staggered along the first direction (left-right direction) to improve the integration of the conductive structure.

[0093] Based on the above example, the ratio of the overlapping area between the orthographic projections of conductive elements of different layers on the substrate 10 to the area of ​​the orthographic projections of the conductive elements on the substrate 10 is less than or equal to 0.2, that is, the area of ​​the overlapping area between the orthographic projections of any conductive element on the substrate 10 and the orthographic projections of other conductive elements on the substrate 10 does not exceed 0.2 times the area of ​​the orthographic projections of the conductive element on the substrate 10, so as to avoid too many relative areas of the conductive elements in the direction perpendicular to the substrate 10 and generate a large parasitic capacitance.

[0094] For example, when two conductive members in different layers partially face each other in a direction perpendicular to the substrate 10, the area of ​​the overlapped region between the orthographic projections of the two conductive members on the substrate 10 is less than or equal to 0.2 times the area of ​​the orthographic projection of each of the two conductive members on the substrate 10. That is, if a conductive member of one layer only faces a portion of a conductive member of another layer, then the projection area of ​​the facing region on the substrate 10 is less than 0.2 times the projection area of ​​each of the facing conductive members on the substrate 10.

[0095] For another example, when two or more conductive elements in different layers partially face each other in a direction perpendicular to the substrate 10, the projected area of ​​each conductive element facing other conductive elements on the substrate 10 is less than or equal to 0.2 times the projected area of ​​the conductive element on the substrate 10. Figure 3 , the upper conductive member and the two conductive members of the lower layer partially face each other in the direction perpendicular to the substrate 10, that is, the left and right ends of the upper conductive member both extend above the two conductive members of the lower layer. The orthographic projections of these three conductive members on the substrate 10 have two overlapping areas, such as Figure 3 As shown at A and B. Each conductive member of the lower layer corresponds to one overlapping area, and the area ratio of the orthographic projection of each conductive member of the lower layer on the substrate 10 to the corresponding overlapping area is greater than or equal to 5. That is, the area ratio of the orthographic projection of the conductive member on the left side on the substrate 10 to the overlapping area on the left side (A) is greater than or equal to 5, and the area ratio of the orthographic projection of the conductive member on the right side on the substrate 10 to the overlapping area on the right side (B) is greater than or equal to 5. The conductive member of the upper layer corresponds to two overlapping areas (A and B), and the area ratio of the orthographic projection of the conductive member of the upper layer on the substrate 10 to the two overlapping areas is greater than or equal to 5.

[0096] Continue reading Figure 3 In order to facilitate the manufacture of the multi-layer conductive structure, the second dielectric layer 30 includes a plurality of layers stacked in sequence in a direction away from the substrate 10, and the number of layers is greater than or equal to the number of layers of the conductive structure. One layer of conductive structure is correspondingly arranged in one layer and is in contact with the adjacent layer. Except for the outermost conductive structure located away from the substrate 10, the top surface of each layer of the remaining conductive structure is lower than the top surface of the corresponding layer.

[0097] The number of layers is greater than or equal to the number of layers of the conductive structure, so that each layer of the conductive structure can be arranged in one layer. In order to improve the space utilization of the semiconductor structure, the number of layers is equal to the number of the conductive structure, so that each layer is provided with a conductive structure, thereby avoiding vacancy in the layer and reducing the thickness of the second dielectric layer 30.

[0098] The materials of the multiple layers can be different, for example, some layers are low-k materials to reduce parasitic capacitance between conductive structures. In other examples, the materials of the multiple layers are the same so that the multiple layers are integrated to reduce the separation between the layers. Low-k materials include silicon oxycarbon nitride (SiONC), silicon oxycarbide (SiOC) and silicon carbide (SiC).

[0099] The conductive structure disposed in a layer contacts the adjacent layer, for example, the conductive structure of the innermost layer (bottommost layer) close to the substrate 10 contacts the layer above it, and the conductive structure of the outermost layer (topmost layer) away from the substrate 10 contacts the layer below it. When the number of layers of the conductive structure is greater than or equal to 3, the conductive structure located in the middle layer contacts both the layer above it and the layer below it.

[0100] It can be understood that the bottom surface of the bottommost conductive structure is located in the corresponding layer to avoid exposing the bottom surface of the conductive structure of this layer, thereby ensuring a certain distance between the conductive structure and the first dielectric layer 20 to separate the conductive structure from the first dielectric layer 20. Except for the bottommost conductive structure, the top and bottom surfaces of each other conductive structure are exposed.

[0101] Among them, except for the outermost (top) conductive structure located far away from the substrate 10, the top surface of each other conductive structure is lower than the top surface of the corresponding layer, that is, the top surface of the topmost conductive structure can be flush with the top surface of the corresponding layer, and the top surface of each other conductive structure is lower than the top surface of the corresponding layer, so that two adjacent layers are partially staggered in the direction perpendicular to the substrate 10 to ensure insulation isolation between the two adjacent conductive structures and avoid bridging.

[0102] Continue reading Figure 3The plug is used to connect the substrate 10 and the corresponding conductive structure, and penetrates the first dielectric layer 20 and the second dielectric layer 30 located below the corresponding conductive structure. The plug can be a conductive column, and the material of the plug can be the same as that of the conductive structure, so that the plug and the conductive structure are integrated, which can reduce the contact resistance between the plug and the conductive structure on the one hand, and facilitate the manufacturing of the plug and the conductive structure together on the other hand.

[0103] like Figure 3 As shown, the top surface of the plug contacts the bottom surface of the conductive structure, and the bottom surface of the plug is located in the substrate 10, and the bottom surfaces of the plugs connecting the conductive structures of different layers are flush. The top surface of the plug contacts the bottom surface of the corresponding conductive structure, for example, the orthographic projection of the conductive structure on the substrate 10 covers the orthographic projection of the corresponding plug on the substrate 10, so as to ensure the contact area between the corresponding conductive structure and the plug. The bottom surface of the plug is located in the substrate 10, that is, the plug extends into the substrate 10, so as to increase the contact area between the plug and the substrate 10. The bottom surfaces of the plugs are flush, so that the plug holes accommodating the plugs can be formed together, simplifying the manufacturing steps of the plug holes.

[0104] In some specific examples, such as Figure 3 and Figure 2 As shown, the second dielectric layer 30 includes a first layer 31 and a second layer 32 , the at least two conductive structures include a first conductive structure 71 and a second conductive structure 72 , and the plug includes a first plug 61 electrically connected to the first conductive structure 71 and a second plug 62 electrically connected to the second conductive structure 72 .

[0105] The first conductive structure 71 is disposed in the first layer 31, and the top surface of the first conductive structure 71 is lower than the top surface of the first layer 31. The second layer 32 is disposed on the first conductive structure 71 and the first layer 31. The second conductive structure 72 is disposed in the second layer 32, and the second conductive structure 72 is located on the top surface of the first layer 31.

[0106] The top surface of the first conductive structure 71 is lower than the top surface of the first layer 31, and the top surface of the first conductive structure 71 is exposed, and the bottom surface of the first conductive structure 71 is higher than the bottom surface of the first layer 31. The second layer 32 covers the top surface of the first conductive structure 71 and the top surface of the first layer 31, and the material of the second layer 32 is different from that of the first layer 31, and the material of the second layer 32 includes a low dielectric constant material. The second conductive structure 72 is located in the second layer 32, and the top surface of the second conductive structure 72 is flush with the top surface of the second layer 32 and exposed. The bottom surface of the second conductive structure 72 contacts the top surface of the first layer 31, and the height difference between the bottom surface of the second conductive structure 72 and the top surface of the first conductive structure 71 is greater than or equal to 5nm.

[0107] The first plug 61 connects the first conductive structure 71 and the substrate 10, and the second plug 62 connects the second conductive structure 72 and the substrate 10. The top surface of the first plug 61 is lower than the top surface of the first layer 31 and higher than the bottom surface of the first layer 31, and the top surface of the second plug 62 is flush with the top surface of the first layer 31. The first plug 61 and the second plug 62 have different heights to respectively adapt to the first conductive structure 71 and the second conductive structure 72.

[0108] Continue reading Figure 3 The semiconductor structure further includes a gate structure 90, which is located in the first dielectric layer 20. The top surface of the gate structure 90 is flush with the top surface of the first dielectric layer 20, and the top surface of the gate structure 90 is lower than the bottom surface of the innermost conductive structure close to the substrate 10. The gate structure 90 includes a gate dielectric layer, a gate conductive layer, and a capping layer covering the gate dielectric layer and the gate conductive layer.

[0109] The substrate 10 further includes a first source and drain region and a second source and drain region, which are respectively located on both sides of the gate structure 90, and the first source and drain region and the second source and drain region are respectively in contact with the plug. A channel region is connected between the first source and drain region and the second source and drain region is opposite to the gate structure 90. The first source and drain region, the second source and drain region, the channel region and the gate structure 90 form a transistor, and the transistor is externally connected through the plug.

[0110] In summary, the semiconductor structure in the embodiment of the present disclosure includes a substrate 10, a first dielectric layer 20 and a second dielectric layer 30, at least two layers of conductive structures disposed in the second dielectric layer 30 and spaced apart from each other, and a plug connected between each conductive structure and the substrate 10. The at least two layers of conductive structures are arranged in sequence in a direction away from the substrate 10, so that the spacing between the conductive structures in the same layer increases, so as to reduce the bridging of the conductive structures in the same layer, and avoid the semiconductor structure from short-circuiting and failing. In the two adjacent layers of conductive structures, the top surface of the conductive structure close to the substrate 10 is lower than the bottom surface of the conductive structure away from the substrate 10, so as to separate the two adjacent layers of conductive structures, so as to avoid the bridging of the two adjacent layers of conductive structures, and further avoid the semiconductor structure from short-circuiting and failing.

[0111] See also Figure 4 The present disclosure also provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0112] Step S100: forming a first dielectric layer on a substrate, wherein the first dielectric layer covers the substrate.

[0113] See also Figure 5, a first dielectric layer 20 is deposited on the substrate 10. The substrate 10 may include a base layer and a barrier layer (not shown) covering the base layer, the base layer may be made of silicon, germanium, silicon germanium, etc., the barrier layer may be made of silicon nitride or silicon oxynitride, etc., and the first dielectric layer 20 may be an oxide layer, such as a silicon oxide layer.

[0114] Step S200: forming a first layer on the first dielectric layer, a first conductive structure in the first layer, a first plug connecting the first conductive structure and the substrate, and a second layer on the first layer and the first conductive structure, a second conductive structure in the second layer, and a second plug connecting the second conductive structure and the substrate, wherein the top surface of the first conductive structure is lower than the bottom surface of the second conductive structure, and the first layer and the second layer form a second dielectric layer.

[0115] See also Figure 5 and Figure 2 , forming a first layer 31, a first conductive structure 71, a first plug 61, a second layer 32, a second conductive structure 72 and a second plug 62. The first layer 31 covers the first dielectric layer 20, the first conductive structure 71 is formed in the first layer 31, and the top surface of the first conductive structure 71 is exposed. The top surface of the first conductive structure 71 can be lower than the top surface of the first layer 31, and the bottom surface of the first conductive structure 71 is higher than the bottom surface of the first layer 31, so that part of the first layer 31 is located below the first conductive structure 71, thereby ensuring that the first conductive structure 71 is spaced apart from the first dielectric layer 20.

[0116] The second layer 32 is located on the first layer 31 and the first conductive structure 71, that is, the second layer 32 covers the first layer 31 and the first conductive structure 71. In the example where the top surface of the first conductive structure 71 is lower than the top surface of the first layer 31, the top surface of the first conductive structure 71 is covered with the second layer 32 to ensure isolation of the first conductive structure 71. The second layer 32 and the first layer 31 form the second dielectric layer 30.

[0117] The material of the second layer 32 can be the same as that of the first layer 31, for example, both are silicon nitride, so that the first layer 31 and the second layer 32 form a whole. The material of the second layer 32 can also be different from that of the first layer 31, for example, the material of the first layer 31 is silicon nitride, and the material of the second layer 32 is a low dielectric constant material, so as to reduce the parasitic capacitance in the second layer 32.

[0118] The second conductive structure 72 is disposed in the second layer 32, and the bottom surface of the second conductive structure 72 is higher than the top surface of the first conductive structure 71. For example, the height difference between the bottom surface of the second conductive structure 72 and the top surface of the first conductive structure 71 is greater than or equal to 5 nm. In this way, the second conductive structure 72 and the first conductive structure 71 are spaced apart in a direction away from the substrate 10, so as to separate the first conductive structure 71 and the second conductive structure 72, avoid bridging of the first conductive structure 71 and the second conductive structure 72, and avoid short circuit and failure of the semiconductor structure.

[0119] The top and bottom surfaces of the second conductive structure 72 are exposed. For example, the bottom surface of the second conductive structure 72 may be flush with the top surface of the first layer 31, and the top surface of the second conductive structure 72 may be flush with the top surface of the second layer 32. The second conductive structure 72 is disposed in the second layer 32, and the first conductive structure 71 is disposed in the first layer 31. The second conductive structure 72 and the first conductive structure 71 are disposed in different layers, so that the spacing between the structures in the first conductive structure 71 is increased, and the distance between the structures in the second conductive structure 72 is increased, thereby reducing the bridging in the first conductive structure 71 and the bridging in the second conductive structure 72, and preventing the semiconductor structure from short-circuiting and failing.

[0120] The orthographic projections of the second conductive structure 72 and the first conductive structure 71 on the substrate 10 have a partially overlapping area, that is, the second conductive structure 72 and the first conductive structure 71 have a partial area facing each other, so as to improve the space utilization rate of the semiconductor structure. The second conductive structure 72 and the first conductive structure 71 may each include at least one conductive member, and the area ratio of the overlapping area of ​​the conductive member in the second conductive structure 72 and the conductive member in the first conductive structure 71 on the orthographic projection of the substrate 10 to the area of ​​the conductive member in the second conductive structure 72 or the conductive member in the first conductive structure 71 on the substrate 10 is less than or equal to 0.2, so as to avoid the first conductive structure 71 and the second conductive structure 72 facing each other too much and generating a large parasitic capacitance.

[0121] The first plug 61 penetrates the first dielectric layer 20 and the first layer 31 located below the first conductive structure 71 to connect the first conductive structure 71 and the substrate 10. For example, the top surface of the first plug 61 contacts the bottom surface of the first conductive structure 71, and the bottom surface of the first plug 61 is lower than the top surface of the substrate 10 to increase the contact area between the first plug 61 and the substrate 10.

[0122] The second plug 62 penetrates the first dielectric layer 20 and the first layer 31 to connect the second conductive structure 72 and the substrate 10. For example, the top surface of the second plug 62 contacts the bottom surface of the second conductive structure 72, and the bottom surface of the second plug 62 is lower than the top surface of the substrate 10 to increase the contact area between the second plug 62 and the substrate 10. The bottom surface of the second plug 62 can be flush with the bottom surface of the first plug 61, so that the first plug 61 and the second plug 62 can be manufactured at the same time.

[0123] In summary, in the method for manufacturing the semiconductor structure in the embodiment of the present disclosure, a first dielectric layer 20 is formed on the substrate 10, and a first layer 31 is formed on the first dielectric layer 20, a first conductive structure 71 is formed in the first layer 31, a first plug 61 is formed to connect the first conductive structure 71 and the substrate 10, a second layer 32 is formed on the first layer 31 and the first conductive structure 71, a second conductive structure 72 is formed in the second layer 32, and a second plug 62 is formed to connect the second conductive structure 72 and the substrate 10. The first conductive structure 71 and the second conductive structure 72 are disposed in the first layer 31 and the second layer 32, respectively, so that the spacing of the internal structure of the first conductive structure 71 is increased, and the distance of the internal structure of the second conductive structure 72 is increased, thereby reducing the bridging in the first conductive structure 71 and the bridging in the second conductive structure 72, and preventing the semiconductor structure from failing due to a short circuit. The top surface of the first conductive structure 71 is lower than the bottom surface of the second conductive structure 72, that is, the second conductive structure 72 and the first conductive structure 71 are spaced apart in a direction away from the substrate 10, so as to separate the first conductive structure 71 and the second conductive structure 72, avoid bridging of the first conductive structure 71 and the second conductive structure 72, and further avoid short circuit and failure of the semiconductor structure.

[0124] For some examples, see Figures 5 to 10 , forming a first layer 31, a first conductive structure 71 in the first layer 31, a first plug 61 connecting the first conductive structure 71 and the substrate 10, and a second layer 32 on the first layer 31 and the first conductive structure 71, a second conductive structure 72 in the second layer 32, and a second plug 62 connecting the second conductive structure 72 and the substrate 10 on the first dielectric layer 20 (step S200), including:

[0125] Step S201 : forming a first layer 31 on the first dielectric layer 20 , wherein the first layer 31 covers the first dielectric layer 20 .

[0126] See also Figure 5, a first layer 31 is deposited on the first dielectric layer 20, and the material of the first layer 31 is different from that of the first dielectric layer 20. The material of the first layer 31 may be silicon nitride, and the thickness of the first layer 31 may be 60-70 nm. In this way, the thickness of the first layer 31 is relatively large, so that a first plug 61 and a second plug 62 of different heights can be made in the first layer 31, respectively connecting the staggered first conductive structure 71 and the second conductive structure 72. After the first layer 31 is formed, the top surface of the first layer 31 is planarized, and the thickness of the first layer 31 is retained to be about 60 nm.

[0127] Step S202 : removing a portion of the first layer 31 and a portion of the first dielectric layer 20 to form a plurality of contact holes 40 arranged at intervals, wherein the plurality of contact holes 40 all expose the substrate 10 .

[0128] See also Figure 6 , the first layer 31 and the first dielectric layer 20 are etched to form a plurality of contact holes 40 penetrating the first layer 31 and the first dielectric layer 20. The plurality of contact holes 40 are arranged at intervals and expose the substrate 10. The plurality of contact holes 40 may also extend into the substrate 10 to increase the area of ​​the exposed substrate 10.

[0129] Step S203 : removing part of the first layer 31 to form a first groove 33 communicating with part of the contact holes 40 , the contact holes 40 at the bottom of the first groove 33 form first plug holes 41 , and the remaining contact holes 40 form second plug holes 42 .

[0130] See also Figure 6 , the first layer 31 is etched to form a first groove 33, and the first groove 33 is used to accommodate the first conductive structure 71. The depth of the first groove 33 can be 30nm, and the first groove 33 is connected to a part of the contact hole 40, that is, the first groove 33 and the part of the contact hole 40 have a partial overlap area. For example, the first layer 31 near the part of the contact hole 40 is etched to form the first groove 33.

[0131] When forming the first grooves 33, the number of the first grooves 33 is less than the number of the contact holes 40, the size of the first grooves 33 can be increased, and the intervals between the first grooves 33 can also be increased, so that the size and interval of the conductive layer 51 subsequently formed in the first grooves 33 are larger, thereby reducing the resistance of the conductive layer 51 in the first grooves 33 and reducing the bridging of the conductive layer 51 in the same layer.

[0132] The contact hole 40 connected to the first groove 33 forms a first plug hole 41, and the remaining contact holes 40 form a second plug hole 42, that is, the opening end of the first plug hole 41 is located at the bottom surface of the first groove 33, and the opening end of the second plug hole 42 is located at the top surface of the first layer 31, and the height of the first plug hole 41 is lower than the height of the second plug hole 42.

[0133] Step S204: forming a conductive layer 51 filled in the first plug hole 41, the second plug hole 42, the first groove 33 and located on the first layer 31; the conductive layer 51 located in the first plug hole 41 forms a first plug 61; and the conductive layer 51 located in the second plug hole 42 forms a second plug 62.

[0134] See also Figure 7 and Figure 8 A conductive layer 51 is deposited in the first plug hole 41 , the second plug hole 42 , the first groove 33 , and on the first layer 31 . The conductive layer 51 fills the first plug hole 41 , the second plug hole 42 , the first groove 33 , and covers the first layer 31 .

[0135] The conductive layer 51 can be formed by two-step deposition, for example, the conductive layer 51 in the first plug hole 41, the second plug hole 42 and the first groove 33 is first formed by chemical vapor deposition (CVD) so that the conductive layer 51 can better fill the first plug hole 41, the second plug hole 42 and the first groove 33. The conductive layer 51 on the first layer 31 can be formed by physical vapor deposition (PVD).

[0136] The thickness of the conductive layer 51 on the first layer 31 may be 23 nm. The conductive layer 51 in the first plug hole 41 forms a first plug 61 . The conductive layer 51 in the second plug hole 42 forms a second plug 62 . The top surface of the second plug 62 is higher than that of the first plug 61 .

[0137] Step S205: remove part of the conductive layer 51, and the remaining conductive layer 51 located in the first groove 33 forms a first conductive structure 71, and the remaining conductive layer 51 located on the first layer 31 forms a second conductive structure 72, wherein the top surface of the first conductive structure 71 is lower than the top surface of the first layer 31, and the first conductive structure 71 and the second conductive structure 72 are spaced apart along the first direction.

[0138] The conductive layer 51 is etched by a patterning process, that is, a photoresist is developed and the developed photoresist is used as a mask to etch the conductive layer 51. When etching the conductive layer 51, the conductive layer 51 on the first layer 31 is etched to form a second conductive structure 72, which covers the second plug 62, that is, the second conductive structure 72 is in contact with the second plug 62.

[0139] The second conductive structure 72 is spaced apart from the first groove 33 along a first direction, and the first direction is parallel to the substrate 10, so that the remaining conductive layer 51 in the first groove 33 is spaced apart from the second conductive structure 72 along a direction parallel to the substrate 10. The remaining conductive layer 51 in the first groove 33 is spaced apart from the second conductive structure 72 along a left-right direction, so as to avoid bridging of the side surfaces of the remaining conductive layer 51 in the first groove 33 and the second conductive structure 72.

[0140] See also Fig. 9 In the process of etching the conductive layer 51 on the first layer 31 to form the second conductive structure 72, part of the conductive layer 51 in the first groove 33 will also be consumed, so that the top surface of the remaining conductive layer 51 in the first groove 33 is lower than the top surface of the first layer 31. The remaining conductive layer 51 in the first groove 33 forms the first conductive structure 71, and the top surface of the first conductive structure 71 is lower than the top surface of the first layer 31, so as to ensure that the first conductive structure 71 is staggered with the second conductive structure 72 on the first layer 31, that is, the first conductive structure 71 and the second conductive structure 72 are spaced apart in a direction perpendicular to the substrate 10 (up and down direction), so as to avoid bridging of the surfaces of the first conductive structure 71 and the second conductive structure 72, and to avoid short circuit of the semiconductor structure.

[0141] Step S206 : forming a second layer 32 on the first layer 31 and the first conductive structure 71 , wherein the second layer 32 exposes a top surface of the second conductive structure 72 .

[0142] See also Fig.10 , a second layer 32 is deposited on the first layer 31 and the first conductive structure 71, the second layer 32 covers the first layer 31 and the first conductive structure 71, and covers the side of the second conductive structure 72, exposing the top surface of the second conductive structure 72. The second layer 32 can ensure the internal isolation of the second conductive structure 72. The material of the second layer 32 can be the same as that of the first layer 31, so that the first layer 31 and the second layer 32 form a whole.

[0143] For other examples, see Figures 11 to 17 , forming a first layer 31, a first conductive structure 71 in the first layer 31, a first plug 61 connecting the first conductive structure 71 and the substrate 10, and a second layer 32 on the first layer 31 and the first conductive structure 71, a second conductive structure 72 in the second layer 32, and a second plug 62 connecting the second conductive structure 72 and the substrate 10 on the first dielectric layer 20 (step S200), including:

[0144] Step S201 ′: forming a first layer 31 on the first dielectric layer 20 , wherein the first layer 31 covers the first dielectric layer 20 .

[0145] Step S202 ′: removing a portion of the first layer 31 and a portion of the first dielectric layer 20 to form a plurality of contact holes 40 disposed at intervals, wherein the plurality of contact holes 40 all expose the substrate 10 .

[0146] Step S203 ′: removing part of the first layer 31 to form a first groove 33 communicating with part of the contact holes 40 , the contact holes 40 at the bottom of the first groove 33 form first plug holes 41 , and the remaining contact holes 40 form second plug holes 42 .

[0147] See also Fig.11 Step S201', step S202' and step S203' may refer to step S201, step S202 and step S203 respectively, and the details are referred to above, which will not be repeated here.

[0148] Step S204′: depositing a conductive material 52 in the first plug hole 41, the second plug hole 42 and the first groove 33, and removing part of the conductive material 52 in the first groove 33. The conductive material 52 in the first plug hole 41 forms a first plug 61, and the conductive material 52 in the first groove 33 forms a first conductive structure 71. The top surface of the first conductive structure 71 is lower than the top surface of the first layer 31.

[0149] See also Fig.11 and Fig.12 , depositing conductive material 52 in the first plug hole 41, the second plug hole 42, the first groove 33, and on the first layer 31, and etching back to remove the conductive material 52 on the first layer 31 and part of the conductive material 52 in the first groove 33. On the one hand, the first layer 31 and the conductive material 52 in the second plug hole 42 are exposed, and on the other hand, the top surface of the conductive material 52 in the first groove 33 is lower than the top surface of the first layer 31.

[0150] The conductive material 52 in the first plug hole 41 forms a first plug 61, and the conductive material 52 in the first groove 33 forms a first conductive structure 71. The first conductive structure 71 is in contact with the first plug 61, and the top surface of the first conductive structure 71 is lower than the top surface of the first layer 31. The conductive material 52 in the second plug hole 42 forms a second plug 62. The top surface of the second plug 62 is higher than the top surface of the first conductive structure 71, for example, the top surface of the second plug 62 is flush with the top surface of the first layer 31.

[0151] Step S205 ′: forming a second layer 32 , wherein the second layer 32 covers the first conductive structure 71 , the second plug 62 and the first layer 31 .

[0152] See also Fig.13, a second layer 32 is deposited on the first conductive structure 71, the second plug 62 and the first layer 31, and the second layer 32 covers the first conductive structure 71, the second plug 62 and the first layer 31. The second layer 32 covers the top surface of the first conductive structure 71 to cover the top surface of the first conductive structure 71, so as to isolate the first conductive structure 71. The material of the second layer 32 can be the same as that of the first layer 31, for example, both are silicon nitride. The material of the second layer 32 can also be a low dielectric constant material to reduce parasitic capacitance.

[0153] Step S206 ′: removing a portion of the second layer 32 to form a second groove 34 , wherein the second groove 34 exposes the second plug 62 and at least exposes a portion of the first layer 31 .

[0154] See also Fig.14 , the second layer 32 is etched to form a second groove 34, which penetrates the second layer 32 and exposes the second plug 62 and a portion of the first layer 31. In some examples, in order to increase the size of the second groove 34, the second groove 34 may also expose a portion of the first layer 31, that is, the orthographic projection of the first groove 33 on the substrate 10 and the orthographic projection of the second groove 34 on the substrate 10 have a partial overlap area.

[0155] Step S207 ′: depositing a conductive material 52 at least in the second groove 34 . The conductive material 52 in the second groove 34 forms a second conductive structure 72 , and the conductive material 52 in the second plug hole 42 forms a second plug 62 .

[0156] See also Fig.14 and Fig.15 , depositing the conductive material 52 at least in the second groove 34, so that the conductive material 52 at least fills the second groove 34. Fig.15 and Figure 2 The conductive material 52 in the second groove 34 forms a second conductive structure 72 , and the second conductive structure 72 contacts the second plug 62 .

[0157] For some possible implementations, see Fig.12 and Fig.16 , depositing a conductive material 52 on the first plug hole 41, the second plug hole 42 and the first groove 33, and removing a portion of the conductive material 52 located in the first groove 33, including:

[0158] Conductive material 52 is deposited in the first plug hole 41, in the second plug hole 42, in the first groove 33, and on the first layer 31; the conductive material 52 on the first layer 31 is removed to expose the first layer 31; the conductive material 52 in the first groove 33 and the second plug hole 42 is etched back, the width of the first groove 33 along the first direction is greater than the width of the second plug hole 42 along the first direction, and the top surface of the remaining conductive material 52 in the first groove 33 is made lower than the top surface of the remaining conductive material 52 in the second plug hole 42 by utilizing the load effect of etching.

[0159] Among them, by depositing and etching back the conductive material 52, the first layer 31 is exposed, and the conductive material 52 in the first groove 33 and the second plug hole 42 is also exposed. The conductive material 52 is continuously etched back. Since the size of the first groove 33 is larger than the size of the second plug hole 42, due to the load effect of etching, the depth of the conductive material 52 removed in the first groove 33 is greater than the depth of the conductive material 52 removed in the second plug hole 42, so that the top surface of the conductive material 52 remaining in the first groove 33 is lower than the top surface of the conductive material 52 remaining in the second plug hole 42. When the conductive material 52 is subsequently deposited in the second groove 34, the second groove 34 exposes the second plug hole 42, and the conductive material 52 will fill the second plug hole 42 to ensure the integrity of the second plug 62.

[0160] For other possible implementations, see Fig.12 and Fig.17 , depositing a conductive material 52 on the first plug hole 41, the second plug hole 42 and the first groove 33, and removing a portion of the conductive material 52 located in the first groove 33, including:

[0161] Conductive material 52 is deposited in the first plug hole 41, in the second plug hole 42, in the first groove 33, and on the first layer 31; the conductive material 52 on the first layer 31 is removed to expose the first layer 31; a protective layer 80 is formed on the conductive material 52 in the second plug hole 42, and the protective layer 80 is spaced apart from the first groove 33; part of the conductive material 52 in the first groove 33 is etched so that the top surface of the remaining conductive material 52 in the first groove 33 is lower than the top surface of the first layer 31; the protective layer 80 is removed to expose the conductive material 52 in the second plug hole 42.

[0162] The first layer 31 is exposed by depositing and etching back the conductive material 52, and the conductive material 52 in the first groove 33 and the second plug hole 42 is also exposed. Before continuing to etch the conductive material 52, a protective layer 80 is formed on the conductive material 52 in the second plug hole 42, and the first groove 33 is exposed while covering the conductive material 52 in the second plug hole 42, that is, the protective layer 80 is spaced from the first groove 33. The conductive material 52 is further etched, that is, the conductive material 52 in the first groove 33 is etched away to reduce the height of the conductive material 52 in the first groove 33, so that the top surface of the remaining conductive material 52 in the first groove 33 is lower than the top surface of the first layer 31, and then the protective layer 80 is removed.

[0163] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, a first dielectric layer, and a second dielectric layer are stacked; At least two layers of conductive structures are arranged in the second dielectric layer and are spaced apart from each other; a plug connected between each of the conductive structures and the substrate; The at least two layers of conductive structures are arranged in sequence in a direction away from the substrate, and among two adjacent layers of conductive structures, a top surface of a layer of conductive structures close to the substrate is lower than a bottom surface of a layer of conductive structures away from the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The second dielectric layer includes a plurality of layers stacked in sequence in a direction away from the substrate, and the number of the layers is greater than or equal to the number of layers of the conductive structure; One layer of the conductive structure is correspondingly arranged in one of the layers and contacts the adjacent layers. Except for the outermost conductive structure located away from the substrate, the top surface of each of the other conductive structures is lower than the top surface of the corresponding layer.

3. The semiconductor structure according to claim 1, characterized in that: The conductive structures of different layers have a partially overlapping area in the orthographic projection of the substrate.

4. The semiconductor structure according to claim 3, characterized in that: Each layer of the conductive structure includes at least one conductive element, and the ratio of the area of ​​the overlapped area between the conductive elements of different layers on the orthographic projection of the substrate to the orthographic projection of the conductive element on the substrate is less than or equal to 0.

2.

5. The semiconductor structure according to claim 2, characterized in that: The second dielectric layer includes a first layer and a second layer, the at least two layers of conductive structures include a first conductive structure and a second conductive structure, and the plug includes a first plug electrically connected to the first conductive structure and a second plug electrically connected to the second conductive structure; The first conductive structure is arranged in the first layer, and the top surface of the first conductive structure is lower than the top surface of the first layer, the second layer is arranged on the first conductive structure and the first layer, the second conductive structure is arranged in the second layer, and the second conductive structure is located on the top surface of the first layer, the top surface of the first plug is lower than the top surface of the first layer and higher than the bottom surface of the first layer, and the top surface of the second plug is flush with the top surface of the first layer.

6. The semiconductor structure according to claim 5, characterized in that: The material of the second layer includes a low dielectric constant material, and a height difference between a top surface of the first conductive structure and a bottom surface of the second conductive structure is greater than or equal to 5 nm.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The top surface of the plug contacts the bottom surface of the conductive structure, and the bottom surface of the plug is located in the substrate, and the bottom surfaces of the plug connecting the conductive structures of different layers are flush.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further comprises: A gate structure located in the first dielectric layer, wherein a top surface of the gate structure is flush with a top surface of the first dielectric layer and is lower than a bottom surface of the conductive structure at the innermost layer close to the substrate; The substrate includes a first source-drain region and a second source-drain region located at two sides of the gate structure, and the first source-drain region and the second source-drain region are respectively in contact with the plug.

9. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first dielectric layer on a substrate, wherein the first dielectric layer covers the substrate; A first layer, a first conductive structure located in the first layer, a first plug connecting the first conductive structure and the substrate, and a second layer located on the first layer and the first conductive structure, a second conductive structure located in the second layer, and a second plug connecting the second conductive structure and the substrate are formed on the first dielectric layer. The top surface of the first conductive structure is lower than the bottom surface of the second conductive structure. The first layer and the second layer form a second dielectric layer.

10. The manufacturing method according to claim 9, characterized in that: A first layer, a first conductive structure in the first layer, and a first plug connecting the first conductive structure and the substrate are formed on the first dielectric layer, and a second layer on the first layer and the first conductive structure, a second conductive structure in the second layer, and a second plug connecting the second conductive structure and the substrate are formed, including: forming a first layer on the first dielectric layer, wherein the first layer covers the first dielectric layer; Removing part of the first layer and part of the first dielectric layer to form a plurality of contact holes arranged at intervals, wherein the plurality of contact holes all expose the substrate; Removing part of the first layer to form a first groove connected to part of the contact holes, the contact holes located at the bottom of the first groove form first plug holes, and the remaining contact holes form second plug holes; forming a conductive layer filled in the first plug hole, the second plug hole, the first groove and located on the first layer, wherein the conductive layer located in the first plug hole forms the first plug, and the conductive layer located in the second plug hole forms the second plug; removing part of the conductive layer, so that the remaining conductive layer in the first groove forms the first conductive structure, and the remaining conductive layer on the first layer forms the second conductive structure, wherein the top surface of the first conductive structure is lower than the top surface of the first layer, and the first conductive structure and the second conductive structure are spaced apart along a first direction; A second layer is formed on the first layer and the first conductive structure, wherein the second layer exposes a top surface of the second conductive structure.

11. The manufacturing method according to claim 9, characterized in that: A first layer, a first conductive structure located in the first layer, and a first plug connecting the first conductive structure and the substrate are formed on the first dielectric layer, and a second layer located on the first layer and the first conductive structure, a second conductive structure located in the second layer, and a second plug connecting the second conductive structure and the substrate are formed, including: forming a first layer on the first dielectric layer, wherein the first layer covers the first dielectric layer; Removing part of the first layer and part of the first dielectric layer to form a plurality of contact holes arranged at intervals, wherein the plurality of contact holes all expose the substrate; Removing part of the first layer to form a first groove connected to part of the contact holes, the contact holes located at the bottom of the first groove form first plug holes, and the remaining contact holes form second plug holes; Depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove, so that the conductive material in the first plug hole forms a first plug, and the conductive material in the first groove forms a first conductive structure, wherein a top surface of the first conductive structure is lower than a top surface of the first layer; forming a second layer, wherein the second layer covers the first conductive structure, the second plug and the first layer; removing a portion of the second layer to form a second groove, wherein the second groove exposes the second plug and at least exposes a portion of the first layer; A conductive material is deposited at least in the second groove, the conductive material in the second groove forms the second conductive structure, and the conductive material in the second plug hole forms a second plug.

12. The manufacturing method according to claim 11, characterized in that: Depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove, comprises: Depositing a conductive material in the first plug hole, in the second plug hole, in the first groove, and on the first layer; removing the conductive material on the first layer to expose the first layer; The conductive material in the first groove and the second plug hole is etched back, wherein the width of the first groove along the first direction is greater than the width of the second plug hole along the first direction, and the top surface of the conductive material remaining in the first groove is made lower than the top surface of the conductive material remaining in the second plug hole by utilizing the load effect of etching.

13. The manufacturing method according to claim 11, characterized in that: Depositing a conductive material in the first plug hole, the second plug hole, and the first groove, and removing a portion of the conductive material in the first groove, comprises: Depositing a conductive material in the first plug hole, in the second plug hole, in the first groove, and on the first layer; removing the conductive material on the first layer to expose the first layer; forming a protective layer on the conductive material in the second plug hole, wherein the protective layer is spaced apart from the first groove; Etching a portion of the conductive material in the first groove so that a top surface of the remaining conductive material in the first groove is lower than a top surface of the first layer; The protection layer is removed to expose the conductive material in the second plug hole.

14. The manufacturing method according to claim 11, characterized in that: The orthographic projection of the first groove on the substrate and the orthographic projection of the second groove on the substrate have a partially overlapping area.

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