Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming an initial gate structure and an interlayer dielectric layer on a substrate, and enabling the interlayer dielectric layer to be located on the side wall of the initial gate structure; a gate isolation structure is formed in the interlayer dielectric layer and the initial gate structure, the gate isolation structure penetrates through the initial gate structure in a second direction parallel to the surface of the substrate to form discrete gate structures, the first direction is perpendicular to the second direction, the gate isolation structure comprises a first region and a second region located on the first region, and the second region is perpendicular to the first region; the first region has a first projection on the surface of the substrate, the second region has a second projection on the surface of the substrate, the first projection is located in the range of the second projection, and the top surface of the first region is lower than that of the gate structure; after the gate isolation structure is formed, the connecting layer is formed on the gate isolation structure, the connecting layer has the third projection on the surface of the substrate, and the third projection is located in the range of the second projection, so that the risk of electric leakage between the connecting layer and the gate structure is reduced, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Ultra-advanced semiconductor processes require the use of ultra-via and gate cut-off processes. When the gate cut-off process is integrated with the metal connection process, the short circuit problem between the metal connection structure and the gate structure needs to be considered. The distance between the metal connection structure and the gate structure needs to be large enough to meet reliability performance.

[0003] Therefore, there is a need to improve the integration of the gate cut-off process and the metal connection process. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a gate structure and an interlayer dielectric layer located on the substrate, the interlayer dielectric layer is also located on the side wall of the gate structure, the gate structure is parallel to a first direction, and the first direction is parallel to the substrate surface; a gate isolation structure located in the interlayer dielectric layer, the gate isolation structure penetrates the gate structure along a second direction parallel to the substrate surface, the second direction is perpendicular to the first direction, the gate isolation structure comprises a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the range of the second projection, and the top surface of the first region is lower than the top surface of the gate structure; a connecting layer located on the gate isolation structure, the connecting layer has a third projection on the substrate surface, and the third projection is located within the range of the second projection.

[0006] Optionally, the gate structure and the interlayer dielectric layer also have a protective layer on their surfaces; and the gate isolation structure is also located in the protective layer.

[0007] Optionally, it also includes: a source and drain layer located in the substrate on both sides of the gate structure along the second direction; a metal structure located in the interlayer dielectric layer, the metal structure is electrically connected to the source and drain layer and is parallel to the first direction; and the connecting layer is electrically connected to the metal structure.

[0008] Optionally, it further includes: a first dielectric layer located on the surface of the interlayer dielectric layer; and the metal structure is also located in the first dielectric layer.

[0009] Optionally, it further includes: an etch stop layer located on the surface of the first dielectric layer and a second dielectric layer located on the surface of the etch stop layer; the connecting layer is located in the etch stop layer and the second dielectric layer.

[0010] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial gate structure and an interlayer dielectric layer on the substrate, the interlayer dielectric layer is also located on the side wall of the initial gate structure, the initial gate structure is parallel to a first direction, and the first direction is parallel to the substrate surface; forming a gate isolation structure in the interlayer dielectric layer and the initial gate structure, the gate isolation structure penetrates the initial gate structure along a second direction parallel to the substrate surface to form a discrete gate structure, the first direction and the second direction are perpendicular to each other, the gate isolation structure comprises a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the range of the second projection, and the top surface of the first region is lower than the top surface of the gate structure; after forming the gate isolation structure, forming a connecting layer on the gate isolation structure, the connecting layer has a third projection on the substrate surface, and the third projection is located within the range of the second projection.

[0011] Optionally, before forming the gate isolation structure and before forming the initial gate structure and the interlayer dielectric layer, a protective layer is formed on the initial gate structure and the interlayer dielectric layer; the gate isolation structure is also located in the protective layer.

[0012] Optionally, the method for forming the gate isolation structure includes: etching the protective layer, the initial gate structure and the interlayer dielectric layer until the substrate is exposed, forming a first groove and an initial second groove located on the first groove in the initial gate structure and the interlayer dielectric layer, the initial second groove is also located in the protective layer, the first groove and the initial second groove are both parallel to the second direction, and the initial second groove is connected to the first groove; forming a sacrificial layer in the first groove; after forming the sacrificial layer, etching the side wall of the initial second groove to form a second groove, the projection of the first groove on the substrate surface is located within the projection range of the second groove on the substrate surface; after forming the second groove, removing the sacrificial layer to expose the first groove; forming the gate isolation structure in the first groove and the second groove.

[0013] Optionally, the formation process of the second groove includes one of a dry etching process and a wet etching process or a combination of both; the process parameters of the dry etching process include: the etching gas includes a halogen element gas, and the etching power ranges from 3000W to 8000W.

[0014] Optionally, the method for forming the second groove further includes: forming a mask layer on the surface of the protective layer, the mask layer exposing the initial second groove and a portion of the surface of the protective layer adjacent to the initial second groove; after forming the mask layer, etching the sidewall of the initial second groove.

[0015] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material layer in the first groove, the initial second groove and on the surface of the protective layer; etching back the sacrificial material layer until the initial second groove is exposed, and forming the sacrificial layer in the first groove.

[0016] Optionally, the material of the sacrificial layer includes an organic material, and the organic material includes amorphous carbon, amorphous silicon or photoresist.

[0017] Optionally, before forming the gate isolation structure, a source-drain layer is formed in the substrate on both sides of the initial gate structure; after forming the gate isolation structure, a metal structure is formed in the interlayer dielectric layer, the metal structure is electrically connected to the source-drain layer, and the metal structure is parallel to the first direction; the connecting layer is electrically connected to the metal structure.

[0018] Optionally, after forming the gate isolation structure and before forming the metal structure, a first dielectric layer is formed on the surface of the interlayer dielectric layer; and the metal structure is also located in the first dielectric layer.

[0019] Optionally, the method for forming the metal structure includes: forming a third groove in the first dielectric layer and the interlayer dielectric layer, the third groove exposing the source and drain layer; and forming the metal structure in the third groove.

[0020] Optionally, after forming the metal structure and before forming the connection layer, an etch stop layer and a second dielectric layer located on the surface of the etch stop layer are formed on the surface of the first dielectric layer; the connection layer is located in the etch stop layer and the second dielectric layer.

[0021] Optionally, the method for forming the connecting layer includes: forming a fourth groove in the second dielectric layer, the etch stop layer and the first dielectric layer, the fourth groove being parallel to the second direction; the fourth groove exposing the surface of the metal structure; and forming the connecting layer in the fourth groove.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the gate isolation structure includes a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the range of the second projection, the top surface of the first region is lower than the top surface of the gate structure, and after the gate isolation structure is formed, a connecting layer is formed on the gate isolation structure, the connecting layer has a third projection on the substrate surface, and the third projection is located within the range of the second projection. The shape of the gate isolation structure increases the distance between the gate structure and the connecting layer, which is beneficial to reducing the risk of leakage between the connecting layer and the gate structure and improving device performance.

[0024] In the semiconductor structure provided by the technical solution of the present invention, the gate isolation structure includes a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the range of the second projection, the top surface of the first region is lower than the top surface of the gate structure, and after the gate isolation structure is formed, a connecting layer is formed on the gate isolation structure, the connecting layer has a third projection on the substrate surface, and the third projection is located within the range of the second projection. The shape of the gate isolation structure increases the distance between the gate structure and the connecting layer, which is beneficial to reducing the risk of leakage between the connecting layer and the gate structure and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0026] Figures 4 to 13 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0028] As described in the background art, it is necessary to improve the integration of the gate cut-off process and the metal connection process.

[0029] Figures 1 to 3 It is a structural diagram of a semiconductor structure.

[0030] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 The schematic diagram of the top view of the structure of the first dielectric layer, the second dielectric layer, the stop layer, the protection structure and the isolation layer is omitted. Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 3 yes Figure 1 The schematic cross-sectional structure diagram along the EE1 direction in FIG. 1 , wherein the semiconductor structure comprises: a substrate, wherein the substrate comprises a base 100, a plurality of fins 101 and an isolation layer 102 located on the base 100, wherein the isolation layer 102 is located on the sidewalls of the plurality of fins 101, and the top surface of the isolation layer 102 is lower than the top surface of the plurality of fins 101, and the plurality of fins 101 are parallel to a first direction X; a gate structure 103 located on the surface of the substrate, wherein the gate structure 103 spans across the plurality of fins 101, and the gate structure 103 is parallel to a second direction Y, and the second direction Y is perpendicular to the first direction X; source and drain doped regions (not shown in the figure) located in the fins 101 on both sides of the gate structure 103; a first dielectric layer (not shown in the figure) located on the substrate; a gate structure 103 located on the gate structure 103 and a protection structure 104 on the first dielectric layer; a gate isolation layer 105 located on the substrate, the gate isolation layer 105 penetrates the gate structure 103 along a first direction X; a metal layer 106 located on the substrate, the metal layer 106 is also located in the first dielectric layer and the protection structure 104, and penetrates the gate isolation layer 105, the metal layer 106 is electrically connected to the source and drain doped regions, and the metal layer 106 is parallel to the second direction Y; a stop layer 107 located on the protection structure 104; a second dielectric layer 108 located on the stop layer 107; a contact layer 109 located on part of the gate isolation layer 105, the contact layer 109 is located in the second dielectric layer 108 and the stop layer 107, and the contact layer 109 is electrically connected to the metal layer 106.

[0031] In the above structure, the contact layer 109 is located on the gate isolation layer 105, and the materials of the gate isolation layer 105 and the stop layer 107 are both silicon nitride. The gate structure 103 is formed by a process of replacing a polysilicon gate with a metal gate. After the gate structure 103 is formed, an opening (not shown in the figure) is formed in the gate structure 103, and then an insulating dielectric layer (not shown in the figure) is formed in the opening and on the first dielectric layer, and then the insulating dielectric layer is planarized by a chemical mechanical polishing process to form the gate isolation layer 105 in the opening. The top surface of the gate isolation layer 105 is higher than the top surface of the gate structure 103, and the top surface of the gate isolation layer 105 is uneven. When forming the contact layer 109, it is necessary to first etch the second dielectric layer 108 and the stop layer 107 to form a groove. Since the stop layer 107 and the gate isolation layer 105 are made of the same material, the etching process is likely to damage the higher gate isolation layer 105, making the distance between the contact layer 109 and the gate structure 103 closer, which is prone to the risk of short circuit (as shown in area A), which is not conducive to the stability of device performance.

[0032] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein the gate isolation structure includes a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the range of the second projection, the top surface of the first region is lower than the top surface of the gate structure, and after the gate isolation structure is formed, a connecting layer is formed on the gate isolation structure, the connecting layer has a third projection on the substrate surface, the third projection is located within the range of the second projection, and the shape of the gate isolation structure increases the distance between the gate structure and the connecting layer, which is beneficial to reducing the risk of leakage between the connecting layer and the gate structure and improving device performance.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 13 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0035] Please refer to Figures 4 to 6 , Figure 4 yes Figure 5 and Figure 6 The top view of the structure of the interlayer dielectric layer and the protective layer is omitted. Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 6 yes Figure 4A schematic diagram of the cross-sectional structure along the EE1 direction is provided, wherein a substrate is provided; an initial gate structure 203 and an interlayer dielectric layer 204 are formed on the substrate, wherein the interlayer dielectric layer 204 is also located on the side wall of the initial gate structure 203, and the initial gate structure 203 is parallel to a first direction X, and the first direction X is parallel to the surface of the substrate 200.

[0036] In this embodiment, the substrate includes a base 200, a plurality of fins 201 and an isolation layer 202 located on the base 200, the isolation layer 202 is located between adjacent fins 201, and the top surface of the isolation layer 202 is lower than the top surface of the fins 201, the plurality of fins 201 are parallel to a second direction Y, the second direction Y is parallel to the surface of the base 200, and is perpendicular to the first direction X. In this embodiment, the substrate is a three-dimensional structure. In another embodiment, the substrate may be a planar structure.

[0037] The material of the initial gate structure 203 includes metal.

[0038] Subsequently, a gate isolation structure is formed in the interlayer dielectric layer 204 and the initial gate structure 203, and the gate isolation structure penetrates the initial gate structure 203 along the second direction Y parallel to the substrate surface to form a discrete gate structure, and the gate isolation structure includes a first region and a second region located on the first region, the first region has a first projection on the surface of the substrate 200, and the second region has a second projection on the surface of the substrate, the first projection is located within the range of the second projection, and the top surface of the first region is lower than the top surface of the gate structure.

[0039] In this embodiment, before forming the gate isolation structure and before forming the initial gate structure 203 and the interlayer dielectric layer 204 , a protection layer 205 is further formed on the initial gate structure 203 and the interlayer dielectric layer 204 .

[0040] In this embodiment, the gate isolation structure is also located in the protection layer 205 .

[0041] In this embodiment, before forming the gate isolation structure, a source-drain layer 206 is formed in the substrate on both sides of the initial gate structure 203 .

[0042] Specifically, the method for forming the initial gate structure 203, the interlayer dielectric layer 204 and the source / drain layer 206 includes: forming a dummy gate layer (not shown in the figure) on the substrate, the dummy gate layer spanning the plurality of fins 201 and being located on the side walls and top surfaces of some of the plurality of fins 201; forming the source / drain layer 206 in the fins 201 on both sides of the dummy gate layer; after forming the source / drain layer 206, forming the interlayer dielectric layer 204 on the substrate, the interlayer dielectric layer 204 being located on the side walls of the dummy gate layer and exposing the top surface of the dummy gate layer; and replacing the dummy gate layer with the initial gate structure 203.

[0043] In this embodiment, the method for forming the gate isolation structure is shown in FIG. Figures 7 to 12 .

[0044] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 A top view of the structure. Figure 8 yes Figure 7 The cross-sectional structural schematic diagram along the DD1 direction in the figure shows that the protective layer 205, the initial gate structure 203 and the interlayer dielectric layer 204 are etched until the substrate 200 is exposed, and a first groove 207 and an initial second groove 208 located on the first groove 207 are formed in the initial gate structure 203 and the interlayer dielectric layer 204, and the initial second groove 208 is also located in the protective layer 205, and the first groove 207 and the initial second groove 208 are both parallel to the second direction Y, and the initial second groove 208 is connected to the first groove 207.

[0045] In this embodiment, after the substrate 200 is exposed, the substrate 200 is further etched, and the first groove 207 is still located in the substrate 200. Specifically, the first groove 207 is also located in the isolation layer 202 and the base 200.

[0046] The etching process includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the etching process is a dry etching process, which is beneficial to improving the morphology of the first groove 207 and the initial second groove 208 formed.

[0047] Please refer to Fig. 9 , Fig. 9 The viewing direction is the same as Figure 8 , a sacrificial layer 209 is formed in the first groove 207 .

[0048] In this embodiment, the method for forming the sacrificial layer 209 includes: forming a sacrificial material layer (not shown in the figure) in the first groove 207, the initial second groove 208 and on the surface of the protective layer 205; etching back the sacrificial material layer until the initial second groove 208 is exposed, and forming the sacrificial layer 209 in the first groove 207.

[0049] The material of the sacrificial layer 209 includes an organic material, and the organic material includes amorphous carbon, amorphous silicon or photoresist. In this embodiment, the material of the sacrificial layer 209 is amorphous carbon.

[0050] Please Figure 8 and Fig. 9 Based on this, continue to refer to Fig.10 After forming the sacrificial layer 209 , the sidewall of the initial second groove 208 is etched to form a second groove 210 , and the projection of the first groove 207 on the surface of the substrate 200 is within the projection range of the second groove 210 on the surface of the substrate 200 .

[0051] The second groove 210 is used to form the second region of the gate isolation structure.

[0052] In this embodiment, the method for forming the second groove 210 also includes: forming a mask layer (not shown in the figure) on the surface of the protective layer 205, wherein the mask layer exposes the initial second groove 208 and a portion of the surface of the protective layer 205 adjacent to the initial second groove 208; after forming the mask layer, etching the side wall of the initial second groove 208.

[0053] The second groove 210 is formed by a process including a dry etching process and a wet etching process or a combination of the two.

[0054] In this embodiment, the etching process of the second groove 210 is a dry etching process.

[0055] Specifically, the process parameters of the dry etching process include: the etching gas includes a halogen gas, and the etching power ranges from 3000 W to 8000 W. In this embodiment, the halogen gas includes Cl2 or BCl3.

[0056] Please refer to Fig.11 , Fig.11 The viewing direction is the same as Fig.10 After forming the second groove 210, the sacrificial layer 209 (eg Fig.10 As shown), the first groove 207 is exposed.

[0057] In this embodiment, the process of removing the sacrificial layer 209 is an ashing process.

[0058] Please refer to Fig.12 , Fig.12 The viewing direction is the same as Fig.11 , the gate isolation structure 211 is formed in the first groove 207 and the second groove 210 , and a discrete gate structure 300 is formed with the initial gate structure 203 .

[0059] The material of the gate isolation structure 211 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0060] In this embodiment, the material of the gate isolation structure 211 is silicon nitride.

[0061] The gate isolation structure 211 includes a first region I and a second region II located on the first region I, the first region I has a first projection on the surface of the substrate 200, the second region II has a second projection on the surface of the substrate 200, the first projection is located within the range of the second projection, and the top surface of the first region I is lower than the top surface of the gate structure 300.

[0062] Please refer to Fig.13 , Fig.13 The viewing direction is the same as Fig.12 After forming the gate isolation structure 211, a connection layer 212 is formed on the gate isolation structure 211, and the connection layer 212 has a third projection on the surface of the substrate 200, and the third projection is located within the range of the second projection.

[0063] Thus, the shape of the gate isolation structure 211 increases the distance between the gate structure 300 and the connection layer 212 , which helps to reduce the risk of leakage between the connection layer 212 and the gate structure 300 and improves device performance.

[0064] In this embodiment, the connection layer 212 includes an adhesion layer (not shown in the figure) and a contact layer (not shown in the figure) located on the surface of the adhesion layer; the material of the contact layer includes metal, and the metal includes copper, gold or tungsten.

[0065] In this embodiment, after forming the gate isolation structure 211 , a metal structure (not shown) is further formed in the interlayer dielectric layer 204 , the metal structure is electrically connected to the source / drain layer 206 , and the metal structure is parallel to the first direction X. Specifically, the metal structure is also located in the protective layer 205 .

[0066] In this embodiment, the connection layer 212 is electrically connected to the metal structure.

[0067] In this embodiment, after forming the gate isolation structure 211 and before forming the metal structure, a first dielectric layer 213 is formed on the surface of the interlayer dielectric layer 204 ; the metal structure is also located in the first dielectric layer 213 .

[0068] Specifically, after forming the gate isolation structure 211 and before forming the metal structure, a first dielectric layer 213 is formed on the surface of the protection layer 205 ; the metal structure is also located in the protection layer 205 .

[0069] In this embodiment, the method for forming the metal structure includes: forming a third groove (not shown in the figure) in the first dielectric layer 213 and the interlayer dielectric layer 204, wherein the third groove exposes the source / drain layer 206; and forming the metal structure in the third groove.

[0070] In this embodiment, after the metal structure is formed and before the connection layer 212 is formed, an etch stop layer 214 and a second dielectric layer 215 located on the surface of the etch stop layer 214 are formed on the surface of the first dielectric layer 213; the connection layer 212 is located within the etch stop layer 214 and the second dielectric layer 215.

[0071] In this embodiment, the method for forming the connecting layer 212 includes: forming a fourth groove (not shown in the figure) in the second dielectric layer 215, the etch stop layer 214 and the first dielectric layer 213, and the fourth groove is parallel to the second direction Y; the fourth groove exposes the surface of the metal structure; and forming the connecting layer 212 in the fourth groove.

[0072] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.13 The semiconductor structure includes: a substrate; a gate structure 300 and an interlayer dielectric layer 204 (such as Figure 6As shown), the interlayer dielectric layer 204 is also located on the side wall of the gate structure 300, and the gate structure 300 is parallel to the first direction X, and the first direction X is parallel to the substrate surface; the gate isolation structure 211 is located in the interlayer dielectric layer 204, and the gate isolation structure 211 penetrates the gate structure 300 along a second direction Y parallel to the substrate surface, and the first direction X and the second direction Y are perpendicular to each other. The gate isolation structure 211 includes a first region I and a second region II located on the first region I, the first region I has a first projection on the substrate surface, and the second region II has a second projection on the substrate surface, the first projection is within the range of the second projection, and the top surface of the first region I is lower than the top surface of the gate structure 300; the connection layer 212 is located on the gate isolation structure 211, and the connection layer 212 has a third projection on the substrate surface, and the third projection is within the range of the second projection.

[0073] Thus, the shape of the gate isolation structure 211 increases the distance between the gate structure 300 and the connection layer 212 , which helps to reduce the risk of leakage between the connection layer 212 and the gate structure 300 and improves device performance.

[0074] In this embodiment, a protective layer 205 is further provided on the surfaces of the gate structure 300 and the interlayer dielectric layer 204 ; and the gate isolation structure 211 is also located in the protective layer 205 .

[0075] In this embodiment, the semiconductor structure further includes: a source-drain layer (such as Figure 4 As shown in the figure), it is located in the substrate on both sides of the gate structure 300 along the second direction Y; the metal structure (not shown in the figure) is located in the interlayer dielectric layer 204, the metal structure is electrically connected to the source and drain layer, and is parallel to the first direction X; the connecting layer 212 is electrically connected to the metal structure.

[0076] In this embodiment, the semiconductor structure further includes: a first dielectric layer 213 located on the surface of the interlayer dielectric layer 204 ; and the metal structure is also located in the first dielectric layer 213 . Specifically, the metal structure is also located in the protective layer 205 .

[0077] In this embodiment, the semiconductor structure further includes: an etch stop layer 214 located on the surface of the first dielectric layer 213 and a second dielectric layer 215 located on the surface of the etch stop layer 214 ; the connection layer 212 is located in the etch stop layer 214 and the second dielectric layer 215 .

[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A gate structure and an interlayer dielectric layer located on the substrate, wherein the interlayer dielectric layer is also located on a sidewall of the gate structure, the gate structure is parallel to a first direction, and the first direction is parallel to a surface of the substrate; a gate isolation structure located in the interlayer dielectric layer, the gate isolation structure penetrating the gate structure along a second direction parallel to the substrate surface, the second direction being perpendicular to the first direction, the gate isolation structure comprising a first region and a second region located on the first region, the first region having a first projection on the substrate surface, the second region having a second projection on the substrate surface, the first projection being within the range of the second projection, and a top surface of the first region being lower than a top surface of the gate structure; A connection layer located on the gate isolation structure, wherein the connection layer has a third projection on the substrate surface, and the third projection is located within the range of the second projection.

2. The semiconductor structure according to claim 1, wherein: The surfaces of the gate structure and the interlayer dielectric layer also have a protective layer; the gate isolation structure is also located in the protective layer.

3. The semiconductor structure according to claim 1, wherein: Also includes: Source and drain layers are located in the substrate on both sides of the gate structure along the second direction; a metal structure, located in the interlayer dielectric layer, the metal structure being electrically connected to the source / drain layer and parallel to the first direction; The connection layer is electrically connected to the metal structure.

4. The semiconductor structure according to claim 3, characterized in that Also includes: A first dielectric layer located on the surface of the interlayer dielectric layer; The metal structure is also located in the first dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that Also includes: An etch stop layer located on a surface of the first dielectric layer and a second dielectric layer located on a surface of the etch stop layer; The connection layer is located in the etch stop layer and the second dielectric layer.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an initial gate structure and an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is also located on a sidewall of the initial gate structure, the initial gate structure is parallel to a first direction, and the first direction is parallel to a surface of the substrate; A gate isolation structure is formed in the interlayer dielectric layer and the initial gate structure, the gate isolation structure penetrates the initial gate structure along a second direction parallel to the substrate surface to form a discrete gate structure, the first direction and the second direction are perpendicular to each other, the gate isolation structure comprises a first region and a second region located on the first region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the first projection is located within the second projection range, and a top surface of the first region is lower than a top surface of the gate structure; After forming the gate isolation structure, a connection layer is formed on the gate isolation structure, wherein the connection layer has a third projection on the substrate surface, and the third projection is located within the second projection range.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the gate isolation structure, and before forming the initial gate structure and the interlayer dielectric layer, a protection layer is formed on the initial gate structure and the interlayer dielectric layer; the gate isolation structure is also located in the protection layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the gate isolation structure comprises: etching the protective layer, the initial gate structure and the interlayer dielectric layer until the substrate is exposed, forming a first groove and an initial second groove located on the first groove in the initial gate structure and the interlayer dielectric layer, the initial second groove is also located in the protective layer, the first groove and the initial second groove are both parallel to the second direction, and the initial second groove is connected to the first groove; forming a sacrificial layer in the first groove; after forming the sacrificial layer, etching the side wall of the initial second groove to form a second groove, the projection of the first groove on the surface of the substrate is located within the projection range of the second groove on the surface of the substrate; after forming the second groove, removing the sacrificial layer to expose the first groove; forming the gate isolation structure in the first groove and the second groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: The forming process of the second groove includes one of a dry etching process and a wet etching process or a combination of the two; the process parameters of the dry etching process include: the etching gas includes a halogen element gas, and the etching power ranges from 3000W to 8000W.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the second groove further includes: forming a mask layer on the surface of the protective layer, wherein the mask layer exposes the initial second groove and a portion of the protective layer surface adjacent to the initial second groove; and after forming the mask layer, etching the sidewall of the initial second groove.

11. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the sacrificial layer includes: forming a sacrificial material layer in the first groove, the initial second groove and on the surface of the protective layer; etching back the sacrificial material layer until the initial second groove is exposed, and forming the sacrificial layer in the first groove.

12. The method for forming a semiconductor structure according to claim 8, wherein: The material of the sacrificial layer includes an organic material, and the organic material includes amorphous carbon, amorphous silicon or photoresist.

13. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the gate isolation structure, source and drain layers are formed in the substrate on both sides of the initial gate structure; after forming the gate isolation structure, a metal structure is formed in the interlayer dielectric layer, the metal structure is electrically connected to the source and drain layers, and the metal structure is parallel to the first direction; the connection layer is electrically connected to the metal structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming the gate isolation structure and before forming the metal structure, a first dielectric layer is formed on the surface of the interlayer dielectric layer; the metal structure is also located in the first dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the metal structure comprises: forming a third groove in the first dielectric layer and the interlayer dielectric layer, wherein the third groove exposes the source and drain layer; and forming the metal structure in the third groove.

16. The method for forming a semiconductor structure according to claim 15, wherein: After forming the metal structure and before forming the connection layer, an etch stop layer and a second dielectric layer located on the surface of the etch stop layer are formed on the surface of the first dielectric layer; the connection layer is located in the etch stop layer and the second dielectric layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the connection layer includes: forming a fourth groove in the second dielectric layer, the etch stop layer and the first dielectric layer, wherein the fourth groove is parallel to the second direction; the fourth groove exposes the surface of the metal structure; and forming the connection layer in the fourth groove.

Images