SGT structure with np-pn doped polycrystalline silicon

Abstract

The invention discloses an SGT structure with np-pn doped polycrystalline silicon, based on a Con.SGT structure, a groove is etched in the center of an N-drift region above an N + substrate, and the groove is filled with a silicon dioxide dielectric layer and two parts of different doped polycrystalline silicon which are isolated from each other up and down; the upper control grid is composed of a heavily-doped N-type polycrystalline silicon n1 region and a medium-doped P-type polycrystalline silicon p1 region from top to bottom, the thickness of the n1 region is larger than or equal to that of the p1 region, and a polycrystalline silicon n1p1 junction is formed. And the shielding grid at the lower part consists of a heavily doped P-type polycrystalline silicon p2 region and a medium doped N-type polycrystalline silicon n2 region from top to bottom, and the thickness of the p2 region is equal to that of the n2 region, so that a polycrystalline silicon p2n2 junction is formed. The invention belongs to the technical field of power semiconductor devices, and solves the problems of poor dynamic characteristics and insufficient electrostatic protection capability caused by structural limitation of a traditional SGT.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices and relates to a SGT structure with np-pn doped polysilicon. Background Art

[0002] Shielded gate trench MOSFET (SGT) is another type of trench gate MOSFET developed based on the existing trench gate MOSFET (VUMOS). Compared with the VUMOS structure, the SGT structure divides the trench gate into two parts, the upper part is the control gate, and the lower part is the shield gate, which is connected to the source. Although the SGT structure can improve the contradiction between the on-resistance and breakdown voltage of the device and reduce the gate-drain capacitance, in practical applications, the gate-source capacitance and drain-source capacitance are still large, resulting in poor dynamic characteristics of the device; in addition, when subjected to electrostatic discharge (ESD), due to the large difference between the positive and reverse capacitances of the gate source, the forward and reverse withstand voltages of the device during ESD are asymmetric, making its electrostatic protection ability insufficient. Summary of the invention

[0003] The purpose of the present invention is to provide an SGT structure with np-pn doped polysilicon, which solves the problem that the traditional SGT has poor dynamic characteristics and insufficient electrostatic protection capability due to structural limitations.

[0004] The technical solution adopted by the present invention is to have an SGT structure with np-pn doped polysilicon, based on the structure of Con.SGT, in N + N on the substrate - A groove is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two parts of differently doped polysilicon isolated at the top and bottom; the upper polysilicon serves as a control gate G, which is composed of a heavily doped N-type polysilicon n1 region and a medium-doped P-type polysilicon p1 region from top to bottom, and the thickness of the n1 region is greater than or equal to the thickness of the p1 region, forming a polysilicon n1p1 junction; the lower polysilicon serves as a shielding gate SG, which is composed of a heavily doped P-type polysilicon p2 region and a medium-doped N-type polysilicon n2 region from top to bottom, and the thickness of the p2 region is equal to the thickness of the n2 region, forming a polysilicon p2n2 junction.

[0005] The SGT structure with np-pn doped polysilicon of the present invention is also characterized in that:

[0006] The structure of Con.SGT is, in N + N on the substrate -A trench is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two separated upper and lower heavily doped N-type polysilicon layers; the upper heavily doped N-type polysilicon serves as the gate G, and the lower heavily doped N-type polysilicon serves as the shielding gate SG; the thickness of the gate oxide layer on both sides of the trench sidewall gate G is less than the thickness of the isolation oxide layer on both sides and above and below the shielding gate SG; the entire device is symmetrically distributed with the center of the trench as the axis, and the N - The surface of the epitaxial layer is provided with a P body region; on the surface of the P body region on both sides, N + source area, and P ++ Contact area; in N + Source region and P ++ The contact area has a source S on the surface and a + A drain electrode D is disposed on the surface of the substrate; a shielding gate electrode SG is connected to a source electrode S.

[0007] Inside the control gate G, the doping concentration of the p1 region ranges from 5×10 15 cm -3 ~1×10 18 cm -3 , the thickness of the p1 region ranges from 0.2 to 0.5 μm.

[0008] Inside the control gate G, the doping concentration of the n1 region ranges from 5×10 19 cm -3 ~1×10 20 cm -3 , the thickness of the n1 region ranges from 0.5 to 0.8 μm.

[0009] Inside the shielding gate SG, the doping concentration of the n2 region ranges from 5×10 14 cm -3 ~1×10 18 cm -3 , the thickness of the n2 region is 1 / 2 of the total thickness of the shielding gate SG.

[0010] Inside the shielding gate SG, the doping concentration of the p2 region ranges from 5×10 19 cm -3 ~1×10 20 cm -3 .

[0011] The beneficial effect of the present invention is that n1p1 and p2n2 junctions are introduced into the control gate polysilicon and shield gate polysilicon of the existing SGT, thereby generating two series junction capacitors C n1p1 and C p2n2Without affecting the breakdown voltage and on-resistance of the device, the gate-source capacitance and drain-source capacitance of the device can be effectively reduced, and the dynamic characteristics of the device can be improved; at the same time, the difference between the forward and reverse withstand voltages of the gate-source ESD of the device can be reduced, and the electrostatic protection capability of the device can be significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a basic structural diagram of a traditional SGT MOSFET;

[0013] Figure 2 It is a basic structural diagram of the np-pn-SGT of the present invention;

[0014] Figure 3 Schematic diagram of the capacitor structure of np-pn-SGT of the present invention;

[0015] Figure 4 Schematic diagram of the capacitance equivalent circuit of the np-pn-SGT of the present invention;

[0016] Figure 5 It is a comparison diagram of the breakdown characteristics of the np-pn-SGT of the present invention and the traditional SGT;

[0017] Figure 6 It is a comparison diagram of the conduction characteristics of the np-pn-SGT of the present invention and the traditional SGT;

[0018] Figure 7 is a comparison diagram of the transfer characteristics of the np-pn-SGT of the present invention and the traditional SGT;

[0019] Figure 8 It is a comparison diagram of gate charge curves of np-pn-SGT1 of the present invention and traditional SGT;

[0020] Fig. 9 is N in the np-pn-SGT of the present invention p1 With N n2 Impact on gate-source capacitance;

[0021] Fig.10 is N in the np-pn-SGT of the present invention p1 With N n2 Impact on gate-drain capacitance;

[0022] Fig.11 is N in the np-pn-SGT of the present invention p1 With N n2 Impact on drain-source capacitance;

[0023] Fig.12 It is D in np-pn-SGT of the present invention. p1 Impact on gate-source capacitance;

[0024] Fig.13 It is D in np-pn-SGT of the present invention. p1 Impact on gate-drain capacitance;

[0025] Fig.14 It is a comparison diagram of the gate-source capacitance of the np-pn-SGT of the present invention and the traditional SGT;

[0026] Fig.15 It is a comparison diagram of the gate-drain capacitance of the np-pn-SGT of the present invention and the traditional SGT;

[0027] Fig.16 1 is a comparison diagram of the drain-source capacitance of the np-pn-SGT of the present invention and the conventional SGT;

[0028] Fig.17 It is a comparison diagram of the switching characteristics of the np-pn-SGT of the present invention and the traditional SGT;

[0029] Fig.18 This is the electrostatic discharge waveform of the traditional SGT under the HBM model;

[0030] Fig.19 It is the electrostatic discharge waveform of the np-pn-SGT of the present invention under the HBM model. DETAILED DESCRIPTION

[0031] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] The “up, down, left, and right” directions mentioned in the following text are all intuitive descriptions of the cells in the corresponding drawings and are not intended to limit the positions of the various regions in the actual device structure.

[0033] Reference Figure 1 The structure of the traditional SGT (hereinafter referred to as Con.SGT in the text and drawings) is that + N on the substrate - A deep trench is etched in the center of the drift region, and the trench is filled with a silicon dioxide dielectric layer and two separated upper and lower heavily doped N-type polysilicon layers; the upper heavily doped N-type polysilicon layer serves as the gate G, and the lower heavily doped N-type polysilicon layer serves as the shielding gate SG; the gate oxide layer on both sides of the trench sidewall gate G is thinner, and the isolation oxide layer on both sides and above and below the shielding gate SG is thicker (that is, the gate oxide layer thickness on both sides of the trench sidewall gate G is less than the isolation oxide layer thickness on both sides and above and below the shielding gate SG); the entire device is symmetrically distributed with the center of the trench as the axis, and the N - The surface of the epitaxial layer is provided with a P body region; on the surface of the P body region on both sides, N + source area, and P ++ Contact area; in N + Source region and P++ The contact area has a source S on the surface and a + A drain electrode D is disposed on the surface of the substrate; a shielding gate electrode SG is connected to a source electrode S.

[0034] Reference Figure 2 The present invention has an np-pn doped polysilicon SGT structure (hereinafter referred to as np-pnSGT in the text and drawings). Based on the structure of the aforementioned Con.SGT, different types and doses of doping are performed on the polysilicon in the trench. The specific structure is: + N on the substrate - A groove is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two parts of polysilicon with different dopings that are isolated at the top and bottom. The upper polysilicon serves as the control gate G, which is composed of a heavily doped N-type polysilicon n1 region and a medium-doped P-type polysilicon p1 region from top to bottom, and the thickness of the n1 region is greater than or equal to the thickness of the p1 region, forming a polysilicon n1p1 junction. The lower polysilicon serves as the shielding gate SG, which is composed of a heavily doped P-type polysilicon p2 region and a medium-doped N-type polysilicon n2 region from top to bottom, and the thickness of the p2 region is equal to the thickness of the n2 region, forming a polysilicon p2n2 junction. The other parts have the same structure as Con.SGT.

[0035] Inside the control gate G, the medium-doped p1 region (P-type polysilicon) has a doping concentration N p1 The value range is 5×10 15 cm -3 ~1×10 18 cm -3 , p1 region thickness D p1 The value range is 0.2~0.5μm; the heavily doped n1 region doping (N-type polysilicon) concentration N n1 The value range is 5×10 19 cm -3 ~1×10 20 cm -3 , the thickness D of the n1 region n1 The value range is 0.5~0.8μm;

[0036] The doping concentration N of the n2 region (N-type polysilicon) inside the shielding gate SG n2 The value range is 5×10 14 cm -3 ~1×10 18 cm -3 ; The thickness of n2 region D n2 is 1 / 2 of the total thickness of the shielding gate SG; the doping concentration of the heavily doped p2 region (P-type polysilicon) is N p2 The value range is 5×10 19 cm -3 ~1×1020 cm -3 .

[0037] contrast Figure 1 , Figure 2 It can be seen that the np-pn SGT of the present invention is different from the Con.SGT in that the control gate and the shielding gate are both filled with P-type and N-type doped polysilicon, so a polysilicon n1p1 junction is formed inside the two gates, and a polysilicon p2n2 junction is formed inside the shielding gate. Moreover, when the thickness of the n1 region and the p1 region inside the control gate are the same (i.e., D n1 =D p1 ), so that the junction surface of the n1p1 junction is higher than the junction surface of the J1 junction, the threshold voltage will change with the change of the doping concentration of the p1 region; when the thickness of the n1 region inside the control gate is thicker than the p1 region (that is, D n1 >D p1 ), when the junction surface of the n1p1 junction is at the same height as the junction surface of the J1 junction, the threshold voltage remains unchanged.

[0038] Reference Figure 3 , is a schematic diagram of the capacitance structure of the np-pn-SGT of the present invention. The np-pn SGT of the present invention forms an n1p1 junction inside the control gate by changing the polysilicon doping concentration, thereby introducing a junction capacitance C n1p1 , to reduce the gate-source capacitance C GS and gate-drain capacitance C GD ; A p2n2 junction is formed inside the shielding gate, thereby introducing a junction capacitance C p2n2 , to reduce the drain-source capacitance C DS .

[0039] Reference Figure 4 , is a schematic diagram of the capacitance equivalent circuit of the np-pn-SGT of the present invention. It is equivalent to adding a parallel branch between the gate and the source, consisting of C pp and C GS2 The parallel connection formed by C n1p1 Series structure; C is connected in series on the two parallel paths between the gate and the drain. n1p1 ; Between drain and source and C J1 C is connected in series on the parallel path p2n2 .

[0040] The SGT with np-pn doped polysilicon of the present invention is also applicable to the SGT structure with the control gate and the shielding gate arranged on the left and right; the doping method of the polysilicon inside the control gate can also be extended to the VUMOS structure to solve the problem of asymmetric ESD gate-source forward and reverse withstand voltages.

[0041] Feature Verification

[0042] In order to evaluate the characteristics of the SGT with np-pn doped polysilicon of the present invention, taking the voltage level of 100V as an example, the breakdown characteristics, conduction characteristics, transfer characteristics, gate charge and capacitance characteristics of the above np-pn-SGT are simulated and verified respectively using professional simulation software, and compared with the characteristics of the traditional SGT (Con.SGT). During the simulation, only the doping concentration and thickness of the p1 region of the control gate and the n2 region of the shielding gate are changed, and the other parameters are exactly the same as those of Con.SGT.

[0043] 1. Comparison of electrical characteristics.

[0044] Reference Figure 5 , is a comparison of the breakdown characteristic curves of the np-pn-SGT of the present invention and the traditional SGT. It can be seen that the breakdown characteristic of the np-pn-SGT is very close to that of the Con.SGT, the breakdown voltage is reduced by 2V, and the change of the polysilicon doping concentration has no effect on the breakdown characteristic of the device.

[0045] Reference Figure 6 , is a comparison chart of the conduction characteristics of the np-pn-SGT of the present invention and the traditional SGT. It can be seen that the breakdown characteristics of the np-pn-SGT are almost the same as those of the Con.SGT, and the change of the polysilicon doping concentration has no effect on the conduction characteristics of the device.

[0046] Reference Figure 7 , is a comparison of the transfer characteristics of the np-pn-SGT of the present invention and the traditional SGT. It can be seen that the concentration N in the p1 region of the np-pn-SGT of the present invention is p1 Its thickness D p1 And the concentration N in the n2 region n2 Any change will affect the threshold voltage of the device. p1 =0.5μm, D n2 =1.5μm remains unchanged, N p1 From 1×10 18 cm -3 Reduce 5×10 15 cm -3 、N n2 From 1×10 18 cm -3 Reduce 5×10 14 cm -3 When D n2 =1.5μm remains unchanged, N p1 =N n2 =1×10 16 cm -3 , D p1 =0.2μm, the threshold voltage is 2V, which is the same as the threshold voltage (2V) of the conventional SGT.

[0047] Reference Figure 8 , is a comparison of the gate charge curves of the np-pn-SGT of the present invention and the traditional SGT. It can be seen that the duration of the Miller platform and the total gate charge are related to the concentration N in the p1 region. p1 Its thickness D p1 And the concentration N in the n2 region n2 Compared with the traditional SGT, when the N p1 =5×10 15 cm -3 、N n2 =5×10 14 cm -3 , D p1 =0.5μm, D n2 =1.5μm, the duration of the Miller platform is shortened, the gate charge is reduced, and the U corresponding to the Miller platform is GS However, when N p1 =N n2 =1×10 16 cm -3 , D p1 =0.2μm, D n2 =1.5μm, the U corresponding to the Miller platform GS The values ​​are equal, Q of np-pn-SGT T =15.4nC, Q of Con.SGT T =21.3nC, therefore, the gate charge of np-pn-SGT is reduced by 27.7%.

[0048] Depend on Figure 5 , Figure 6 , Figure 7 , Figure 8 It can be seen that compared with the traditional SGT, the breakdown voltage of np-pn-SGT is slightly reduced, the conduction characteristics remain unchanged, the threshold voltage increases significantly with the change of p1 region doping concentration and thickness, while the gate charge decreases significantly with the change of p1 region doping concentration and thickness.

[0049] Reference Fig. 9 , Fig.10 , Fig.11 , is the doping concentration N in the p1 region of the np-pn-SGT of the present invention p1 and the n2 region doping concentration N n2 , respectively for the gate-source capacitance C GS , gate-drain capacitance C GD and drain-source capacitance C DS It can be seen that as the doping concentration N p1 、N n2 As N decreases, the capacitance of np-pn-SGT also decreases.p1 =N n2 =5×10 15 cm -3 At U DS C of np-pn-SGT under zero bias GS , C GD , C DS With N p1 =N n2 =1×10 18 cm -3 Compared with the time, the decreases were 6.3%, 47.5%, and 4.8%, respectively. n2 From 5×10 15 cm -3 Further reduced to 5×10 14 cm -3 At U DS C under zero bias DS It will decrease by 10.1%.

[0050] Reference Fig.12 , Fig.13 , is the thickness D of the p1 region in the np-pn-SGT of the present invention p1 The influence on gate-source capacitance and gate-drain capacitance respectively. p1 =5×10 15 cm -3 , N n2 =5×10 14 cm -3 No change, D p1 When the thickness increases from 0.5 μm to 0.65 μm, C GS Reduced by 14.5%, C GD A decrease of 26.3%.

[0051] Depend on Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 It can be seen that reducing the doping concentration N in the p1 region p1 Or the doping concentration N in the n2 region n2 , C GS , C GD , C DS will decrease; increase the thickness D of the p1 region p1 , C GS , C GD However, this will lead to an increase in the threshold voltage of the device.

[0052] Reference Fig.14 , Fig.15 , Fig.16, is a comparison diagram of the gate-source capacitance, gate-drain capacitance and drain-source capacitance of the np-pn-SGT of the present invention and the traditional SGT. p1 =N n2 =1×10 16 cm -3 , D p1 =0.2μm, D n2 =1.5μm, with U DS The increase of C of np-pn-SGT GS , C GD , C DS The capacitance is lower than that of Con.SGT. DS C of np-pn-SGT under zero bias GS , C GD , C DS They are 1007pF, 215pF and 1060pF respectively, which are reduced by 7.9%, 49% and 12.7% respectively compared with Con.SGT.

[0053] Reference Fig.17 , is a comparison of the switching characteristic curves of the np-pn-SGT of the present invention and the traditional SGT. It can be seen that the reduction of parasitic capacitance makes U GS The rise time is faster, the turn-on time of np-pn-SGT has no significant change, while the turn-off time is significantly reduced. The total turn-off time is 61ns, which is 7.6% less than that of Con.SGT.

[0054] from Figure 7 to Figure 17 It can be seen that the np-pn-SGT of the present invention introduces n1 region and p1 region (D n1 >D p1 ), the threshold voltage can be kept unchanged, while the gate charge, gate-source capacitance, gate-drain capacitance and turn-off time can be reduced, thereby effectively improving the dynamic characteristics of the SGT MOSFET.

[0055] 2. Comparison of gate-source electrostatic protection capabilities.

[0056] The level of gate-source ESD forward and reverse withstand voltage is related to the gate-source capacitance. When the gate-source is subjected to forward static voltage, the gate-source capacitance is large; when the gate-source is subjected to reverse static voltage, the gate-source capacitance is reduced due to the series depletion layer capacitance. Therefore, the forward and reverse withstand voltages of SGT gate-source are different.

[0057] In the traditional SGT control gate, an n1p1 junction is introduced inside, and a p2n2 junction is introduced inside the shielded gate. GS (+), the n1p1 junction and the p2n2 junction are both reverse biased, so two depletion layer capacitors C are connected in series between the gate and the source.n1p1 and C p2n2 , so that the gate-source capacitance is reduced; at the reverse gate-source voltage V GS (-), the n1p1 junction and the p2n2 junction are both forward biased, and the gate-source capacitance changes very little. In addition, by adjusting the doping concentration of polysilicon, the depletion layer capacitance C n1p1 and C p2n2 The size of the device can be reduced to reduce the difference between the forward and reverse withstand voltages of ESD, thereby improving the electrostatic protection capability of the device.

[0058] Reference Fig.18 , is the electrostatic discharge waveform of the traditional SGT under the HBM model. It can be seen that when a positive static voltage V is applied between the gate and the source GS (+), the peak discharge current is 1.108A, and the gate-source forward withstand voltage of the device is 1662V; a reverse static voltage V is applied between the gate and source. GS When (-), the discharge current peak is 1.201A, and the gate-source ESD reverse withstand voltage of the device is 1802V. It can be seen that the gate-source ESD forward withstand voltage is significantly lower than the reverse withstand voltage, with a difference of 140V. Since static voltage does not distinguish between directions, if the gate-source ESD withstand voltage is asymmetric, the electrostatic protection capability of the device will deteriorate.

[0059] Reference Fig.19 , is the electrostatic discharge waveform of the np-pn-SGT of the present invention under the HBM model. Compared with the traditional SGT, the positive static voltage V is applied between the gate and the source. GS (+), the discharge current peak is 1.308A, and the corresponding gate-source ESD forward withstand voltage is 1962V, which is 18.1% higher than the ESD forward withstand voltage of traditional SGT; a reverse static voltage V is applied between the gate and source. GS (-), the discharge current peak is 1.329A, and the corresponding gate-source ESD reverse withstand voltage is 1994V, which is 10.7% higher than that of traditional SGT. In addition, the gate-source ESD forward and reverse withstand voltages of np-pn-SGT differ by 32V, which is 77.1% lower than that of traditional SGT.

[0060] It can be seen that the introduction of n1p1 junction in the control gate generates a series depletion layer capacitance C n1p1 , which can reduce the capacitance under the forward gate-source voltage, increase the ESD gate-source forward withstand voltage, reduce the difference between the forward and reverse withstand voltages of the ESD gate-source, improve the electrostatic protection capability, and effectively avoid device failure problems caused by electrostatic stress.

[0061] Example 1

[0062] Based on the structure of Con.SGT mentioned above, different types and dosages of doping are performed on polysilicon in the trench. The specific structure is: + N on the substrate- A deeper trench is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two parts of differently doped polysilicon isolated at the top and bottom; the upper polysilicon serves as the control gate G, which is composed of a heavily doped N-type polysilicon n1 region and a medium-doped P-type polysilicon p1 region from top to bottom, and the thickness of the n1 region is greater than or equal to the thickness of the p1 region, forming a polysilicon n1p1 junction; the lower polysilicon serves as the shielding gate SG, which is composed of a heavily doped P-type polysilicon p2 region and a medium-doped N-type polysilicon n2 region from top to bottom, and the thickness of the p2 region is equal to the thickness of the n2 region, forming a polysilicon p2n2 junction; the other parts have the same structure as Con.SGT.

[0063] The doping concentration N of the p1 region inside the control gate G p1 The value is 1×10 18 cm -3 , p1 region thickness D p1 The value range is 0.5μm, and the doping concentration range of n1 region is 1×10 20 cm -3 , the thickness of the n1 region is 0.5μm; the doping concentration of the n2 region inside the shielding gate SG is N n2 The value is 1×10 18 cm -3 ; The thickness of n2 region D n2 The thickness of the shielding gate SG is 1 / 2, and the doping concentration of the p2 region is in the range of 1×10 20 cm -3 .

[0064] According to simulation prediction, the breakdown voltage V BR is 112V, the on-resistance R on is 11.8mΩ, the threshold voltage V TH is 2.2V; C under zero bias GS , C GD , C DS They are 1030pF, 282pF, and 1124pF respectively; the gate-source ESD forward and reverse withstand voltages are very close, all at 1955V.

[0065] The gate-source EDS of the present embodiment 1 has the closest forward and reverse withstand voltages and the highest electrostatic protection capability.

[0066] Example 2

[0067] The structure of the embodiment 1 is different from that of the embodiment 1.

[0068] The doping concentration N of the p1 region inside the control gate G p1 The value range is 5×10 15 cm -3 , p1 region thickness D p1The value range is 0.5μm, and the doping concentration range of n1 region is 1×10 20 cm -3 , the thickness of the n1 region is 0.5μm; the doping concentration of the n2 region inside the shielding gate SG is N n2 The value range is 5×10 14 cm -3 ; The thickness of n2 region D n2 The thickness of the shielding gate SG is 1 / 2, and the doping concentration of the p2 region is in the range of 1×10 20 cm -3 .

[0069] According to simulation prediction, the breakdown voltage of the device structure of Example 2 is 112V, the on-resistance is 11.8mΩ, the threshold voltage is 2.6V, and the C of the np-pn-SGT under zero bias is GS , C GD , C DS They are 980pF, 148pF, and 946pF respectively. The gate-source ESD forward and reverse withstand voltages are 1980V and 1995V respectively.

[0070] The gate capacitance of the second embodiment is the smallest and the dynamic characteristics are the best, but the threshold voltage is affected.

[0071] Example 3

[0072] The structure of the embodiment 1 is different from that of the embodiment 1.

[0073] The doping concentration N of the p1 region inside the control gate G p1 The value is 1×10 16 cm -3 , p1 region thickness D p1 The value is 0.2μm, and the doping concentration range of n1 region is 1×10 20 cm -3 , the thickness of the n1 region is 0.8 μm; the doping concentration of the n2 region inside the shielding gate SG is N n2 The value is 1×10 16 cm -3 ; The thickness of n2 region D n2 The thickness of the shielding gate SG is 1 / 2, and the doping concentration of the p2 region is in the range of 1×10 20 cm -3 .

[0074] According to simulation prediction, the breakdown voltage V BR is 112V, the on-resistance R on =11.8mΩ, threshold voltage V TH is 2V; C under zero bias GS , C GD , CDS They are 1007pF, 215pF, and 1060pF respectively; the gate-source ESD forward and reverse withstand voltages are 1962V and 1994V respectively.

[0075] The device of the third embodiment can take into account both dynamic characteristics and electrostatic protection capabilities under the premise that the threshold voltage remains unchanged.

[0076] Example 4

[0077] The structure of the embodiment 1 is different from that of the embodiment 1.

[0078] The doping concentration N of the p1 region inside the control gate G p1 The value is 1×10 17 cm -3 , p1 region thickness D p1 The value is 0.5μm, and the doping concentration range of n1 region is 5×10 19 cm -3 , the thickness of the n1 region is 0.5μm; the doping concentration of the n2 region inside the shielding gate SG is N n2 The value is 1×10 17 cm -3 ; The thickness of n2 region D n2 The thickness of the shielding gate SG is 1 / 2, and the doping concentration of the p2 region is in the range of 5×10 19 cm -3 .

[0079] According to simulation prediction, the breakdown voltage V BR is 112V, the on-resistance R on =11.8mΩ, threshold voltage V TH is 2.1V; C under zero bias GS , C GD , C DS They are 1013pF, 245pF, and 1108pF respectively; the gate-source ESD forward and reverse withstand voltages are 1958V and 1983V respectively.

[0080] The device of the fourth embodiment can take into account the threshold voltage, dynamic characteristics and ESD capability at the same time.

[0081] In summary, the np-pn doped polysilicon SGT of the present invention can effectively reduce the gate capacitance and gate charge and improve the dynamic characteristics of the device while ensuring the static characteristics such as breakdown voltage and on-resistance; at the same time, it can reduce the difference between the forward and reverse withstand voltages of the gate-source ESD and improve the electrostatic protection capability of the device.

Claims

1. SGT structure with np-pn doped polysilicon, based on the structure of Con.SGT, characterized by: In N + N on the substrate - A groove is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two parts of differently doped polysilicon isolated at the top and bottom; the upper polysilicon serves as a control gate G, which is composed of a heavily doped N-type polysilicon n1 region and a medium-doped P-type polysilicon p1 region from top to bottom, and the thickness of the n1 region is greater than or equal to the thickness of the p1 region, forming a polysilicon n1p1 junction; the lower polysilicon serves as a shielding gate SG, which is composed of a heavily doped P-type polysilicon p2 region and a medium-doped N-type polysilicon n2 region from top to bottom, and the thickness of the p2 region is equal to the thickness of the n2 region, forming a polysilicon p2n2 junction.

2. The SGT structure having np-pn doped polysilicon according to claim 1, characterized in that: The structure of Con.SGT is that in N + N on the substrate - A trench is etched in the center of the drift region, which is filled with a silicon dioxide dielectric layer and two separated upper and lower heavily doped N-type polysilicon layers; the upper heavily doped N-type polysilicon serves as the gate G, and the lower heavily doped N-type polysilicon serves as the shielding gate SG; the thickness of the gate oxide layer on both sides of the trench sidewall gate G is less than the thickness of the isolation oxide layer on both sides and above and below the shielding gate SG; the entire device is symmetrically distributed with the center of the trench as the axis, and the N - The surface of the epitaxial layer is provided with a P body region; on the surface of the P body region on both sides, N + source area, and P ++ Contact area; in N + Source region and P ++ The contact area surface is provided with a source S, and the back side N + A drain electrode D is disposed on the surface of the substrate; a shielding gate electrode SG is connected to a source electrode S.

3. The SGT structure having np-pn doped polysilicon according to claim 1, characterized in that: The doping concentration of the p1 region inside the control gate G is in the range of 5×10 15 cm -3 ~1×10 18 cm -3 , the thickness of the p1 region ranges from 0.2 to 0.5 μm.

4. The SGT structure having np-pn doped polysilicon according to claim 1, characterized in that: The doping concentration of the n1 region inside the control gate G is in the range of 5×10 19 cm -3 ~1×10 20 cm -3 , the thickness of the n1 region ranges from 0.5 to 0.8 μm.

5. The SGT structure having np-pn doped polysilicon according to claim 1, characterized in that: The doping concentration of the n2 region inside the shielding gate SG is in the range of 5×10 14 cm -3 ~1×10 18 cm -3 , the thickness of the n2 region is 1 / 2 of the total thickness of the shielding gate SG.

6. The SGT structure with np-pn doped polysilicon according to claim 1, characterized in that: The doping concentration of the p2 region inside the shielding gate SG is in the range of 5×10 19 cm -3 ~1×10 20 cm -3 .

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