Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device includes: a substrate; the heterostructure is positioned on one side of the thickness direction of the substrate; the source electrode, the drain electrode and the grid electrode are located on the side, away from the substrate, of the heterostructure, the source electrode, the grid electrode and the drain electrode are sequentially distributed at intervals in the first direction, and the first direction is perpendicular to the thickness direction; the cap layer is located on the side, away from the substrate, of the heterostructure and located on the side, close to the drain electrode, of the grid electrode, the cap layer comprises a plurality of step layers which are sequentially distributed in the first direction, and the distances between the step layers and the heterostructure are sequentially increased in the first direction. According to the invention, the current collapse effect can be inhibited or even eliminated, and the on-resistance is reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Gallium nitride high electron mobility transistor (HEMT) has the characteristics of high mobility, high breakdown field strength and wide band gap, and can be well applied to industries such as power electronics and industrial power. However, in the high-voltage off state, a very high electric field will appear inside the transistor, especially on the side of the gate close to the drain, and the transistor is easily broken down. Under the action of the high electric field, electrons are captured by internal defects, resulting in a current collapse effect. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a semiconductor device and a manufacturing method thereof, which can suppress or even eliminate the current collapse effect and reduce the on-resistance.

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] substrate;

[0006] A heterostructure located on one side of the substrate in a thickness direction;

[0007] A source electrode, a drain electrode and a gate electrode are respectively located on a side of the heterostructure away from the substrate, and the source electrode, the gate electrode and the drain electrode are sequentially spaced and distributed along a first direction, and the first direction is perpendicular to the thickness direction;

[0008] A cap layer is located on a side of the heterostructure away from the substrate and on a side of the gate close to the drain, wherein the cap layer includes a plurality of stepped layers sequentially distributed along the first direction, and the spacing between the plurality of stepped layers and the heterostructure increases sequentially along the first direction.

[0009] According to the semiconductor device of the present application, a cap layer is provided on the side of the gate close to the drain, and the cap layer includes a plurality of stepped layers sequentially distributed along a first direction, and the spacing between the plurality of stepped layers and the heterostructure increases sequentially along the first direction, so as to adjust the off-state electric field on the side of the gate close to the drain, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance.

[0010] According to an embodiment of the present application, the stepped layer includes a plurality of finger-shaped strips extending along the first direction, and the plurality of finger-shaped strips are spaced apart along a second direction, and the second direction is perpendicular to the first direction and the thickness direction, respectively.

[0011] According to an embodiment of the present application, an overall length of the cap layer along the first direction is no greater than one third of a distance between the gate and the drain.

[0012] According to an embodiment of the present application, adjacent step layers are arranged at intervals, or adjacent step layers are connected.

[0013] According to an embodiment of the present application, the cap layer is spaced apart from the gate, or the cap layer is connected to the gate.

[0014] According to an embodiment of the present application, the distance between the cap layer and the gate is 0.5 μm-2 μm.

[0015] According to an embodiment of the present application, the thicknesses of the plurality of stepped layers are the same, and / or the lengths of the plurality of stepped layers along the first direction are the same.

[0016] According to one embodiment of the present application, the thickness of the step layer is 10nm-100nm.

[0017] According to an embodiment of the present application, the substrate includes a sapphire substrate, the heterostructure includes an AlGaN / GaN heterojunction, and the cap layer includes a P-GaN cap layer.

[0018] In a second aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0019] Providing a substrate and a heterostructure located on one side of the substrate in a thickness direction;

[0020] forming a source electrode and a drain electrode on a side of the heterostructure away from the substrate, wherein the source electrode and the drain electrode are sequentially spaced and distributed along a first direction;

[0021] forming a cap layer on a side of the heterostructure away from the substrate, the cap layer being located between the source electrode and the drain electrode, the cap layer comprising a plurality of stepped layers sequentially distributed along the first direction, the spacing between the plurality of stepped layers and the heterostructure sequentially increasing along the first direction, and the first direction being perpendicular to the thickness direction;

[0022] A gate is formed on a side of the heterostructure facing away from the substrate, and the gate is located on a side of the cap layer close to the source.

[0023] According to the manufacturing method of the semiconductor device of the present application, a cap layer is set on the side of the gate close to the drain, and the cap layer includes a plurality of step layers distributed in sequence along a first direction, and the spacing between the plurality of step layers and the heterostructure increases in sequence along the first direction, so as to adjust the off-state electric field on the side of the gate close to the drain, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance.

[0024] According to one embodiment of the present application, forming a source and a drain on a side of the heterostructure away from the substrate includes:

[0025] forming a first dielectric layer on a side of the heterostructure facing away from the substrate;

[0026] A source electrode and a drain electrode are formed on a side of the first dielectric layer away from the heterostructure, and the source electrode and the drain electrode respectively penetrate the first dielectric layer along the thickness direction and extend into the heterostructure.

[0027] According to one embodiment of the present application, forming a cap layer on a side of the heterostructure facing away from the substrate includes:

[0028] A passivation layer is formed on a side of the first dielectric layer away from the heterostructure; the source electrode and the drain electrode also penetrate through the passivation layer respectively;

[0029] forming a groove in the passivation layer and the first dielectric layer between the source electrode and the drain electrode, the groove comprising a stepped sidewall close to the drain electrode;

[0030] A cap layer is formed on the bottom of the groove, the stepped sidewall, and the edge of the groove close to the stepped sidewall.

[0031] According to an embodiment of the present application, forming a gate on a side of the heterostructure away from the substrate includes:

[0032] forming a second dielectric layer on a side of the passivation layer away from the first dielectric layer, and the second dielectric layer covers the cap layer;

[0033] A gate is formed which penetrates the second dielectric layer and the passivation layer along the thickness direction and extends into the first dielectric layer.

[0034] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0035] By setting a cap layer on the side of the gate close to the drain, the cap layer includes a plurality of step layers distributed in sequence along a first direction, and the spacing between the plurality of step layers and the heterostructure increases in sequence along the first direction, so as to adjust the off-state electric field on the side of the gate close to the drain, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0038] Figure 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0039] Figure 2 is a top view of a semiconductor device provided in an embodiment of the present application;

[0040] Figure 3 It is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0041] Figure 4 It is one of the structural schematic diagrams in the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0042] Figure 5 This is the second structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0043] Figure 6 This is the third structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0044] Figure 7 This is the fourth structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0045] Figure 8 This is the fifth structural diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] Fig. 9 This is the sixth structural schematic diagram of the method for manufacturing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0048] The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0049] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, wherein the semiconductor device may include a gallium nitride (GaN) high electron mobility transistor (HEMT).

[0050] like Figure 1 As shown, the semiconductor device provided in the embodiment of the present application includes a substrate 1, a heterostructure 2, a source 3, a drain 4, a gate 5 and a cap layer 6.

[0051] Among them, the selection of the material of the substrate 1 is crucial to the performance and reliability of the device. The selection of the material of the substrate 1 can be based on the considerations of small lattice mismatch with GaN, good thermal conductivity and good process compatibility. For example, the substrate 1 can include a silicon substrate, a silicon carbide substrate, a sapphire substrate or a GaN substrate. In some embodiments, the substrate 1 includes a sapphire substrate, which can greatly improve the pressure resistance of the device in the vertical direction.

[0052] The heterostructure 2 is located on one side of the substrate 1 in the thickness direction X. A two-dimensional electron gas 2DEG is formed in the heterostructure 2. The two-dimensional electron gas 2DEG is the main channel for electron transmission. The electrons in the two-dimensional electron gas 2DEG have extremely high mobility, which realizes efficient current conduction, improves the switching speed of the device, and reduces the on-resistance.

[0053] In some embodiments, the heterostructure 2 includes a channel layer 21 and a barrier layer 22. The channel layer 21 is located on one side of the substrate 1, and the barrier layer 22 is located on the side of the channel layer 21 away from the substrate 1. The channel layer 21 and the barrier layer 22 form a heterojunction. Due to the difference in the band structures of the two materials of the channel layer 21 and the barrier layer 22, a band bend is formed at the interface between the channel layer 21 and the barrier layer 22, thereby generating a potential well in the channel layer 21, and electrons are confined in the potential well to form a two-dimensional electron gas 2DEG. The channel layer 21 provides a low-impedance transmission path for electrons, and the barrier layer 22 has a high band gap and breakdown field strength, which can protect the channel layer 21 from high electric field damage and improve the breakdown voltage and reliability of the device.

[0054] The channel layer 21 may include GaN, the barrier layer 22 may include AlGaN, and the channel layer 21 and the barrier layer 22 may form an AlGaN / GaN heterojunction, that is, the heterostructure 2 may include an AlGaN / GaN heterojunction. The thickness of the channel layer 21 may be 200 nm, and the thickness of the barrier layer 22 may be 25 nm.

[0055] In some embodiments, the heterostructure 2 further includes a buffer layer 23, and the buffer layer 23 is located between the substrate 1 and the channel layer 21. The buffer layer 23 can alleviate the lattice mismatch and thermal mismatch between the substrate 1 and the heterojunction, reduce the stress generated thereby, and improve the quality of the heterojunction. By adjusting the thickness of the buffer layer 23, etc., the electrical properties of the device can be optimized, such as reducing the on-resistance and increasing the breakdown voltage. Among them, the buffer layer 23 can include GaN. The thickness of the buffer layer 23 can be 1μm-2μm.

[0056] The source 3 and the drain 4 are respectively located on the side of the heterostructure 2 away from the substrate 1, and the source 3 and the drain 4 are sequentially spaced and distributed along the first direction Y, and the first direction Y is perpendicular to the thickness direction X. Figure 2 As shown, the source 3 and the drain 4 can extend along the second direction Z, respectively, and the second direction Z is perpendicular to the first direction Y and the thickness direction X. The source 3 and the drain 4 are respectively connected to the heterostructure 2, and the source 3 and the drain 4 use the two-dimensional electron gas 2DEG formed in the heterostructure 2 as a conductive channel to realize the transmission of current. When a voltage is applied between the source 3 and the drain 4, the electrons in the two-dimensional electron gas 2DEG flow along the channel to form a current from the source 3 to the drain 4.

[0057] In the case where the heterostructure 2 includes a channel layer 21 and a barrier layer 22, the source electrode 3 and the drain electrode 4 may extend from a side of the barrier layer 22 away from the channel layer 21 to the inside of the barrier layer 22 along the thickness direction X. The source electrode 3 may include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. The drain electrode 4 may include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0058] In some embodiments, the semiconductor device further includes a first dielectric layer 71, the first dielectric layer 71 is located on the side of the heterostructure 2 away from the substrate 1, and the source 3 and the drain 4 can also penetrate the first dielectric layer 71 to connect with the heterostructure 2. In the case where the heterostructure 2 includes a channel layer 21 and a barrier layer 22, the first dielectric layer 71 is located on the side of the barrier layer 22 away from the channel layer 21, and the source 3 and the drain 4 can penetrate the first dielectric layer 71 along the thickness direction X from the side of the first dielectric layer 71 away from the barrier layer 22, and extend into the barrier layer 22. The first dielectric layer 71 can include one or more combinations of silicon oxide, silicon nitride, and aluminum oxide.

[0059] The gate 5 is located on the side of the heterostructure 2 facing away from the substrate 1, and the gate 5 is spaced apart from the heterostructure 2 along the thickness direction X. The gate 5 is located between the source 3 and the drain 4, and the gate 5 is spaced apart from the source 3 and the drain 4, respectively, that is, the source 3, the gate 5 and the drain 4 are spaced apart in sequence along the first direction Y. Figure 2 As shown, the gate 5 may extend along the second direction Z. The gate 5 is located above the two-dimensional electron gas 2DEG formed in the heterostructure 2. The concentration and shape of the two-dimensional electron gas 2DEG may be controlled by adjusting the voltage of the gate 5, thereby controlling the current between the source 3 and the drain 4. The gate 5 may include one or more combinations of copper, platinum, tungsten, gold, nickel, and chromium.

[0060] The cap layer 6 is located on the side of the heterostructure 2 facing away from the substrate 1, and the cap layer 6 is located on the side of the gate 5 close to the drain 4, that is, the cap layer 6 is located between the gate 5 and the drain 4, and the cap layer 6 and the drain 4 are spaced apart along the first direction Y. In the case where the semiconductor device includes the first dielectric layer 71, the cap layer 6 is located on the side of the first dielectric layer 71 facing away from the heterostructure 2.

[0061] The cap layer 6 includes a plurality of stepped layers 61 (at least two stepped layers 61) sequentially distributed along the first direction Y, that is, the cap layer 6 can be a stepped structure, and each stepped layer 61 corresponds to a step in the stepped structure. The stepped layer 61 can be horizontally arranged along the first direction Y, that is, the stepped layer 61 is arranged parallel to the substrate 1.

[0062] The spacing between the multiple step layers 61 and the heterostructure 2 increases successively along the first direction Y. The spacing between the step layer 61 and the heterostructure 2 includes the spacing between the bottom surface of the step layer 61 (the surface of the step layer 61 close to the substrate 1) and the top surface of the heterostructure 2 (the surface of the heterostructure 2 away from the substrate 1), and / or the spacing between the top surface of the step layer 61 (the surface of the step layer 61 away from the substrate 1) and the top surface of the heterostructure 2. The closer the step layer 61 is to the drain 4, the larger the spacing between the step layer 61 and the heterostructure 2, and the farther the step layer 61 is from the heterostructure 2; the closer the step layer 61 is to the gate 5, the smaller the spacing between the step layer 61 and the heterostructure 2, and the closer the step layer 61 is to the heterostructure 2.

[0063] In some embodiments, the cap layer 6 includes three stepped layers 61, namely, a first stepped layer 61a, a second stepped layer 61b, and a third stepped layer 61c. The first stepped layer 61a, the second stepped layer 61b, and the third stepped layer 61c are sequentially distributed between the gate 5 and the drain 4, that is, the first stepped layer 61a is arranged close to the gate 5, the third stepped layer 61c is arranged close to the drain 4, and the second stepped layer 61 is located between the first stepped layer 61a and the third stepped layer 61c. The spacing between the bottom surface of the first stepped layer 61a, the bottom surface of the second stepped layer 61b, and the bottom surface of the third stepped layer 61c and the top surface of the heterostructure 2 increases sequentially, and the spacing between the top surface of the first stepped layer 61a, the top surface of the second stepped layer 61b, and the top surface of the third stepped layer 61c and the top surface of the heterostructure 2 increases sequentially.

[0064] It should be noted that the cap layer 6 may also include two stepped layers 61, or more than three stepped layers 61. The number of stepped layers 61 may be set according to actual needs and is not specifically limited here.

[0065] The sizes of different step layers 61 may be the same or different. The size of the step layer 61 includes the thickness of the step layer 61, the length along the first direction Y and / or the width along the second direction Z. The thickness of the step layer 61 is required to be thin to avoid affecting the concentration of the two-dimensional electron gas in the heterostructure 2.

[0066] In the case where the heterostructure 2 includes an AlGaN / GaN heterojunction, the cap layer 6 may include a P-GaN cap layer, that is, the plurality of step layers 61 in the cap layer 6 include P-GaN, respectively.

[0067] In the related art, the gallium nitride (GaN) high electron mobility transistor (HEMT) grows a heterojunction on a silicon substrate wafer. In order to achieve a higher voltage resistance of the device, a thicker buffer layer needs to be grown on the silicon substrate wafer first, but the wafer is prone to warping after the buffer layer grows, resulting in cracks. Therefore, the material property limitations of the silicon substrate wafer make it difficult to apply to high-voltage (greater than 900V) gallium nitride power devices. Moreover, in the high-voltage off state, a very high electric field will appear inside the device, especially on the side of the gate close to the drain, and the device is easily broken down. Under the action of the high electric field, electrons are captured by internal defects, resulting in a current collapse effect. The related technology generally uses gate and source multi-field plates to modulate the electric field peak distribution to achieve higher voltage resistance of the device, but the multi-field plate structure process is complex and introduces multiple lithography layers.

[0068] The substrate 1 in this embodiment can be a sapphire substrate with high insulation properties. The sapphire substrate has high lateral withstand voltage (greater than 900V) and low leakage characteristics, which greatly improves the withstand voltage of the semiconductor device, without growing an excessively thick buffer layer on the substrate 1, to avoid the wafer from warping and causing cracks. In addition, a cap layer 6 is provided on the side of the gate 5 close to the drain 4, and the cap layer 6 includes a plurality of step layers 61 distributed in sequence along the first direction Y (the direction of the gate 5 toward the drain 4), and the spacing between the plurality of step layers 61 and the heterostructure 2 increases in sequence along the first direction Y, so as to adjust the off-state electric field on the side of the gate 5 close to the drain 4, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance. In addition, the structure of the cap layer 6 is simple, and compared with the multi-field plate structure in the related art, the photolithography level is less, the manufacturing process is simple, and the production efficiency is improved.

[0069] In some embodiments, the semiconductor device further includes a passivation layer (i.e., a first passivation layer 72), and the first passivation layer 72 is located on a side of the first dielectric layer 71 away from the heterostructure 2. The source 3 and the drain 4 can respectively penetrate the first passivation layer 72 and the first dielectric layer 71 along the thickness direction X from a layer of the first passivation layer 72 away from the first dielectric layer 71, and extend into the barrier layer 22. The gate 5 can penetrate the first passivation layer 72 along the thickness direction X from a side of the first passivation layer 72 away from the first dielectric layer 71, and extend into the first dielectric layer 71. The first passivation layer 72 may include one or more combinations of silicon oxide and silicon nitride.

[0070] A groove may be provided in the first passivation layer 72 and the first dielectric layer 71, and the groove may extend from the side of the first passivation layer 72 away from the first dielectric layer 71 along the thickness direction X to the inside of the first dielectric layer 71, that is, the bottom of the groove is located in the first dielectric layer 71. The side wall of the groove close to the drain 4 is a stepped side wall, and the stepped side wall includes a plurality of vertical surfaces (the vertical surface is perpendicular to the first direction Y) and a plurality of horizontal surfaces (the horizontal surface is perpendicular to the thickness direction X), and the plurality of vertical surfaces and the plurality of horizontal surfaces are alternately connected along the first direction Y. The spacing between the plurality of horizontal surfaces and the heterostructure 2 increases successively along the first direction Y.

[0071] The cap layer 6 is located at the bottom and stepped sidewall of the groove and the edge of the groove close to the stepped sidewall (the edge is located on the side of the first passivation layer 72 facing away from the substrate 1), the cap layer 6 located at the bottom of the groove can correspond to a stepped layer 61, the cap layer 6 on each horizontal plane can correspond to a stepped layer 61, and the cap layer 6 at the edge of the groove close to the stepped sidewall can correspond to a stepped layer 61, so that the cap layer 6 includes a plurality of stepped layers 61 distributed in sequence along the first direction Y, and the spacing between the plurality of stepped layers 61 and the heterostructure 2 increases in sequence along the first direction Y. For example, the first stepped layer 61a is located at the bottom of the groove, the second stepped layer 61b is located at the stepped sidewall of the groove, and the third stepped layer 61c is located at the edge of the groove close to the stepped sidewall (the surface of the first passivation layer 72 facing away from the substrate 1).

[0072] In some embodiments, the semiconductor device further includes a second dielectric layer 73, which is located on the side of the first passivation layer 72 away from the first dielectric layer 71, and the second dielectric layer 73 fills the groove. The second dielectric layer 73 can cover the source 3 and the drain 4, and the source 3 and the drain 4 can also penetrate the second dielectric layer 73 along the thickness direction X, that is, the source 3 and the drain 4 can penetrate the second dielectric layer 73, the first passivation layer 72 and the first dielectric layer 71 along the thickness direction X, and extend into the barrier layer 22. The gate 5 can penetrate the second dielectric layer 73 along the thickness direction X, that is, the gate 5 can penetrate the second dielectric layer 73 and the first passivation layer 72 along the thickness direction X, and extend into the first dielectric layer 71. The second dielectric layer 73 can include one or more combinations of silicon oxide, silicon nitride and aluminum oxide.

[0073] In some embodiments, the stepped layers 61 may extend along the second direction Z. The stepped layers 61 may have the same length along the second direction Z. The stepped layers 61 may have the same length along the second direction Z as the source 3 , the drain 4 , and the gate 5 .

[0074] In some embodiments, Figure 2 As shown, the step layer 61 includes a plurality of finger-shaped strips 611, and the plurality of finger-shaped strips 611 extend respectively along the first direction Y, and the plurality of finger-shaped strips 611 are arranged at intervals along the second direction Z. The spacing between adjacent finger-shaped strips 611 may be the same or different. In some embodiments, the plurality of finger-shaped strips 611 in the step layer 61 are uniformly distributed along the second direction Z. The overall length of the plurality of finger-shaped strips 611 in the step layer 61 along the second direction Z may be the same as the length of the source 3, the drain 4, and the gate 5 along the second direction Z.

[0075] The number of finger bars in different stepped layers 61 may be the same, and the finger bars 611 in different stepped layers 61 are arranged in one-to-one correspondence. For example, the multiple finger bars in the first stepped layer 61a are arranged in one-to-one correspondence with the multiple finger bars in the second stepped layer 61b, and the multiple finger bars in the second stepped layer 61b are arranged in one-to-one correspondence with the multiple finger bars in the third stepped layer 61c.

[0076] It should be noted that the number of finger-shaped strips 611 in the step layer 61 can be set according to actual needs and is not specifically limited here. The width of the finger-shaped strips 611 along the second direction Z can be set according to actual needs and is not specifically limited here. The spacing between adjacent finger-shaped strips 611 in the step layer 61 can be set according to actual needs and is not specifically limited here.

[0077] The stepped layer 61 in this embodiment includes a plurality of finger-shaped strips 611 spaced apart along the second direction Z, which can suppress the current collapse phenomenon while reducing the influence of the cap layer 6 on the concentration of the two-dimensional electron gas formed in the underlying heterostructure 2, so that the conduction performance of the device is not affected.

[0078] In some embodiments, the cap layer 6 is connected to the gate 5, that is, the cap layer 6 is in contact with the gate 5. When the cap layer 6 includes a plurality of stepped layers 61, the stepped layer 61 closest to the gate 5 in the cap layer 6 is connected to the gate 5, for example, the first stepped layer 61a may be connected to the gate 5. When the stepped layer 61 includes a plurality of finger strips 611, the plurality of finger strips 611 in the stepped layer 61 closest to the gate 5 are respectively connected to the gate 5.

[0079] In some embodiments, the cap layer 6 is spaced apart from the gate 5. When the cap layer 6 includes a plurality of stepped layers 61, the stepped layer 61 closest to the gate 5 in the cap layer 6 is spaced apart from the gate 5, for example, the first stepped layer 61a may be spaced apart from the gate 5. When the stepped layer 61 includes a plurality of finger strips 611, the plurality of finger strips 611 in the stepped layer 61 closest to the gate 5 are spaced apart from the gate 5, respectively, and the spacing between the plurality of finger strips 611 in the stepped layer 61 closest to the gate 5 and the gate 5 may be the same.

[0080] In some embodiments, the distance between the cap layer 6 and the gate 5 is 0.5 μm-2 μm.

[0081] It should be noted that the provision of the cap layer 6 will lead to a decrease in the concentration of the two-dimensional electron gas in the heterostructure 2 below, and the cap layer 6 located on the side of the gate 5 has a more obvious effect on the concentration of the two-dimensional electron gas below. In this embodiment, the cap layer 6 is spaced apart from the gate 5, that is, the cap layer 6 is floated, which can reduce the effect of the cap layer 6 on the concentration of the two-dimensional electron gas below, and the concentration of the two-dimensional electron gas between the floating cap layers 6 is not affected at all, so that the conduction performance of the device is not affected while suppressing the current collapse phenomenon.

[0082] In some embodiments, adjacent stepped layers 61 are spaced apart. Adjacent stepped layers 61 may be spaced apart along the first direction Y, and / or, adjacent stepped layers 61 may be spaced apart along the thickness direction X. In the case where the stepped layers 61 include a plurality of finger bars 611, the plurality of finger bars 611 in each stepped layer 61 may be spaced apart in a one-to-one correspondence with the plurality of finger bars 611 in the adjacent stepped layers 61. For example, the plurality of finger bars 611 in the first stepped layer 61a are spaced apart in a one-to-one correspondence with the plurality of finger bars 611 in the second stepped layer 61b, and the plurality of finger bars 611 in the second stepped layer 61b are spaced apart in a one-to-one correspondence with the plurality of finger bars 611 in the third stepped layer 61c.

[0083] In some embodiments, adjacent stepped layers 61 are connected. Adjacent stepped layers 61 may partially overlap and connect along the thickness direction X, and adjacent stepped layers 61 may partially overlap and connect along the first direction Y. In the case where the stepped layers 61 include a plurality of finger bars 611, the plurality of finger bars 611 in each stepped layer 61 may be connected in a one-to-one correspondence with the plurality of finger bars 611 in the adjacent stepped layers 61. For example, the plurality of finger bars 611 in the first stepped layer 61a are connected in a one-to-one correspondence with the plurality of finger bars 611 in the second stepped layer 61b, and the plurality of finger bars 611 in the second stepped layer 61b are connected in a one-to-one correspondence with the plurality of finger bars 611 in the third stepped layer 61c.

[0084] In some embodiments, the overall length of the cap layer 6 along the first direction Y is no greater than one third of the spacing between the gate 5 and the drain 4. When adjacent step layers 61 in the cap layer 6 are connected, or adjacent step layers 61 in the cap layer 6 are spaced apart along the thickness direction X, the overall length of the cap layer 6 along the first direction Y is the length of the cap layer 6 along the first direction Y. When adjacent step layers 61 in the cap layer 6 are spaced apart along the first direction Y, the overall length of the cap layer 6 along the first direction Y is the sum of the length of each step layer 61 along the first direction Y and the length of each gap (the gap between adjacent step layers 61) along the first direction Y. For example, the first step layer 61a, the second step layer 61b and the third step layer 61c are arranged at intervals along the first direction Y, and the overall length of the cap layer 6 along the first direction Y is the sum of the length of the first step layer 61a along the first direction Y, the length of the second step layer 61b along the first direction Y, the length of the third step layer 61c along the first direction Y, the length of the first gap (the gap between the first step layer 61a and the second step layer 61b) along the first direction Y, and the length of the second gap (the gap between the second step layer 61b and the third step layer 61c) along the first direction Y.

[0085] The lengths of the multiple stepped layers 61 in the cap layer 6 along the first direction Y may be the same or different. In some embodiments, the lengths of the multiple stepped layers 61 in the cap layer 6 along the first direction Y are the same.

[0086] The thicknesses of the plurality of stepped layers 61 in the cap layer 6 may be the same or different. In some embodiments, the thicknesses of the plurality of stepped layers 61 in the cap layer 6 are the same.

[0087] The multiple stepped layers 61 in the cap layer 6 of this embodiment have the same length and thickness, so that the multiple stepped layers 61 can be formed simultaneously during the manufacturing process, thereby simplifying the process flow and improving production efficiency.

[0088] In some embodiments, the thickness of the stepped layer 61 is 10 nm-100 nm. The thickness of the stepped layer 61 can be set to be relatively thin to avoid affecting the concentration of the two-dimensional electron gas below.

[0089] In some embodiments, the semiconductor device further includes a source contact 81, a drain contact 82, and a gate contact 83. The source contact 81 is located on the side of the source 3 facing away from the substrate 1 and connected to the source 3, the drain contact 82 is located on the side of the drain 4 facing away from the substrate 1 and connected to the drain 4, and the gate contact 83 is located on the side of the gate 5 facing away from the substrate 1 and connected to the gate 5. The source contact 81, the drain contact 82, and the gate contact 83 are used to be electrically connected to an external circuit to guide current from the external circuit into the interior of the transistor, or to guide current inside the transistor to the external circuit.

[0090] The source contact 81 , the drain contact 82 and the gate contact 83 may respectively include one or more combinations of copper, platinum, tungsten, gold, nickel and chromium.

[0091] In some embodiments, the semiconductor device further includes a third dielectric layer 74, which is located on a side of the second dielectric layer 73 away from the first passivation layer 72, and the third dielectric layer 74 may cover the source 3, the drain 4 and the gate 5. The third dielectric layer 74 may include one or more combinations of silicon oxide, silicon nitride and aluminum oxide.

[0092] The source contact 81 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the source 3, the drain contact 82 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the drain 4, and the gate contact 83 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the gate 5.

[0093] The source contact 81, the drain contact 82 and the gate contact 83 may be damascene structures, that is, the source contact 81, the drain contact 82 and the gate contact 83 may include a first part and a second part connected to each other, and the cross-sectional area of ​​the first part along the first direction Y is greater than the cross-sectional area of ​​the second part along the first direction Y. The first parts of the source contact 81, the drain contact 82 and the gate contact 83 are respectively located in a layer of the third dielectric layer 74 away from the substrate 1, and the second parts of the source contact 81, the drain contact 82 and the gate contact 83 respectively penetrate the third dielectric layer 74 along the thickness direction X, and the second part of the source contact 81 is connected between the first part of the source contact 81 and the source 3, the second part of the drain contact 82 is connected between the first part of the drain contact 82 and the drain 4, and the second part of the gate contact 83 is connected between the first part of the gate contact 83 and the gate 5.

[0094] In some embodiments, the semiconductor device further includes a second passivation layer 75, which covers the source contact 81, the drain contact 82, the gate contact 83 and the third dielectric layer 74. The second passivation layer 75 is used to seal the protection circuit. The second passivation layer 75 may include one or more combinations of silicon oxide and silicon nitride.

[0095] The second passivation layer 75 includes a first opening 91, a second opening 92, and a third opening 93. The first opening 91, the second opening 92, and the third opening 93 penetrate the second passivation layer 75 along the thickness direction X, respectively, and the first opening 91 exposes the source contact 81, the second opening 92 exposes the drain contact 82, and the third opening 93 exposes the gate contact 83. Electrical connection with an external circuit is achieved through the exposed source contact 81, the drain contact 82, and the gate contact 83.

[0096] In some embodiments, the semiconductor device further includes an isolation region 10 , which extends from the first dielectric layer 71 along the thickness direction X through the barrier layer 22 and the channel layer 21 to the buffer layer 23 , and the isolation region 10 is disposed around the device to isolate the device from other devices.

[0097] According to the semiconductor device provided by the embodiment of the present application, a cap layer 6 is provided on the side of the gate 5 close to the drain 4, and the cap layer 6 includes a plurality of step layers 61 distributed in sequence along the first direction Y (the direction of the gate 5 toward the drain 4), and the spacing between the plurality of step layers 61 and the heterostructure 2 increases in sequence along the first direction Y, so as to adjust the off-state electric field on the side of the gate 5 close to the drain 4, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance. In addition, the structure of the cap layer 6 is simple, so that the production of the cap layer 6 is simple, thereby simplifying the production process and improving production efficiency.

[0098] Correspondingly, an embodiment of the present application also provides a method for manufacturing a semiconductor device, which can manufacture the semiconductor device in the above embodiment.

[0099] like Figure 3 As shown, the method for manufacturing a semiconductor device provided in an embodiment of the present application includes steps 110 to 140.

[0100] Step 110: providing a substrate and a heterostructure located on one side of the substrate in a thickness direction.

[0101] Combination Figure 4 As shown, a substrate 1 is first provided, and the substrate 1 may include a silicon substrate, a silicon carbide substrate, a sapphire substrate or a GaN substrate, etc. In some embodiments, the substrate 1 includes a sapphire substrate, which can greatly improve the withstand voltage capability of the device in the vertical direction.

[0102] Then, a heterostructure 2 is formed on one side of the substrate 1 in the thickness direction X. A two-dimensional electron gas 2DEG is formed in the heterostructure 2, and the two-dimensional electron gas 2DEG is a main channel for electron transmission.

[0103] In some embodiments, the heterostructure 2 includes a buffer layer 23, a channel layer 21 and a barrier layer 22. Figure 4 As shown, a buffer layer 23 is first formed on one side of the substrate 1 in the thickness direction X by using a thin film deposition process. Then, a channel layer 21 is formed on the side of the buffer layer 23 away from the substrate 1 by using a thin film deposition process. Then, a barrier layer 22 is formed on the side of the channel layer 21 away from the buffer layer 23 by using a thin film deposition process. Among them, the thin film deposition process includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc.

[0104] The channel layer 21 and the barrier layer 22 form a heterojunction. Due to the difference in the band structures of the two materials of the channel layer 21 and the barrier layer 22, a band bend is formed at the interface between the channel layer 21 and the barrier layer 22, thereby generating a potential well in the channel layer 21, and electrons are confined in the potential well to form a two-dimensional electron gas 2DEG.

[0105] The buffer layer 23 may include GaN. The thickness of the buffer layer 23 may be 1 μm-2 μm. The channel layer 21 may include GaN, the barrier layer 22 may include AlGaN, and the channel layer 21 and the barrier layer 22 may form an AlGaN / GaN heterojunction, that is, the heterostructure 2 may include an AlGaN / GaN heterojunction. The thickness of the channel layer 21 may be 200 nm, and the thickness of the barrier layer 22 may be 25 nm.

[0106] After the substrate 1 and the heterostructure 2 are formed, an epitaxial wafer is obtained, and impurities on the surface of the epitaxial wafer are removed by a chemical reagent (such as acetone, etc.) to facilitate subsequent film layer production.

[0107] Step 120: forming a source electrode and a drain electrode on a side of the heterostructure facing away from the substrate, wherein the source electrode and the drain electrode are sequentially spaced apart and distributed along a first direction, and the first direction is perpendicular to the thickness direction.

[0108] Combination Figure 5 As shown, the source 3 and the drain 4 are respectively located on the side of the heterostructure 2 away from the substrate 1 and extend into the heterostructure 2 along the thickness direction X. The source 3 and the drain 4 are sequentially spaced and distributed along the first direction Y, and the first direction Y is perpendicular to the thickness direction X. Figure 2 As shown, the source 3 and the drain 4 can extend along the second direction Z, respectively, and the second direction Z is perpendicular to the first direction Y and the thickness direction X. The source 3 and the drain 4 are respectively connected to the heterostructure 2, and the source 3 and the drain 4 use the two-dimensional electron gas 2DEG formed in the heterostructure 2 as a conductive channel to realize the transmission of current. When a voltage is applied between the source 3 and the drain 4, the electrons in the two-dimensional electron gas 2DEG flow along the channel to form a current from the source 3 to the drain 4.

[0109] In some embodiments, forming a source and a drain on a side of the heterostructure facing away from the substrate in step 120 includes:

[0110] forming a first dielectric layer on a side of the heterostructure facing away from the substrate;

[0111] A source electrode and a drain electrode are formed on a side of the first dielectric layer away from the heterostructure, and the source electrode and the drain electrode respectively penetrate the first dielectric layer along the thickness direction and extend into the heterostructure.

[0112] Combination Figure 5 As shown, a thin film deposition process is first used to form a first dielectric layer 71 on the side of the barrier layer 22 away from the channel layer 21. The first dielectric layer 71 may include one or more combinations of silicon oxide, silicon nitride, and aluminum oxide.

[0113] Then, an etching process is used to form a source hole and a drain hole in the first dielectric layer 71, and the source hole and the drain hole respectively penetrate the first dielectric layer 71 along the thickness direction X. By electron beam evaporation, an ohmic metal layer is formed on the side of the first dielectric layer 71 away from the heterostructure 2, and the electrode layer fills the source hole and the drain hole. Through annealing, metal atoms diffuse into the heterostructure 2 to achieve good electrical contact. Then, an etching process is used to etch the ohmic metal layer to form a source 3 and a drain 4. The source 3 and the drain 4 respectively penetrate the first dielectric layer 71 along the thickness direction X from the side of the first dielectric layer 71 away from the heterostructure 2, and extend to the barrier layer 22.

[0114] The source electrode 3 may include one or more combinations of copper, titanium, aluminum, nickel, gold, etc. The drain electrode 4 may include one or more combinations of copper, titanium, aluminum, nickel, gold, etc.

[0115] Then, the isolation region is defined by photolithography, and the isolation region 10 of the device is formed by ion implantation. The isolation region 10 extends from the first dielectric layer 71 along the thickness direction X through the barrier layer 22 and the channel layer 21 to the buffer layer 23, and the isolation region 10 is arranged around the device to isolate the device from other devices.

[0116] Step 130: forming a cap layer on a side of the heterostructure facing away from the substrate, the cap layer being located between the source and the drain, the cap layer comprising a plurality of stepped layers sequentially distributed along a first direction, and the spacing between the plurality of stepped layers and the heterostructure sequentially increasing along the first direction.

[0117] Combination Figure 6 and Figure 7 As shown, the cap layer 6 is located on the side of the heterostructure 2 facing away from the substrate 1, and the cap layer 6 is arranged between the source 3 and the drain 4 along the first direction Y. The cap layer 6 includes a plurality of stepped layers 61 (at least two stepped layers 61) sequentially distributed along the first direction Y, and the stepped layers 61 can be arranged horizontally along the first direction Y, that is, the stepped layers 61 are arranged parallel to the substrate 1.

[0118] The spacing between the multiple stepped layers 61 and the heterostructure 2 increases sequentially along the first direction Y. The closer the stepped layer 61 is to the drain 4, the larger the spacing between the stepped layer 61 and the heterostructure 2, and the farther the stepped layer 61 is from the heterostructure 2; the closer the stepped layer 61 is to the gate 5, the smaller the spacing between the stepped layer 61 and the heterostructure 2, and the closer the stepped layer 61 is to the heterostructure 2.

[0119] The sizes of different step layers 61 may be the same or different. The size of the step layer 61 includes the thickness of the step layer 61, the length along the first direction Y and / or the width along the second direction Z. The thickness of the step layer 61 is required to be thin to avoid affecting the concentration of the two-dimensional electron gas in the heterostructure 2.

[0120] In the case where the heterostructure 2 includes an AlGaN / GaN heterojunction, the cap layer 6 may include a P-GaN cap layer, that is, the plurality of step layers 61 in the cap layer 6 include P-GaN, respectively.

[0121] In some embodiments, forming a cap layer on a side of the heterostructure facing away from the substrate in step 130 includes:

[0122] A passivation layer is formed on the side of the first dielectric layer away from the heterostructure; the source electrode and the drain electrode also penetrate the passivation layer respectively;

[0123] forming a groove in the passivation layer and the first dielectric layer between the source and the drain, the groove comprising a stepped sidewall close to the drain;

[0124] A cap layer is formed on the bottom of the groove, the stepped sidewall and the edge of the groove close to the stepped sidewall.

[0125] like Figure 6 As shown, a thin film deposition process is first used to form a passivation layer (ie, first passivation layer 72) on the side of the first dielectric layer 71 away from the heterostructure 2. The source electrode 3 and the drain electrode 4 also penetrate the first passivation layer 72 along the thickness direction X respectively.

[0126] Then, an etching process is used to form a groove 60 in the first passivation layer 72 and the first dielectric layer 71. The number of etchings can be matched based on the number of step layers 61 in the cap layer 6. For example, if the cap layer 6 includes three step layers, namely the first step layer 61a, the second step layer 61b and the third step layer 61c, two etchings can be used to form the groove 60 in the first passivation layer 72 and the first dielectric layer 71. The groove can extend from the side of the first passivation layer 72 away from the first dielectric layer 71 along the thickness direction X to the inside of the first dielectric layer 71, that is, the bottom of the groove 60 is located in the first dielectric layer 71, and the sidewall of the groove 60 close to the drain 4 is a stepped sidewall.

[0127] Then, a thin film deposition process is used to form an initial cap layer on the surface of the first passivation layer 72 facing away from the first dielectric layer 71 and the bottom and sidewall of the groove 60. An etching process is used to etch the initial cap layer to form a cap layer 6, such as Figure 7 As shown. The cap layer 6 covers the bottom and stepped sidewall of the groove 60 and the edge of the groove 60 close to the stepped sidewall, so that the cap layer 6 includes a plurality of stepped layers 61. For example, the first stepped layer 61a in the cap layer 6 is located at the bottom of the groove 60, the second stepped layer 61b in the cap layer 6 is located at the stepped sidewall of the groove 60, and the third stepped layer 61c in the cap layer 6 is located at the edge of the groove 60 close to the stepped sidewall.

[0128] Step 140: forming a gate on a side of the heterostructure facing away from the substrate, wherein the gate is located on a side of the cap layer close to the source.

[0129] Combination Figure 8 and Fig. 9 As shown, the gate 5 is located on the side of the heterostructure 2 facing away from the substrate 1, and the gate 5 and the heterostructure 2 are spaced apart in the thickness direction X. The gate 5 is located on the side of the cap layer 6 close to the source 3, that is, the gate 5 is located between the source 3 and the cap layer 6, and the gate 5 and the source 3 are spaced apart in the first direction Y. Figure 2 As shown, the gate 5 may extend along the second direction Z. The gate 5 is located above the two-dimensional electron gas 2DEG formed in the heterostructure 2. The concentration and shape of the two-dimensional electron gas 2DEG may be controlled by adjusting the voltage of the gate 5, thereby controlling the current between the source 3 and the drain 4. The gate 5 may include one or more combinations of copper, platinum, tungsten, gold, nickel, and chromium.

[0130] In some embodiments, forming a gate on a side of the heterostructure facing away from the substrate includes:

[0131] forming a second dielectric layer on a side of the passivation layer away from the first dielectric layer, and the second dielectric layer covers the cap layer;

[0132] A gate is formed which penetrates the second dielectric layer and the passivation layer in the thickness direction and extends into the first dielectric layer.

[0133] After forming the cap layer 6, as Figure 8 As shown, a second dielectric layer 73 is formed on the side of the first passivation layer 72 away from the first dielectric layer 71 by a thin film deposition process, and the second dielectric layer 73 fills the groove 60 and covers the cap layer 6. The source 3 and the drain 4 may also penetrate the second dielectric layer 73 along the thickness direction X. The second dielectric layer 73 may include one or more combinations of silicon oxide, silicon nitride, and aluminum oxide.

[0134] Then, if Fig. 9 As shown, an ohmic metal layer is deposited by electron beam evaporation process, and the ohmic metal layer is etched by etching process to form a gate 5. The gate 5 can penetrate the second dielectric layer 73 and the first passivation layer 72 along the thickness direction X and extend into the first dielectric layer 71.

[0135] In some embodiments, the stepped layer 61 may extend along the second direction Z.

[0136] In some embodiments, Figure 2 As shown, the stepped layer 61 includes a plurality of finger-shaped strips 611 , and the plurality of finger-shaped strips 611 extend along the first direction Y respectively, and the plurality of finger-shaped strips 611 are arranged at intervals along the second direction Z.

[0137] The stepped layer 61 in this embodiment includes a plurality of finger-shaped strips 611 spaced apart along the second direction Z, which can suppress the current collapse phenomenon while reducing the influence of the cap layer 6 on the concentration of the two-dimensional electron gas formed in the underlying heterostructure 2, so that the conduction performance of the device is not affected.

[0138] In some embodiments, the cap layer 6 is connected to the gate 5 , that is, the cap layer 6 is in contact with the gate 5 .

[0139] In some embodiments, the cap layer 6 is spaced apart from the gate 5 .

[0140] In some embodiments, the distance between the cap layer 6 and the gate 5 is 0.5 μm-2 μm.

[0141] In this embodiment, the cap layer 6 is spaced apart from the gate 5, that is, the cap layer 6 is floating, which can reduce the influence of the cap layer 6 on the concentration of the two-dimensional electron gas below, and the concentration of the two-dimensional electron gas between the floating cap layers 6 is not affected in any way, thereby suppressing the current collapse phenomenon while keeping the conduction performance of the device unaffected.

[0142] In some embodiments, adjacent stepped layers 61 are arranged at intervals.

[0143] In some embodiments, adjacent stepped layers 61 are connected.

[0144] In some embodiments, the entire length of the cap layer 6 along the first direction Y is no greater than one third of the distance between the gate 5 and the drain 4 .

[0145] In some embodiments, the thickness of the stepped layer 61 is 10 nm-100 nm. The thickness of the stepped layer 61 can be set to be relatively thin to avoid affecting the concentration of the two-dimensional electron gas below.

[0146] In some embodiments, the method for manufacturing a semiconductor device further includes:

[0147] Forming a third dielectric layer on a side of the second dielectric layer away from the first passivation layer, wherein the third dielectric layer covers the source electrode, the drain electrode and the gate electrode;

[0148] A source contact, a drain contact and a gate contact are formed on the side of the third dielectric layer away from the second dielectric layer, penetrating the third dielectric layer in the thickness direction, and the source contact is connected to the source, the drain contact is connected to the drain, and the gate contact is connected to the gate;

[0149] forming a second passivation layer covering the source contact, the drain contact, and the gate contact;

[0150] A first opening, a second opening and a third opening are formed to penetrate the second passivation layer along the thickness direction, and the first opening exposes the source contact, the second opening exposes the drain contact, and the third opening exposes the gate contact.

[0151] Combination Figure 1 As shown, a thin film deposition process is first used to form a third dielectric layer 74 on the side of the second dielectric layer 73 away from the first passivation layer 72, and the third dielectric layer 74 can cover the source 3, the drain 4 and the gate 5. The third dielectric layer 74 can include one or more combinations of silicon oxide, silicon nitride and aluminum oxide.

[0152] Then, an etching process is used to form a first through hole, a second through hole and a third through hole that penetrate the third dielectric layer 74 along the thickness direction X, and the first through hole exposes the source electrode 3, the second through hole exposes the drain electrode 4, and the third through hole exposes the gate electrode 5. A thin film deposition process is used to form a metal layer on the side of the third dielectric layer 74 away from the second dielectric layer 73, and the metal layer fills the first through hole, the second through hole and the third through hole. An etching process is used to etch the metal layer to form a source contact 81, a drain contact 82 and a gate contact 83.

[0153] The source contact 81 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the source 3, the drain contact 82 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the drain 4, and the gate contact 83 penetrates the third dielectric layer 74 along the thickness direction X from the side of the third dielectric layer 74 away from the substrate 1 and is connected to the gate 5.

[0154] Then, a thin film deposition process is used to form a second passivation layer 75 covering the source contact 81, the drain contact 82, the gate contact 83 and the third dielectric layer 74. The second passivation layer 75 is used to seal the protection circuit. The second passivation layer 75 may include one or more combinations of silicon oxide and silicon nitride.

[0155] By using an etching process, a first opening 91, a second opening 92, and a third opening 93 are formed in the second passivation layer 75. The first opening 91, the second opening 92, and the third opening 93 penetrate the second passivation layer 75 along the thickness direction X, respectively, and the first opening 91 exposes the source contact 81, the second opening 92 exposes the drain contact 82, and the third opening 93 exposes the gate contact 83. Electrical connection with an external circuit is achieved through the exposed source contact 81, the drain contact 82, and the gate contact 83.

[0156] According to the method for manufacturing a semiconductor device provided by an embodiment of the present application, a cap layer 6 is provided on the side of the gate 5 close to the drain 4, and the cap layer 6 includes a plurality of step layers 61 sequentially distributed along the first direction Y (the direction of the gate 5 toward the drain 4), and the spacing between the plurality of step layers 61 and the heterostructure 2 increases sequentially along the first direction Y, so as to adjust the off-state electric field on the side of the gate 5 close to the drain 4, reduce the peak value of the off-state electric field, greatly improve the lateral breakdown voltage, suppress or even eliminate the current collapse effect, and reduce the on-resistance. In addition, the structure of the cap layer 6 is simple, so that the cap layer 6 is simple to manufacture, thereby simplifying the manufacturing process and improving production efficiency.

[0157] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0158] In the description of the present application, “plurality” means two or more.

[0159] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0160] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: substrate; A heterostructure located on one side of the substrate in a thickness direction; A source electrode, a drain electrode and a gate electrode are respectively located on a side of the heterostructure away from the substrate, and the source electrode, the gate electrode and the drain electrode are sequentially spaced and distributed along a first direction, and the first direction is perpendicular to the thickness direction; A cap layer is located on a side of the heterostructure away from the substrate and on a side of the gate close to the drain, wherein the cap layer includes a plurality of stepped layers sequentially distributed along the first direction, and the spacing between the plurality of stepped layers and the heterostructure increases sequentially along the first direction.

2. The semiconductor device according to claim 1, wherein: The stepped layer includes a plurality of finger-shaped strips extending along the first direction, and the plurality of finger-shaped strips are distributed at intervals along a second direction, and the second direction is respectively perpendicular to the first direction and the thickness direction.

3. The semiconductor device according to claim 1, wherein: An overall length of the cap layer along the first direction is no greater than one third of a distance between the gate and the drain.

4. The semiconductor device according to claim 1, wherein: Adjacent step layers are arranged at intervals, or adjacent step layers are connected.

5. The semiconductor device according to claim 1, wherein: The cap layer is spaced apart from the gate, or the cap layer is connected to the gate.

6. The semiconductor device according to claim 5, characterized in that: The distance between the cap layer and the gate is 0.5 μm-2 μm.

7. The semiconductor device according to claim 1, wherein: The thicknesses of the plurality of stepped layers are the same, and / or the lengths of the plurality of stepped layers along the first direction are the same.

8. The semiconductor device according to claim 7, characterized in that The thickness of the stepped layer is 10nm-100nm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The substrate includes a sapphire substrate, the heterostructure includes an AlGaN / GaN heterojunction, and the cap layer includes a P-GaN cap layer.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate and a heterostructure located on one side of the substrate in a thickness direction; forming a source electrode and a drain electrode on a side of the heterostructure away from the substrate, wherein the source electrode and the drain electrode are sequentially spaced apart along a first direction, and the first direction is perpendicular to the thickness direction; forming a cap layer on a side of the heterostructure away from the substrate, the cap layer being located between the source electrode and the drain electrode, the cap layer comprising a plurality of stepped layers sequentially distributed along the first direction, and the spacing between the plurality of stepped layers and the heterostructure sequentially increasing along the first direction; A gate is formed on a side of the heterostructure facing away from the substrate, and the gate is located on a side of the cap layer close to the source.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The forming of a source and a drain on a side of the heterostructure away from the substrate comprises: forming a first dielectric layer on a side of the heterostructure facing away from the substrate; A source electrode and a drain electrode are formed on a side of the first dielectric layer away from the heterostructure, and the source electrode and the drain electrode respectively penetrate the first dielectric layer along the thickness direction and extend into the heterostructure.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The forming of a cap layer on a side of the heterostructure facing away from the substrate comprises: A passivation layer is formed on a side of the first dielectric layer away from the heterostructure; the source electrode and the drain electrode also penetrate through the passivation layer respectively; forming a groove in the passivation layer and the first dielectric layer between the source electrode and the drain electrode, the groove comprising a stepped sidewall close to the drain electrode; A cap layer is formed on the bottom of the groove, the stepped sidewall, and the edge of the groove close to the stepped sidewall.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: The step of forming a gate on a side of the heterostructure facing away from the substrate comprises: forming a second dielectric layer on a side of the passivation layer away from the first dielectric layer, and the second dielectric layer covers the cap layer; A gate is formed which penetrates the second dielectric layer and the passivation layer along the thickness direction and extends into the first dielectric layer.

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