Three-dimensional structure GaN integrated circuit chip and preparation method thereof

Abstract

The invention discloses a GaN integrated circuit chip with a three-dimensional structure and a preparation method thereof, the chip comprises a GaN substrate, and a plurality of stages of wiring dielectric layers and isolation dielectric layers which are sequentially staggered and stacked from bottom to top, at least one nth integrated circuit is clamped between the nth wiring dielectric layer and the (n-1) th isolation dielectric layer, n is a positive integer, and n is a positive integer. The zero-level isolation dielectric layer is a substrate dielectric layer; at least one nth-stage first through hole which penetrates through the nth-stage isolation dielectric layer and is communicated with the (n + 1) th-stage integrated circuit and the nth-stage integrated circuit is formed in the nth-stage isolation dielectric layer; and the (n + 1) th-level integrated circuit and the nth-level integrated circuit are connected through a wire or a metal bonding effect based on the nth-level first through hole. According to the chip provided by the invention, the utilization rate and the integration degree of the wafer can be improved through three-dimensional wiring.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chips, and in particular relates to a three-dimensional GaN integrated circuit chip and a preparation method thereof. Background Art

[0002] In recent years, in order to meet the trend of higher power and higher frequency electronic devices and the increasing miniaturization of integrated circuits, the design and preparation process of the third-generation semiconductor materials represented by gallium nitride (GaN) have made great progress. GaN is a new type of wide bandgap semiconductor material with a wide bandgap width, which brings the characteristics of high voltage resistance, breakdown resistance, and radiation resistance, and is particularly suitable for high-power radio frequency electronic devices. With the development of gallium nitride P-type doping technology and molecular beam epitaxy process, GaN-based high electron mobility transistors (HEMT) have gradually become the mainstream application of GaN materials in integrated circuits. The principle is to confine the two-dimensional electron gas in the GaN layer with less obstruction by constructing an AlGaN / GaN heterojunction to achieve extremely high electron mobility, peak electron velocity and saturation electron velocity at room temperature, thereby obtaining advantages far higher than those of second-generation semiconductor MOSFET devices. However, with the continuous improvement of integration requirements and the continuous increase in the number of active areas on GaN wafers, wiring on single-layer HEMT devices not only wastes a lot of expensive GaN wafer space, but also is not conducive to the increase of integration. Currently, the active area of ​​a gallium nitride monolithic circuit occupies only 10% of the wafer area, and the remaining space is all used for wiring, resulting in a large amount of gallium nitride space being wasted.

[0003] Therefore, the low integration of GaN transistors with single-layer wiring in current RF chips leads to low wafer utilization. Summary of the invention

[0004] The embodiment of the present invention provides a three-dimensional GaN integrated circuit chip and a method for preparing the same, which can solve the problem of low wafer utilization rate caused by low integration of GaN transistors with single-layer wiring in current radio frequency chips.

[0005] In a first aspect, an embodiment of the present invention provides a three-dimensional GaN integrated circuit chip, comprising:

[0006] A GaN substrate, the GaN substrate comprising a GaN substrate and an insulating substrate dielectric layer arranged on the upper surface of the GaN substrate;

[0007] Multiple levels of wiring dielectric layers and isolation dielectric layers are alternately stacked from bottom to top, and the first level of wiring dielectric layer is arranged on the upper surface of the base dielectric layer;

[0008] At least one n-th level integrated circuit is sandwiched between the n-th level wiring dielectric layer and the n-1-th level isolation dielectric layer, n is a positive integer, and the 0-th level isolation dielectric layer is a base dielectric layer; at least one n-th level first through hole is arranged on the n-th level isolation dielectric layer, which penetrates the n-th level isolation dielectric layer and connects the n+1-th level integrated circuit and the n-th level integrated circuit; the n+1-th level integrated circuit and the n-th level integrated circuit are connected based on the n-th level first through hole through a wire or a metal bonding action.

[0009] In a second aspect, an embodiment of the present invention provides a method for preparing a three-dimensional GaN integrated circuit chip, comprising:

[0010] Prepare a GaN substrate, wherein the GaN substrate comprises a GaN substrate and an insulating substrate dielectric layer arranged on the upper surface of the GaN substrate;

[0011] preparing an n-th level integrated circuit on the upper surface of the n-1-th level isolation dielectric layer, where n is a positive integer and the 0-th level isolation dielectric layer is a base dielectric layer;

[0012] Depositing an n-level wiring dielectric layer on the upper surface of the n-1-level isolation dielectric layer and the n-level integrated circuit;

[0013] An n-level isolation dielectric layer is deposited on the upper surface of the n-level wiring dielectric layer and an n-level first through hole is photoetched on the n-level isolation dielectric layer, wherein the n-level first through hole penetrates the n-level isolation dielectric layer and connects the n+1-level integrated circuit and the n-level integrated circuit; the n+1-level integrated circuit and the n-level integrated circuit are connected based on the n-level first through hole through a wire or metal bonding.

[0014] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: according to the chip provided by the present invention, by arranging each integrated circuit in different wiring dielectric layers at intervals and arranging penetrating through holes in the isolation dielectric layer between two integrated circuits to connect integrated circuits of different levels, three-dimensional wiring can be realized in the semiconductor chip, and the wiring area can be reduced compared with the chip with planar wiring, thereby improving the utilization rate of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic structural diagram of a three-dimensional GaN integrated circuit chip provided by an embodiment of the present invention;

[0016] Figure 2 A specific structural diagram of a three-dimensional GaN integrated circuit chip provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of wiring of an interconnected integrated circuit provided by an embodiment of the present invention;

[0018] Figure 4 A flowchart of a method for preparing a GaN substrate in a three-dimensional structured GaN integrated circuit chip provided by the present invention;

[0019] Figure 5a-5g A schematic diagram of a manufacturing process of a GaN substrate provided in an embodiment of the present invention;

[0020] Figure 6 A flowchart of a method for preparing a three-dimensional GaN integrated circuit chip provided by the present invention;

[0021] Figure 7a-7c A schematic diagram of the manufacturing process of a three-dimensional GaN integrated circuit chip provided in an embodiment of the present invention.

[0022] Reference numerals:

[0023] 1: GaN substrate; 11: GaN base; 111: substrate; 112: buffer layer; 113: channel layer; 114: barrier layer; 115: first passivation layer; 116: second passivation layer; 12: substrate dielectric layer; 2: wiring dielectric layer; 3: isolation dielectric layer; 4: integrated circuit; 5: first through hole; 61: second through hole; 62: source electrode; 71: third through hole; 72: drain electrode; 8: gate electrode; 9: metal electrode. DETAILED DESCRIPTION

[0024] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0025] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0026] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0027] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0028] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0030] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0031] Example 1

[0032] Figure 1 Shown is a schematic structural diagram of a three-dimensional GaN integrated circuit chip provided by an embodiment of the present invention.

[0033] In some embodiments, the three-dimensional structure GaN integrated circuit chip may include a GaN substrate 1 and a multi-level wiring dielectric layer 2 and an isolation dielectric layer 3 that are stacked alternately from bottom to top. An integrated circuit 4 is sandwiched between the wiring dielectric layer 2 and the isolation dielectric layer 3, and a first through hole 5 is also provided on the isolation dielectric layer.

[0034] In one possible implementation, see Figure 1 The GaN substrate 1 may include a GaN base plate 11 and an insulating base dielectric layer 12 .

[0035] Exemplarily, the base dielectric layer 12 may be disposed on the upper surface of the GaN substrate 11 .

[0036] Exemplarily, the GaN substrate 11 may be a GaN-type semiconductor structure.

[0037] In one example, the material of the base dielectric layer 12 may include SiO 2 .

[0038] Optionally, the material of the base dielectric layer 12 may also include insulating materials such as SiN, TiN, and BN.

[0039] In one possible implementation, see Figure 1 At least one n-th level integrated circuit may be sandwiched between the n-th level wiring dielectric layer and the n-1-th level isolation dielectric layer. The n-th level first through hole may penetrate the n-th level isolation dielectric layer and connect the n+1-th level integrated circuit and the n-th level integrated circuit.

[0040] Exemplarily, n is a positive integer.

[0041] Exemplarily, the n-th level integrated circuit and the (n+1)-th level integrated circuit may be connected via a wire or metal bonding based on the n-th level first via.

[0042] For example, see Figure 1 Two first-level integrated circuits 41 are arranged inside the first-level wiring dielectric layer 21, and one second-level integrated circuit 42 is arranged inside the second-level wiring dielectric layer 22. The first-level integrated circuit 41 and the second-level integrated circuit 42 can be connected by using a wire passing through two first-level first through holes 51.

[0043] In one example, the material of the wiring dielectric layer 2 and the isolation dielectric layer 3 may also include SiO2.

[0044] Optionally, the material of the wiring dielectric layer 2 and the isolation dielectric layer 3 may also include insulating materials such as SiN, TiN, and BN.

[0045] According to the chip provided by the present invention, by arranging each integrated circuit in different wiring dielectric layers at intervals and arranging penetrating through holes in the isolation dielectric layer between two integrated circuits to connect integrated circuits of different levels, three-dimensional wiring can be realized in the semiconductor chip. Compared with the chip with planar wiring, the wiring area can be reduced, thereby improving the utilization rate of the wafer.

[0046] Example 2

[0047] Based on Example 1 Figure 2 Shown is a specific structural diagram of a three-dimensional GaN integrated circuit chip provided by an embodiment of the present invention.

[0048] In some embodiments, see Figure 2 The GaN substrate 11 may include a substrate 111 , a buffer layer 112 , a channel layer 113 , a barrier layer 114 , a first passivation layer 115 , and a second passivation layer 116 stacked sequentially from bottom to top.

[0049] A gate groove may be provided on the first passivation layer 115, and a source groove and a drain groove may be provided on part of the barrier layer 114 and the first passivation layer 115 on both sides of the gate groove. The source electrode 62, the gate electrode 8, and the drain electrode 72 are respectively provided in the source groove, the gate groove, and the drain groove. A second through hole 61 and a third through hole 71 penetrating the second passivation layer and the substrate dielectric layer may also be provided above the source electrode 62 and the drain electrode 72. The second through hole 61 may connect the source electrode 62 and the first-level integrated circuit 41, and the third through hole 71 may connect the drain electrode 72 and the first-level integrated circuit. The gate electrode 8, the source electrode 62, and the drain electrode 72 may be connected to the first-level integrated circuit 41 by metal bonding.

[0050] In a possible implementation, the GaN substrate 11 may be a semiconductor structure formed by epitaxially growing an AlGaN / GaN heterojunction on a SiC substrate.

[0051] For example, the substrate 111 may be made of SiC, the buffer layer 112 may be made of GaN, the channel layer 113 may be made of GaN, and the barrier layer 114 may be made of AlGaN. The buffer layer 112, the channel layer 113 and the barrier layer 114 together form an AlGaN / GaN heterojunction.

[0052] In one example, the thickness of the substrate 111 may be less than or equal to 75 μm, the thickness of the buffer layer 112 may be less than or equal to 1.5 μm, the thickness of the channel layer 113 may be less than or equal to 0.5 μm, and the thickness of the barrier layer 114 may be less than or equal to 30 nm.

[0053] In a possible implementation, the first passivation layer 115 and the second passivation layer 116 may be made of an insulating material, such as SiN, to isolate the gate electrode, the drain electrode, and the source electrode.

[0054] In one example, the thickness of the first passivation layer 115 may be less than or equal to 120 nm, and the thickness of the second passivation layer 116 may be less than or equal to 140 nm.

[0055] In some embodiments, the number N of levels of wiring dielectric layers and isolation dielectric layers may be greater than or equal to 2 (only 2 levels are shown here).

[0056] In one possible implementation, see Figure 1 and Figure 2 A metal electrode 9 may be provided on the upper surface of the N-th level isolation dielectric layer, and the N-th level first through hole may penetrate the N-th level isolation dielectric layer and connect the metal electrode 9 and the N-th level integrated circuit.

[0057] For example, see Figure 2 The second-level first through hole 52 can be set between the metal electrode 9 and a second-level integrated circuit 42, and a wire can be passed through the second-level first through hole 52 to connect the metal electrode 9 and the second-level integrated circuit 42.

[0058] In one example, the thickness of the base dielectric layer 12 may be less than or equal to 0.4 μm, the thickness of the first-level wiring dielectric layer 21 may be less than or equal to 1 μm, the thickness of the first-level isolation dielectric layer 31 may be less than or equal to 0.5 μm, the thickness of the second-level wiring dielectric layer 22 may be less than or equal to 1 μm, and the thickness of the second-level isolation dielectric layer 32 may be less than or equal to 1 μm. Such a configuration can prevent wafer warping and stress concentration.

[0059] In one possible implementation, if there are x integrated circuits at the nth level, y integrated circuits at the n+1th level, and z first through holes between the two layers of integrated circuits, and z is less than the maximum value between x and y, then in the wiring medium layer with a larger number of integrated circuits, some of the integrated circuits can be interconnected integrated circuits.

[0060] For example, see Figure 2 , there are two first-level integrated circuits 41 and two second-level integrated circuits 42, and there is only one first-level first through hole, then the two second-level integrated circuits can be interconnected integrated circuits (see Figure 3 ).

[0061] According to the chip provided by the present invention, by arranging each integrated circuit in different wiring dielectric layers at intervals and arranging penetrating through holes in the isolation dielectric layer between two integrated circuits to connect integrated circuits of different levels, three-dimensional wiring can be realized in the semiconductor chip. Compared with the chip with planar wiring, the wiring area can be reduced, thereby improving the utilization rate of the wafer.

[0062] Example 3

[0063] Based on Example 2, Figure 4 The flowchart shown is a method for preparing a GaN substrate in a three-dimensional GaN integrated circuit chip provided by the present invention. As an example but not a limitation, the method for preparing a GaN substrate may include steps S401-S406, and each step is described below.

[0064] S401, preparing a substrate, and sequentially growing a buffer layer, a channel layer and a barrier layer on the substrate.

[0065] For example, a substrate 111 may be provided, and then a GaN / AlGaN heterojunction substrate including a buffer layer 112, a channel layer 113 and a barrier layer 114 may be grown on the substrate to obtain a GaN / AlGaN heterojunction substrate. Figure 5a The structure shown.

[0066] S402 , depositing a first passivation layer on the upper surface of the barrier layer.

[0067] In one example, a 120 nm thick SiN film may be deposited on the upper surface of the barrier layer 114 using a plasma enhanced chemical vapor deposition process to form the first passivation layer 115. Figure 5b The structure shown.

[0068] Exemplarily, SiH4 and NH3 can be used as nitrogen source and silicon source respectively, and the first passivation layer 115 can be deposited by plasma enhanced chemical vapor deposition process under the conditions of flow ratio of NH3:SiH4=1:2, reaction chamber pressure of 600mTorr, deposition temperature of 250°C, and RF power of 60W.

[0069] S403, etching a gate groove on the first passivation layer and sputtering a gate metal in the gate groove to form a gate electrode.

[0070] In one example, a plasma lithography technique may be used to etch a gate groove on the first passivation layer 115 .

[0071] For example, Cl2 or BCl3 can be used as etching gas, and a gate groove is formed on the first passivation layer 115 by photolithography of the gate image area under the conditions of a pressure of 5 mTorr, an upper electrode power of 100 W, a lower electrode power of 10 W, and an etching time of 40 s, to obtain the following: Figure 5c The structure shown.

[0072] In one example, a magnetron sputtering technique may be used to sputter a gate metal into a gate groove on the surface of the first passivation layer 115 to form a gate electrode.

[0073] For example, the GaN substrate after the gate groove is etched (see Figure 5c ) is placed in a magnetron sputtering reaction chamber, and the gate metal is sputtered after the vacuum degree of the reaction chamber reaches 2E10-6Torr. Then the sputtered substrate is soaked in acetone for more than 40 minutes and then ultrasonically treated. The ultrasonically treated substrate is placed in a stripping solution with a temperature of 60°C and heated in a water bath for 5 minutes, and then placed in an acetone solution and an ethanol solution for ultrasonic cleaning for 3 minutes in turn. Finally, the substrate is rinsed and cleaned with ultrapure water and dried with nitrogen gas, so that the gate electrode 8 and the AlGaN barrier layer 114 maintain Schottky contact to form a potential gap as shown in FIG. Figure 5d The structure shown.

[0074] Optionally, the material of the gate metal may be the same as that of the source metal and the drain metal.

[0075] S404, etching the first passivation layer and part of the barrier layer on both sides of the gate groove to form a source groove and a drain groove, and evaporating a source metal and a drain metal in the source groove and the drain groove to form a source electrode and a drain electrode respectively.

[0076] In one example, an inductively coupled plasma device can be used to photolithography the source graphic region and the drain graphic region on the barrier layer 114; then a method similar to that in step S403 can be used to photolithography the source graphic region and the drain graphic region on the first passivation layer 115 by plasma lithography technology to form a source groove and a drain groove.

[0077] For example, the substrate with the gate groove (see Figure 5d ) is placed on a hot plate at 200°C for 5 minutes, and then the photoresist is spun at a speed of 3500 rpm. After the spun is completed, it is baked again on a hot plate at 90°C for 1 minute. The baked substrate is placed in a photolithography machine to expose the photoresist in the electrical isolation area. Finally, the exposed substrate is placed in a developer to remove the photoresist in the electrical isolation area, and then rinsed with ultrapure water and dried with nitrogen to complete the etching of the barrier layer 114.

[0078] In one example, an electron beam evaporation process may be used to evaporate source metal and drain metal in the source groove and the drain groove respectively to form the source electrode 62 and the drain electrode 72 .

[0079] Exemplarily, the substrate that has been subjected to plasma stripping and has been etched with source and drain grooves can be placed in an electron beam evaporation station. After the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2E10-6Torr, the ohmic metal is evaporated on the surface of the barrier layer coated with photoresist. The substrate that has completed the source metal evaporation and the drain metal evaporation is soaked in acetone for more than 40 minutes and subjected to ultrasonic treatment; then it is placed in a stripping solution at a temperature of 60°C and heated in a water bath for 5 minutes. After heating, the substrate is placed in an acetone solution and an ethanol solution in turn for ultrasonic cleaning for 3 minutes. Finally, the cleaned substrate is placed in a rapid annealing furnace, and nitrogen is passed into the annealing furnace for 10 minutes. The annealing furnace temperature is set to 550°C in a nitrogen atmosphere, and high-temperature annealing is performed for 30 seconds to form an ohmic contact between the ohmic metal on the source groove and the drain groove and the barrier layer, thereby forming a source electrode 62 and a drain electrode 72, and obtaining the following. Figure 5e The structure shown.

[0080] Optionally, both the source metal and the drain metal may be a metal stack structure consisting of Ti and Al in sequence from bottom to top.

[0081] S405 , depositing a second passivation layer and a base dielectric layer in sequence on the upper surfaces of the first passivation layer, the gate electrode, the source electrode, and the drain electrode.

[0082] In one example, the second passivation layer 116 may be deposited on the upper surface of the first passivation layer 115 using a plasma enhanced chemical vapor deposition process.

[0083] For example, a method similar to that in step S402 may be used to deposit the second passivation layer 116 with a thickness of 140 nm.

[0084] Alternatively, see Figure 5f A field plate (FP) may also be fabricated on the second passivation layer 116 by a magnetron sputtering physical vapor deposition process before depositing the base dielectric layer 12 to expand the size of the depletion region.

[0085] In one example, the base dielectric layer 12 may be deposited on the upper surface of the second passivation layer 116 by using a low pressure chemical vapor deposition process.

[0086] For example, a low-pressure chemical vapor deposition process can be used, using SiH4 and oxygen as silicon source and oxygen source, and a SiO2 passivation layer (i.e., base dielectric layer 12) with a thickness of 400 nm can be deposited under the conditions of a flow ratio of SiH4:O2=1:1, a reaction chamber pressure of 600 mTorr, and a deposition temperature of 400°C, to obtain the following: Figure 5f The structure shown.

[0087] S406, photolithography a second through hole and a third through hole on the first passivation layer and the base dielectric layer.

[0088] Exemplarily, a second through hole can be photolithographically formed above the source electrode, penetrating the second passivation layer and the base dielectric layer and connecting to the source electrode; a third through hole can be photolithographically formed above the drain electrode, penetrating the second passivation layer and the base dielectric layer and connecting to the drain electrode, to obtain Figure 5g The structure shown.

[0089] In one example, the base dielectric layer may be polished first, and the positions of the second through hole and the third through hole may be located on the base dielectric layer by a photolithography process, and then the steep second through hole and the third through hole may be manufactured by a fluorine dry etching process.

[0090] For example, the base dielectric layer may be polished using a mechanical chemical polishing process.

[0091] Optionally, the process conditions of mechanical chemical polishing can be: using SiO2 abrasive particles with a concentration of 5%, using KOH to control the pH value of the polishing liquid to 10, and the particle size range of SiO2 abrasive particles is 1-100nm. Before and after polishing, the silicon wafer is ultrasonically cleaned in anhydrous ethanol and deionized water for 10 minutes each.

[0092] Exemplarily, the process conditions of fluorine dry etching can be: the reaction gases are CF4 and O2, the CF4 flow rate is 25 sccm, the O2 flow rate is 5 sccm, the reaction chamber pressure is 5 mTorr, the RF power of the upper electrode and the lower electrode is 100 W and 10 W respectively, and the etching depth is 400 nm.

[0093] Example 4

[0094] Figure 6 The flowchart of the method for preparing a three-dimensional GaN integrated circuit chip provided by the present invention is shown. As an example but not a limitation, the method for preparing a three-dimensional GaN integrated circuit chip may include steps S601-S604, each of which is described below.

[0095] S601, preparing a GaN substrate.

[0096] Illustratively, the method in Example 3 may be used to prepare a GaN substrate.

[0097] S602, preparing an n-th level integrated circuit on the upper surface of the n-1-th level isolation dielectric layer.

[0098] Exemplarily, n is a positive integer, and the 0th-level isolation dielectric layer is a base dielectric layer.

[0099] In a possible implementation, a layer of through-hole metal can be first deposited on the upper surface of the n-1th level isolation dielectric layer; then the metal layer is polished, the shape of the integrated circuit is photoetched on the polished metal layer, and the wire is deposited; the nth level integrated circuit is obtained, as shown in FIG. Figure 7a The structure shown.

[0100] In one example, the via metal may be deposited using a magnetron sputtering physical vapor deposition process.

[0101] Exemplarily, the GaN substrate may be placed in a magnetron sputtering reaction chamber, and after the vacuum degree of the reaction chamber reaches 2E10-6 Torr, a through-hole metal is deposited above the first through-hole of the n-1th level.

[0102] Exemplarily, the 0th-level first through hole may be the second through hole and the third through hole.

[0103] Optionally, the through-hole metal may be a stacked structure of TiN and W.

[0104] In one example, a mechanical chemical polishing process may be used to polish the via metal.

[0105] For example, Al2O3 abrasive particles can be used to control the pH value to 4, and 1% hydrogen peroxide can be used as an oxidant to polish and grind the through-hole metal. Before and after polishing, the GaN substrate with the through-hole metal needs to be ultrasonically cleaned in anhydrous ethanol and deionized water for 10 minutes each.

[0106] In one example, a process similar to step S403 in the above embodiment 3 can be used to photolithographically pattern an integrated circuit on a through-hole metal (see Figure 3 ).

[0107] In one example, the conductive lines may be deposited using a magnetron sputtering physical vapor deposition process.

[0108] Exemplarily, the photolithographically processed GaN substrate can be placed in a magnetron sputtering reaction chamber, and after the vacuum degree of the reaction chamber reaches 2E10-6 Torr, the wire metal is deposited on the upper surface of the n-1th isolation dielectric layer d with the integrated circuit image photoresist layer.

[0109] Optionally, the wire metal may be a stacked structure consisting of Ti, TiN, Al, and TiN.

[0110] S603, depositing an n-level wiring dielectric layer on the upper surface of the n-1-level isolation dielectric layer and the n-level integrated circuit.

[0111] In one example, a low pressure chemical vapor deposition process can be used to deposit an n-level wiring dielectric layer on the upper surface of the n-level integrated circuit and the n-1-level isolation dielectric layer so that the n-level integrated circuit is wrapped, and then a mechanical chemical polishing process is used to polish the n-level wiring dielectric layer to obtain a structure as shown in FIG. Figure 7b The structure shown.

[0112] Exemplarily, the method of depositing and polishing the n-th level wiring dielectric layer may be the same as the method of depositing the base dielectric layer in step S405 in embodiment 3 and the method of polishing the base dielectric layer in step S406 in embodiment 4, respectively.

[0113] S604, depositing an n-level isolation dielectric layer on the upper surface of the n-level wiring dielectric layer and photoetching an n-level first through hole on the n-level isolation dielectric layer.

[0114] In one example, a process and conditions similar to the process and conditions for depositing the base dielectric layer and photolithography of the second through hole and the third through hole in step S405 of the above embodiment 3 can be used to deposit an n-level isolation dielectric layer on the upper surface of the n-level wiring dielectric layer and photolithography of the n-level first through hole on the n-level isolation dielectric layer to obtain the following: Figure 7c The structure shown.

[0115] Optionally, when n is less than N, the above steps S602-S604 can be continued to prepare the next level wiring dielectric layer and isolation dielectric layer. When n is equal to N, the preparation can be stopped, and the following is obtained: Figure 1 The three-dimensional structure of the GaN integrated circuit chip is shown.

[0116] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

Claims

1. A three-dimensional GaN integrated circuit chip, characterized in that: include: A GaN substrate, the GaN substrate comprising a GaN substrate and a substrate dielectric layer arranged on the upper surface of the GaN substrate; Multiple levels of wiring dielectric layers and isolation dielectric layers are stacked alternately from bottom to top, wherein the first level of wiring dielectric layer is arranged on the upper surface of the base dielectric layer; At least one n-th level integrated circuit is sandwiched between the n-th level wiring dielectric layer and the n-1-th level isolation dielectric layer, n is a positive integer, and the 0-th level isolation dielectric layer is the base dielectric layer; on the n-th level isolation dielectric layer, at least one n-th level first through hole is arranged that penetrates the n-th level isolation dielectric layer and connects the n+1-th level integrated circuit and the n-th level integrated circuit; the n+1-th level integrated circuit and the n-th level integrated circuit are connected to each other based on the n-th level first through hole through a wire or a metal bonding action.

2. The three-dimensional GaN integrated circuit chip according to claim 1, characterized in that: The base dielectric layer, the wiring dielectric layer, and the isolation dielectric layer are all made of SiO2.

3. The three-dimensional structured GaN integrated circuit chip according to claim 1, characterized in that: The GaN substrate comprises: a substrate, a buffer layer, a channel layer, a barrier layer, a first passivation layer, and a second passivation layer stacked sequentially from bottom to top; A gate groove is provided on the first passivation layer, and a source groove and a drain groove are provided on part of the barrier layer on both sides of the gate groove and the first passivation layer; a source electrode, a gate electrode and a drain electrode are respectively provided in the source groove, the gate groove and the drain groove, and the second passivation layer covers the upper surfaces of the first passivation layer, the source electrode, the gate electrode and the drain electrode; A second through hole and a third through hole penetrating the second passivation layer and the base dielectric layer are provided in the second passivation layer and the base dielectric layer, and the second through hole and the third through hole respectively connect the source electrode and the first-level integrated circuit, and the drain electrode and the first-level integrated circuit.

4. The three-dimensional structured GaN integrated circuit chip according to claim 3, characterized in that: The number N of the wiring dielectric layers and the isolation dielectric layers is a positive integer greater than or equal to 2.

5. The three-dimensional structured GaN integrated circuit chip according to claim 4, characterized in that: The thickness of the base dielectric layer is less than or equal to 0.4 μm, the thickness of the first-level wiring dielectric layer is less than or equal to 1 μm, the thickness of the first-level isolation dielectric layer is less than or equal to 0.5 μm, the thickness of the second-level wiring dielectric layer is less than or equal to 1 μm, and the thickness of the second-level isolation dielectric layer is less than or equal to 0.5 μm.

6. The three-dimensional GaN integrated circuit chip according to claim 3, characterized in that: The thickness of the first passivation layer is less than or equal to 120 nm, and the thickness of the second passivation layer is less than or equal to 140 nm.

7. The three-dimensional GaN integrated circuit chip according to claim 3, characterized in that: The first passivation layer and the second passivation layer are made of SiN.

8. The three-dimensional GaN integrated circuit chip according to claim 3, characterized in that: The gate metal used to prepare the gate electrode, the source metal used to prepare the source electrode, and the drain metal used to prepare the drain electrode are metal stack structures composed of Ti and Al in sequence from bottom to top.

9. A method for preparing a three-dimensional GaN integrated circuit chip, characterized in that: include: Prepare a GaN substrate, wherein the GaN substrate comprises a GaN substrate and an insulating substrate dielectric layer disposed on the upper surface of the GaN substrate; preparing an n-th level integrated circuit on the upper surface of the isolation dielectric layer of the n-1th level, where n is a positive integer, and the isolation dielectric layer of the 0th level is the base dielectric layer; Depositing an n-th level wiring dielectric layer on the upper surface of the n-1-th level isolation dielectric layer and the n-th level integrated circuit; An n-th level isolation dielectric layer is deposited on the upper surface of the n-th level wiring dielectric layer and an n-th level first through hole is photoetched on the n-th level isolation dielectric layer, wherein the n-th level first through hole penetrates the n-th level isolation dielectric layer and connects the n+1-th level integrated circuit and the n-th level integrated circuit; the n+1-th level integrated circuit and the n-th level integrated circuit are connected based on the n-th level first through hole through a wire or metal bonding.

10. The preparation method according to claim 9, characterized in that: The GaN substrate comprises a substrate, a buffer layer, a channel layer, a barrier layer, a first passivation layer and a second passivation layer stacked sequentially from bottom to top, and the preparation of the GaN substrate comprises: preparing a substrate, and sequentially growing a buffer layer, a channel layer and a barrier layer on the substrate; Depositing the first passivation layer on the upper surface of the barrier layer; Etching a gate groove on the first passivation layer, and sputtering a gate metal in the gate groove to form a gate electrode; Etching the first passivation layer and part of the barrier layer on both sides of the gate groove to form a source groove and a drain groove, and evaporating a source metal and a drain metal in the source groove and the drain groove to form a source electrode and a drain electrode respectively; Depositing the second passivation layer and the base dielectric layer in sequence on the upper surfaces of the first passivation layer and the gate electrode, the source electrode, and the drain electrode; On the first passivation layer and the base dielectric layer, a second through hole penetrating the second passivation layer and the base dielectric layer and connecting the source electrode and the first-level integrated circuit, and a third through hole penetrating the second passivation layer and the base dielectric layer and connecting the drain electrode and the first-level integrated circuit are respectively photolithographically formed.

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