Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the reliability of the semiconductor device while improving the threshold voltage of the semiconductor device, the semiconductor device comprises a substrate, a barrier layer, a first cap layer, a second cap layer, a source electrode and a drain electrode, the barrier layer is arranged on one side of the substrate, the first cap layer is arranged on the side, away from the substrate, of the barrier layer, the second cap layer is arranged on the side, away from the substrate, of the first cap layer, the source electrode and the drain electrode are located on the two opposite sides of the first cap layer in the first direction and arranged on the side, away from the substrate, of the barrier layer, and the first direction is parallel to the substrate. The size of the second cap layer in the first direction is smaller than that of the first cap layer in the first direction, the first cap layer and the second cap layer both comprise P-type doped semiconductor materials, and the doping concentration of the first cap layer is smaller than that of the second cap layer. The semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride semiconductor materials are called third-generation semiconductor materials. Compared with the first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance. They can be used as core components in various power conversion systems and have broad prospects in consumer electronics, 5G RF, servers, and telecommunications applications. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to increase the threshold voltage of the semiconductor device while improving the reliability of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a barrier layer, a first cap layer, a second cap layer, a source and a drain. The barrier layer is arranged on one side of the substrate. The first cap layer is arranged on the side of the barrier layer away from the substrate. The second cap layer is arranged on the side of the first cap layer away from the substrate. The source and the drain are located on opposite sides of the first cap layer along a first direction, and are both arranged on the side of the barrier layer away from the substrate, and the first direction is parallel to the substrate. Wherein, the size of the second cap layer along the first direction is smaller than the size of the first cap layer along the first direction. The first cap layer and the second cap layer both include P-type doped semiconductor material, and the doping concentration of the first cap layer is less than the doping concentration of the second cap layer.

[0006] The semiconductor device provided by the above-mentioned embodiments of the present disclosure comprises a first cap layer and a second cap layer, wherein the second cap layer is arranged on a side of the first cap layer in the semiconductor device away from the substrate, and both the first cap layer and the second cap layer comprise P-type doped semiconductor materials, and the doping concentration of the first cap layer is less than the doping concentration of the second cap layer. On the one hand, since the second cap layer is arranged on a side of the first cap layer in the semiconductor device away from the substrate, that is, the first cap layer is located between the second cap layer and the barrier layer, in the process of forming the second cap layer in the semiconductor device, when the P-type impurities in the second cap layer diffuse, the P-type The impurities will first diffuse into the first cap layer, which can avoid or alleviate the diffusion of P-type impurities in the second cap layer into the barrier layer. This can reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer and interfering with the polarization effect of the barrier layer, which is beneficial to improving the polarization effect of the barrier layer. It can also reduce the probability of changes in the characteristics of the connection interface between the first cap layer and the barrier layer (for example, the increase in the trap state density at the connection interface between the first cap layer and the barrier layer, etc.) and affecting the control ability of the gate layer in the semiconductor device, which is beneficial to reducing the probability of problems such as dynamic on-resistance degradation in semiconductor devices, and thus is beneficial to improving the reliability of semiconductor devices.

[0007] On the other hand, since the doping concentration of the first cap layer (i.e., the concentration of P-type impurities in the first cap layer) is less than the doping concentration of the second cap layer (i.e., the concentration of P-type impurities in the second cap layer), that is, the doping concentration of the first cap layer is relatively small, in the process of forming the first cap layer in the semiconductor device, the P-type impurities in the first cap layer may not diffuse or may diffuse in a small amount into the barrier layer, which can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer and interfering with the polarization effect of the barrier layer, which is beneficial to further improve the polarization effect of the barrier layer, and can also further reduce the probability of changes in the characteristics of the connection interface between the first cap layer and the barrier layer (for example, the density of trap states at the connection interface between the first cap layer and the barrier layer increases) and affecting the control ability of the gate layer in the semiconductor device, which is beneficial to further reduce the probability of problems such as dynamic on-resistance degradation in the semiconductor device, and thus is beneficial to further improve the reliability of the semiconductor device.

[0008] On the other hand, since the doping concentration of the first cap layer (i.e., the concentration of P-type impurities in the first cap layer) is less than the doping concentration of the second cap layer (i.e., the concentration of P-type impurities in the second cap layer), that is, the doping concentration of the second cap layer is relatively large, there is an energy band difference (e.g., conduction band difference) between the second cap layer and the barrier layer, and the energy band difference (e.g., conduction band difference) between the second cap layer and the barrier layer can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer and the channel layer, which is conducive to depleting the two-dimensional electron gas (2DEG) below the second cap layer, so that the semiconductor device realizes an enhanced working mode. And due to the depletion effect of the second cap layer in the semiconductor device on the two-dimensional electron gas (2DEG) below the second cap layer, the semiconductor device needs to overcome a higher potential barrier when it is turned on, which is conducive to increasing the threshold voltage of the semiconductor device.

[0009] In some embodiments, the semiconductor device includes a plurality of the second capping layers, and the plurality of the second capping layers are spaced apart along the first direction.

[0010] In some embodiments, the semiconductor device further comprises a gate layer, which is disposed on a side of the first capping layer away from the substrate, and covers two side surfaces of the second capping layer opposite to each other along the first direction and a surface of the second capping layer away from the substrate.

[0011] The semiconductor device provided by the above-mentioned embodiment of the present disclosure, in the case where the semiconductor device includes a first cap layer and a second cap layer, by making the gate layer in the semiconductor device be arranged on a side of the first cap layer away from the substrate, and the gate layer covers two side surfaces of the second cap layer opposite to each other along a first direction (i.e., the arrangement direction of the source and the drain in the semiconductor device), and a surface of a side of the second cap layer away from the substrate, i.e., the second cap layer is not arranged between a partial area in the gate layer and the first cap layer, when the semiconductor device is turned on (i.e., the gate layer in the semiconductor device is under a forward voltage bias), part of the two-dimensional electron gas (Two-dimensional electron gas) in the semiconductor device is The two-dimensional electron gas (2DEG) can be collected in the gate layer and in the partial area between the first capping layer where the second capping layer is not provided through the first capping layer, without passing through the second capping layer. On the one hand, since the doping concentration of the first capping layer (i.e., the concentration of P-type impurities in the first capping layer) is less than the doping concentration of the second capping layer (i.e., the concentration of P-type impurities in the second capping layer), that is, the doping concentration of the first capping layer is relatively small, there are fewer electron traps in the first capping layer, which is beneficial to reducing the probability of electrons in the two-dimensional electron gas (2DEG) being captured by electron traps during transmission, and further beneficial to maintaining the concentration of the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer and the channel layer, so that the concentration of the two-dimensional electron gas (2DEG) is more stable, thereby avoiding or reducing the probability of the threshold voltage positive drift phenomenon caused by the electrons being captured by electron traps during transmission, which is beneficial to improving the stability of the threshold voltage of the semiconductor device.

[0012] On the other hand, since the doping concentration of the first capping layer (i.e., the concentration of P-type impurities in the first capping layer) is relatively small, there is an approximately uniformly distributed electric field in the first capping layer, which is beneficial for accelerating electrons in the first capping layer and smoothly transitioning to the interface between the first capping layer and the gate layer, which can reduce the scattering and energy loss of electrons during the transmission process, and thus is beneficial for improving the performance stability of semiconductor devices.

[0013] On the other hand, since the doping concentration of the first capping layer (i.e., the concentration of P-type impurities in the first capping layer) is less than the doping concentration of the second capping layer (i.e., the concentration of P-type impurities in the second capping layer), that is, the doping concentration of the second capping layer is relatively large, there is an energy band difference (e.g., conduction band difference) between the second capping layer and the barrier layer. The energy band difference (e.g., conduction band difference) between the second capping layer and the barrier layer can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer and the channel layer, which is beneficial to depleting the two-dimensional electron gas (2DEG) under the second capping layer, thereby enabling the semiconductor device to achieve an enhanced operating mode.

[0014] Furthermore, due to the depletion effect of the second cap layer in the semiconductor device on the two-dimensional electron gas (2DEG) below the second cap layer, the semiconductor device needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device.

[0015] In summary, in the case where the semiconductor device includes a first cap layer and a second cap layer, by providing the gate layer in the semiconductor device on a side of the first cap layer away from the substrate, and the gate layer covers two opposite side surfaces of the second cap layer along a first direction (i.e., the arrangement direction of the source and the drain in the semiconductor device), as well as a surface of the second cap layer away from the substrate, the threshold voltage of the semiconductor device can be increased while improving the stability of the threshold voltage of the semiconductor device and the performance stability of the semiconductor device.

[0016] In some embodiments, the gate layer contacts a portion of a surface of the first capping layer.

[0017] In some embodiments, a dimension of the gate layer along the first direction is smaller than or equal to a dimension of the first capping layer along the first direction.

[0018] In some embodiments, a dimension of the second capping layer along a second direction is the same as a dimension of the first capping layer along the second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0019] In some embodiments, the doping concentration of the first capping layer is less than or equal to 5×10 17 cm -3 .

[0020] In some embodiments, the doping concentration of the second capping layer is greater than or equal to 5×10 18 cm -3, and less than or equal to 10×10 19 cm -3 .

[0021] In some embodiments, the semiconductor device further comprises a protective layer, the protective layer is disposed between the first capping layer and the second capping layer, and the protective layer and the first capping layer overlap in a thickness direction of the substrate.

[0022] In some embodiments, the material of the protection layer is different from the material of the second capping layer.

[0023] In some embodiments, the material of the protection layer includes at least one of aluminum gallium nitride and aluminum nitride.

[0024] In some embodiments, the material of the protection layer includes a P-type doped semiconductor material, and the doping concentration of the protection layer is less than the doping concentration of the second capping layer.

[0025] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises the following steps:

[0026] A barrier layer is formed on one side of the substrate.

[0027] A first capping layer is formed on a side of the barrier layer away from the substrate.

[0028] A second capping layer is formed on a side of the first capping layer away from the substrate.

[0029] A source electrode and a drain electrode are formed. The source electrode and the drain electrode are located on opposite sides of the first cap layer along a first direction and are both arranged on a side of the barrier layer away from the substrate, and the first direction is parallel to the substrate.

[0030] The size of the second capping layer along the first direction is smaller than the size of the first capping layer along the first direction. The first capping layer and the second capping layer both include P-type doped semiconductor materials, and the doping concentration of the first capping layer is smaller than the doping concentration of the second capping layer.

[0031] In some embodiments, the forming of the first capping layer and the forming of the second capping layer include the following steps:

[0032] A first initial capping layer and a second initial capping layer are sequentially formed on a side of the barrier layer away from the substrate.

[0033] The first initial capping layer and the second initial capping layer are removed to form a source region and a drain region to be formed, and a first capping layer and a third capping layer are formed. The first capping layer and the third capping layer overlap in the thickness direction of the substrate.

[0034] A portion of the third capping layer is removed to form a second capping layer.

[0035] In another aspect, a chip is provided, wherein the chip includes the semiconductor device described in any one of the above embodiments.

[0036] In another aspect, an electronic device is provided, wherein the electronic device comprises a circuit board and the chip as described above, wherein the chip is electrically connected to the circuit board.

[0037] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0039] Figure 1 FIG. 1 is a schematic diagram of a structure of an electronic device according to some embodiments Figure 1 ;

[0040] Figure 2 FIG. 1 is a schematic diagram of a structure of an electronic device according to some embodiments Figure 2 ;

[0041] Figure 3 A schematic cross-sectional view of a chip according to some embodiments Figure 1 ;

[0042] Figure 4 A schematic cross-sectional view of a chip according to some embodiments Figure 2 ;

[0043] Figure 5 A cross-sectional view of a semiconductor device according to some embodiments Figure 1 ;

[0044] Figure 6 A cross-sectional view of a semiconductor device according to some embodiments Figure 2 ;

[0045] Figure 7 A cross-sectional view of a semiconductor device according to some embodiments Figure 3 ;

[0046] Figure 8 A cross-sectional view of a semiconductor device according to some embodiments Figure 4 ;

[0047] Fig. 9 FIG. 1 is a top view of a first capping layer and a second capping layer in a semiconductor device according to some embodiments. Figure 1 ;

[0048] Fig.10 FIG. 1 is a top view of a first capping layer and a second capping layer in a semiconductor device according to some embodiments. Figure 2 ;

[0049] Fig.11 A cross-sectional view of a semiconductor device according to some embodiments Figure 5 ;

[0050] Fig.12 A cross-sectional view of a semiconductor device according to some embodiments Figure 6 ;

[0051] Fig.13 A cross-sectional view of a semiconductor device according to some embodiments Figure 7 ;

[0052] Fig.14 A cross-sectional view of a semiconductor device according to some embodiments Figure 8 ;

[0053] Fig.15 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0054] Fig.16 for Fig.15 A schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0055] Fig.17 for Fig.15 A schematic structural diagram of a semiconductor device corresponding to step S2 and step S3 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0056] Fig.18 for Fig.15 A schematic structural diagram of a semiconductor device corresponding to step S4 in the flowchart of the method for preparing a semiconductor device in FIG.

[0057] Fig.19 for Fig.15 A schematic structural diagram of the semiconductor device corresponding to step S5 and step S6 in the flowchart of the method for preparing the semiconductor device.

[0058] Reference numerals:

[0059] 1000-electronic device; 100-chip; 200-circuit board; 10-semiconductor device; 1-substrate; 2-buffer layer; 31-first insertion layer; 32-second insertion layer; 4-channel layer; 5-barrier layer; 61-first capping layer; 62-second capping layer; 63-third capping layer; 64-fourth capping layer; 61a-first initial capping layer; 62a-second initial capping layer; 7-passivation layer; 8-protective layer; G-gate layer; S-source; D-drain; Sa-source region to be formed; Da-drain region to be formed. DETAILED DESCRIPTION

[0060] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0061] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0062] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0063] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0064] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0065] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0066] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0067] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0068] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0069] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0070] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0071] The words "exemplary" or "for example" are used herein to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific way.

[0072] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0073] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0074] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include communication equipment (e.g., satellite communication equipment, wireless television receiver, etc.), radar equipment (e.g., millimeter wave radar, weather radar, etc.), radio navigation equipment (e.g., GPS receiver, etc.), etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1000. Figure 1 In the figure, the electronic device 1000 is taken as a communication device as an example for illustration.

[0075] In some embodiments, Figure 2 As shown, Figure 2 1 is a schematic diagram of the structure of an electronic device 1000 according to some embodiments. The electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0076] Exemplarily, the circuit board 200 may include a printed circuit board (PCB) or the like.

[0077] For example, the circuit board 200 may include a plurality of conductive layers. The plurality of conductive layers within the circuit board 200 may be separated from each other by a dielectric layer.

[0078] The chip 100 is described in detail below.

[0079] In some embodiments, Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 1 and 2 are schematic cross-sectional views of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0080] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0081] The semiconductor device 10 described above will be described in detail below.

[0082] In some embodiments, please refer to Figure 3 and Figure 4 , a semiconductor device 10 may include a substrate 1 .

[0083] By way of example, the material of the substrate 1 in the semiconductor device 10 may include one of silicon (Si), silicon carbide (SiC), sapphire, and the like.

[0084] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a buffer layer 2. The buffer layer 2 may be disposed on one side of the substrate 1.

[0085] By setting a buffer layer 2 in the semiconductor device 10, and the buffer layer 2 is set on one side of the substrate 1, other film layer structures set on the side of the buffer layer 2 in the semiconductor device 10 away from the substrate 1 can be bonded, and the substrate 1 can be protected to prevent the substrate 1 from being invaded by some metal ions.

[0086] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) At least one of N, (0≤x, y≤1).

[0087] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) N, one of (0≤x,y≤1).

[0088] For another example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) Multiple (greater than or equal to two) of N, (0≤x, y≤1).

[0089] For example, the buffer layer 2 in the semiconductor device 10 can be formed by a process such as Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE) or Physical Vapor Deposition (PVD).

[0090] Exemplarily, the buffer layer 2 in the semiconductor device 10 may be a single-layer structure, that is, along the third direction (ie, the thickness direction of the substrate 1 ) Z, the buffer layer 2 includes a film layer structure.

[0091] Alternatively, the buffer layer 2 in the semiconductor device 10 may be a multi-layer (greater than or equal to two layers) structure. That is, along the third direction (ie, the thickness direction of the substrate 1) Z, the buffer layer 2 includes a multi-layer (greater than or equal to two layers) film structure.

[0092] For example, please refer to Figure 4 The semiconductor device 10 may further include a first insertion layer 31. The first insertion layer 31 in the semiconductor device 10 may be disposed between the substrate 1 and a buffer layer 2 in the semiconductor device 10.

[0093] The material of the first insertion layer 31 in the semiconductor device 10 may include aluminum nitride (AIN) or the like.

[0094] By setting the first insertion layer 31 between the substrate 1 and the buffer layer 2 in the semiconductor device 10, on the one hand, when the lattice constant between the substrate 1 and the buffer layer 2 in the semiconductor device 10 does not match or the thermal expansion coefficient is different, the first insertion layer 31 can alleviate the stress caused by the lattice constant mismatch or the thermal expansion coefficient difference between the substrate 1 and the buffer layer 2 in the semiconductor device 10, avoid the stress caused by the lattice constant mismatch or the thermal expansion coefficient difference between the substrate 1 and the buffer layer 2 in the semiconductor device 10 from affecting the performance of the semiconductor device 10, which is beneficial to improving the performance of the semiconductor device 10.

[0095] On the other hand, the first insertion layer 31 in the semiconductor device 10 can improve the interface characteristics between the substrate 1 and the buffer layer 2 in the semiconductor device 10, reduce the interface defects between the substrate 1 and the buffer layer 2 in the semiconductor device 10, and help improve the stability and reliability of the semiconductor device 10.

[0096] On the other hand, the material of the substrate 1 in the semiconductor device 10 includes silicon (Si) and silicon carbide (SiC), and the material of the buffer layer 2 in the semiconductor device 10 includes a plurality of nitride Al x In y Ga (1-x-y) In the case of at least one of N, (0≤x, y≤1), the first insertion layer 31 arranged between the substrate 1 and the buffer layer 2 in the semiconductor device 10 can prevent the silicon (Si) element in the substrate 1 and the gallium (Ga) element in the buffer layer 2 from undergoing a back-etching or regrowth etch reaction at high temperature, thereby avoiding damage to the substrate 1 and the buffer layer 2 in the semiconductor device 10, which is beneficial to improving the yield of the semiconductor device 10 and further improving the stability and reliability of the semiconductor device 10.

[0097] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a channel layer 4. The channel layer 4 in the semiconductor device 10 may be disposed on one side of the substrate 1.

[0098] Exemplarily, please continue to refer to Figure 3 and Figure 4 , in the case where the semiconductor device 10 includes a buffer layer 2, the channel layer 4 in the semiconductor device 10 may be disposed on a side of the buffer layer 2 away from the substrate 1.

[0099] Exemplarily, the material of the channel layer 4 in the semiconductor device 10 may include gallium nitride (GaN).

[0100] Exemplarily, the channel layer 4 in the semiconductor device 10 may be formed by processes such as Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Physical Vapor Deposition (PVD).

[0101] In some embodiments, please continue to refer to Figure 3 and Figure 4 , the semiconductor device 10 may further include a barrier layer 5. The barrier layer 5 is disposed on one side of the substrate 1 in the semiconductor device 10.

[0102] Exemplarily, the material of the barrier layer 5 in the semiconductor device 10 may include nitrides Al x In y Ga (1-x-y) N, at least one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0103] For example, the material of the barrier layer 5 in the semiconductor device 10 may include a nitride Al x In y Ga (1-x-y) N, one of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0104] Again for example, the material of the barrier layer 5 in the semiconductor device 10 may include nitrides Al x In y Ga (1-x-y) N, multiple (greater than or equal to two) of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0105] For example, the barrier layer 5 in the semiconductor device 10 can be formed by a process such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or physical vapor deposition (PVD).

[0106] For example, please refer to Figure 3 and Figure 4 , the barrier layer 5 in the semiconductor device 10 can be arranged on a side of the channel layer 4 away from the substrate 1 . That is, the channel layer 4 is arranged between the barrier layer 5 and the substrate 1 .

[0107] When the barrier layer 5 in the semiconductor device 10 is arranged on the side of the channel layer 4 away from the substrate 1, and the band gap width (Band gap) of the material of the barrier layer 5 (for example, aluminum gallium nitride (AlGaN)) is greater than the band gap width (Band gap) of the material of the channel layer 4 (for example, gallium nitride (GaN)), due to the different electron affinities (Electron Affinity) and work functions (Work Function) of the material of the barrier layer 5 (for example, aluminum gallium nitride (AlGaN)) and the material of the channel layer 4 (for example, gallium nitride (GaN)), a heterojunction structure will be formed at the connection interface between the barrier layer 5 and the channel layer 4. This heterojunction structure will cause the band structure of the channel layer 4 to bend, thereby forming a potential well in the channel layer 4. In order to balance the charge distribution at the connection interface between the barrier layer 5 and the channel layer 4, the electrons in the barrier layer 5 will transfer to the potential well in the channel layer 4. The potential well in the channel layer 4 can restrict the electrons so that the electrons can only move freely in the direction parallel to the connection interface between the barrier layer 5 and the channel layer 4, thereby inducing the formation of a two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0108] It should be noted that the above-mentioned band gap refers to the fact that the energy of electrons in solids cannot take continuous values, but forms some discontinuous energy bands, among which the energy difference between the conduction band and the valence band is the band gap. Specifically, for bound electrons to become free electrons or holes, they must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0109] For example, please refer to Figure 3 and Figure 4In the case where a two-dimensional electron gas (2DEG) is formed in the semiconductor device 10 , the semiconductor device 10 may be used to form a high electron mobility transistor (HEMT).

[0110] For example, please refer to Figure 4 In the case where the barrier layer 5 in the semiconductor device 10 is disposed on a side of the channel layer 4 away from the substrate 1, the semiconductor device 10 may further include a second insertion layer 32. The second insertion layer 32 in the semiconductor device 10 may be disposed between the channel layer 4 and the barrier layer 5 in the semiconductor device 10.

[0111] The material of the second insertion layer 32 in the semiconductor device 10 may include aluminum nitride (AIN) or the like.

[0112] By setting a second insertion layer 32 between the channel layer 4 and the barrier layer 5 in the semiconductor device 10, on the one hand, the second insertion layer 32 in the semiconductor device 10 can enhance the polarization effect between the channel layer 4 and the barrier layer 5, which is beneficial to increase the concentration of two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4.

[0113] On the other hand, the second insertion layer 32 in the semiconductor device 10 can enhance the confinement of the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, so that the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4 is further confined within a certain dimension (for example, a two-dimensional plane), which is beneficial to improving the electron mobility in the semiconductor device 10, and further beneficial to improving the performance of the semiconductor device 10.

[0114] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a gate layer G. The gate layer G may be disposed on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1 .

[0115] The gate layer G in the semiconductor device 10 is a key electrode for controlling the conductivity of the semiconductor device 10 . The gate layer G does not directly participate in the conduction of current, but controls the carrier concentration in the channel layer 4 in the semiconductor device 10 through the electric field effect, thereby controlling the current in the semiconductor device 10 .

[0116] By way of example, the material of the gate layer G in the semiconductor device 10 may include at least one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0117] For example, the material of the gate layer G in the semiconductor device 10 may include one of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0118] For another example, the material of the gate layer G in the semiconductor device 10 may include multiple (greater than or equal to two) conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0119] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a source S and a drain D. The source S and the drain D are located on opposite sides of the gate layer G in the semiconductor device 10 along the first direction X, and are both arranged on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1. The first direction X is parallel to the substrate 1 in the semiconductor device 10.

[0120] For example, please refer to Figure 3 and Figure 4 In the case where a two-dimensional electron gas (2DEG) is formed in the semiconductor device 10, the source S and the drain D in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas (2DEG), which can reduce the contact resistance between the source S in the semiconductor device 10 and the two-dimensional electron gas (2DEG), and the contact resistance between the drain D in the semiconductor device 10 and the two-dimensional electron gas (2DEG), and can form a low-impedance current channel between the source S, the drain D and the two-dimensional electron gas (2DEG) in the semiconductor device 10, so that the current can flow smoothly, which is beneficial to improving the performance of the semiconductor device 10.

[0121] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a passivation layer 7 . The passivation layer 7 may cover the gate layer G, the source electrode S, and the drain electrode D in the semiconductor device 10 .

[0122] By setting a passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers the gate layer G, the source S and the drain D in the semiconductor device 10, on the one hand, the passivation layer 7 can block harmful substances in the external environment (for example, oxygen, water, etc.), and avoid direct contact between harmful substances in the external environment (for example, oxygen, water, etc.) and the source S, drain D, and gate layer G in the semiconductor device 10, thereby preventing the source S, drain D, and gate layer G in the semiconductor device 10 from being damaged, which is beneficial to improving the stability of the semiconductor device 10 and extending the service life of the semiconductor device 10.

[0123] On the other hand, the passivation layer 7 has a certain mechanical strength, which can protect the source S, drain D and gate layer G in the semiconductor device 10 to a certain extent, and prevent the source S, drain D and gate layer G in the semiconductor device 10 from being mechanically damaged, which is beneficial to further improve the stability of the semiconductor device 10 and further extend the service life of the semiconductor device 10.

[0124] Exemplarily, the material of the passivation layer 7 in the semiconductor device 10 may include at least one of silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), and the like.

[0125] For example, the material of the passivation layer 7 in the semiconductor device 10 may include one of silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), and the like.

[0126] For another example, the material of the passivation layer 7 in the semiconductor device 10 may include multiple (greater than or equal to two) of silicon nitride (Si3N4), silicon oxide (SiO2), aluminum nitride (AlN), and aluminum oxide (Al2O3).

[0127] Exemplarily, the passivation layer 7 in the semiconductor device 10 may be a single-layer structure, that is, along the third direction (ie, the thickness direction of the substrate 1 ) Z, the passivation layer 7 includes a film layer structure.

[0128] Alternatively, the passivation layer 7 in the semiconductor device 10 may be a multi-layer (greater than or equal to two layers) structure. That is, along the third direction Z (ie, the thickness direction of the substrate 1 ), the passivation layer 7 includes a multi-layer (greater than or equal to two layers) film structure.

[0129] For example, the passivation layer 7 in the semiconductor device 10 may be a two-layer structure. Along the third direction (ie, the thickness direction of the substrate 1 ) Z, the passivation layer 7 may include a silicon nitride (Si 3 N 4 ) layer and an aluminum nitride (AlN) layer.

[0130] For example, the passivation layer 7 in the semiconductor device 10 may be formed by at least one of a chemical vapor deposition process (CVD) and a physical vapor deposition process (PVD).

[0131] For example, the passivation layer 7 in the semiconductor device 10 may be formed by a process selected from the group consisting of a chemical vapor deposition process (CVD) and a physical vapor deposition process (PVD).

[0132] For another example, the passivation layer 7 in the semiconductor device 10 may be formed by multiple (greater than or equal to two) processes including a chemical vapor deposition process (Chemical Vapor Deposition, CVD) and a physical vapor deposition process (Physical Vapor Deposition, PVD).

[0133] In some embodiments, please refer to Figure 3 and Figure 4 The semiconductor device 10 may further include a fourth capping layer 64. The fourth capping layer 64 may be disposed on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1. The fourth capping layer 64 includes a P-type doped semiconductor material, and the doping concentration of the fourth capping layer 64 (i.e., the concentration of the P-type impurities in the fourth capping layer 64) is greater than or equal to 5×10 18 cm -3 , and less than or equal to 1×10 20 cm -3 .

[0134] The semiconductor device 10 includes a fourth cap layer 64, which is disposed on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1, and the fourth cap layer 64 includes a P-type doped semiconductor material, and the doping concentration of the fourth cap layer 64 (i.e., the concentration of the P-type impurities in the fourth cap layer 64) is greater than or equal to 5×10 18 cm -3 , and less than or equal to 1×10 20 cm -3On the one hand, an energy band difference (for example, a conduction band difference) can be created between the fourth cap layer 64 and the barrier layer 5, and the energy band difference (for example, a conduction band difference) between the fourth cap layer 64 and the barrier layer 5 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is beneficial to depleting the two-dimensional electron gas (2DEG) under the fourth cap layer 64, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0135] On the other hand, due to the depletion effect of the fourth cap layer 64 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) located below the fourth cap layer 64, the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to improving the threshold voltage of the semiconductor device 10.

[0136] For example, the material of the fourth capping layer 64 in the semiconductor device 10 may include p-type gallium nitride (p-GaN), which may be formed by doping gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

[0137] Please continue reading Figure 3 and Figure 4 During the process of forming the fourth capping layer 64 in the semiconductor device 10 , P-type impurities (eg, magnesium (Mg)) are generally doped into the semiconductor material (eg, gallium nitride (GaN)) as impurities to provide hole carriers, thereby adjusting the conductivity of the fourth capping layer 64 .

[0138] Ideally, the P-type impurities (e.g., magnesium (Mg)) in the fourth capping layer 64 should be evenly distributed in the semiconductor material (e.g., gallium nitride (GaN)) in the fourth capping layer 64. However, in the actual preparation process, due to the influence of various factors (e.g., temperature, electric field, etc.), the P-type impurities (e.g., magnesium (Mg)) in the fourth capping layer 64 may diffuse and may diffuse into the barrier layer 5 in the semiconductor device 10.

[0139] When P-type impurities (for example, magnesium (Mg)) in the fourth cap layer 64 diffuse into the barrier layer 5 in the semiconductor device 10, on the one hand, it is easy to cause changes in the characteristics of the connection interface between the fourth cap layer 64 and the barrier layer 5 (for example, the density of trap states at the connection interface between the fourth cap layer 64 and the barrier layer 5 increases, etc.), and affect the control ability of the gate layer G in the semiconductor device 10, thereby causing problems such as dynamic on-resistance degradation in the semiconductor device 10, thereby reducing the reliability of the semiconductor device 10.

[0140] On the other hand, when the P-type impurities (eg, magnesium (Mg)) in the fourth capping layer 64 diffuse into the barrier layer 5 , additional charges and electric fields will be introduced into the barrier layer 5 , which may easily interfere with the polarization effect of the barrier layer 5 .

[0141] Based on this, in some embodiments, such as Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, Figure 5 , Figure 6 , Figure 7 and Figure 8 All are cross-sectional schematic diagrams of semiconductor devices 10 according to some embodiments. The semiconductor device 10 may further include a first cap layer 61 and a second cap layer 62. The first cap layer 61 is disposed on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1. The second cap layer 62 is disposed on a side of the first cap layer 61 in the semiconductor device 10 away from the substrate 1. In other words, the first cap layer 61 in the semiconductor device 10 is closer to the barrier layer 5 than the second cap layer 62.

[0142] The first capping layer 61 and the second capping layer 62 in the semiconductor device 10 both include P-type doped semiconductor materials, and the doping concentration of the first capping layer 61 is lower than the doping concentration of the second capping layer 62 .

[0143] By making the semiconductor device 10 include a first capping layer 61 and a second capping layer 62, the second capping layer 62 is arranged on a side of the first capping layer 61 in the semiconductor device 10 away from the substrate 1, and the first capping layer 61 and the second capping layer 62 both include P-type doped semiconductor materials, and the doping concentration of the first capping layer 61 is less than the doping concentration of the second capping layer 62. On the one hand, since the second capping layer 62 is arranged on a side of the first capping layer 61 in the semiconductor device 10 away from the substrate 1, that is, the first capping layer 61 is located between the second capping layer 62 and the barrier layer 5, in the process of forming the second capping layer 62 in the semiconductor device 10, when the P-type impurities in the second capping layer 62 diffuse, the P-type The impurities will first diffuse into the first cap layer 61, which can avoid or alleviate the diffusion of P-type impurities in the second cap layer 62 into the barrier layer 5, which can reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 5 and interfering with the polarization effect of the barrier layer 5, which is beneficial to improving the polarization effect of the barrier layer 5. It can also reduce the probability of changes in the characteristics of the connection interface between the first cap layer 61 and the barrier layer 5 (for example, the increase in the trap state density at the connection interface between the first cap layer 61 and the barrier layer 5, etc.), and affect the control ability of the gate layer G in the semiconductor device 10, which is beneficial to reduce the probability of problems such as dynamic on-resistance degradation in the semiconductor device 10, and thus help to improve the reliability of the semiconductor device 10.

[0144] On the other hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of P-type impurities in the first cap layer 61) is less than the doping concentration of the second cap layer 62 (i.e., the concentration of P-type impurities in the second cap layer 62), that is, the doping concentration of the first cap layer 61 is relatively small, in the process of forming the first cap layer 61 in the semiconductor device 10, the P-type impurities in the first cap layer 61 may not diffuse or only diffuse in a small amount into the barrier layer 5, which can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 5 and interfering with the polarization effect of the barrier layer 5, which is beneficial to further improve the polarization effect of the barrier layer 5, and can also further reduce the probability of changes in the characteristics of the connection interface between the first cap layer 61 and the barrier layer 5 (for example, the increase in the trap state density at the connection interface between the first cap layer 61 and the barrier layer 5, etc.), and affecting the control ability of the gate layer G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as dynamic on-resistance degradation in the semiconductor device 10, and thus is beneficial to further improve the reliability of the semiconductor device 10.

[0145] On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is less than the doping concentration of the second capping layer 62 (i.e., the concentration of P-type impurities in the second capping layer 62), that is, the doping concentration of the second capping layer 62 is relatively large, there is an energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5. The energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is beneficial to depleting the two-dimensional electron gas (2DEG) below the second capping layer 62, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0146] Furthermore, due to the depletion effect of the second cap layer 62 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) below the second cap layer 62 , the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10 .

[0147] For example, the material of the first cap layer 61 and the material of the second cap layer 62 in the semiconductor device 10 may both include p-type gallium nitride (p-GaN). P-type gallium nitride (p-GaN) may be formed by doping gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

[0148] For example, when doping elements such as iron (Fe) and magnesium (Mg) into gallium nitride (GaN) materials to form p-type gallium nitride (p-GaN), a gas-phase doping process or an ion implantation process may be used.

[0149] For example, the doping concentration of the first capping layer 61 in the semiconductor device 10 may be less than or equal to 5×10 17 cm -3 That is, the concentration of the P-type impurities (eg, magnesium (Mg)) in the first capping layer 61 may be less than or equal to 5×10 17 cm -3 .

[0150] For example, the doping concentration of the first capping layer 61 in the semiconductor device 10 may be 3×10 17 cm -3 , 4×10 17 cm -3 or 5×10 17cm -3 wait.

[0151] For example, the doping concentration of the second capping layer 62 in the semiconductor device 10 may be greater than or equal to 5×10 18 cm -3 , and less than or equal to 10×10 19 cm -3 That is, the concentration of the P-type impurities (eg, magnesium (Mg)) in the second capping layer 62 may be greater than or equal to 5×10 18 cm -3 , and less than or equal to 10×10 19 cm -3 .

[0152] For example, the doping concentration of the second capping layer 62 in the semiconductor device 10 may be 5×10 18 cm -3 , 6×10 18 cm -3 ,7×10 18 cm -3 , 8×10 18 cm -3 ,9×10 18 cm -3 , 10×10 18 cm -3 , 3×10 19 cm -3 , 5×10 19 cm -3 , 8×10 19 cm -3 or 10×10 19 cm -3 wait.

[0153] For example, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 , the semiconductor device 10 includes at least one second capping layer 62 .

[0154] For example, see Figure 5 and Figure 7 , the semiconductor device 10 may include a second capping layer 62 .

[0155] For another example, please continue to see Figure 6 and Figure 8The semiconductor device 10 may include a plurality of second capping layers 62. When the semiconductor device 10 includes a plurality of second capping layers 62, the plurality of second capping layers 62 may be spaced apart along the first direction (ie, the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0156] It should be noted that Figure 6 and Figure 8 In the illustrated embodiment, only the semiconductor device 10 including two second capping layers 62 is used as an example for illustration. However, when the semiconductor device 10 includes multiple second capping layers 62, the number of second capping layers 62 in the semiconductor device 10 is not limited to this. The number of second capping layers 62 in the semiconductor device 10 can be set based on actual needs. For example, the number of second capping layers 62 in the semiconductor device 10 can be 3, 4, 5, 6, 7 or 8, etc.

[0157] For example, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 , a dimension h2 of the second capping layer 62 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than a dimension h1 of the first capping layer 61 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0158] For example, Fig. 9 and Fig.10 As shown, Fig. 9 and Fig.10 1 and 1 are schematic top views of the first capping layer 61 and the second capping layer 62 in the semiconductor device 10 according to some embodiments. It should be noted that: Fig. 9 and Fig.10 The difference is that Fig. 9 In the illustrated embodiment, the semiconductor device 10 includes a second capping layer 62. Fig.10 In the illustrated embodiment, the semiconductor device 10 includes a plurality of (eg, two) second capping layers 62 .

[0159] The dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y is the same as the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y. The second direction Y is perpendicular to the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and the second direction Y and the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X are both parallel to the substrate 1 in the semiconductor device 10.

[0160] It should be noted that the above “the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y is the same as the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y” means that the difference between the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y and the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y is within a preset threshold range. The threshold range is a relatively small numerical range. For example, the threshold range can be a process accuracy range when forming the first capping layer 61 and the second capping layer 62 with the same dimension along the second direction Y.

[0161] When the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y is the same as the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y, the threshold range of the difference between the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y and the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y can be 0-0.1 μm.

[0162] For example, when the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y is the same as the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y, the difference between the dimension d2 of the second capping layer 62 in the semiconductor device 10 along the second direction Y and the dimension d1 of the first capping layer 61 in the semiconductor device 10 along the second direction Y can be 0, 0.01μm, 0.03μm, 0.05μm, 0.06μm, 0.08μm or 0.1μm, etc.

[0163] For example, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 When the semiconductor device 10 includes a first capping layer 61 and a second capping layer 62 , the source S and the drain D in the semiconductor device 10 can be located on opposite sides of the first capping layer 61 along the first direction X, and both are arranged on the side of the barrier layer 5 away from the substrate 1 .

[0164] In some embodiments, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 In the case where the semiconductor device 10 includes a first capping layer 61 and a second capping layer 62, the gate layer G in the semiconductor device 10 can be arranged on a side of the first capping layer 61 away from the substrate 1, and the gate layer G covers two side surfaces of the second capping layer 62 opposite to each other along the first direction X, as well as a surface of a side of the second capping layer 62 away from the substrate 1.

[0165] In the case where the semiconductor device 10 includes a first cap layer 61 and a second cap layer 62, by setting the gate layer G in the semiconductor device 10 on a side of the first cap layer 61 away from the substrate 1, and the gate layer G covers two side surfaces of the second cap layer 62 opposite to each other along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and a surface of the side of the second cap layer 62 away from the substrate 1, i.e., a partial area in the gate layer G and between the first cap layer 61 where the second cap layer 62 is not set, when the semiconductor device 10 is turned on (i.e., the gate layer G in the semiconductor device 10 is under a forward voltage bias), a portion of the two-dimensional electron gas (2DEG) in the semiconductor device 10 can be collected through the first cap layer 61 by a partial area in the gate layer G and between the first cap layer 61 where the second cap layer 62 is not set, without passing through the second cap layer 62.

[0166] On the one hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is less than the doping concentration of the second capping layer 62 (i.e., the concentration of P-type impurities in the second capping layer 62), that is, the doping concentration of the first capping layer 61 is relatively small, there are fewer electron traps in the first capping layer 61, which is beneficial to reducing the probability of electrons in the two-dimensional electron gas (2DEG) being captured by electron traps during transmission, and further beneficial to maintaining the concentration of the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, so that the concentration of the two-dimensional electron gas (2DEG) is more stable, thereby avoiding or reducing the probability of a positive drift of the threshold voltage due to the capture of electrons by electron traps during transmission, which is beneficial to improving the stability of the threshold voltage of the semiconductor device 10.

[0167] On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is relatively small, there is an approximately uniformly distributed electric field in the first capping layer 61, which is beneficial for electrons to accelerate in the first capping layer 61 and smoothly transition to the interface between the first capping layer 61 and the gate layer G, which can reduce the scattering and energy loss of electrons during the transmission process, and is beneficial to improving the performance stability of the semiconductor device 10.

[0168] On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is less than the doping concentration of the second capping layer 62 (i.e., the concentration of P-type impurities in the second capping layer 62), that is, the doping concentration of the second capping layer 62 is relatively large, there is an energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5. The energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is beneficial to depleting the two-dimensional electron gas (2DEG) below the second capping layer 62, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0169] Furthermore, due to the depletion effect of the second cap layer 62 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) below the second cap layer 62 , the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10 .

[0170] In summary, in the case where the semiconductor device 10 includes a first cap layer 61 and a second cap layer 62, by setting the gate layer G in the semiconductor device 10 on the side of the first cap layer 61 away from the substrate 1, and the gate layer G covers the two opposite side surfaces of the second cap layer 62 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), as well as the surface of the side of the second cap layer 62 away from the substrate 1, the threshold voltage of the semiconductor device 10 can be increased while improving the stability of the threshold voltage of the semiconductor device 10 and the performance stability of the semiconductor device 10.

[0171] For example, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 , the gate layer G in the semiconductor device 10 may contact a portion of the surface of the first capping layer 61 .

[0172] For example, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8 , a dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is less than or equal to a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0173] For example, see Figure 5 and Figure 6 , a dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0174] For another example, please continue to see Figure 7 and Figure 8 , a dimension hG of the gate layer G in the semiconductor device 10 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is equal to a dimension h1 of the first cap layer 61 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10).

[0175] It should be noted that the above “the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X” means that the difference between the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is within a preset threshold range. The threshold range is a relatively small numerical range. For example, the threshold range can be a process accuracy range when forming the first cap layer 61 and the gate layer G with equal dimensions along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0176] When a dimension hG of the gate layer G in the semiconductor device 10 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) is equal to a dimension h1 of the first cap layer 61 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), a threshold range of the difference between the dimension hG of the gate layer G in the semiconductor device 10 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) and the dimension h1 of the first cap layer 61 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) can be 0-2 μm.

[0177] For example, when a dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is equal to a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the difference between the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X can be 0, 0.1μm, 0.3μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.6μm, 1.8μm or 2μm, etc.

[0178] In some embodiments, Fig.11 , Fig.12 , Fig.13 and Fig.14 As shown, Fig.11 , Fig.12 , Fig.13 and Fig.14 1 and 2 are schematic cross-sectional views of a semiconductor device 10 according to some embodiments. Fig.11 as well as Fig.12 ,and Fig.13 as well as Fig.14 The difference is that Fig.11 and Fig.12 In the embodiment shown, the dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X. Fig.13 and Fig.14 In the illustrated embodiment, a dimension hG of the gate layer G in the semiconductor device 10 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10 ) is equal to a dimension h1 of the first cap layer 61 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10 ).

[0179] Fig.11 as well as Fig.13 ,and Fig.12 as well as Fig.14 The difference is that Fig.11 and Fig.13 In the illustrated embodiment, the semiconductor device 10 includes a second capping layer 62. Fig.12 and 14 In the illustrated embodiment, the semiconductor device 10 includes a plurality of (eg, two) second capping layers 62 .

[0180] Please continue reading Fig.11 , Fig.12 , Fig.13 and Fig.14 The semiconductor device 10 may further include a protection layer 8. The protection layer 8 may be disposed between the first capping layer 61 and the second capping layer 62 in the semiconductor device 10.

[0181] The protective layer 8 and the first cap layer 61 in the semiconductor device 10 overlap in the third direction (i.e., the thickness direction of the substrate 1 in the semiconductor device 10) Z. That is, the shape and size of the cross section of the protective layer 8 perpendicular to the third direction (i.e., the thickness direction of the substrate 1 in the semiconductor device 10) Z are the same as the shape and size of the cross section of the first cap layer 61 perpendicular to the third direction (i.e., the thickness direction of the substrate 1 in the semiconductor device 10) Z.

[0182] For example, see Fig.11 , Fig.12 , Fig.13 and Fig.14 , a dimension h8 of the protection layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0183] It should be noted that the above “the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X” means that the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is within a preset threshold range. The threshold range is a relatively small numerical range. For example, the threshold range can be a process accuracy range when forming the first cap layer 61 and the protective layer 8 having the same dimension along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0184] When the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the threshold range of the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X can be 0-0.5μm.

[0185] For example, when the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is the same as the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, the difference between the dimension h8 of the protective layer 8 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and the dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X can be 0, 0.1μm, 0.2μm, 0.3μm, 0.4μm or 0.5μm, etc.

[0186] In the case where the semiconductor device 10 includes a first cap layer 61 and a second cap layer 62, by setting a protective layer 8 between the first cap layer 61 and the second cap layer 62, and the protective layer 8 and the first cap layer 61 overlap in the third direction (i.e., the thickness direction of the substrate 1 in the semiconductor device 10) Z, when the second cap layer 62 in the semiconductor device 10 is formed by an etching process, the first cap layer 61 can be protected to avoid damage to the first cap layer 61 caused by the etching process, which is beneficial to improving the performance of the finally formed semiconductor device 10 and enhancing the reliability of the semiconductor device 10.

[0187] For example, please refer to Fig.11 , Fig.12 , Fig.13 and Fig.14 , the material of the protection layer 8 in the semiconductor device 10 is different from the material of the second capping layer 62 .

[0188] By making the material of the protective layer 8 and the material of the second cap layer 62 in the semiconductor device 10 different, when the second cap layer 62 in the semiconductor device 10 is formed by an etching process, the etching rate of the material of the protective layer 8 and the etching rate of the material of the second cap layer 62 are different. When the second cap layer 62 in the semiconductor device 10 is formed by an etching process, the material of the protective layer 8 and the material of the second cap layer 62 can be selectively etched, and the etching process can be stopped at the protective layer 8, so that the protective layer 8 can protect the first cap layer 61 arranged on the side of the protective layer 8 away from the second cap layer 62, thereby avoiding damage to the first cap layer 61 due to the etching process, which is beneficial to improving the performance of the finally formed semiconductor device 10 and enhancing the reliability of the semiconductor device 10.

[0189] Exemplarily, the material of the protection layer 8 in the semiconductor device 10 may include at least one of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN).

[0190] For example, the material of the protection layer 8 in the semiconductor device 10 may include aluminum gallium nitride (AlGaN) or aluminum nitride (AlN).

[0191] For another example, the material of the protection layer 8 in the semiconductor device 10 may include aluminum gallium nitride (AlGaN) and aluminum nitride (AlN).

[0192] Exemplarily, the material of the protection layer 8 in the semiconductor device 10 may include a P-type doped semiconductor material, and the doping concentration of the protection layer 8 is lower than the doping concentration of the second capping layer 62 .

[0193] For example, the material of the protection layer 8 in the semiconductor device 10 may include at least one of p-type aluminum gallium nitride (p-AlGaN) and p-type aluminum nitride (p-AlN).

[0194] P-type aluminum gallium nitride (p-AlGaN) can be formed by doping aluminum gallium nitride (AlGaN) materials with elements such as iron (Fe) and magnesium (Mg). P-type aluminum nitride (p-AlN) can be formed by doping aluminum nitride (AlN) materials with elements such as iron (Fe) and magnesium (Mg).

[0195] The method for manufacturing the semiconductor device 10 is described in detail below.

[0196] In some embodiments, Fig.15 As shown, Fig.15 FIG. 1 is a flow chart of a method for preparing a semiconductor device 10 according to some embodiments. It should be noted that: Fig.15 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Fig.15Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1 to S4.

[0197] S1: Fig.16 As shown, Fig.16 for Fig.15 A schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0198] For example, the barrier layer 5 may be formed on one side of the substrate 1 in the semiconductor device 10 by a process such as Metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Physical Vapor Deposition (PVD).

[0199] S2: Fig.17 As shown, Fig.17 for Fig.15 A schematic structural diagram of the semiconductor device 10 corresponding to step S2 and step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0200] S3: Please continue reading Fig.17 A second capping layer 62 is formed on a side of the first capping layer 61 away from the substrate 1 .

[0201] S4: Fig.18 As shown, Fig.18 for Fig.15 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S4 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A source electrode S and a drain electrode D are formed. The source electrode S and the drain electrode D are located on opposite sides of the first cap layer 61 along a first direction X, and are both arranged on a side of the barrier layer 5 away from the substrate 1, and the first direction X is parallel to the substrate 1.

[0202] Exemplarily, a portion of the barrier layer 5 in the source region and the drain region may be removed by a photolithography process to reduce the thickness of the barrier layer 5 to facilitate the formation of the source S and the drain D. When a portion of the barrier layer 5 in the source region and the drain region is removed by a photolithography process, a mixed gas such as Cl2 / ClB3 may be used as an etching gas.

[0203] Exemplarily, source and drain metals (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) can be grown by a sputtering process, and the source and drain metals (e.g., titanium (Ti), aluminum (Al), titanium nitride (TiN), etc.) outside the source region and the drain region can be removed by a dry etching process to form a source S and a drain D.

[0204] Among them, the dimension h2 of the second capping layer 62 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the dimension h1 of the first capping layer 61 in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X.

[0205] The first capping layer 61 and the second capping layer 62 in the semiconductor device 10 both include P-type doped semiconductor materials, and the doping concentration of the first capping layer 61 is lower than the doping concentration of the second capping layer 62 .

[0206] For example, the material of the first cap layer 61 and the material of the second cap layer 62 in the semiconductor device 10 may both include p-type gallium nitride (p-GaN). P-type gallium nitride (p-GaN) may be formed by doping gallium nitride (GaN) material with elements such as iron (Fe) and magnesium (Mg).

[0207] For example, when doping elements such as iron (Fe) and magnesium (Mg) into gallium nitride (GaN) materials to form p-type gallium nitride (p-GaN), a gas-phase doping process or an ion implantation process may be used.

[0208] By making the semiconductor device 10 include a first capping layer 61 and a second capping layer 62, the second capping layer 62 is arranged on a side of the first capping layer 61 in the semiconductor device 10 away from the substrate 1, and the first capping layer 61 and the second capping layer 62 both include P-type doped semiconductor materials, and the doping concentration of the first capping layer 61 is less than the doping concentration of the second capping layer 62. On the one hand, since the second capping layer 62 is arranged on a side of the first capping layer 61 in the semiconductor device 10 away from the substrate 1, that is, the first capping layer 61 is located between the second capping layer 62 and the barrier layer 5, in the process of forming the second capping layer 62 in the semiconductor device 10, when the P-type impurities in the second capping layer 62 diffuse, the P-type The impurities will first diffuse into the first cap layer 61, which can avoid or alleviate the diffusion of P-type impurities in the second cap layer 62 into the barrier layer 5, which can reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 5 and interfering with the polarization effect of the barrier layer 5, which is beneficial to improving the polarization effect of the barrier layer 5. It can also reduce the probability of changes in the characteristics of the connection interface between the first cap layer 61 and the barrier layer 5 (for example, the increase in the trap state density at the connection interface between the first cap layer 61 and the barrier layer 5, etc.), and affect the control ability of the gate layer G in the semiconductor device 10, which is beneficial to reduce the probability of problems such as dynamic on-resistance degradation in the semiconductor device 10, and thus help to improve the reliability of the semiconductor device 10.

[0209] On the other hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of P-type impurities in the first cap layer 61) is less than the doping concentration of the second cap layer 62 (i.e., the concentration of P-type impurities in the second cap layer 62), that is, the doping concentration of the first cap layer 61 is relatively small, in the process of forming the first cap layer 61 in the semiconductor device 10, the P-type impurities in the first cap layer 61 may not diffuse or only diffuse in a small amount into the barrier layer 5, which can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 5 and interfering with the polarization effect of the barrier layer 5, which is beneficial to further improve the polarization effect of the barrier layer 5, and can also further reduce the probability of changes in the characteristics of the connection interface between the first cap layer 61 and the barrier layer 5 (for example, the increase in the trap state density at the connection interface between the first cap layer 61 and the barrier layer 5, etc.), and affecting the control ability of the gate layer G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as dynamic on-resistance degradation in the semiconductor device 10, and thus is beneficial to further improve the reliability of the semiconductor device 10.

[0210] On the other hand, since the doping concentration of the first cap layer 61 (i.e., the concentration of the P-type impurities in the first cap layer 61) is less than the doping concentration of the second cap layer 62 (i.e., the concentration of the P-type impurities in the second cap layer 62), that is, the doping concentration of the second cap layer 62 is relatively large, there is an energy band difference (e.g., conduction band difference) between the second cap layer 62 and the barrier layer 5, and the energy band difference (e.g., conduction band difference) between the second cap layer 62 and the barrier layer 5 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is conducive to depleting the two-dimensional electron gas (2DEG) below the second cap layer 62, so that the semiconductor device 10 realizes an enhanced working mode. And due to the depletion effect of the second cap layer 62 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) located below the second cap layer 62, the semiconductor device 10 needs to overcome a higher barrier when it is turned on, which is conducive to increasing the threshold voltage of the semiconductor device 10.

[0211] In some embodiments, please refer to Fig.15 The step S2 (ie, forming the first capping layer 61 ) and the step S3 (ie, forming the second capping layer 62 ) in the method for preparing the semiconductor device 10 include steps S231 - S233 .

[0212] S231: Please continue reading Fig.17 , a first initial capping layer 61 a and a second initial capping layer 62 a are sequentially formed on a side of the barrier layer 5 away from the substrate 1 .

[0213] For example, a first initial capping layer 61 a and a second initial capping layer 62 a may be formed in sequence on a side of the barrier layer 5 in the semiconductor device 10 away from the substrate 1 by a process such as a metal-organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), or a physical vapor deposition (PVD).

[0214] Exemplarily, both the first initial capping layer 61 a and the second initial capping layer 62 a include P-type doped semiconductor materials, and the doping concentration of the first initial capping layer 61 a is less than the doping concentration of the second initial capping layer 62 a .

[0215] For example, the material of the first initial capping layer 61a and the material of the second initial capping layer 62a may both include p-type gallium nitride (p-GaN), which may be formed by doping GaN material with elements such as iron (Fe) and magnesium (Mg).

[0216] Exemplarily, when the first initial capping layer 61a and the second initial capping layer 62a both include P-type doped semiconductor materials, and the doping concentration of the first initial capping layer 61a is less than the doping concentration of the second initial capping layer 62a, a gas-phase doping process or an ion implantation process may be used to dope P-type impurities (e.g., magnesium (Mg)) into the semiconductor material (e.g., gallium nitride (GaN)) to form the first initial capping layer 61a and the second initial capping layer 62a, respectively.

[0217] Alternatively, a gas-phase doping process or an ion implantation process may be used to dope P-type impurities (eg, magnesium (Mg)) into a semiconductor material (eg, gallium nitride (GaN)) to form the second initial capping layer 62 a .

[0218] During the formation of the second initial capping layer 62a, part of the P-type impurities (eg, magnesium (Mg)) in the second initial capping layer 62a diffuses into the first initial capping layer 61a, so that the first initial capping layer 61a includes a P-type doped semiconductor material.

[0219] S232: Please continue reading Fig.17 , the first initial capping layer 61a and the second initial capping layer 62a of the source region Sa and the drain region Da to be formed are removed to form the first capping layer 61 and the third capping layer 63. The first capping layer 61 and the third capping layer 63 overlap in the thickness direction of the substrate 1.

[0220] Exemplarily, a photolithography process may be used to remove the first preliminary capping layer 61 a and the second preliminary capping layer 62 a where the source region Sa and the drain region Da are to be formed, so as to form the first capping layer 61 and the third capping layer 63 .

[0221] When the first preliminary capping layer 61 a and the second preliminary capping layer 62 a of the to-be-formed source region Sa and the to-be-formed drain region Da are removed by a photolithography process, a mixed gas such as Cl 2 / N 2 / O 2 may be used as an etching gas.

[0222] S233: Please continue reading Fig.17, remove part of the third capping layer 63 to form the second capping layer 62.

[0223] Exemplarily, a photolithography process may be used to remove a portion of the third capping layer 63 to form the second capping layer 62. When a photolithography process is used to remove a portion of the third capping layer 63, a mixed gas such as Cl2 / N2 / O2 may be used as an etching gas.

[0224] In some embodiments, please refer to Fig.15 The method for preparing the semiconductor device 10 may further include step S5.

[0225] S5: Fig.19 As shown, Fig.19 Schematic diagram of the structure of the semiconductor device 10 corresponding to step S5 and step S6 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A gate layer G is formed on a side of the first cap layer 61 away from the substrate 1. The gate layer G covers two side surfaces of the second cap layer 62 opposite to each other along the first direction X, and a surface of one side of the second cap layer 62 away from the substrate 1.

[0226] For example, a gate metal (eg, titanium nitride (TiN) etc.) may be grown by a sputtering process, and the gate metal (eg, titanium nitride (TiN) etc.) outside the gate region may be removed by a dry etching process to form a gate layer G.

[0227] In the case where the semiconductor device 10 includes a first cap layer 61 and a second cap layer 62, by setting the gate layer G in the semiconductor device 10 on a side of the first cap layer 61 away from the substrate 1, and the gate layer G covers two side surfaces of the second cap layer 62 opposite to each other along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), and a surface of the side of the second cap layer 62 away from the substrate 1, i.e., the second cap layer 62 is not set between a partial area in the gate layer G and the first cap layer 61, when the semiconductor device 10 is turned on (i.e., the gate layer G in the semiconductor device 10 is under a forward voltage bias), part of the two-dimensional electron gas (Two-dimensional electron gas) in the semiconductor device 10 is generated. The two-dimensional electron gas (two-dimensional electron gas, 2DEG) can be collected by the gate layer G and the partial area between the first cap layer 61 where the second cap layer 62 is not set through the first cap layer 61, without passing through the second cap layer 62. On the one hand, since the doping concentration of the first cap layer 61 (that is, the concentration of P-type impurities in the first cap layer 61) is less than the doping concentration of the second cap layer 62 (that is, the concentration of P-type impurities in the second cap layer 62), that is, the doping concentration of the first cap layer 61 is relatively small, there are fewer electron traps in the first cap layer 61, which is beneficial to reducing the probability that electrons in the two-dimensional electron gas (two-dimensional electron gas, 2DEG) are captured by electron traps during transmission, and further beneficial to maintaining the concentration of the two-dimensional electron gas (two-dimensional electron gas, 2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, so that the concentration of the two-dimensional electron gas (two-dimensional electron gas, 2DEG) is more stable, thereby avoiding or reducing the probability of the threshold voltage positive drift phenomenon caused by the capture of electrons by electron traps during transmission, which is beneficial to improving the stability of the threshold voltage of the semiconductor device 10.

[0228] On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is relatively small, there is an approximately uniformly distributed electric field in the first capping layer 61, which is beneficial for electrons to accelerate in the first capping layer 61 and smoothly transition to the interface between the first capping layer 61 and the gate layer G, which can reduce the scattering and energy loss of electrons during the transmission process, and is beneficial to improving the performance stability of the semiconductor device 10.

[0229] On the other hand, since the doping concentration of the first capping layer 61 (i.e., the concentration of P-type impurities in the first capping layer 61) is less than the doping concentration of the second capping layer 62 (i.e., the concentration of P-type impurities in the second capping layer 62), that is, the doping concentration of the second capping layer 62 is relatively large, there is an energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5. The energy band difference (e.g., conduction band difference) between the second capping layer 62 and the barrier layer 5 can be used to regulate the two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 5 and the channel layer 4, which is beneficial to depleting the two-dimensional electron gas (2DEG) below the second capping layer 62, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0230] Furthermore, due to the depletion effect of the second cap layer 62 in the semiconductor device 10 on the two-dimensional electron gas (2DEG) below the second cap layer 62 , the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10 .

[0231] In summary, in the case where the semiconductor device 10 includes a first cap layer 61 and a second cap layer 62, by setting the gate layer G in the semiconductor device 10 on the side of the first cap layer 61 away from the substrate 1, and the gate layer G covers the two opposite side surfaces of the second cap layer 62 along the first direction X (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10), as well as the surface of the side of the second cap layer 62 away from the substrate 1, the threshold voltage of the semiconductor device 10 can be increased while improving the stability of the threshold voltage of the semiconductor device 10 and the performance stability of the semiconductor device 10.

[0232] In some embodiments, please refer to Fig.15 The method for preparing the semiconductor device 10 may further include step S6.

[0233] S6: Please continue reading Fig.19 , forming a passivation layer 7. The passivation layer 7 covers the gate layer G, the source electrode S and the drain electrode D in the semiconductor device 10.

[0234] For example, the passivation layer 7 in the semiconductor device 10 may be formed by at least one of a chemical vapor deposition process (CVD) and a physical vapor deposition process (PVD).

[0235] By forming a passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers the gate layer G, the source S and the drain D in the semiconductor device 10, on the one hand, the passivation layer 7 can block harmful substances in the external environment (for example, oxygen, water, etc.), and avoid direct contact between harmful substances in the external environment (for example, oxygen, water, etc.) and the source S, drain D, and gate layer G in the semiconductor device 10, thereby preventing the source S, drain D, and gate layer G in the semiconductor device 10 from being damaged, which is beneficial to improving the stability of the semiconductor device 10 and extending the service life of the semiconductor device 10.

[0236] On the other hand, the passivation layer 7 has a certain mechanical strength, which can protect the source S, drain D and gate layer G in the semiconductor device 10 to a certain extent, and prevent the source S, drain D and gate layer G in the semiconductor device 10 from being mechanically damaged, which is beneficial to further improve the stability of the semiconductor device 10 and further extend the service life of the semiconductor device 10.

[0237] It should be noted that Fig.17 and Fig.18 In the following, the semiconductor device 10 including a second cap layer 62 is taken as an example to schematically illustrate step S2, step S3 and step S4 in the method for preparing the semiconductor device 10. Fig.19 In the figure, only the semiconductor device 10 includes a second cap layer 62, and the size hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is smaller than the size h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X is taken as an example to schematically illustrate step S5 in the method for preparing the semiconductor device 10. However, in the present disclosure, the number of second capping layers 62 in the semiconductor device 10, and the size relationship between the size hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and the size h1 of the first capping layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X are not limited to this, and the number of second capping layers 62 in the semiconductor device 10, and the size relationship between the size hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X, and the size h1 of the first capping layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X can be set according to actual needs.

[0238] For example, there may be a plurality of second capping layers 62 in the semiconductor device 10 .

[0239] For another example, a dimension hG of the gate layer G in the semiconductor device 10 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X and a dimension h1 of the first cap layer 61 along the first direction (i.e., the arrangement direction of the source S and the drain D in the semiconductor device 10) X may be equal.

[0240] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A barrier layer, disposed on one side of the substrate; A first capping layer is disposed on a side of the barrier layer away from the substrate; A second capping layer is disposed on a side of the first capping layer away from the substrate; a source electrode and a drain electrode, located on opposite sides of the first cap layer along a first direction, and both arranged on a side of the barrier layer away from the substrate, wherein the first direction is parallel to the substrate; Wherein, the size of the second capping layer along the first direction is smaller than the size of the first capping layer along the first direction; The first capping layer and the second capping layer both include P-type doped semiconductor materials, and the doping concentration of the first capping layer is less than the doping concentration of the second capping layer.

2. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plurality of the second capping layers, and the plurality of the second capping layers are spaced apart along the first direction.

3. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a gate layer, which is arranged on a side of the first cap layer away from the substrate; The gate layer covers two side surfaces of the second cap layer that are opposite to each other along the first direction, and a surface of the second cap layer that is away from the substrate.

4. The semiconductor device according to claim 3, characterized in that The gate layer contacts a portion of a surface of the first capping layer.

5. The semiconductor device according to claim 3, characterized in that A dimension of the gate layer along the first direction is smaller than or equal to a dimension of the first capping layer along the first direction.

6. The semiconductor device according to claim 1, wherein: A size of the second capping layer along a second direction is the same as a size of the first capping layer along the second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

7. The semiconductor device according to claim 1, wherein: The doping concentration of the first capping layer is less than or equal to 5×10 17 cm -3 .

8. The semiconductor device according to claim 7, characterized in that The doping concentration of the second capping layer is greater than or equal to 5×10 18 cm -3 , and less than or equal to 10×10 19 cm -3 .

9. The semiconductor device according to any one of claims 1 to 3 and 5 to 8, characterized in that: The semiconductor device further comprises a protection layer disposed between the first capping layer and the second capping layer; The protection layer and the first capping layer overlap in a thickness direction of the substrate.

10. The semiconductor device according to claim 9, characterized in that The material of the protection layer is different from the material of the second capping layer.

11. The semiconductor device according to claim 10, characterized in that The material of the protection layer includes at least one of aluminum gallium nitride and aluminum nitride.

12. The semiconductor device according to claim 9, characterized in that The material of the protection layer includes a P-type doped semiconductor material, and the doping concentration of the protection layer is less than the doping concentration of the second capping layer.

13. A method for preparing a semiconductor device, characterized in that: include: forming a barrier layer on one side of the substrate; forming a first capping layer on a side of the barrier layer away from the substrate; forming a second capping layer on a side of the first capping layer away from the substrate; forming a source electrode and a drain electrode; the source electrode and the drain electrode are located on opposite sides of the first cap layer along a first direction, and are both arranged on a side of the barrier layer away from the substrate, and the first direction is parallel to the substrate; Wherein, the size of the second capping layer along the first direction is smaller than the size of the first capping layer along the first direction; The first capping layer and the second capping layer both include P-type doped semiconductor materials, and the doping concentration of the first capping layer is less than the doping concentration of the second capping layer.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The forming of the first capping layer and the forming of the second capping layer include: forming a first initial capping layer and a second initial capping layer in sequence on a side of the barrier layer away from the substrate; removing the first initial capping layer and the second initial capping layer in the to-be-formed source region and the to-be-formed drain region to form a first capping layer and a third capping layer, wherein the first capping layer and the third capping layer overlap in the thickness direction of the substrate; A portion of the third capping layer is removed to form a second capping layer.

15. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

16. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 15, wherein the chip is electrically connected to the circuit board.

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