Shield gate trench MOSFET device structure and manufacturing method
By setting the width of the second trench and the third trench in the shielded gate trench MOSFET device to be larger than the first trench, the problem of contact hole alignment limitation caused by the reduction of the trench width is solved, and the electrical parameters of the device are improved and reliability.
Patent Information
- Application Number
- CN202411608071.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2024-12-27
AI Technical Summary
When existing shielded gate trench MOSFET devices reduce the trench width, the widths of source polysilicon and gate polysilicon are simultaneously reduced, thereby limiting the photolithography alignment process of source polysilicon and gate polysilicon contact holes, affecting the electrical parameters and reliability of the device. .
The widths of the second and third trenches are designed to be greater than the width of the first trench and are independently set in the lithography process to increase the ease of alignment while meeting the electrical parameters and reliability requirements of the device, through the trench The inner wall of the groove forms a field oxygen layer and a gate oxygen layer to ensure the accuracy of the contact holes.
The accuracy of exposure alignment of source polysilicon and gate polysilicon holes is improved, the effective proportion of active regions is increased, and the electrical parameters and reliability requirements of the device are met, such as the reverse voltage withstand value BVDSS.
Smart Images
Figure CN119208381A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of integrated circuits, and in particular to a shielded gate trench MOSFET device structure and a manufacturing method. Background Art
[0002] Shielded-Gate Trench MOSFET (SGT-MOSFET) is an advanced discrete device MOSFET structure with high breakdown voltage, low on-resistance and fast switching speed. The general structure of shielded-gate trench MOSFET is to fill the trench with polysilicon, which is divided into two parts: the polysilicon located in the lower part of the trench forms the source polysilicon (source poly), also known as shielded gate polysilicon), which is short-circuited with the source of the device; the polysilicon located in the upper part of the trench constitutes the polysilicon gate (gate poly), and there is a silicon oxide film layer between the two layers of polysilicon.
[0003] With the development of technology, a higher current density is needed, that is, a smaller internal resistance per unit area. This requires more SGT-MOSFET units to be connected in parallel within the same area. The width of each unit is called pitch, so the pitch of each unit needs to be reduced, and the width of the trench also needs to be reduced. Therefore, higher requirements are placed on the hole lithography alignment process, which is also a key factor limiting the reduction of pitch. If the hole alignment deviates, it will cause a short circuit between the gate and the drain, the chip will fail and be scrapped, and the device will fail directly due to leakage. Summary of the invention
[0004] In view of the deficiencies in the prior art, the present invention discloses a shielded gate trench MOSFET device structure and a manufacturing method.
[0005] The technical solution adopted by the present invention is as follows:
[0006] A shielded gate trench MOSFET device structure includes at least one group of MOSFET units; the MOSFET unit includes an active region and a terminal region;
[0007] The active area includes a first trench, and a shielding gate structure is formed in the first trench; a body region and a source region are formed on both sides of the outside of the first trench, and the body region and the source region are connected to the source region metal through a source region contact hole;
[0008] The terminal region includes a second trench and a third trench, a source lead-out structure is formed in the second trench, and the source lead-out structure includes source polysilicon; the second source polysilicon is connected to the source region metal through a source polysilicon contact hole;
[0009] A gate lead-out structure is formed in the third trench, wherein the gate lead-out structure includes gate polysilicon; the gate polysilicon is connected to the gate metal through a gate polysilicon contact hole;
[0010] The width of the second trench and the width of the third trench are greater than the width of the first trench, and the width of the second trench meets the requirements of the photolithography alignment process of the source polysilicon contact hole, and the width of the third trench meets the requirements of the photolithography alignment process of the gate polysilicon contact hole.
[0011] A further technical solution is that the width of the second groove is in the range of 0.6um to 1.0um; the width of the third groove is in the range of 0.6um to 1.0um; and the width of the first groove is in the range of 0.25um to 0.4um.
[0012] A further technical solution is that the second grooves and the third grooves are arranged crosswise with each other.
[0013] Its further technical solution is that when the shielded gate trench MOSFET device structure includes multiple groups of MOSTFET units, the first trenches, the second trenches and the third trenches in the multiple groups of MOSTFET units are parallel to each other, the multiple groups of source metals of the first trenches and the second trenches of the multiple MOSFET units in the MOSTFET device are integrated, the gate polysilicon in the MOSFET unit is connected to the gate metal line through the gate polysilicon contact hole, and the gate metal lines of the multiple groups of MOSFET units are all connected to the gate metal.
[0014] Its further technical solution is that the shielding gate structure of the active area includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, and a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; an IPO oxide layer is formed between the gate polysilicon and the source polysilicon.
[0015] A further technical solution is that, in the source lead-out structure, a field oxide layer is formed between the inner wall of the second trench and the source polysilicon.
[0016] A further technical solution is that the gate lead-out structure includes gate polysilicon and source polysilicon; the gate polysilicon and the inner wall of the third trench form a field oxide layer, the source polysilicon and the inner wall of the third trench form a field oxide layer, and a field oxide layer is formed between the gate polysilicon and the source polysilicon.
[0017] A method for manufacturing a shielded gate trench MOSFET device comprises the following steps:
[0018] Growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, and forming a first trench, a second trench, and a third trench, and forming a field oxide layer at the bottom and sidewall of the first trench, the second trench, and the third trench;
[0019] Depositing source polysilicon to backfill the first trench, the second trench and the third trench, and planarizing to the surface of the epitaxial layer;
[0020] Etching a portion of the thickness of the source polysilicon in the first trench and the third trench, and etching away the field oxide layer on the sidewalls of the corresponding first trench and the third trench;
[0021] forming a field oxide layer again on the sidewalls of the first trench and the third trench and on the upper portion of the source polysilicon;
[0022] After photolithography and etching processes, the oxide layer on the sidewall and bottom of the first trench is etched away, and then a gate oxide layer is formed on the sidewall and bottom of the first trench;
[0023] Depositing gate polysilicon, backfilling the first trench and the third trench, and planarizing to the surface of the epitaxial layer;
[0024] Doping is performed on the front side of the first trench to form a body region and a source region; then an active region contact hole, a source polysilicon contact hole and a gate polysilicon contact hole are formed respectively; and then source region metal and gate region metal are formed.
[0025] A further technical solution is to form an active area contact hole beside the first trench by photolithography and etching of the contact hole; to form a source polysilicon contact hole above the second trench; and to form a gate polysilicon contact hole 109 above the third trench.
[0026] A further technical solution is that multiple groups of source metals of the first trenches and the second trenches of multiple MOSFET units in the MOSTFET device are formed as one body.
[0027] The beneficial effects of the present invention are as follows:
[0028] The present invention provides a terminal structure of a shielded gate trench MOSFET, which solves the problem that the widths of source polysilicon and gate polysilicon are simultaneously reduced due to the reduction of the trench width, thereby causing the alignment limitation of the source polysilicon contact hole and the gate polysilicon contact hole photolithography process.
[0029] In the technical solution proposed by the present invention, the width of the second groove and the width of the third groove are greater than the width of the first groove. Such a setting can make the width of the second groove and the third groove independent of the first groove, make the second groove and the third groove wider, increase the ease of alignment, and at the same time cooperate with the gate lead-out structure and the source lead-out structure, without affecting the design of making the first groove narrower. Not only does it solve the limitation of exposure alignment of gate polysilicon and source polysilicon holes, but it also increases the effective proportion of the active area and meets the electrical parameters and reliability requirements of the device, such as reverse withstand voltage value BVDSS (drain-source breakdown voltage). BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 Schematic diagram of the layout of the shielded gate trench MOSFET device structure in an embodiment of the present invention.
[0031] Figure 2 for Figure 1 Screenshot along line d in the middle.
[0032] Figure 3 for Figure 1 Screenshot along line b.
[0033] Figure 4 FIG. 4 is a schematic diagram of a step of forming a groove in an embodiment of the present invention.
[0034] Figure 5 Schematic diagram of the step of backfilling the trench in an embodiment of the present invention.
[0035] Figure 6 Schematic diagram of the etching step in an embodiment of the present invention.
[0036] Figure 7 FIG. 4 is a schematic diagram of the step of growing a field oxide layer again in an embodiment of the present invention.
[0037] Figure 8 Schematic diagram of the step of growing a gate oxide layer in an embodiment of the present invention.
[0038] Fig. 9 Schematic diagram of the active area in the step of depositing gate polysilicon in an embodiment of the present invention.
[0039] Fig.10 Schematic diagram of the terminal region in the step of depositing gate polysilicon in an embodiment of the present invention.
[0040] Fig.11 It is a partial screenshot of the active area in an embodiment of the present invention.
[0041] Fig.12 for Figure 3 The figure includes a partial screenshot of the source polysilicon contact hole structure.
[0042] Fig.13 for Figure 1 Screenshot along line c.
[0043] In the figure: 1, first trench; 2, second trench; 3, third trench; 100, substrate; 101, epitaxial layer; 102, trench; 103, field oxide layer; 104, source polysilicon; 105, gate oxide layer; 106, gate polysilicon; 107, source contact hole; 108, source polysilicon contact hole; 109, gate polysilicon contact hole; 110, source region metal; 111, gate region metal; 112, source region; 113, dielectric layer; 114, body region. DETAILED DESCRIPTION
[0044] The specific implementation of the present invention will be described below in conjunction with the accompanying drawings.
[0045] Figure 1 FIG. 1 is a schematic diagram of the layout of the shielded gate trench MOSFET device structure in an embodiment of the present invention. Figure 1 As shown, the shielded gate trench MOSFET device structure includes at least one group of MOSFET units. The MOSFET unit includes an active area and a terminal area. In this embodiment, the active area refers to the part of the MOS tube that includes the key structure of the transistor, including but not limited to the source area (source), the body area (body), etc., and the termination area (termination area) generally refers to the part used for electrical connection and protection.
[0046] Figure 2 for Figure 1 Screenshot along line d in the middle. Fig.11 It is a partial screenshot of the active area in an embodiment of the present invention. Fig.11 It also reflects Figure 1 A part of the structure along the a line section. Figure 1 , Figure 2 and Fig.11 As shown, the active area includes a first trench 1, and a shielded gate structure is formed in the first trench 1. The shielded gate structure includes a gate polysilicon 106 and a source polysilicon 104. A field oxide layer 103 is formed between the source polysilicon 106 and the inner wall of the first trench 1, and a gate oxide layer 105 is formed between the gate polysilicon 106 and the inner wall of the first trench 1. An IPO oxide layer is formed between the gate polysilicon 106 and the source polysilicon 104. A body region 114 is formed on the outer side of the first trench 1, and a source region 112 is formed at a position above the body region 114 on the outer side of the first trench 1. A dielectric layer 113 is formed on the upper part of the first trench 1 and covers the source region. A source contact hole 107 passes through the dielectric layer, and one end of the source contact metal in the source contact hole 107 contacts the source region metal 110, and the other end contacts the source region 112 and the body region 114. In this embodiment, the body region 114 is P-type, and the source region 112 is N-type.
[0047] The termination region includes a second trench 2 and a third trench 3 . Figure 3 for Figure 1 Screenshot along line b. Fig.12 for Figure 3 The figure includes some screenshots of the source polysilicon contact hole structure, such as Figure 3 , Fig.12 As shown, a source lead-out structure is formed in the second trench 2, and the source lead-out structure includes a source polysilicon 104. A field oxide layer 103 is formed between the inner wall of the second trench 2 and the source polysilicon 104. The source polysilicon 104 is connected to the source metal 110 through a source polysilicon contact hole 108.
[0048] Fig.13 for Figure 1 A screenshot along line c in Figure 2. Fig.13 As shown, a gate lead-out structure is formed in the third trench 3, and the gate lead-out structure includes a gate polysilicon 106. The gate polysilicon 106 is connected to the gate metal 111 through a gate polysilicon contact hole 109. The gate polysilicon 106 and the inner wall of the third trench 3 form a field oxide layer, the source polysilicon 104 and the inner wall of the third trench 3 form a field oxide layer 103, and the field oxide layer 103 is formed between the gate polysilicon 106 and the source polysilicon 104.
[0049] Combination Figure 1 to Figure 3 as well as Figure 11 to Figure 13 In this embodiment, the width of the second trench 2 and the width of the third trench 3 are greater than the width of the first trench 1. Moreover, the width of the second trench 2 and the width of the third trench 3 at least meet the requirements of the photolithography alignment process of the source polysilicon contact hole 108 of the second trench 2 and the gate polysilicon contact hole 109 of the third trench 3. With such a setting, the widths of the second trench 2 and the third trench 3 can be separated from the first trench 1, and the second trench 2 and the third trench 3 can be made wider to increase the ease of alignment. At the same time, in conjunction with the gate lead-out structure and the source lead-out structure, it does not affect the design of making the first trench 1 narrower. Not only does it solve the limitation of exposure alignment of the gate polysilicon and source polysilicon holes, but it can also ensure that the structure meets the electrical requirements and reliability of the device while increasing the proportion of the active area. For example, the reverse withstand voltage value BVDSS (drain-source breakdown voltage) of the device will not be reduced.
[0050] Preferably, the width of the second trench 2 is in the range of 0.6um to 1.0um, the width of the third trench 3 is in the range of 0.6um to 1.0um, and the width of the first trench 1 is in the range of 0.25um to 0.4um. Of course, the above-mentioned width ranges of the second trench 2 and the third trench 3 are preferred values, and those skilled in the art can further widen the widths of the second trench 2 and the third trench 3 according to actual needs or process conditions without affecting the electrical characteristics of the device.
[0051] Further, such as Figure 1 As shown, the second trenches 2 and the third trenches 3 are arranged alternately and crosswise, which can further reduce the area of the MOSTFET unit.
[0052] Further, such as Figure 1 As shown, when the shielded gate trench MOSFET device structure includes multiple groups of MOSTFET units, the first trench 1, the second trench 2 and the third trench 3 in the multiple groups of MOSTFET units are parallel to each other, and the source metal 110 of the first trench 1 and the second trench 2 of the MOSTFET device is integrated, the gate polysilicon 106 is connected to the gate metal line through the gate polysilicon contact hole 109, and the gate metal lines of the multiple groups of MOSTFET units are connected to the gate metal 111. .
[0053] The following is a description of a method for manufacturing a shielded gate trench MOSFET device structure, which specifically includes:
[0054] Step 1: Forming a groove. Figure 4 FIG. 1 is a schematic diagram of a step of forming a groove in an embodiment of the present invention. Figure 4 As shown, a second conductive type epitaxial layer 101 of target thickness is grown on a first conductive type substrate 100, and a trench 102 of target depth is formed. The trench 102 includes a first trench 1, a second trench 2 and a third trench 3, and a field oxide layer 103 is formed at the bottom and sidewall of the trench 102.
[0055] Generally, the first conductivity type is N type, and the second conductivity type is P type, or the first conductivity type may be P type, and the second conductivity type may be N type. The groove 102 may be formed by processes such as groove photolithography and etching. The field oxide layer 103 may be formed by, but not limited to, thermal oxidation, CVD deposition, and the like. The target thickness and target depth in this step and subsequent steps are determined according to the device model and functional parameters, and can be specifically adjusted by those skilled in the art according to known techniques. For example, in this step, for a common 30V SGTMOSFET device, generally speaking, the thickness of the epitaxial layer 101 is about 2.8um, the resistivity is about 0.07ohm-cm, and the depth of the groove 102 is about 1.3um. The specific values of the target thickness and target depth in the subsequent steps will not be repeated.
[0056] Step 2: Backfill the trench. Figure 5 FIG. 1 is a schematic diagram of the step of backfilling the trench in an embodiment of the present invention. Figure 5 As shown, source polysilicon 104 of target thickness is deposited to backfill the trench 102 , and is planarized to the surface of the epitaxial layer 101 by CMP.
[0057] Step 3: Etching. Figure 6 Schematic diagram of the etching step in the embodiment of the present invention. Figure 6 As shown, a pattern to be etched is formed by a photolithography process, and a photoresist is used as a mask layer. In the first trench 1 and the third trench 3, the source polysilicon 104 of a target thickness is etched away. Specifically, the thickness of the etched source polysilicon 104 is a portion of the depth of the first trench 1 and the third trench 3, and the corresponding field oxide layer 103 on the sidewalls of the corresponding first trench 1 and the third trench 3 is etched away. Then the photoresist is removed.
[0058] Step 4: Grow the field oxide layer again. Figure 7 FIG. 1 is a schematic diagram of the step of growing the field oxide layer again in an embodiment of the present invention. Figure 7As shown, a field oxide layer 103 with a target thickness is formed on the sidewalls of the first trench 1 and the third trench 3 and on the upper portion of the source polysilicon 104. Specifically, the field oxide layer 103 can be formed by, but is not limited to, thermal oxidation, CVD deposition, and the like.
[0059] Step 5: grow a gate oxide layer. Figure 8 FIG. 1 is a schematic diagram of the step of growing a gate oxide layer in an embodiment of the present invention. Figure 8 As shown, a pattern to be etched is formed by a photolithography process, and the field oxide layer 103 on the sidewalls and bottom of the first trench 1 in the active area is etched away using the photoresist as a masking layer, the photoresist is removed, and then a gate oxide layer 105 is generated on the sidewalls and bottom of the first trench 1 using a thermal oxidation method.
[0060] Step 6: deposit gate polysilicon. Fig. 9 Schematic diagram of the active area in the step of depositing gate polysilicon in an embodiment of the present invention. Fig.10 FIG. 1 is a schematic diagram of the terminal region in the step of depositing gate polysilicon in an embodiment of the present invention. Fig. 9 , Fig.10 As shown, gate polysilicon is deposited, the first trench and the third trench are backfilled, and CMP is performed to planarize the surface of the epitaxial layer 101 .
[0061] Step 7: Ion implantation of impurities and annealing are performed on the front side of the first trench to form a body region 114, followed by photolithography implantation of impurities and annealing to form a source region 112. In an embodiment of the present invention, the body region 114 is of P type and the source region 112 is of N type, and the type of implanted impurities can be determined according to the doping type.
[0062] Step 8, depositing a dielectric layer, and then performing photolithography and etching of contact holes to form active area contact holes 107, source polysilicon contact holes 108, and gate polysilicon contact holes 109, respectively;
[0063] Step 9: metal deposition, metal photolithography, and etching to form source metal 110 and gate metal 111. Figure 1 As shown, the source metal 110 of the first trench 1 and the second trench 2 of the MOSTFET device is integrated. The gate polysilicon 106 is connected to the gate metal line through the gate polysilicon contact hole 109, and the gate metal lines of multiple groups of MOSTFET devices are all connected to the gate metal 111.
[0064] The structures related to steps 7 to 9 can be referred to Figure 10 to Figure 12 ,exist Figure 10 to Figure 12 An active region contact hole 107, a source polysilicon contact hole 108, a gate polysilicon contact hole 109, and a source region metal 110 and a gate region metal 111 are shown.
[0065] In this embodiment, the specific process parameters of steps 1 to 9 are adjusted and selected by technicians in this field based on general process knowledge and device parameter requirements of integrated circuits. The specific process parameters are not the content to be protected by this application and will not be repeated in this article.
[0066] The above description is an explanation of the present invention, not a limitation of the present invention. The scope of the present invention is defined in the claims. The present invention may be modified in any form without violating the basic structure of the present invention.
Claims
1. A shielded gate trench MOSFET device structure, characterized in that: The device comprises at least one group of MOSFET units; the MOSFET unit comprises an active region and a terminal region; The active area includes a first trench, and a shielding gate structure is formed in the first trench; a body region and a source region are formed on both sides of the outside of the first trench, and the body region and the source region are connected to the source region metal through a source region contact hole; The terminal region includes a second trench and a third trench, a source lead-out structure is formed in the second trench, and the source lead-out structure includes source polysilicon; the second source polysilicon is connected to the source region metal through a source polysilicon contact hole; A gate lead-out structure is formed in the third trench, wherein the gate lead-out structure includes gate polysilicon; the gate polysilicon is connected to the gate metal through a gate polysilicon contact hole; The width of the second trench and the width of the third trench are greater than the width of the first trench, and the width of the second trench meets the requirements of the photolithography alignment process of the source polysilicon contact hole, and the width of the third trench meets the requirements of the photolithography alignment process of the gate polysilicon contact hole.
2. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The width of the second groove is in the range of 0.6um to 1.0um; the width of the third groove is in the range of 0.6um to 1.0um; and the width of the first groove is in the range of 0.25um to 0.4um.
3. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The second grooves and the third grooves are arranged to cross each other with an interval.
4. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: When the shielded gate trench MOSFET device structure includes multiple groups of MOSTFET units, the first trenches, the second trenches and the third trenches in the multiple groups of MOSTFET units are parallel to each other; the multiple groups of source metals of the first trenches and the second trenches of the multiple MOSFET units in the MOSTFET device are integrated; the gate polysilicon in the MOSFET unit is connected to the gate metal line through the gate polysilicon contact hole, and the gate metal lines of the multiple groups of MOSFET units are all connected to the gate metal.
5. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The shielding gate structure of the active area includes gate polysilicon and source polysilicon; a field oxide layer is formed between the source polysilicon and the inner wall of the first trench, a gate oxide layer is formed between the gate polysilicon and the inner wall of the first trench; and an IPO oxide layer is formed between the gate polysilicon and the source polysilicon.
6. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: In the source lead-out structure, a field oxide layer is formed between the inner wall of the second trench and the source polysilicon.
7. The shielded gate trench MOSFET device structure according to claim 1, characterized in that: The gate lead-out structure includes gate polysilicon and source polysilicon; the gate polysilicon and the inner wall of the third trench form a field oxide layer, the source polysilicon and the inner wall of the third trench form a field oxide layer, and a field oxide layer is formed between the gate polysilicon and the source polysilicon.
8. A method for manufacturing a shielded gate trench MOSFET device, characterized in that: The following steps are involved: Growing an epitaxial layer of a second conductivity type on a substrate of a first conductivity type, and forming a first trench, a second trench, and a third trench, and forming a field oxide layer at the bottom and sidewall of the first trench, the second trench, and the third trench; Depositing source polysilicon to backfill the first trench, the second trench and the third trench, and planarizing to the surface of the epitaxial layer; Etching a portion of the thickness of the source polysilicon in the first trench and the third trench, and etching away the field oxide layer on the sidewalls of the corresponding first trench and the third trench; forming a field oxide layer again on the sidewalls of the first trench and the third trench and on the upper portion of the source polysilicon; After photolithography and etching processes, the oxide layer on the sidewall and bottom of the first trench is etched away, and then a gate oxide layer is formed on the sidewall and bottom of the first trench; Depositing gate polysilicon, backfilling the first trench and the third trench, and planarizing to the surface of the epitaxial layer; Doping is performed on the front side of the first trench to form a body region and a source region; and then an active region contact hole, a source polysilicon contact hole and a gate polysilicon contact hole are formed respectively; Then the source metal and gate metal are formed.
9. The method for manufacturing a shielded gate trench MOSFET device according to claim 8, characterized in that: Through photolithography and etching of the contact holes, an active area contact hole is formed beside the first trench; a source polysilicon contact hole is formed above the second trench; and a gate polysilicon contact hole 109 is formed above the third trench.
10. The method for manufacturing a shielded gate trench MOSFET device according to claim 8, characterized in that: Multiple groups of source metals of the first trenches and the second trenches of multiple MOSFET units in the MOSTFET device are formed as one.